1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8723DPHYREG_H__ 16 #define __INC_HAL8723DPHYREG_H__ 17 18 #define rSYM_WLBT_PAPE_SEL 0x64 19 /* 20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 21 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 23 * 3. RF register 0x00-2E 24 * 4. Bit Mask for BB/RF register 25 * 5. Other definition for BB/RF R/W 26 * */ 27 28 29 /* 30 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 31 * 1. Page1(0x100) 32 * */ 33 #define rPMAC_Reset 0x100 34 #define rPMAC_TxStart 0x104 35 #define rPMAC_TxLegacySIG 0x108 36 #define rPMAC_TxHTSIG1 0x10c 37 #define rPMAC_TxHTSIG2 0x110 38 #define rPMAC_PHYDebug 0x114 39 #define rPMAC_TxPacketNum 0x118 40 #define rPMAC_TxIdle 0x11c 41 #define rPMAC_TxMACHeader0 0x120 42 #define rPMAC_TxMACHeader1 0x124 43 #define rPMAC_TxMACHeader2 0x128 44 #define rPMAC_TxMACHeader3 0x12c 45 #define rPMAC_TxMACHeader4 0x130 46 #define rPMAC_TxMACHeader5 0x134 47 #define rPMAC_TxDataType 0x138 48 #define rPMAC_TxRandomSeed 0x13c 49 #define rPMAC_CCKPLCPPreamble 0x140 50 #define rPMAC_CCKPLCPHeader 0x144 51 #define rPMAC_CCKCRC16 0x148 52 #define rPMAC_OFDMRxCRC32OK 0x170 53 #define rPMAC_OFDMRxCRC32Er 0x174 54 #define rPMAC_OFDMRxParityEr 0x178 55 #define rPMAC_OFDMRxCRC8Er 0x17c 56 #define rPMAC_CCKCRxRC16Er 0x180 57 #define rPMAC_CCKCRxRC32Er 0x184 58 #define rPMAC_CCKCRxRC32OK 0x188 59 #define rPMAC_TxStatus 0x18c 60 61 /* 62 * 2. Page2(0x200) 63 * 64 * The following two definition are only used for USB interface. */ 65 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 66 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 67 68 /* 69 * 3. Page8(0x800) 70 * */ 71 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC // RF BW Setting?? */ 72 73 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 74 #define rFPGA0_PSDFunction 0x808 75 76 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 77 78 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 79 #define rFPGA0_RFTiming2 0x814 80 81 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 82 #define rFPGA0_XA_HSSIParameter2 0x824 83 #define rFPGA0_XB_HSSIParameter1 0x828 84 #define rFPGA0_XB_HSSIParameter2 0x82c 85 #define rTxAGC_B_Rate18_06 0x830 86 #define rTxAGC_B_Rate54_24 0x834 87 #define rTxAGC_B_CCK1_55_Mcs32 0x838 88 #define rTxAGC_B_Mcs03_Mcs00 0x83c 89 90 #define rTxAGC_B_Mcs07_Mcs04 0x848 91 #define rTxAGC_B_Mcs11_Mcs08 0x84c 92 93 #define rFPGA0_XA_LSSIParameter 0x840 94 #define rFPGA0_XB_LSSIParameter 0x844 95 96 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 97 #define rFPGA0_RFSleepUpParameter 0x854 98 99 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 100 #define rFPGA0_XCD_SwitchControl 0x85c 101 102 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 103 #define rFPGA0_XB_RFInterfaceOE 0x864 104 105 #define rTxAGC_B_Mcs15_Mcs12 0x868 106 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 107 108 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 109 #define rFPGA0_XCD_RFInterfaceSW 0x874 110 111 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 112 #define rFPGA0_XCD_RFParameter 0x87c 113 114 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 115 #define rFPGA0_AnalogParameter2 0x884 116 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 117 #define rFPGA0_AnalogParameter4 0x88c 118 119 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 120 #define rFPGA0_XB_LSSIReadBack 0x8a4 121 #define rFPGA0_XC_LSSIReadBack 0x8a8 122 #define rFPGA0_XD_LSSIReadBack 0x8ac 123 124 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 125 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 126 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 127 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now // RF Interface Readback Value */ 128 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 129 130 /* 131 * 4. Page9(0x900) 132 * */ 133 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC // RF BW Setting?? */ 134 #define rFPGA1_TxBlock 0x904 /* Useless now */ 135 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 136 #define rFPGA1_TxInfo 0x90c /* Useless now // Status report?? */ 137 #define rDPDT_control 0x92c 138 #define rfe_ctrl_anta_src 0x930 139 #define rS0S1_PathSwitch 0x948 140 #define rBBrx_DFIR 0x954 141 142 /* 143 * 5. PageA(0xA00) 144 * 145 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 146 #define rCCK0_System 0xa00 147 148 #define rCCK0_AFESetting 0xa04 /* Disable init gain now // Select RX path by RSSI */ 149 #define rCCK0_CCA 0xa08 /* Disable init gain now // Init gain */ 150 151 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 152 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 153 154 #define rCCK0_RxHP 0xa14 155 156 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 157 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 158 159 #define rCCK0_TxFilter1 0xa20 160 #define rCCK0_TxFilter2 0xa24 161 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 162 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 163 #define rCCK0_TRSSIReport 0xa50 164 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 165 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 166 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 167 168 /* 169 * PageB(0xB00) 170 * */ 171 #define rPdp_AntA 0xb00 172 #define rPdp_AntA_4 0xb04 173 #define rPdp_AntA_8 0xb08 174 #define rPdp_AntA_C 0xb0c 175 #define rPdp_AntA_10 0xb10 176 #define rPdp_AntA_14 0xb14 177 #define rPdp_AntA_18 0xb18 178 #define rPdp_AntA_1C 0xb1c 179 #define rPdp_AntA_20 0xb20 180 #define rPdp_AntA_24 0xb24 181 182 #define rConfig_Pmpd_AntA 0xb28 183 #define rConfig_ram64x16 0xb2c 184 185 #define rBndA 0xb30 186 #define rHssiPar 0xb34 187 188 #define rConfig_AntA 0xb68 189 #define rConfig_AntB 0xb6c 190 191 #define rPdp_AntB 0xb70 192 #define rPdp_AntB_4 0xb74 193 #define rPdp_AntB_8 0xb78 194 #define rPdp_AntB_C 0xb7c 195 #define rPdp_AntB_10 0xb80 196 #define rPdp_AntB_14 0xb84 197 #define rPdp_AntB_18 0xb88 198 #define rPdp_AntB_1C 0xb8c 199 #define rPdp_AntB_20 0xb90 200 #define rPdp_AntB_24 0xb94 201 202 #define rConfig_Pmpd_AntB 0xb98 203 204 #define rBndB 0xba0 205 206 #define rAPK 0xbd8 207 #define rPm_Rx0_AntA 0xbdc 208 #define rPm_Rx1_AntA 0xbe0 209 #define rPm_Rx2_AntA 0xbe4 210 #define rPm_Rx3_AntA 0xbe8 211 #define rPm_Rx0_AntB 0xbec 212 #define rPm_Rx1_AntB 0xbf0 213 #define rPm_Rx2_AntB 0xbf4 214 #define rPm_Rx3_AntB 0xbf8 215 /* 216 * 6. PageC(0xC00) 217 * */ 218 #define rOFDM0_LSTF 0xc00 219 220 #define rOFDM0_TRxPathEnable 0xc04 221 #define rOFDM0_TRMuxPar 0xc08 222 #define rOFDM0_TRSWIsolation 0xc0c 223 224 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 225 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 226 #define rOFDM0_XBRxAFE 0xc18 227 #define rOFDM0_XBRxIQImbalance 0xc1c 228 #define rOFDM0_XCRxAFE 0xc20 229 #define rOFDM0_XCRxIQImbalance 0xc24 230 #define rOFDM0_XDRxAFE 0xc28 231 #define rOFDM0_XDRxIQImbalance 0xc2c 232 233 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD // DM tune init gain */ 234 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 235 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 236 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 237 238 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 239 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 240 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 241 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 242 243 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 244 #define rOFDM0_XAAGCCore2 0xc54 245 #define rOFDM0_XBAGCCore1 0xc58 246 #define rOFDM0_XBAGCCore2 0xc5c 247 #define rOFDM0_XCAGCCore1 0xc60 248 #define rOFDM0_XCAGCCore2 0xc64 249 #define rOFDM0_XDAGCCore1 0xc68 250 #define rOFDM0_XDAGCCore2 0xc6c 251 252 #define rOFDM0_AGCParameter1 0xc70 253 #define rOFDM0_AGCParameter2 0xc74 254 #define rOFDM0_AGCRSSITable 0xc78 255 #define rOFDM0_HTSTFAGC 0xc7c 256 257 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 258 #define rOFDM0_XATxAFE 0xc84 259 #define rOFDM0_XBTxIQImbalance 0xc88 260 #define rOFDM0_XBTxAFE 0xc8c 261 #define rOFDM0_XCTxIQImbalance 0xc90 262 #define rOFDM0_XCTxAFE 0xc94 263 #define rOFDM0_XDTxIQImbalance 0xc98 264 #define rOFDM0_XDTxAFE 0xc9c 265 266 #define rOFDM0_RxIQExtAnta 0xca0 267 #define rOFDM0_TxCoeff1 0xca4 268 #define rOFDM0_TxCoeff2 0xca8 269 #define rOFDM0_TxCoeff3 0xcac 270 #define rOFDM0_TxCoeff4 0xcb0 271 #define rOFDM0_TxCoeff5 0xcb4 272 #define rOFDM0_TxCoeff6 0xcb8 273 #define rOFDM0_RxHPParameter 0xce0 274 #define rOFDM0_TxPseudoNoiseWgt 0xce4 275 #define rOFDM0_FrameSync 0xcf0 276 #define rOFDM0_DFSReport 0xcf4 277 278 /* 279 * 7. PageD(0xD00) 280 * */ 281 #define rOFDM1_LSTF 0xd00 282 #define rOFDM1_TRxPathEnable 0xd04 283 284 #define rOFDM1_CFO 0xd08 /* No setting now */ 285 #define rOFDM1_CSI1 0xd10 286 #define rOFDM1_SBD 0xd14 287 #define rOFDM1_CSI2 0xd18 288 #define rOFDM1_CFOTracking 0xd2c 289 #define rOFDM1_TRxMesaure1 0xd34 290 #define rOFDM1_IntfDet 0xd3c 291 #define rOFDM1_PseudoNoiseStateAB 0xd50 292 #define rOFDM1_PseudoNoiseStateCD 0xd54 293 #define rOFDM1_RxPseudoNoiseWgt 0xd58 294 295 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 296 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 297 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 298 299 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 300 #define rOFDM_ShortCFOCD 0xdb0 301 #define rOFDM_LongCFOAB 0xdb4 302 #define rOFDM_LongCFOCD 0xdb8 303 #define rOFDM_TailCFOAB 0xdbc 304 #define rOFDM_TailCFOCD 0xdc0 305 #define rOFDM_PWMeasure1 0xdc4 306 #define rOFDM_PWMeasure2 0xdc8 307 #define rOFDM_BWReport 0xdcc 308 #define rOFDM_AGCReport 0xdd0 309 #define rOFDM_RxSNR 0xdd4 310 #define rOFDM_RxEVMCSI 0xdd8 311 #define rOFDM_SIGReport 0xddc 312 313 314 /* 315 * 8. PageE(0xE00) 316 * */ 317 #define rTxAGC_A_Rate18_06 0xe00 318 #define rTxAGC_A_Rate54_24 0xe04 319 #define rTxAGC_A_CCK1_Mcs32 0xe08 320 #define rTxAGC_A_Mcs03_Mcs00 0xe10 321 #define rTxAGC_A_Mcs07_Mcs04 0xe14 322 #define rTxAGC_A_Mcs11_Mcs08 0xe18 323 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 324 325 #define rFPGA0_IQK 0xe28 326 #define rTx_IQK_Tone_A 0xe30 327 #define rRx_IQK_Tone_A 0xe34 328 #define rTx_IQK_PI_A 0xe38 329 #define rRx_IQK_PI_A 0xe3c 330 331 #define rTx_IQK 0xe40 332 #define rRx_IQK 0xe44 333 #define rIQK_AGC_Pts 0xe48 334 #define rIQK_AGC_Rsp 0xe4c 335 #define rTx_IQK_Tone_B 0xe50 336 #define rRx_IQK_Tone_B 0xe54 337 #define rTx_IQK_PI_B 0xe58 338 #define rRx_IQK_PI_B 0xe5c 339 #define rIQK_AGC_Cont 0xe60 340 341 #define rBlue_Tooth 0xe6c 342 #define rRx_Wait_CCA 0xe70 343 #define rTx_CCK_RFON 0xe74 344 #define rTx_CCK_BBON 0xe78 345 #define rTx_OFDM_RFON 0xe7c 346 #define rTx_OFDM_BBON 0xe80 347 #define rTx_To_Rx 0xe84 348 #define rTx_To_Tx 0xe88 349 #define rRx_CCK 0xe8c 350 351 #define rTx_Power_Before_IQK_A 0xe94 352 #define rTx_Power_After_IQK_A 0xe9c 353 354 #define rRx_Power_Before_IQK_A 0xea0 355 #define rRx_Power_Before_IQK_A_2 0xea4 356 #define rRx_Power_After_IQK_A 0xea8 357 #define rRx_Power_After_IQK_A_2 0xeac 358 359 #define rTx_Power_Before_IQK_B 0xeb4 360 #define rTx_Power_After_IQK_B 0xebc 361 362 #define rRx_Power_Before_IQK_B 0xec0 363 #define rRx_Power_Before_IQK_B_2 0xec4 364 #define rRx_Power_After_IQK_B 0xec8 365 #define rRx_Power_After_IQK_B_2 0xecc 366 367 #define rRx_OFDM 0xed0 368 #define rRx_Wait_RIFS 0xed4 369 #define rRx_TO_Rx 0xed8 370 #define rStandby 0xedc 371 #define rSleep 0xee0 372 #define rPMPD_ANAEN 0xeec 373 374 /* 375 * 7. RF Register 0x00-0x2E (RF 8256) 376 * RF-0222D 0x00-3F 377 * 378 * Zebra1 */ 379 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 380 #define rZebra1_TRxEnable1 0x1 381 #define rZebra1_TRxEnable2 0x2 382 #define rZebra1_AGC 0x4 383 #define rZebra1_ChargePump 0x5 384 #define rZebra1_Channel 0x7 /* RF channel switch */ 385 386 /* #endif */ 387 #define rZebra1_TxGain 0x8 /* Useless now */ 388 #define rZebra1_TxLPF 0x9 389 #define rZebra1_RxLPF 0xb 390 #define rZebra1_RxHPFCorner 0xc 391 392 /* Zebra4 */ 393 #define rGlobalCtrl 0 /* Useless now */ 394 #define rRTL8256_TxLPF 19 395 #define rRTL8256_RxLPF 11 396 397 /* RTL8258 */ 398 #define rRTL8258_TxLPF 0x11 /* Useless now */ 399 #define rRTL8258_RxLPF 0x13 400 #define rRTL8258_RSSILPF 0xa 401 402 /* 403 * RL6052 Register definition 404 * */ 405 #define RF_AC 0x00 /* */ 406 407 #define RF_IQADJ_G1 0x01 /* */ 408 #define RF_IQADJ_G2 0x02 /* */ 409 #define RF_BS_PA_APSET_G1_G4 0x03 410 #define RF_BS_PA_APSET_G5_G8 0x04 411 #define RF_POW_TRSW 0x05 /* */ 412 413 #define RF_GAIN_RX 0x06 /* */ 414 #define RF_GAIN_TX 0x07 /* */ 415 416 #define RF_TXM_IDAC 0x08 /* */ 417 #define RF_IPA_G 0x09 /* */ 418 #define RF_TXBIAS_G 0x0A 419 #define RF_TXPA_AG 0x0B 420 #define RF_IPA_A 0x0C /* */ 421 #define RF_TXBIAS_A 0x0D 422 #define RF_BS_PA_APSET_G9_G11 0x0E 423 #define RF_BS_IQGEN 0x0F /* */ 424 425 #define RF_MODE1 0x10 /* */ 426 #define RF_MODE2 0x11 /* */ 427 428 #define RF_RX_AGC_HP 0x12 /* */ 429 #define RF_TX_AGC 0x13 /* */ 430 #define RF_BIAS 0x14 /* */ 431 #define RF_IPA 0x15 /* */ 432 #define RF_TXBIAS 0x16 433 #define RF_POW_ABILITY 0x17 /* */ 434 #define RF_MODE_AG 0x18 /* */ 435 #define rRfChannel 0x18 /* RF channel and BW switch */ 436 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 437 #define RF_TOP 0x19 /* */ 438 439 #define RF_RX_G1 0x1A /* */ 440 #define RF_RX_G2 0x1B /* */ 441 442 #define RF_RX_BB2 0x1C /* */ 443 #define RF_RX_BB1 0x1D /* */ 444 445 #define RF_RCK1 0x1E /* */ 446 #define RF_RCK2 0x1F /* */ 447 448 #define RF_TX_G1 0x20 /* */ 449 #define RF_TX_G2 0x21 /* */ 450 #define RF_TX_G3 0x22 /* */ 451 452 #define RF_TX_BB1 0x23 /* */ 453 454 #define RF_T_METER 0x24 /* */ 455 456 #define RF_SYN_G1 0x25 /* RF TX Power control */ 457 #define RF_SYN_G2 0x26 /* RF TX Power control */ 458 #define RF_SYN_G3 0x27 /* RF TX Power control */ 459 #define RF_SYN_G4 0x28 /* RF TX Power control */ 460 #define RF_SYN_G5 0x29 /* RF TX Power control */ 461 #define RF_SYN_G6 0x2A /* RF TX Power control */ 462 #define RF_SYN_G7 0x2B /* RF TX Power control */ 463 #define RF_SYN_G8 0x2C /* RF TX Power control */ 464 465 #define RF_RCK_OS 0x30 /* RF TX PA control */ 466 467 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 468 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 469 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 470 #define RF_TX_BIAS_A 0x35 471 #define RF_TX_BIAS_D 0x36 472 #define RF_LOBF_9 0x38 473 #define RF_RXRF_A3 0x3C /* */ 474 #define RF_TRSW 0x3F 475 476 #define RF_TXRF_A2 0x41 477 #define RF_T_METER_88E 0x42 478 #define RF_TXPA_G4 0x46 479 #define RF_TXPA_A4 0x4B 480 #define RF_0x52 0x52 481 #define RF_WE_LUT 0xEF 482 #define RF_S0S1 0xB0 483 484 /* 485 * Bit Mask 486 * 487 * 1. Page1(0x100) */ 488 #define bBBResetB 0x100 /* Useless now? */ 489 #define bGlobalResetB 0x200 490 #define bOFDMTxStart 0x4 491 #define bCCKTxStart 0x8 492 #define bCRC32Debug 0x100 493 #define bPMACLoopback 0x10 494 #define bTxLSIG 0xffffff 495 #define bOFDMTxRate 0xf 496 #define bOFDMTxReserved 0x10 497 #define bOFDMTxLength 0x1ffe0 498 #define bOFDMTxParity 0x20000 499 #define bTxHTSIG1 0xffffff 500 #define bTxHTMCSRate 0x7f 501 #define bTxHTBW 0x80 502 #define bTxHTLength 0xffff00 503 #define bTxHTSIG2 0xffffff 504 #define bTxHTSmoothing 0x1 505 #define bTxHTSounding 0x2 506 #define bTxHTReserved 0x4 507 #define bTxHTAggreation 0x8 508 #define bTxHTSTBC 0x30 509 #define bTxHTAdvanceCoding 0x40 510 #define bTxHTShortGI 0x80 511 #define bTxHTNumberHT_LTF 0x300 512 #define bTxHTCRC8 0x3fc00 513 #define bCounterReset 0x10000 514 #define bNumOfOFDMTx 0xffff 515 #define bNumOfCCKTx 0xffff0000 516 #define bTxIdleInterval 0xffff 517 #define bOFDMService 0xffff0000 518 #define bTxMACHeader 0xffffffff 519 #define bTxDataInit 0xff 520 #define bTxHTMode 0x100 521 #define bTxDataType 0x30000 522 #define bTxRandomSeed 0xffffffff 523 #define bCCKTxPreamble 0x1 524 #define bCCKTxSFD 0xffff0000 525 #define bCCKTxSIG 0xff 526 #define bCCKTxService 0xff00 527 #define bCCKLengthExt 0x8000 528 #define bCCKTxLength 0xffff0000 529 #define bCCKTxCRC16 0xffff 530 #define bCCKTxStatus 0x1 531 #define bOFDMTxStatus 0x2 532 533 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 534 #define RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0)) 535 536 /* 2. Page8(0x800) */ 537 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 538 #define bJapanMode 0x2 539 #define bCCKTxSC 0x30 540 #define bCCKEn 0x1000000 541 #define bOFDMEn 0x2000000 542 543 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 544 #define bOFDMTxDACPhase 0x40000 545 #define bXATxAGC 0x3f 546 547 #define bAntennaSelect 0x0300 548 549 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 550 #define bXCTxAGC 0xf000 551 #define bXDTxAGC 0xf0000 552 553 #define bPAStart 0xf0000000 /* Useless now */ 554 #define bTRStart 0x00f00000 555 #define bRFStart 0x0000f000 556 #define bBBStart 0x000000f0 557 #define bBBCCKStart 0x0000000f 558 #define bPAEnd 0xf /* Reg0x814 */ 559 #define bTREnd 0x0f000000 560 #define bRFEnd 0x000f0000 561 #define bCCAMask 0x000000f0 /* T2R */ 562 #define bR2RCCAMask 0x00000f00 563 #define bHSSI_R2TDelay 0xf8000000 564 #define bHSSI_T2RDelay 0xf80000 565 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 566 #define bIGFromCCK 0x200 567 #define bAGCAddress 0x3f 568 #define bRxHPTx 0x7000 569 #define bRxHPT2R 0x38000 570 #define bRxHPCCKIni 0xc0000 571 #define bAGCTxCode 0xc00000 572 #define bAGCRxCode 0x300000 573 574 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 575 #define b3WireAddressLength 0x400 576 577 #define b3WireRFPowerDown 0x1 /* Useless now 578 * #define bHWSISelect 0x8 */ 579 #define b5GPAPEPolarity 0x40000000 580 #define b2GPAPEPolarity 0x80000000 581 #define bRFSW_TxDefaultAnt 0x3 582 #define bRFSW_TxOptionAnt 0x30 583 #define bRFSW_RxDefaultAnt 0x300 584 #define bRFSW_RxOptionAnt 0x3000 585 #define bRFSI_3WireData 0x1 586 #define bRFSI_3WireClock 0x2 587 #define bRFSI_3WireLoad 0x4 588 #define bRFSI_3WireRW 0x8 589 #define bRFSI_3Wire 0xf 590 591 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 592 593 #define bRFSI_TRSW 0x20 /* Useless now */ 594 #define bRFSI_TRSWB 0x40 595 #define bRFSI_ANTSW 0x100 596 #define bRFSI_ANTSWB 0x200 597 #define bRFSI_PAPE 0x400 598 #define bRFSI_PAPE5G 0x800 599 #define bBandSelect 0x1 600 #define bHTSIG2_GI 0x80 601 #define bHTSIG2_Smoothing 0x01 602 #define bHTSIG2_Sounding 0x02 603 #define bHTSIG2_Aggreaton 0x08 604 #define bHTSIG2_STBC 0x30 605 #define bHTSIG2_AdvCoding 0x40 606 #define bHTSIG2_NumOfHTLTF 0x300 607 #define bHTSIG2_CRC8 0x3fc 608 #define bHTSIG1_MCS 0x7f 609 #define bHTSIG1_BandWidth 0x80 610 #define bHTSIG1_HTLength 0xffff 611 #define bLSIG_Rate 0xf 612 #define bLSIG_Reserved 0x10 613 #define bLSIG_Length 0x1fffe 614 #define bLSIG_Parity 0x20 615 #define bCCKRxPhase 0x4 616 617 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 618 619 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 620 621 #define bLSSIReadBackData 0xfffff /* T65 RF */ 622 623 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 624 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 625 #define bRegulator0Standby 0x1 626 #define bRegulatorPLLStandby 0x2 627 #define bRegulator1Standby 0x4 628 #define bPLLPowerUp 0x8 629 #define bDPLLPowerUp 0x10 630 #define bDA10PowerUp 0x20 631 #define bAD7PowerUp 0x200 632 #define bDA6PowerUp 0x2000 633 #define bXtalPowerUp 0x4000 634 #define b40MDClkPowerUP 0x8000 635 #define bDA6DebugMode 0x20000 636 #define bDA6Swing 0x380000 637 638 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 639 640 #define b80MClkDelay 0x18000000 /* Useless */ 641 #define bAFEWatchDogEnable 0x20000000 642 643 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 644 #define bXtalCap23 0x3 645 #define bXtalCap92x 0x0f000000 646 #define bXtalCap 0x0f000000 647 648 #define bIntDifClkEnable 0x400 /* Useless */ 649 #define bExtSigClkEnable 0x800 650 #define bBandgapMbiasPowerUp 0x10000 651 #define bAD11SHGain 0xc0000 652 #define bAD11InputRange 0x700000 653 #define bAD11OPCurrent 0x3800000 654 #define bIPathLoopback 0x4000000 655 #define bQPathLoopback 0x8000000 656 #define bAFELoopback 0x10000000 657 #define bDA10Swing 0x7e0 658 #define bDA10Reverse 0x800 659 #define bDAClkSource 0x1000 660 #define bAD7InputRange 0x6000 661 #define bAD7Gain 0x38000 662 #define bAD7OutputCMMode 0x40000 663 #define bAD7InputCMMode 0x380000 664 #define bAD7Current 0xc00000 665 #define bRegulatorAdjust 0x7000000 666 #define bAD11PowerUpAtTx 0x1 667 #define bDA10PSAtTx 0x10 668 #define bAD11PowerUpAtRx 0x100 669 #define bDA10PSAtRx 0x1000 670 #define bCCKRxAGCFormat 0x200 671 #define bPSDFFTSamplepPoint 0xc000 672 #define bPSDAverageNum 0x3000 673 #define bIQPathControl 0xc00 674 #define bPSDFreq 0x3ff 675 #define bPSDAntennaPath 0x30 676 #define bPSDIQSwitch 0x40 677 #define bPSDRxTrigger 0x400000 678 #define bPSDTxTrigger 0x80000000 679 #define bPSDSineToneScale 0x7f000000 680 #define bPSDReport 0xffff 681 682 /* 3. Page9(0x900) */ 683 #define bOFDMTxSC 0x30000000 /* Useless */ 684 #define bCCKTxOn 0x1 685 #define bOFDMTxOn 0x2 686 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 687 #define bDebugItem 0xff /* reset debug page and LWord */ 688 #define bAntL 0x10 689 #define bAntNonHT 0x100 690 #define bAntHT1 0x1000 691 #define bAntHT2 0x10000 692 #define bAntHT1S1 0x100000 693 #define bAntNonHTS1 0x1000000 694 695 /* 4. PageA(0xA00) */ 696 #define bCCKBBMode 0x3 /* Useless */ 697 #define bCCKTxPowerSaving 0x80 698 #define bCCKRxPowerSaving 0x40 699 700 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 701 702 #define bCCKScramble 0x8 /* Useless */ 703 #define bCCKAntDiversity 0x8000 704 #define bCCKCarrierRecovery 0x4000 705 #define bCCKTxRate 0x3000 706 #define bCCKDCCancel 0x0800 707 #define bCCKISICancel 0x0400 708 #define bCCKMatchFilter 0x0200 709 #define bCCKEqualizer 0x0100 710 #define bCCKPreambleDetect 0x800000 711 #define bCCKFastFalseCCA 0x400000 712 #define bCCKChEstStart 0x300000 713 #define bCCKCCACount 0x080000 714 #define bCCKcs_lim 0x070000 715 #define bCCKBistMode 0x80000000 716 #define bCCKCCAMask 0x40000000 717 #define bCCKTxDACPhase 0x4 718 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 719 #define bCCKr_cp_mode0 0x0100 720 #define bCCKTxDCOffset 0xf0 721 #define bCCKRxDCOffset 0xf 722 #define bCCKCCAMode 0xc000 723 #define bCCKFalseCS_lim 0x3f00 724 #define bCCKCS_ratio 0xc00000 725 #define bCCKCorgBit_sel 0x300000 726 #define bCCKPD_lim 0x0f0000 727 #define bCCKNewCCA 0x80000000 728 #define bCCKRxHPofIG 0x8000 729 #define bCCKRxIG 0x7f00 730 #define bCCKLNAPolarity 0x800000 731 #define bCCKRx1stGain 0x7f0000 732 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 733 #define bCCKRxAGCSatLevel 0x1f000000 734 #define bCCKRxAGCSatCount 0xe0 735 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 736 #define bCCKFixedRxAGC 0x8000 737 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 738 #define bCCKAntennaPolarity 0x2000 739 #define bCCKTxFilterType 0x0c00 740 #define bCCKRxAGCReportType 0x0300 741 #define bCCKRxDAGCEn 0x80000000 742 #define bCCKRxDAGCPeriod 0x20000000 743 #define bCCKRxDAGCSatLevel 0x1f000000 744 #define bCCKTimingRecovery 0x800000 745 #define bCCKTxC0 0x3f0000 746 #define bCCKTxC1 0x3f000000 747 #define bCCKTxC2 0x3f 748 #define bCCKTxC3 0x3f00 749 #define bCCKTxC4 0x3f0000 750 #define bCCKTxC5 0x3f000000 751 #define bCCKTxC6 0x3f 752 #define bCCKTxC7 0x3f00 753 #define bCCKDebugPort 0xff0000 754 #define bCCKDACDebug 0x0f000000 755 #define bCCKFalseAlarmEnable 0x8000 756 #define bCCKFalseAlarmRead 0x4000 757 #define bCCKTRSSI 0x7f 758 #define bCCKRxAGCReport 0xfe 759 #define bCCKRxReport_AntSel 0x80000000 760 #define bCCKRxReport_MFOff 0x40000000 761 #define bCCKRxRxReport_SQLoss 0x20000000 762 #define bCCKRxReport_Pktloss 0x10000000 763 #define bCCKRxReport_Lockedbit 0x08000000 764 #define bCCKRxReport_RateError 0x04000000 765 #define bCCKRxReport_RxRate 0x03000000 766 #define bCCKRxFACounterLower 0xff 767 #define bCCKRxFACounterUpper 0xff000000 768 #define bCCKRxHPAGCStart 0xe000 769 #define bCCKRxHPAGCFinal 0x1c00 770 #define bCCKRxFalseAlarmEnable 0x8000 771 #define bCCKFACounterFreeze 0x4000 772 #define bCCKTxPathSel 0x10000000 773 #define bCCKDefaultRxPath 0xc000000 774 #define bCCKOptionRxPath 0x3000000 775 776 /* 5. PageC(0xC00) */ 777 #define bNumOfSTF 0x3 /* Useless */ 778 #define bShift_L 0xc0 779 #define bGI_TH 0xc 780 #define bRxPathA 0x1 781 #define bRxPathB 0x2 782 #define bRxPathC 0x4 783 #define bRxPathD 0x8 784 #define bTxPathA 0x1 785 #define bTxPathB 0x2 786 #define bTxPathC 0x4 787 #define bTxPathD 0x8 788 #define bTRSSIFreq 0x200 789 #define bADCBackoff 0x3000 790 #define bDFIRBackoff 0xc000 791 #define bTRSSILatchPhase 0x10000 792 #define bRxIDCOffset 0xff 793 #define bRxQDCOffset 0xff00 794 #define bRxDFIRMode 0x1800000 795 #define bRxDCNFType 0xe000000 796 #define bRXIQImb_A 0x3ff 797 #define bRXIQImb_B 0xfc00 798 #define bRXIQImb_C 0x3f0000 799 #define bRXIQImb_D 0xffc00000 800 #define bDC_dc_Notch 0x60000 801 #define bRxNBINotch 0x1f000000 802 #define bPD_TH 0xf 803 #define bPD_TH_Opt2 0xc000 804 #define bPWED_TH 0x700 805 #define bIfMF_Win_L 0x800 806 #define bPD_Option 0x1000 807 #define bMF_Win_L 0xe000 808 #define bBW_Search_L 0x30000 809 #define bwin_enh_L 0xc0000 810 #define bBW_TH 0x700000 811 #define bED_TH2 0x3800000 812 #define bBW_option 0x4000000 813 #define bRatio_TH 0x18000000 814 #define bWindow_L 0xe0000000 815 #define bSBD_Option 0x1 816 #define bFrame_TH 0x1c 817 #define bFS_Option 0x60 818 #define bDC_Slope_check 0x80 819 #define bFGuard_Counter_DC_L 0xe00 820 #define bFrame_Weight_Short 0x7000 821 #define bSub_Tune 0xe00000 822 #define bFrame_DC_Length 0xe000000 823 #define bSBD_start_offset 0x30000000 824 #define bFrame_TH_2 0x7 825 #define bFrame_GI2_TH 0x38 826 #define bGI2_Sync_en 0x40 827 #define bSarch_Short_Early 0x300 828 #define bSarch_Short_Late 0xc00 829 #define bSarch_GI2_Late 0x70000 830 #define bCFOAntSum 0x1 831 #define bCFOAcc 0x2 832 #define bCFOStartOffset 0xc 833 #define bCFOLookBack 0x70 834 #define bCFOSumWeight 0x80 835 #define bDAGCEnable 0x10000 836 #define bTXIQImb_A 0x3ff 837 #define bTXIQImb_B 0xfc00 838 #define bTXIQImb_C 0x3f0000 839 #define bTXIQImb_D 0xffc00000 840 #define bTxIDCOffset 0xff 841 #define bTxQDCOffset 0xff00 842 #define bTxDFIRMode 0x10000 843 #define bTxPesudoNoiseOn 0x4000000 844 #define bTxPesudoNoise_A 0xff 845 #define bTxPesudoNoise_B 0xff00 846 #define bTxPesudoNoise_C 0xff0000 847 #define bTxPesudoNoise_D 0xff000000 848 #define bCCADropOption 0x20000 849 #define bCCADropThres 0xfff00000 850 #define bEDCCA_H 0xf 851 #define bEDCCA_L 0xf0 852 #define bLambda_ED 0x300 853 #define bRxInitialGain 0x7f 854 #define bRxAntDivEn 0x80 855 #define bRxAGCAddressForLNA 0x7f00 856 #define bRxHighPowerFlow 0x8000 857 #define bRxAGCFreezeThres 0xc0000 858 #define bRxFreezeStep_AGC1 0x300000 859 #define bRxFreezeStep_AGC2 0xc00000 860 #define bRxFreezeStep_AGC3 0x3000000 861 #define bRxFreezeStep_AGC0 0xc000000 862 #define bRxRssi_Cmp_En 0x10000000 863 #define bRxQuickAGCEn 0x20000000 864 #define bRxAGCFreezeThresMode 0x40000000 865 #define bRxOverFlowCheckType 0x80000000 866 #define bRxAGCShift 0x7f 867 #define bTRSW_Tri_Only 0x80 868 #define bPowerThres 0x300 869 #define bRxAGCEn 0x1 870 #define bRxAGCTogetherEn 0x2 871 #define bRxAGCMin 0x4 872 #define bRxHP_Ini 0x7 873 #define bRxHP_TRLNA 0x70 874 #define bRxHP_RSSI 0x700 875 #define bRxHP_BBP1 0x7000 876 #define bRxHP_BBP2 0x70000 877 #define bRxHP_BBP3 0x700000 878 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 879 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 880 #define bRxSettle_TRSW 0x7 881 #define bRxSettle_LNA 0x38 882 #define bRxSettle_RSSI 0x1c0 883 #define bRxSettle_BBP 0xe00 884 #define bRxSettle_RxHP 0x7000 885 #define bRxSettle_AntSW_RSSI 0x38000 886 #define bRxSettle_AntSW 0xc0000 887 #define bRxProcessTime_DAGC 0x300000 888 #define bRxSettle_HSSI 0x400000 889 #define bRxProcessTime_BBPPW 0x800000 890 #define bRxAntennaPowerShift 0x3000000 891 #define bRSSITableSelect 0xc000000 892 #define bRxHP_Final 0x7000000 893 #define bRxHTSettle_BBP 0x7 894 #define bRxHTSettle_HSSI 0x8 895 #define bRxHTSettle_RxHP 0x70 896 #define bRxHTSettle_BBPPW 0x80 897 #define bRxHTSettle_Idle 0x300 898 #define bRxHTSettle_Reserved 0x1c00 899 #define bRxHTRxHPEn 0x8000 900 #define bRxHTAGCFreezeThres 0x30000 901 #define bRxHTAGCTogetherEn 0x40000 902 #define bRxHTAGCMin 0x80000 903 #define bRxHTAGCEn 0x100000 904 #define bRxHTDAGCEn 0x200000 905 #define bRxHTRxHP_BBP 0x1c00000 906 #define bRxHTRxHP_Final 0xe0000000 907 #define bRxPWRatioTH 0x3 908 #define bRxPWRatioEn 0x4 909 #define bRxMFHold 0x3800 910 #define bRxPD_Delay_TH1 0x38 911 #define bRxPD_Delay_TH2 0x1c0 912 #define bRxPD_DC_COUNT_MAX 0x600 913 /* #define bRxMF_Hold 0x3800 */ 914 #define bRxPD_Delay_TH 0x8000 915 #define bRxProcess_Delay 0xf0000 916 #define bRxSearchrange_GI2_Early 0x700000 917 #define bRxFrame_Guard_Counter_L 0x3800000 918 #define bRxSGI_Guard_L 0xc000000 919 #define bRxSGI_Search_L 0x30000000 920 #define bRxSGI_TH 0xc0000000 921 #define bDFSCnt0 0xff 922 #define bDFSCnt1 0xff00 923 #define bDFSFlag 0xf0000 924 #define bMFWeightSum 0x300000 925 #define bMinIdxTH 0x7f000000 926 #define bDAFormat 0x40000 927 #define bTxChEmuEnable 0x01000000 928 #define bTRSWIsolation_A 0x7f 929 #define bTRSWIsolation_B 0x7f00 930 #define bTRSWIsolation_C 0x7f0000 931 #define bTRSWIsolation_D 0x7f000000 932 #define bExtLNAGain 0x7c00 933 934 /* 6. PageE(0xE00) */ 935 #define bSTBCEn 0x4 /* Useless */ 936 #define bAntennaMapping 0x10 937 #define bNss 0x20 938 #define bCFOAntSumD 0x200 939 #define bPHYCounterReset 0x8000000 940 #define bCFOReportGet 0x4000000 941 #define bOFDMContinueTx 0x10000000 942 #define bOFDMSingleCarrier 0x20000000 943 #define bOFDMSingleTone 0x40000000 944 /* #define bRxPath1 0x01 */ 945 /* #define bRxPath2 0x02 */ 946 /* #define bRxPath3 0x04 */ 947 /* #define bRxPath4 0x08 */ 948 /* #define bTxPath1 0x10 */ 949 /* #define bTxPath2 0x20 */ 950 #define bHTDetect 0x100 951 #define bCFOEn 0x10000 952 #define bCFOValue 0xfff00000 953 #define bSigTone_Re 0x3f 954 #define bSigTone_Im 0x7f00 955 #define bCounter_CCA 0xffff 956 #define bCounter_ParityFail 0xffff0000 957 #define bCounter_RateIllegal 0xffff 958 #define bCounter_CRC8Fail 0xffff0000 959 #define bCounter_MCSNoSupport 0xffff 960 #define bCounter_FastSync 0xffff 961 #define bShortCFO 0xfff 962 #define bShortCFOTLength 12 /* total */ 963 #define bShortCFOFLength 11 /* fraction */ 964 #define bLongCFO 0x7ff 965 #define bLongCFOTLength 11 966 #define bLongCFOFLength 11 967 #define bTailCFO 0x1fff 968 #define bTailCFOTLength 13 969 #define bTailCFOFLength 12 970 #define bmax_en_pwdB 0xffff 971 #define bCC_power_dB 0xffff0000 972 #define bnoise_pwdB 0xffff 973 #define bPowerMeasTLength 10 974 #define bPowerMeasFLength 3 975 #define bRx_HT_BW 0x1 976 #define bRxSC 0x6 977 #define bRx_HT 0x8 978 #define bNB_intf_det_on 0x1 979 #define bIntf_win_len_cfg 0x30 980 #define bNB_Intf_TH_cfg 0x1c0 981 #define bRFGain 0x3f 982 #define bTableSel 0x40 983 #define bTRSW 0x80 984 #define bRxSNR_A 0xff 985 #define bRxSNR_B 0xff00 986 #define bRxSNR_C 0xff0000 987 #define bRxSNR_D 0xff000000 988 #define bSNREVMTLength 8 989 #define bSNREVMFLength 1 990 #define bCSI1st 0xff 991 #define bCSI2nd 0xff00 992 #define bRxEVM1st 0xff0000 993 #define bRxEVM2nd 0xff000000 994 #define bSIGEVM 0xff 995 #define bPWDB 0xff00 996 #define bSGIEN 0x10000 997 998 #define bSFactorQAM1 0xf /* Useless */ 999 #define bSFactorQAM2 0xf0 1000 #define bSFactorQAM3 0xf00 1001 #define bSFactorQAM4 0xf000 1002 #define bSFactorQAM5 0xf0000 1003 #define bSFactorQAM6 0xf0000 1004 #define bSFactorQAM7 0xf00000 1005 #define bSFactorQAM8 0xf000000 1006 #define bSFactorQAM9 0xf0000000 1007 #define bCSIScheme 0x100000 1008 1009 #define bNoiseLvlTopSet 0x3 /* Useless */ 1010 #define bChSmooth 0x4 1011 #define bChSmoothCfg1 0x38 1012 #define bChSmoothCfg2 0x1c0 1013 #define bChSmoothCfg3 0xe00 1014 #define bChSmoothCfg4 0x7000 1015 #define bMRCMode 0x800000 1016 #define bTHEVMCfg 0x7000000 1017 1018 #define bLoopFitType 0x1 /* Useless */ 1019 #define bUpdCFO 0x40 1020 #define bUpdCFOOffData 0x80 1021 #define bAdvUpdCFO 0x100 1022 #define bAdvTimeCtrl 0x800 1023 #define bUpdClko 0x1000 1024 #define bFC 0x6000 1025 #define bTrackingMode 0x8000 1026 #define bPhCmpEnable 0x10000 1027 #define bUpdClkoLTF 0x20000 1028 #define bComChCFO 0x40000 1029 #define bCSIEstiMode 0x80000 1030 #define bAdvUpdEqz 0x100000 1031 #define bUChCfg 0x7000000 1032 #define bUpdEqz 0x8000000 1033 1034 /* Rx Pseduo noise */ 1035 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1036 #define bRxPesudoNoise_A 0xff 1037 #define bRxPesudoNoise_B 0xff00 1038 #define bRxPesudoNoise_C 0xff0000 1039 #define bRxPesudoNoise_D 0xff000000 1040 #define bPesudoNoiseState_A 0xffff 1041 #define bPesudoNoiseState_B 0xffff0000 1042 #define bPesudoNoiseState_C 0xffff 1043 #define bPesudoNoiseState_D 0xffff0000 1044 1045 /* 7. RF Register 1046 * Zebra1 */ 1047 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1048 #define bZebra1_TRxControl 0xc00 1049 #define bZebra1_TRxGainSetting 0x07f 1050 #define bZebra1_RxCorner 0xc00 1051 #define bZebra1_TxChargePump 0x38 1052 #define bZebra1_RxChargePump 0x7 1053 #define bZebra1_ChannelNum 0xf80 1054 #define bZebra1_TxLPFBW 0x400 1055 #define bZebra1_RxLPFBW 0x600 1056 1057 /* Zebra4 */ 1058 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1059 #define bRTL8256RegModeCtrl0 0x40 1060 #define bRTL8256_TxLPFBW 0x18 1061 #define bRTL8256_RxLPFBW 0x600 1062 1063 /* RTL8258 */ 1064 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1065 #define bRTL8258_RxLPFBW 0xc00 1066 #define bRTL8258_RSSILPFBW 0xc0 1067 1068 1069 /* 1070 * Other Definition 1071 * */ 1072 1073 /* byte endable for sb_write */ 1074 #define bByte0 0x1 /* Useless */ 1075 #define bByte1 0x2 1076 #define bByte2 0x4 1077 #define bByte3 0x8 1078 #define bWord0 0x3 1079 #define bWord1 0xc 1080 #define bDWord 0xf 1081 1082 /* for PutRegsetting & GetRegSetting BitMask */ 1083 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1084 #define bMaskByte1 0xff00 1085 #define bMaskByte2 0xff0000 1086 #define bMaskByte3 0xff000000 1087 #define bMaskHWord 0xffff0000 1088 #define bMaskLWord 0x0000ffff 1089 #define bMaskDWord 0xffffffff 1090 #define bMaskH3Bytes 0xffffff00 1091 #define bMask12Bits 0xfff 1092 #define bMaskH4Bits 0xf0000000 1093 #define bMaskOFDM_D 0xffc00000 1094 #define bMaskCCK 0x3f3f3f3f 1095 1096 1097 #define bEnable 0x1 /* Useless */ 1098 #define bDisable 0x0 1099 1100 #define LeftAntenna 0x0 /* Useless */ 1101 #define RightAntenna 0x1 1102 1103 #define tCheckTxStatus 500 /* 500ms // Useless */ 1104 #define tUpdateRxCounter 100 /* 100ms */ 1105 1106 #define rateCCK 0 /* Useless */ 1107 #define rateOFDM 1 1108 #define rateHT 2 1109 1110 /* define Register-End */ 1111 #define bPMAC_End 0x1ff /* Useless */ 1112 #define bFPGAPHY0_End 0x8ff 1113 #define bFPGAPHY1_End 0x9ff 1114 #define bCCKPHY0_End 0xaff 1115 #define bOFDMPHY0_End 0xcff 1116 #define bOFDMPHY1_End 0xdff 1117 1118 /* define max debug item in each debug page 1119 * #define bMaxItem_FPGA_PHY0 0x9 1120 * #define bMaxItem_FPGA_PHY1 0x3 1121 * #define bMaxItem_PHY_11B 0x16 1122 * #define bMaxItem_OFDM_PHY0 0x29 1123 * #define bMaxItem_OFDM_PHY1 0x0 */ 1124 1125 #define bPMACControl 0x0 /* Useless */ 1126 #define bWMACControl 0x1 1127 #define bWNICControl 0x2 1128 1129 #define PathA 0x0 /* Useless */ 1130 #define PathB 0x1 1131 #define PathC 0x2 1132 #define PathD 0x3 1133 1134 #endif 1135