1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The full GNU General Public License is included in this distribution in the 15*4882a593Smuzhiyun * file called LICENSE. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Contact Information: 18*4882a593Smuzhiyun * wlanfae <wlanfae@realtek.com> 19*4882a593Smuzhiyun * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20*4882a593Smuzhiyun * Hsinchu 300, Taiwan. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Larry Finger <Larry.Finger@lwfinger.net> 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun *****************************************************************************/ 25*4882a593Smuzhiyun /************************************************************* 26*4882a593Smuzhiyun * File Name: odm_reg.h 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * Description: 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * This file is for general register definition. 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun ************************************************************/ 34*4882a593Smuzhiyun #ifndef __HAL_ODM_REG_H__ 35*4882a593Smuzhiyun #define __HAL_ODM_REG_H__ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /*@ 38*4882a593Smuzhiyun * Register Definition 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* @MAC REG */ 43*4882a593Smuzhiyun #define ODM_BB_RESET 0x002 44*4882a593Smuzhiyun #define ODM_DUMMY 0x4fe 45*4882a593Smuzhiyun #define RF_T_METER_OLD 0x24 46*4882a593Smuzhiyun #define RF_T_METER_NEW 0x42 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define ODM_EDCA_VO_PARAM 0x500 49*4882a593Smuzhiyun #define ODM_EDCA_VI_PARAM 0x504 50*4882a593Smuzhiyun #define ODM_EDCA_BE_PARAM 0x508 51*4882a593Smuzhiyun #define ODM_EDCA_BK_PARAM 0x50C 52*4882a593Smuzhiyun #define ODM_TXPAUSE 0x522 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* @LTE_COEX */ 55*4882a593Smuzhiyun #define REG_LTECOEX_CTRL 0x07C0 56*4882a593Smuzhiyun #define REG_LTECOEX_WRITE_DATA 0x07C4 57*4882a593Smuzhiyun #define REG_LTECOEX_READ_DATA 0x07C8 58*4882a593Smuzhiyun #define REG_LTECOEX_PATH_CONTROL 0x70 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* @BB REG */ 61*4882a593Smuzhiyun #define ODM_FPGA_PHY0_PAGE8 0x800 62*4882a593Smuzhiyun #define ODM_PSD_SETTING 0x808 63*4882a593Smuzhiyun #define ODM_AFE_SETTING 0x818 64*4882a593Smuzhiyun #define ODM_TXAGC_B_6_18 0x830 65*4882a593Smuzhiyun #define ODM_TXAGC_B_24_54 0x834 66*4882a593Smuzhiyun #define ODM_TXAGC_B_MCS32_5 0x838 67*4882a593Smuzhiyun #define ODM_TXAGC_B_MCS0_MCS3 0x83c 68*4882a593Smuzhiyun #define ODM_TXAGC_B_MCS4_MCS7 0x848 69*4882a593Smuzhiyun #define ODM_TXAGC_B_MCS8_MCS11 0x84c 70*4882a593Smuzhiyun #define ODM_ANALOG_REGISTER 0x85c 71*4882a593Smuzhiyun #define ODM_RF_INTERFACE_OUTPUT 0x860 72*4882a593Smuzhiyun #define ODM_TXAGC_B_MCS12_MCS15 0x868 73*4882a593Smuzhiyun #define ODM_TXAGC_B_11_A_2_11 0x86c 74*4882a593Smuzhiyun #define ODM_AD_DA_LSB_MASK 0x874 75*4882a593Smuzhiyun #define ODM_ENABLE_3_WIRE 0x88c 76*4882a593Smuzhiyun #define ODM_PSD_REPORT 0x8b4 77*4882a593Smuzhiyun #define ODM_R_ANT_SELECT 0x90c 78*4882a593Smuzhiyun #define ODM_CCK_ANT_SELECT 0xa07 79*4882a593Smuzhiyun #define ODM_CCK_PD_THRESH 0xa0a 80*4882a593Smuzhiyun #define ODM_CCK_RF_REG1 0xa11 81*4882a593Smuzhiyun #define ODM_CCK_MATCH_FILTER 0xa20 82*4882a593Smuzhiyun #define ODM_CCK_RAKE_MAC 0xa2e 83*4882a593Smuzhiyun #define ODM_CCK_CNT_RESET 0xa2d 84*4882a593Smuzhiyun #define ODM_CCK_TX_DIVERSITY 0xa2f 85*4882a593Smuzhiyun #define ODM_CCK_FA_CNT_MSB 0xa5b 86*4882a593Smuzhiyun #define ODM_CCK_FA_CNT_LSB 0xa5c 87*4882a593Smuzhiyun #define ODM_CCK_NEW_FUNCTION 0xa75 88*4882a593Smuzhiyun #define ODM_OFDM_PHY0_PAGE_C 0xc00 89*4882a593Smuzhiyun #define ODM_OFDM_RX_ANT 0xc04 90*4882a593Smuzhiyun #define ODM_R_A_RXIQI 0xc14 91*4882a593Smuzhiyun #define ODM_R_A_AGC_CORE1 0xc50 92*4882a593Smuzhiyun #define ODM_R_A_AGC_CORE2 0xc54 93*4882a593Smuzhiyun #define ODM_R_B_AGC_CORE1 0xc58 94*4882a593Smuzhiyun #define ODM_R_AGC_PAR 0xc70 95*4882a593Smuzhiyun #define ODM_R_HTSTF_AGC_PAR 0xc7c 96*4882a593Smuzhiyun #define ODM_TX_PWR_TRAINING_A 0xc90 97*4882a593Smuzhiyun #define ODM_TX_PWR_TRAINING_B 0xc98 98*4882a593Smuzhiyun #define ODM_OFDM_FA_CNT1 0xcf0 99*4882a593Smuzhiyun #define ODM_OFDM_PHY0_PAGE_D 0xd00 100*4882a593Smuzhiyun #define ODM_OFDM_FA_CNT2 0xda0 101*4882a593Smuzhiyun #define ODM_OFDM_FA_CNT3 0xda4 102*4882a593Smuzhiyun #define ODM_OFDM_FA_CNT4 0xda8 103*4882a593Smuzhiyun #define ODM_TXAGC_A_6_18 0xe00 104*4882a593Smuzhiyun #define ODM_TXAGC_A_24_54 0xe04 105*4882a593Smuzhiyun #define ODM_TXAGC_A_1_MCS32 0xe08 106*4882a593Smuzhiyun #define ODM_TXAGC_A_MCS0_MCS3 0xe10 107*4882a593Smuzhiyun #define ODM_TXAGC_A_MCS4_MCS7 0xe14 108*4882a593Smuzhiyun #define ODM_TXAGC_A_MCS8_MCS11 0xe18 109*4882a593Smuzhiyun #define ODM_TXAGC_A_MCS12_MCS15 0xe1c 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* RF REG */ 112*4882a593Smuzhiyun #define ODM_GAIN_SETTING 0x00 113*4882a593Smuzhiyun #define ODM_CHANNEL 0x18 114*4882a593Smuzhiyun #define ODM_RF_T_METER 0x24 115*4882a593Smuzhiyun #define ODM_RF_T_METER_92D 0x42 116*4882a593Smuzhiyun #define ODM_RF_T_METER_88E 0x42 117*4882a593Smuzhiyun #define ODM_RF_T_METER_92E 0x42 118*4882a593Smuzhiyun #define ODM_RF_T_METER_8812 0x42 119*4882a593Smuzhiyun #define REG_RF_TX_GAIN_OFFSET 0x55 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* @ant Detect Reg */ 122*4882a593Smuzhiyun #define ODM_DPDT 0x300 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* PSD Init */ 125*4882a593Smuzhiyun #define ODM_PSDREG 0x808 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* @92D path Div */ 128*4882a593Smuzhiyun #define PATHDIV_REG 0xB30 129*4882a593Smuzhiyun #define PATHDIV_TRI 0xBA0 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /*@ 133*4882a593Smuzhiyun * Bitmap Definition 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 136*4882a593Smuzhiyun /* TX AGC */ 137*4882a593Smuzhiyun #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20 138*4882a593Smuzhiyun #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24 139*4882a593Smuzhiyun #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28 140*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c 141*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30 142*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34 143*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38 144*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c 145*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40 146*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44 147*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48 148*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c 149*4882a593Smuzhiyun #if defined(CONFIG_WLAN_HAL_8814AE) 150*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8 151*4882a593Smuzhiyun #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc 152*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0 153*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4 154*4882a593Smuzhiyun #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8 155*4882a593Smuzhiyun #endif 156*4882a593Smuzhiyun #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20 157*4882a593Smuzhiyun #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24 158*4882a593Smuzhiyun #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28 159*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c 160*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30 161*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34 162*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38 163*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c 164*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40 165*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44 166*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48 167*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c 168*4882a593Smuzhiyun #if defined(CONFIG_WLAN_HAL_8814AE) 169*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8 170*4882a593Smuzhiyun #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc 171*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0 172*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4 173*4882a593Smuzhiyun #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8 174*4882a593Smuzhiyun #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820 175*4882a593Smuzhiyun #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824 176*4882a593Smuzhiyun #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828 177*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c 178*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830 179*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834 180*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838 181*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c 182*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840 183*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844 184*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848 185*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c 186*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8 187*4882a593Smuzhiyun #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc 188*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0 189*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4 190*4882a593Smuzhiyun #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8 191*4882a593Smuzhiyun #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20 192*4882a593Smuzhiyun #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24 193*4882a593Smuzhiyun #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28 194*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c 195*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30 196*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34 197*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38 198*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c 199*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40 200*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44 201*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48 202*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c 203*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8 204*4882a593Smuzhiyun #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc 205*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0 206*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4 207*4882a593Smuzhiyun #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8 208*4882a593Smuzhiyun #endif 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define is_tx_agc_byte0_jaguar 0xff 211*4882a593Smuzhiyun #define is_tx_agc_byte1_jaguar 0xff00 212*4882a593Smuzhiyun #define is_tx_agc_byte2_jaguar 0xff0000 213*4882a593Smuzhiyun #define is_tx_agc_byte3_jaguar 0xff000000 214*4882a593Smuzhiyun #if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\ 215*4882a593Smuzhiyun defined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE) ||\ 216*4882a593Smuzhiyun defined(CONFIG_WLAN_HAL_8197G) 217*4882a593Smuzhiyun #define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3 0x3a00 218*4882a593Smuzhiyun #define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3 0x3a04 219*4882a593Smuzhiyun #define REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3 0x3a08 220*4882a593Smuzhiyun #define REG_TX_AGC_MCS3_0_JAGUAR3 0x3a0c 221*4882a593Smuzhiyun #define REG_TX_AGC_MCS7_4_JAGUAR3 0x3a10 222*4882a593Smuzhiyun #define REG_TX_AGC_MCS11_8_JAGUAR3 0x3a14 223*4882a593Smuzhiyun #define REG_TX_AGC_MCS15_12_JAGUAR3 0x3a18 224*4882a593Smuzhiyun #define REG_TX_AGC_MCS19_16_JAGUAR3 0x3a1c 225*4882a593Smuzhiyun #define REG_TX_AGC_MCS23_20_JAGUAR3 0x3a20 226*4882a593Smuzhiyun #define REG_TX_AGC_MCS27_24_JAGUAR3 0x3a24 227*4882a593Smuzhiyun #define REG_TX_AGC_MCS31_28_JAGUAR3 0x3a28 228*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3 0x3a2c 229*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3 0x3a30 230*4882a593Smuzhiyun #define REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3 0x3a34 231*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3 0x3a38 232*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3 0x3a3c 233*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3 0x3a40 234*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3 0x3a44 235*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3 0x3a48 236*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3 0x3a4c 237*4882a593Smuzhiyun #define REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3 0x3a50 238*4882a593Smuzhiyun #endif 239*4882a593Smuzhiyun #endif 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #define BIT_FA_RESET BIT(0) 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun #endif 244