1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDM_LNA_SAT_H__ 27 #define __PHYDM_LNA_SAT_H__ 28 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 29 /* @1 ============================================================ 30 * 1 Definition 31 * 1 ============================================================ 32 */ 33 34 #define LNA_SAT_VERSION "1.1" 35 36 /*@LNA saturation check*/ 37 #define OFDM_AGC_TAB_0 0 38 #define OFDM_AGC_TAB_2 2 39 40 #define DIFF_RSSI_TO_IGI 10 41 #define ONE_SEC_MS 1000 42 43 #define LNA_CHK_PERIOD 100 /*@ms*/ 44 #define LNA_CHK_CNT 10 /*@checks per callback*/ 45 #define LNA_CHK_DUTY_CYCLE 5 /*@percentage*/ 46 47 #define DELTA_STD 2 48 #define DELTA_MEAN 2 49 #define SNR_STATISTIC_SHIFT 8 50 #define SNR_RPT_MAX 256 51 52 /* @1 ============================================================ 53 * 1 enumrate 54 * 1 ============================================================ 55 */ 56 57 enum lna_sat_timer_state { 58 INIT_LNA_SAT_CHK_TIMMER, 59 CANCEL_LNA_SAT_CHK_TIMMER, 60 RELEASE_LNA_SAT_CHK_TIMMER 61 }; 62 63 #ifdef PHYDM_LNA_SAT_CHK_TYPE2 64 enum lna_sat_chk_type2_status { 65 ORI_TABLE_MONITOR, 66 ORI_TABLE_TRAINING, 67 SAT_TABLE_MONITOR, 68 SAT_TABLE_TRAINING, 69 SAT_TABLE_TRY_FAIL, 70 ORI_TABLE_TRY_FAIL 71 }; 72 73 #endif 74 75 enum lna_sat_type { 76 LNA_SAT_WITH_PEAK_DET = 1, /*type1*/ 77 LNA_SAT_WITH_TRAIN = 2, /*type2*/ 78 }; 79 80 #ifdef PHYDM_HW_SWITCH_AGC_TAB 81 enum lna_pd_th_level { 82 LNA_PD_TH_LEVEL0 = 0, 83 LNA_PD_TH_LEVEL1 = 1, 84 LNA_PD_TH_LEVEL2 = 2, 85 LNA_PD_TH_LEVEL3 = 3 86 }; 87 88 enum agc_tab_switch_state { 89 AGC_SWH_IDLE, 90 AGC_SWH_CCK, 91 AGC_SWH_OFDM 92 }; 93 #endif 94 95 /* @1 ============================================================ 96 * 1 structure 97 * 1 ============================================================ 98 */ 99 100 struct phydm_lna_sat_t { 101 #ifdef PHYDM_LNA_SAT_CHK_TYPE1 102 u8 chk_cnt; 103 u8 chk_duty_cycle; 104 u32 chk_period;/*@ms*/ 105 boolean is_disable_lna_sat_chk; 106 boolean dis_agc_table_swh; 107 #endif 108 #ifdef PHYDM_LNA_SAT_CHK_TYPE2 109 u8 force_traget_macid; 110 u32 snr_var_thd; 111 u32 delta_snr_mean; 112 u16 ori_table_try_fail_times; 113 u16 cnt_lower_snr_statistic; 114 u16 sat_table_monitor_times; 115 u16 force_change_period; 116 u8 is_snr_detail_en; 117 u8 is_force_lna_sat_table; 118 u8 lwr_snr_ratio_bit_shift; 119 u8 cnt_snr_statistic; 120 u16 snr_statistic_sqr[SNR_RPT_MAX]; 121 u8 snr_statistic[SNR_RPT_MAX]; 122 u8 is_sm_done; 123 u8 is_snr_done; 124 u32 cur_snr_var; 125 u8 total_bit_shift; 126 u8 total_cnt_snr; 127 u32 cur_snr_mean; 128 u8 cur_snr_var0; 129 u32 cur_lower_snr_mean; 130 u32 pre_snr_mean; 131 u32 pre_snr_var; 132 u32 pre_lower_snr_mean; 133 u8 nxt_state; 134 u8 pre_state; 135 #endif 136 enum lna_sat_type lna_sat_type; 137 u32 sat_cnt_acc_patha; 138 u32 sat_cnt_acc_pathb; 139 #ifdef PHYDM_IC_ABOVE_3SS 140 u32 sat_cnt_acc_pathc; 141 #endif 142 #ifdef PHYDM_IC_ABOVE_4SS 143 u32 sat_cnt_acc_pathd; 144 #endif 145 u32 check_time; 146 boolean pre_sat_status; 147 boolean cur_sat_status; 148 #ifdef PHYDM_HW_SWITCH_AGC_TAB 149 boolean hw_swh_tab_on; 150 enum odm_rf_band cur_rf_band; 151 #endif 152 struct phydm_timer_list phydm_lna_sat_chk_timer; 153 u32 cur_timer_check_cnt; 154 u32 pre_timer_check_cnt; 155 }; 156 157 /* @1 ============================================================ 158 * 1 function prototype 159 * 1 ============================================================ 160 */ 161 void phydm_lna_sat_chk_init(void *dm_void); 162 163 u8 phydm_get_ofdm_agc_tab(void *dm_void); 164 165 void phydm_lna_sat_chk(void *dm_void); 166 167 void phydm_lna_sat_chk_timers(void *dm_void, u8 state); 168 169 #ifdef PHYDM_LNA_SAT_CHK_TYPE1 170 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) 171 void phydm_lna_sat_chk_bb_init(void *dm_void); 172 173 void phydm_set_ofdm_agc_tab_path(void *dm_void, 174 u8 tab_sel, enum rf_path path); 175 176 u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path); 177 #endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/ 178 #endif 179 180 #ifdef PHYDM_LNA_SAT_CHK_TYPE2 181 void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr); 182 #endif 183 184 void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used, 185 char *output, u32 *_out_len); 186 187 void phydm_lna_sat_chk_watchdog(void *dm_void); 188 189 void phydm_lna_sat_check_init(void *dm_void); 190 191 #ifdef PHYDM_HW_SWITCH_AGC_TAB 192 void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used, 193 char *output, u32 *_out_len); 194 #endif 195 #endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/ 196 #endif 197