1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 const u16 phy_rate_table[] = {
34 /*@20M*/
35 1, 2, 5, 11,
36 6, 9, 12, 18, 24, 36, 48, 54,
37 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
38 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
39 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
40 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
41 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
42 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
43 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
44 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
45 };
46
phydm_traffic_load_decision(void * dm_void)47 void phydm_traffic_load_decision(void *dm_void)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 u8 shift = 0;
51
52 /*@---TP & Trafic-load calculation---*/
53
54 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
55 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
56
57 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
58 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
59
60 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
61 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
62 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
63 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
64
65 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
66 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
67 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
68
69 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
70 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
71
72 dm->total_tp = dm->tx_tp + dm->rx_tp;
73
74 /*@[Calculate TX/RX state]*/
75 if (dm->tx_tp > (dm->rx_tp << 1))
76 dm->txrx_state_all = TX_STATE;
77 else if (dm->rx_tp > (dm->tx_tp << 1))
78 dm->txrx_state_all = RX_STATE;
79 else
80 dm->txrx_state_all = BI_DIRECTION_STATE;
81
82 /*@[Traffic load decision]*/
83 dm->pre_traffic_load = dm->traffic_load;
84
85 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
86 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
87 dm->traffic_load = TRAFFIC_HIGH;
88 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
89 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
90 dm->traffic_load = TRAFFIC_MID;
91 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
92 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
93 dm->traffic_load = TRAFFIC_LOW;
94 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
95 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
96 dm->traffic_load = TRAFFIC_ULTRA_LOW;
97 } else {
98 dm->traffic_load = TRAFFIC_NO_TP;
99 }
100
101 /*@[Calculate consecutive idlel time]*/
102 if (dm->traffic_load == 0)
103 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
104 else
105 dm->consecutive_idlel_time = 0;
106
107 #if 0
108 PHYDM_DBG(dm, DBG_COMMON_FLOW,
109 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
110 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
111 dm->last_rx_ok_cnt);
112
113 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
114 dm->rx_tp);
115 #endif
116 }
117
phydm_cck_new_agc_chk(struct dm_struct * dm)118 void phydm_cck_new_agc_chk(struct dm_struct *dm)
119 {
120 u32 new_agc_addr = 0x0;
121
122 dm->cck_new_agc = false;
123 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
124 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
125 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
126 RTL8721D_SUPPORT || RTL8710C_SUPPORT)
127 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
128 ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
129 ODM_RTL8721D | ODM_RTL8710C)) {
130 new_agc_addr = R_0xa9c;
131 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
132 ODM_RTL8814B | ODM_RTL8197G | ODM_RTL8814C)) {
133 new_agc_addr = R_0x1a9c;
134 }
135
136 /*@1: new agc 0: old agc*/
137 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
138 #endif
139 #if (RTL8723F_SUPPORT)
140 if (dm->support_ic_type & (ODM_RTL8723F))
141 dm->cck_new_agc = true;
142 #endif
143 }
144
145 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)146 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
147 {
148 boolean report_type = 0;
149 #if (RTL8192E_SUPPORT)
150 u32 value_824, value_82c;
151 #endif
152
153 #if (RTL8192E_SUPPORT)
154 if (dm->support_ic_type & (ODM_RTL8192E)) {
155 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
156 * should be equal or CCK RSSI report may be incorrect
157 */
158 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
159 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
160
161 if (value_824 != value_82c)
162 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
163 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
164 report_type = (boolean)value_824;
165 }
166 #endif
167
168 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
169 if (dm->support_ic_type &
170 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
171 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
172
173 if (report_type != 1)
174 pr_debug("[Warning] CCK should be 4bit LNA\n");
175 }
176 #endif
177
178 #if (RTL8821C_SUPPORT)
179 if (dm->support_ic_type & ODM_RTL8821C) {
180 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
181 report_type = 1;
182 }
183 #endif
184
185 dm->cck_agc_report_type = report_type;
186
187 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
188 dm->cck_agc_report_type);
189 }
190
phydm_init_cck_setting(struct dm_struct * dm)191 void phydm_init_cck_setting(struct dm_struct *dm)
192 {
193 u32 reg_tmp = 0;
194 u32 mask_tmp = 0;
195
196 phydm_cck_new_agc_chk(dm);
197
198 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
199 return;
200
201 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
202 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
203 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
204
205 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
206
207 phydm_config_cck_rx_antenna_init(dm);
208
209 if (dm->support_ic_type & ODM_RTL8192F)
210 phydm_config_cck_rx_path(dm, BB_PATH_AB);
211 else if (dm->valid_path_set == BB_PATH_A)
212 phydm_config_cck_rx_path(dm, BB_PATH_A);
213 else if (dm->valid_path_set == BB_PATH_B)
214 phydm_config_cck_rx_path(dm, BB_PATH_B);
215
216 phydm_cck_lna_bit_num_chk(dm);
217 phydm_get_cck_rssi_table_from_reg(dm);
218 }
219
220 #ifdef CONFIG_RFE_BY_HW_INFO
phydm_init_hw_info_by_rfe(struct dm_struct * dm)221 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
222 {
223 #if (RTL8821C_SUPPORT)
224 if (dm->support_ic_type & ODM_RTL8821C)
225 phydm_init_hw_info_by_rfe_type_8821c(dm);
226 #endif
227 #if (RTL8197F_SUPPORT)
228 if (dm->support_ic_type & ODM_RTL8197F)
229 phydm_init_hw_info_by_rfe_type_8197f(dm);
230 #endif
231 #if (RTL8197G_SUPPORT)
232 if (dm->support_ic_type & ODM_RTL8197G)
233 phydm_init_hw_info_by_rfe_type_8197g(dm);
234 #endif
235 }
236 #endif
237
phydm_common_info_self_init(struct dm_struct * dm)238 void phydm_common_info_self_init(struct dm_struct *dm)
239 {
240 u32 reg_tmp = 0;
241 u32 mask_tmp = 0;
242
243 dm->run_in_drv_fw = RUN_IN_DRIVER;
244
245 /*@BB IP Generation*/
246 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
247 dm->ic_ip_series = PHYDM_IC_JGR3;
248 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
249 dm->ic_ip_series = PHYDM_IC_AC;
250 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
251 dm->ic_ip_series = PHYDM_IC_N;
252
253 /*@BB phy-status Generation*/
254 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
255 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
256 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
257 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
258 else
259 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
260
261 phydm_init_cck_setting(dm);
262
263 reg_tmp = ODM_REG(BB_RX_PATH, dm);
264 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
265 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
266 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
267 dm->is_net_closed = &dm->BOOLEAN_temp;
268
269 phydm_init_debug_setting(dm);
270 #endif
271 phydm_init_soft_ml_setting(dm);
272
273 dm->phydm_sys_up_time = 0;
274
275 if (dm->support_ic_type & ODM_IC_1SS)
276 dm->num_rf_path = 1;
277 else if (dm->support_ic_type & ODM_IC_2SS)
278 dm->num_rf_path = 2;
279 #if 0
280 /* @RTK do not has IC which is equipped with 3 RF paths,
281 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
282 */
283 else if (dm->support_ic_type & ODM_IC_3SS)
284 dm->num_rf_path = 3;
285 #endif
286 else if (dm->support_ic_type & ODM_IC_4SS)
287 dm->num_rf_path = 4;
288 else
289 dm->num_rf_path = 1;
290
291 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
292
293 dm->tx_rate = 0xFF;
294 dm->rssi_min_by_path = 0xFF;
295
296 dm->number_linked_client = 0;
297 dm->pre_number_linked_client = 0;
298 dm->number_active_client = 0;
299 dm->pre_number_active_client = 0;
300
301 dm->last_tx_ok_cnt = 0;
302 dm->last_rx_ok_cnt = 0;
303 dm->tx_tp = 0;
304 dm->rx_tp = 0;
305 dm->total_tp = 0;
306 dm->traffic_load = TRAFFIC_LOW;
307
308 dm->nbi_set_result = 0;
309 dm->is_init_hw_info_by_rfe = false;
310 dm->pre_dbg_priority = DBGPORT_RELEASE;
311 dm->tp_active_th = 5;
312 dm->disable_phydm_watchdog = 0;
313
314 dm->u8_dummy = 0xf;
315 dm->u16_dummy = 0xffff;
316 dm->u32_dummy = 0xffffffff;
317 #if (RTL8814B_SUPPORT)
318 /*@------------For spur detection Default Mode------------@*/
319 dm->dsde_sel = DET_CSI;
320 dm->csi_wgt = 4;
321 /*@-------------------------------------------------------@*/
322 #endif
323 dm->pre_is_linked = false;
324 dm->is_linked = false;
325 /*dym bw thre and it can config by registry*/
326 if (dm->en_auto_bw_th == 0)
327 dm->en_auto_bw_th = 20;
328
329 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
330 if (!(dm->is_fcs_mode_enable)) {
331 dm->is_fcs_mode_enable = &dm->boolean_dummy;
332 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
333 }
334 #endif
335 /*init IOT table*/
336 odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
337 }
338
phydm_iot_patch_id_update(void * dm_void,u32 iot_idx,boolean en)339 void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
340 {
341 struct dm_struct *dm = (struct dm_struct *)dm_void;
342 struct phydm_iot_center *iot_table = &dm->iot_table;
343
344 PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
345 switch (iot_idx) {
346 case 0x100f0401:
347 iot_table->patch_id_100f0401 = en;
348 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
349 iot_table->patch_id_100f0401);
350 break;
351 case 0x10120200:
352 iot_table->patch_id_10120200 = en;
353 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
354 iot_table->patch_id_10120200);
355 break;
356 case 0x40010700:
357 iot_table->patch_id_40010700 = en;
358 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
359 iot_table->patch_id_40010700);
360 break;
361 case 0x021f0800:
362 iot_table->patch_id_021f0800 = en;
363 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
364 iot_table->patch_id_021f0800);
365 break;
366 case 0x011f0500:
367 iot_table->patch_id_011f0500 = en;
368 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_011f0500 = %d\n",
369 iot_table->patch_id_011f0500);
370 break;
371 default:
372 pr_debug("[%s] warning!\n", __func__);
373 break;
374 }
375 }
376
phydm_cmn_sta_info_update(void * dm_void,u8 macid)377 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
378 {
379 struct dm_struct *dm = (struct dm_struct *)dm_void;
380 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
381 struct ra_sta_info *ra = NULL;
382
383 if (is_sta_active(sta)) {
384 ra = &sta->ra_info;
385 } else {
386 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
387 __func__);
388 return;
389 }
390
391 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
392 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
393
394 /*@[Calculate TX/RX state]*/
395 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
396 ra->txrx_state = TX_STATE;
397 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
398 ra->txrx_state = RX_STATE;
399 else
400 ra->txrx_state = BI_DIRECTION_STATE;
401
402 ra->is_noisy = dm->noisy_decision;
403 }
404
phydm_common_info_self_update(struct dm_struct * dm)405 void phydm_common_info_self_update(struct dm_struct *dm)
406 {
407 u8 sta_cnt = 0, num_active_client = 0;
408 u32 i, one_entry_macid = 0;
409 u32 ma_rx_tp = 0;
410 u32 tp_diff = 0;
411 struct cmn_sta_info *sta;
412 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
413 PADAPTER adapter = (PADAPTER)dm->adapter;
414 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
415
416 sta = dm->phydm_sta_info[0];
417
418 /* STA mode is linked to AP */
419 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
420 dm->bsta_state = true;
421 else
422 dm->bsta_state = false;
423 #endif
424
425 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
426 sta = dm->phydm_sta_info[i];
427 if (is_sta_active(sta)) {
428 sta_cnt++;
429
430 if (sta_cnt == 1)
431 one_entry_macid = i;
432
433 phydm_cmn_sta_info_update(dm, (u8)i);
434 #ifdef PHYDM_BEAMFORMING_SUPPORT
435 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
436 #endif
437
438 ma_rx_tp = sta->rx_moving_average_tp +
439 sta->tx_moving_average_tp;
440
441 PHYDM_DBG(dm, DBG_COMMON_FLOW,
442 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
443
444 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
445 num_active_client++;
446 }
447 }
448
449 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
450 dm->is_linked = (sta_cnt != 0) ? true : false;
451 #endif
452
453 if (sta_cnt == 1) {
454 dm->is_one_entry_only = true;
455 dm->one_entry_macid = one_entry_macid;
456 dm->one_entry_tp = ma_rx_tp;
457
458 dm->tp_active_occur = 0;
459
460 PHYDM_DBG(dm, DBG_COMMON_FLOW,
461 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
462 dm->one_entry_tp, dm->pre_one_entry_tp);
463
464 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
465 dm->pre_one_entry_tp <= 2) {
466 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
467
468 if (tp_diff > dm->tp_active_th)
469 dm->tp_active_occur = 1;
470 }
471 dm->pre_one_entry_tp = dm->one_entry_tp;
472 } else {
473 dm->is_one_entry_only = false;
474 }
475
476 dm->pre_number_linked_client = dm->number_linked_client;
477 dm->pre_number_active_client = dm->number_active_client;
478
479 dm->number_linked_client = sta_cnt;
480 dm->number_active_client = num_active_client;
481
482 /*Traffic load information update*/
483 phydm_traffic_load_decision(dm);
484
485 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
486
487 dm->is_dfs_band = phydm_is_dfs_band(dm);
488 dm->phy_dbg_info.show_phy_sts_cnt = 0;
489
490 /*[Link Status Check]*/
491 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
492 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
493 dm->pre_is_linked = dm->is_linked;
494 }
495
phydm_common_info_self_reset(struct dm_struct * dm)496 void phydm_common_info_self_reset(struct dm_struct *dm)
497 {
498 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
499
500 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
501 dbg_t->num_qry_beacon_pkt = 0;
502
503 dm->rxsc_l = 0xff;
504 dm->rxsc_20 = 0xff;
505 dm->rxsc_40 = 0xff;
506 dm->rxsc_80 = 0xff;
507 }
508
509 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)510 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
511
512 {
513 void *structure = NULL;
514
515 switch (structure_type) {
516 case PHYDM_FALSEALMCNT:
517 structure = &dm->false_alm_cnt;
518 break;
519
520 case PHYDM_CFOTRACK:
521 structure = &dm->dm_cfo_track;
522 break;
523
524 case PHYDM_ADAPTIVITY:
525 structure = &dm->adaptivity;
526 break;
527 #ifdef CONFIG_PHYDM_DFS_MASTER
528 case PHYDM_DFS:
529 structure = &dm->dfs;
530 break;
531 #endif
532 default:
533 break;
534 }
535
536 return structure;
537 }
538
phydm_phy_info_update(struct dm_struct * dm)539 void phydm_phy_info_update(struct dm_struct *dm)
540 {
541 #if (RTL8822B_SUPPORT)
542 if (dm->support_ic_type == ODM_RTL8822B)
543 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
544 #endif
545 }
546
phydm_hw_setting(struct dm_struct * dm)547 void phydm_hw_setting(struct dm_struct *dm)
548 {
549 #if (RTL8188F_SUPPORT)
550 if (dm->support_ic_type & ODM_RTL8188F)
551 odm_hw_setting_8188F(dm);
552 #endif
553 #if (RTL8821A_SUPPORT)
554 if (dm->support_ic_type & ODM_RTL8821)
555 odm_hw_setting_8821a(dm);
556 #endif
557
558 #if (RTL8814A_SUPPORT)
559 if (dm->support_ic_type & ODM_RTL8814A)
560 phydm_hwsetting_8814a(dm);
561 #endif
562
563 #if (RTL8822B_SUPPORT)
564 if (dm->support_ic_type & ODM_RTL8822B)
565 phydm_hwsetting_8822b(dm);
566 #endif
567
568 #if (RTL8812A_SUPPORT)
569 if (dm->support_ic_type & ODM_RTL8812)
570 phydm_hwsetting_8812a(dm);
571 #endif
572
573 #if (RTL8197F_SUPPORT)
574 if (dm->support_ic_type & ODM_RTL8197F)
575 phydm_hwsetting_8197f(dm);
576 #endif
577
578 #if (RTL8192F_SUPPORT)
579 if (dm->support_ic_type & ODM_RTL8192F)
580 phydm_hwsetting_8192f(dm);
581 #endif
582
583 #if (RTL8822C_SUPPORT)
584 if (dm->support_ic_type & ODM_RTL8822C)
585 phydm_hwsetting_8822c(dm);
586 #endif
587
588 #if (RTL8197G_SUPPORT)
589 if (dm->support_ic_type & ODM_RTL8197G)
590 phydm_hwsetting_8197g(dm);
591 #endif
592
593 #if (RTL8723F_SUPPORT)
594 if (dm->support_ic_type & ODM_RTL8723F)
595 phydm_hwsetting_8723f(dm);
596 #endif
597
598 #if (RTL8821C_SUPPORT)
599 if (dm->support_ic_type & ODM_RTL8821C)
600 phydm_hwsetting_8821c(dm);
601 #endif
602
603 #if (RTL8812F_SUPPORT)
604 if (dm->support_ic_type & ODM_RTL8812F)
605 phydm_hwsetting_8812f(dm);
606 #endif
607
608 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
609 phydm_cck_rx_pathdiv_watchdog(dm);
610 #endif
611 }
612
613 __odm_func__
phydm_chk_bb_rf_pkg_set_valid(struct dm_struct * dm)614 boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
615 {
616 boolean valid = true;
617
618 if (dm->support_ic_type == ODM_RTL8822C) {
619 #if (RTL8822C_SUPPORT)
620 valid = phydm_chk_pkg_set_valid_8822c(dm,
621 RELEASE_VERSION_8822C,
622 RF_RELEASE_VERSION_8822C);
623 #else
624 valid = true; /*@Just for preventing compile warnings*/
625 #endif
626 #if (RTL8812F_SUPPORT)
627 } else if (dm->support_ic_type == ODM_RTL8812F) {
628 valid = phydm_chk_pkg_set_valid_8812f(dm,
629 RELEASE_VERSION_8812F,
630 RF_RELEASE_VERSION_8812F);
631 #endif
632 #if (RTL8197G_SUPPORT)
633 } else if (dm->support_ic_type == ODM_RTL8197G) {
634 valid = phydm_chk_pkg_set_valid_8197g(dm,
635 RELEASE_VERSION_8197G,
636 RF_RELEASE_VERSION_8197G);
637 #endif
638 #if (RTL8812F_SUPPORT)
639 } else if (dm->support_ic_type == ODM_RTL8812F) {
640 valid = phydm_chk_pkg_set_valid_8812f(dm,
641 RELEASE_VERSION_8812F,
642 RF_RELEASE_VERSION_8812F);
643 #endif
644 #if (RTL8198F_SUPPORT)
645 } else if (dm->support_ic_type == ODM_RTL8198F) {
646 valid = phydm_chk_pkg_set_valid_8198f(dm,
647 RELEASE_VERSION_8198F,
648 RF_RELEASE_VERSION_8198F);
649 #endif
650 #if (RTL8814B_SUPPORT)
651 } else if (dm->support_ic_type == ODM_RTL8814B) {
652 valid = phydm_chk_pkg_set_valid_8814b(dm,
653 RELEASE_VERSION_8814B,
654 RF_RELEASE_VERSION_8814B);
655 #endif
656 #if (RTL8814C_SUPPORT)
657 } else if (dm->support_ic_type == ODM_RTL8814C) {
658 valid = phydm_chk_pkg_set_valid_8814b(dm,
659 RELEASE_VERSION_8814C,
660 RF_RELEASE_VERSION_8814C);
661 #endif
662 #if (RTL8723F_SUPPORT)
663 } else if (dm->support_ic_type == ODM_RTL8723F) {
664 valid = phydm_chk_pkg_set_valid_8723f(dm,
665 RELEASE_VERSION_8723F,
666 RF_RELEASE_VERSION_8723F);
667 #endif
668 }
669
670 return valid;
671 }
672
673 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)674 u64 phydm_supportability_init_win(
675 void *dm_void)
676 {
677 struct dm_struct *dm = (struct dm_struct *)dm_void;
678 u64 support_ability = 0;
679
680 switch (dm->support_ic_type) {
681 /*@---------------N Series--------------------*/
682 #if (RTL8188E_SUPPORT)
683 case ODM_RTL8188E:
684 support_ability |=
685 ODM_BB_DIG |
686 ODM_BB_RA_MASK |
687 /*ODM_BB_DYNAMIC_TXPWR |*/
688 ODM_BB_FA_CNT |
689 ODM_BB_RSSI_MONITOR |
690 ODM_BB_CCK_PD |
691 /*ODM_BB_PWR_TRAIN |*/
692 ODM_BB_RATE_ADAPTIVE |
693 ODM_BB_ADAPTIVITY |
694 ODM_BB_CFO_TRACKING |
695 ODM_BB_ENV_MONITOR |
696 ODM_BB_PRIMARY_CCA;
697 break;
698 #endif
699
700 #if (RTL8192E_SUPPORT)
701 case ODM_RTL8192E:
702 support_ability |=
703 ODM_BB_DIG |
704 ODM_BB_RA_MASK |
705 /*ODM_BB_DYNAMIC_TXPWR |*/
706 ODM_BB_FA_CNT |
707 ODM_BB_RSSI_MONITOR |
708 ODM_BB_CCK_PD |
709 /*ODM_BB_PWR_TRAIN |*/
710 ODM_BB_RATE_ADAPTIVE |
711 ODM_BB_ADAPTIVITY |
712 ODM_BB_CFO_TRACKING |
713 ODM_BB_ENV_MONITOR |
714 ODM_BB_PRIMARY_CCA;
715 break;
716 #endif
717
718 #if (RTL8723B_SUPPORT)
719 case ODM_RTL8723B:
720 support_ability |=
721 ODM_BB_DIG |
722 ODM_BB_RA_MASK |
723 /*ODM_BB_DYNAMIC_TXPWR |*/
724 ODM_BB_FA_CNT |
725 ODM_BB_RSSI_MONITOR |
726 ODM_BB_CCK_PD |
727 /*ODM_BB_PWR_TRAIN |*/
728 ODM_BB_RATE_ADAPTIVE |
729 ODM_BB_ADAPTIVITY |
730 ODM_BB_CFO_TRACKING |
731 ODM_BB_ENV_MONITOR |
732 ODM_BB_PRIMARY_CCA;
733 break;
734 #endif
735
736 #if (RTL8703B_SUPPORT)
737 case ODM_RTL8703B:
738 support_ability |=
739 ODM_BB_DIG |
740 ODM_BB_RA_MASK |
741 /*ODM_BB_DYNAMIC_TXPWR |*/
742 ODM_BB_FA_CNT |
743 ODM_BB_RSSI_MONITOR |
744 ODM_BB_CCK_PD |
745 /*ODM_BB_PWR_TRAIN |*/
746 ODM_BB_RATE_ADAPTIVE |
747 ODM_BB_ADAPTIVITY |
748 ODM_BB_CFO_TRACKING |
749 ODM_BB_ENV_MONITOR;
750 break;
751 #endif
752
753 #if (RTL8723D_SUPPORT)
754 case ODM_RTL8723D:
755 support_ability |=
756 ODM_BB_DIG |
757 ODM_BB_RA_MASK |
758 /*ODM_BB_DYNAMIC_TXPWR |*/
759 ODM_BB_FA_CNT |
760 ODM_BB_RSSI_MONITOR |
761 ODM_BB_CCK_PD |
762 ODM_BB_PWR_TRAIN |
763 ODM_BB_RATE_ADAPTIVE |
764 ODM_BB_ADAPTIVITY |
765 ODM_BB_CFO_TRACKING |
766 ODM_BB_ENV_MONITOR;
767 break;
768 #endif
769
770 #if (RTL8710B_SUPPORT)
771 case ODM_RTL8710B:
772 support_ability |=
773 ODM_BB_DIG |
774 ODM_BB_RA_MASK |
775 /*ODM_BB_DYNAMIC_TXPWR |*/
776 ODM_BB_FA_CNT |
777 ODM_BB_RSSI_MONITOR |
778 ODM_BB_CCK_PD |
779 ODM_BB_PWR_TRAIN |
780 ODM_BB_RATE_ADAPTIVE |
781 ODM_BB_ADAPTIVITY |
782 ODM_BB_CFO_TRACKING |
783 ODM_BB_ENV_MONITOR;
784 break;
785 #endif
786
787 #if (RTL8188F_SUPPORT)
788 case ODM_RTL8188F:
789 support_ability |=
790 ODM_BB_DIG |
791 ODM_BB_RA_MASK |
792 /*ODM_BB_DYNAMIC_TXPWR |*/
793 ODM_BB_FA_CNT |
794 ODM_BB_RSSI_MONITOR |
795 ODM_BB_CCK_PD |
796 /*ODM_BB_PWR_TRAIN |*/
797 ODM_BB_RATE_ADAPTIVE |
798 ODM_BB_ADAPTIVITY |
799 ODM_BB_CFO_TRACKING |
800 ODM_BB_ENV_MONITOR;
801 break;
802 #endif
803
804 #if (RTL8192F_SUPPORT)
805 case ODM_RTL8192F:
806 support_ability |=
807 ODM_BB_DIG |
808 ODM_BB_RA_MASK |
809 ODM_BB_FA_CNT |
810 ODM_BB_RSSI_MONITOR |
811 ODM_BB_CCK_PD |
812 ODM_BB_PWR_TRAIN |
813 ODM_BB_RATE_ADAPTIVE |
814 /*ODM_BB_PATH_DIV |*/
815 ODM_BB_ADAPTIVITY |
816 ODM_BB_CFO_TRACKING |
817 ODM_BB_ADAPTIVE_SOML |
818 ODM_BB_ENV_MONITOR;
819 /*ODM_BB_LNA_SAT_CHK |*/
820 /*ODM_BB_PRIMARY_CCA*/
821
822 break;
823 #endif
824
825 /*@---------------AC Series-------------------*/
826
827 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
828 case ODM_RTL8812:
829 case ODM_RTL8821:
830 support_ability |=
831 ODM_BB_DIG |
832 ODM_BB_RA_MASK |
833 ODM_BB_DYNAMIC_TXPWR |
834 ODM_BB_FA_CNT |
835 ODM_BB_RSSI_MONITOR |
836 ODM_BB_CCK_PD |
837 /*ODM_BB_PWR_TRAIN |*/
838 ODM_BB_RATE_ADAPTIVE |
839 ODM_BB_ADAPTIVITY |
840 ODM_BB_CFO_TRACKING |
841 ODM_BB_ENV_MONITOR;
842 break;
843 #endif
844
845 #if (RTL8814A_SUPPORT)
846 case ODM_RTL8814A:
847 support_ability |=
848 ODM_BB_DIG |
849 ODM_BB_RA_MASK |
850 ODM_BB_DYNAMIC_TXPWR |
851 ODM_BB_FA_CNT |
852 ODM_BB_RSSI_MONITOR |
853 ODM_BB_CCK_PD |
854 /*ODM_BB_PWR_TRAIN |*/
855 ODM_BB_RATE_ADAPTIVE |
856 ODM_BB_ADAPTIVITY |
857 ODM_BB_CFO_TRACKING |
858 ODM_BB_ENV_MONITOR;
859 break;
860 #endif
861
862 #if (RTL8822B_SUPPORT)
863 case ODM_RTL8822B:
864 support_ability |=
865 ODM_BB_DIG |
866 ODM_BB_RA_MASK |
867 /*ODM_BB_DYNAMIC_TXPWR |*/
868 ODM_BB_FA_CNT |
869 ODM_BB_RSSI_MONITOR |
870 ODM_BB_CCK_PD |
871 /*ODM_BB_PWR_TRAIN |*/
872 /*ODM_BB_ADAPTIVE_SOML |*/
873 ODM_BB_RATE_ADAPTIVE |
874 /*ODM_BB_PATH_DIV |*/
875 ODM_BB_ADAPTIVITY |
876 ODM_BB_CFO_TRACKING |
877 ODM_BB_ENV_MONITOR;
878 break;
879 #endif
880
881 #if (RTL8821C_SUPPORT)
882 case ODM_RTL8821C:
883 support_ability |=
884 ODM_BB_DIG |
885 ODM_BB_RA_MASK |
886 /*ODM_BB_DYNAMIC_TXPWR |*/
887 ODM_BB_FA_CNT |
888 ODM_BB_RSSI_MONITOR |
889 ODM_BB_CCK_PD |
890 /*ODM_BB_PWR_TRAIN |*/
891 ODM_BB_RATE_ADAPTIVE |
892 ODM_BB_ADAPTIVITY |
893 ODM_BB_CFO_TRACKING |
894 ODM_BB_ENV_MONITOR;
895 break;
896 #endif
897
898 /*@---------------JGR3 Series-------------------*/
899
900 #if (RTL8822C_SUPPORT)
901 case ODM_RTL8822C:
902 support_ability |=
903 ODM_BB_DIG |
904 ODM_BB_RA_MASK |
905 ODM_BB_DYNAMIC_TXPWR |
906 ODM_BB_FA_CNT |
907 ODM_BB_RSSI_MONITOR |
908 ODM_BB_CCK_PD |
909 ODM_BB_RATE_ADAPTIVE |
910 ODM_BB_PATH_DIV |
911 ODM_BB_ADAPTIVITY |
912 ODM_BB_CFO_TRACKING |
913 ODM_BB_ENV_MONITOR;
914 break;
915 #endif
916
917 #if (RTL8814B_SUPPORT)
918 case ODM_RTL8814B:
919 support_ability |=
920 ODM_BB_DIG |
921 ODM_BB_RA_MASK |
922 /*ODM_BB_DYNAMIC_TXPWR |*/
923 ODM_BB_FA_CNT |
924 ODM_BB_RSSI_MONITOR |
925 ODM_BB_CCK_PD |
926 /*ODM_BB_PWR_TRAIN |*/
927 ODM_BB_RATE_ADAPTIVE |
928 ODM_BB_ADAPTIVITY |
929 ODM_BB_CFO_TRACKING;
930 /*ODM_BB_ENV_MONITOR;*/
931 break;
932 #endif
933
934 #if (RTL8723F_SUPPORT)
935 case ODM_RTL8723F:
936 support_ability |=
937 ODM_BB_DIG |
938 ODM_BB_RA_MASK |
939 /* ODM_BB_DYNAMIC_TXPWR |*/
940 ODM_BB_FA_CNT |
941 ODM_BB_RSSI_MONITOR |
942 ODM_BB_CCK_PD |
943 /*ODM_BB_PWR_TRAIN |*/
944 ODM_BB_RATE_ADAPTIVE |
945 ODM_BB_ADAPTIVITY |
946 ODM_BB_CFO_TRACKING |
947 ODM_BB_ENV_MONITOR;
948 break;
949 #endif
950 default:
951 support_ability |=
952 ODM_BB_DIG |
953 ODM_BB_RA_MASK |
954 /*ODM_BB_DYNAMIC_TXPWR |*/
955 ODM_BB_FA_CNT |
956 ODM_BB_RSSI_MONITOR |
957 ODM_BB_CCK_PD |
958 /*ODM_BB_PWR_TRAIN |*/
959 ODM_BB_RATE_ADAPTIVE |
960 ODM_BB_ADAPTIVITY |
961 ODM_BB_CFO_TRACKING |
962 ODM_BB_ENV_MONITOR;
963
964 pr_debug("[Warning] Supportability Init Warning !!!\n");
965 break;
966 }
967
968 return support_ability;
969 }
970 #endif
971
972 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)973 u64 phydm_supportability_init_ce(void *dm_void)
974 {
975 struct dm_struct *dm = (struct dm_struct *)dm_void;
976 u64 support_ability = 0;
977
978 switch (dm->support_ic_type) {
979 /*@---------------N Series--------------------*/
980 #if (RTL8188E_SUPPORT)
981 case ODM_RTL8188E:
982 support_ability |=
983 ODM_BB_DIG |
984 ODM_BB_RA_MASK |
985 /*@ODM_BB_DYNAMIC_TXPWR |*/
986 ODM_BB_FA_CNT |
987 ODM_BB_RSSI_MONITOR |
988 ODM_BB_CCK_PD |
989 /*@ODM_BB_PWR_TRAIN |*/
990 ODM_BB_RATE_ADAPTIVE |
991 ODM_BB_ADAPTIVITY |
992 ODM_BB_CFO_TRACKING |
993 ODM_BB_ENV_MONITOR |
994 ODM_BB_PRIMARY_CCA;
995 break;
996 #endif
997
998 #if (RTL8192E_SUPPORT)
999 case ODM_RTL8192E:
1000 support_ability |=
1001 ODM_BB_DIG |
1002 ODM_BB_RA_MASK |
1003 /*@ODM_BB_DYNAMIC_TXPWR |*/
1004 ODM_BB_FA_CNT |
1005 ODM_BB_RSSI_MONITOR |
1006 ODM_BB_CCK_PD |
1007 /*@ODM_BB_PWR_TRAIN |*/
1008 ODM_BB_RATE_ADAPTIVE |
1009 ODM_BB_ADAPTIVITY |
1010 ODM_BB_CFO_TRACKING |
1011 ODM_BB_ENV_MONITOR |
1012 ODM_BB_PRIMARY_CCA;
1013 break;
1014 #endif
1015
1016 #if (RTL8723B_SUPPORT)
1017 case ODM_RTL8723B:
1018 support_ability |=
1019 ODM_BB_DIG |
1020 ODM_BB_RA_MASK |
1021 /*@ODM_BB_DYNAMIC_TXPWR |*/
1022 ODM_BB_FA_CNT |
1023 ODM_BB_RSSI_MONITOR |
1024 ODM_BB_CCK_PD |
1025 /*@ODM_BB_PWR_TRAIN |*/
1026 ODM_BB_RATE_ADAPTIVE |
1027 ODM_BB_ADAPTIVITY |
1028 ODM_BB_CFO_TRACKING |
1029 ODM_BB_ENV_MONITOR |
1030 ODM_BB_PRIMARY_CCA;
1031 break;
1032 #endif
1033
1034 #if (RTL8703B_SUPPORT)
1035 case ODM_RTL8703B:
1036 support_ability |=
1037 ODM_BB_DIG |
1038 ODM_BB_RA_MASK |
1039 /*@ODM_BB_DYNAMIC_TXPWR |*/
1040 ODM_BB_FA_CNT |
1041 ODM_BB_RSSI_MONITOR |
1042 ODM_BB_CCK_PD |
1043 /*@ODM_BB_PWR_TRAIN |*/
1044 ODM_BB_RATE_ADAPTIVE |
1045 ODM_BB_ADAPTIVITY |
1046 ODM_BB_CFO_TRACKING |
1047 ODM_BB_ENV_MONITOR;
1048 break;
1049 #endif
1050
1051 #if (RTL8723D_SUPPORT)
1052 case ODM_RTL8723D:
1053 support_ability |=
1054 ODM_BB_DIG |
1055 ODM_BB_RA_MASK |
1056 /*@ODM_BB_DYNAMIC_TXPWR |*/
1057 ODM_BB_FA_CNT |
1058 ODM_BB_RSSI_MONITOR |
1059 ODM_BB_CCK_PD |
1060 ODM_BB_PWR_TRAIN |
1061 ODM_BB_RATE_ADAPTIVE |
1062 ODM_BB_ADAPTIVITY |
1063 ODM_BB_CFO_TRACKING |
1064 ODM_BB_ENV_MONITOR;
1065 break;
1066 #endif
1067
1068 #if (RTL8710B_SUPPORT)
1069 case ODM_RTL8710B:
1070 support_ability |=
1071 ODM_BB_DIG |
1072 ODM_BB_RA_MASK |
1073 /*@ODM_BB_DYNAMIC_TXPWR |*/
1074 ODM_BB_FA_CNT |
1075 ODM_BB_RSSI_MONITOR |
1076 ODM_BB_CCK_PD |
1077 /*@ODM_BB_PWR_TRAIN |*/
1078 ODM_BB_RATE_ADAPTIVE |
1079 ODM_BB_ADAPTIVITY |
1080 ODM_BB_CFO_TRACKING |
1081 ODM_BB_ENV_MONITOR;
1082 break;
1083 #endif
1084
1085 #if (RTL8188F_SUPPORT)
1086 case ODM_RTL8188F:
1087 support_ability |=
1088 ODM_BB_DIG |
1089 ODM_BB_RA_MASK |
1090 /*@ODM_BB_DYNAMIC_TXPWR |*/
1091 ODM_BB_FA_CNT |
1092 ODM_BB_RSSI_MONITOR |
1093 ODM_BB_CCK_PD |
1094 /*@ODM_BB_PWR_TRAIN |*/
1095 ODM_BB_RATE_ADAPTIVE |
1096 ODM_BB_ADAPTIVITY |
1097 ODM_BB_CFO_TRACKING |
1098 ODM_BB_ENV_MONITOR;
1099 break;
1100 #endif
1101
1102 #if (RTL8192F_SUPPORT)
1103 case ODM_RTL8192F:
1104 support_ability |=
1105 ODM_BB_DIG |
1106 ODM_BB_RA_MASK |
1107 ODM_BB_FA_CNT |
1108 ODM_BB_RSSI_MONITOR |
1109 ODM_BB_CCK_PD |
1110 ODM_BB_PWR_TRAIN |
1111 ODM_BB_RATE_ADAPTIVE |
1112 /*ODM_BB_PATH_DIV |*/
1113 ODM_BB_ADAPTIVITY |
1114 ODM_BB_CFO_TRACKING |
1115 /*@ODM_BB_ADAPTIVE_SOML |*/
1116 ODM_BB_ENV_MONITOR;
1117 /*@ODM_BB_LNA_SAT_CHK |*/
1118 /*@ODM_BB_PRIMARY_CCA*/
1119 break;
1120 #endif
1121 /*@---------------AC Series-------------------*/
1122
1123 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
1124 case ODM_RTL8812:
1125 case ODM_RTL8821:
1126 support_ability |=
1127 ODM_BB_DIG |
1128 ODM_BB_RA_MASK |
1129 /*@ODM_BB_DYNAMIC_TXPWR |*/
1130 ODM_BB_FA_CNT |
1131 ODM_BB_RSSI_MONITOR |
1132 ODM_BB_CCK_PD |
1133 /*@ODM_BB_PWR_TRAIN |*/
1134 ODM_BB_RATE_ADAPTIVE |
1135 ODM_BB_ADAPTIVITY |
1136 ODM_BB_CFO_TRACKING |
1137 ODM_BB_ENV_MONITOR;
1138 break;
1139 #endif
1140
1141 #if (RTL8814A_SUPPORT)
1142 case ODM_RTL8814A:
1143 support_ability |=
1144 ODM_BB_DIG |
1145 ODM_BB_RA_MASK |
1146 /*@ODM_BB_DYNAMIC_TXPWR |*/
1147 ODM_BB_FA_CNT |
1148 ODM_BB_RSSI_MONITOR |
1149 ODM_BB_CCK_PD |
1150 /*@ODM_BB_PWR_TRAIN |*/
1151 ODM_BB_RATE_ADAPTIVE |
1152 ODM_BB_ADAPTIVITY |
1153 ODM_BB_CFO_TRACKING |
1154 ODM_BB_ENV_MONITOR;
1155 break;
1156 #endif
1157
1158 #if (RTL8822B_SUPPORT)
1159 case ODM_RTL8822B:
1160 support_ability |=
1161 ODM_BB_DIG |
1162 ODM_BB_RA_MASK |
1163 ODM_BB_DYNAMIC_TXPWR |
1164 ODM_BB_FA_CNT |
1165 ODM_BB_RSSI_MONITOR |
1166 ODM_BB_CCK_PD |
1167 /*@ODM_BB_PWR_TRAIN |*/
1168 ODM_BB_RATE_ADAPTIVE |
1169 /*ODM_BB_PATH_DIV |*/
1170 ODM_BB_ADAPTIVITY |
1171 ODM_BB_CFO_TRACKING |
1172 ODM_BB_ENV_MONITOR;
1173 break;
1174 #endif
1175
1176 #if (RTL8821C_SUPPORT)
1177 case ODM_RTL8821C:
1178 support_ability |=
1179 ODM_BB_DIG |
1180 ODM_BB_RA_MASK |
1181 ODM_BB_DYNAMIC_TXPWR |
1182 ODM_BB_FA_CNT |
1183 ODM_BB_RSSI_MONITOR |
1184 ODM_BB_CCK_PD |
1185 /*@ODM_BB_PWR_TRAIN |*/
1186 ODM_BB_RATE_ADAPTIVE |
1187 ODM_BB_ADAPTIVITY |
1188 ODM_BB_CFO_TRACKING |
1189 ODM_BB_ENV_MONITOR;
1190 break;
1191 #endif
1192
1193 /*@---------------JGR3 Series-------------------*/
1194
1195 #if (RTL8822C_SUPPORT)
1196 case ODM_RTL8822C:
1197 support_ability |=
1198 ODM_BB_DIG |
1199 ODM_BB_RA_MASK |
1200 ODM_BB_DYNAMIC_TXPWR |
1201 ODM_BB_FA_CNT |
1202 ODM_BB_RSSI_MONITOR |
1203 ODM_BB_CCK_PD |
1204 ODM_BB_RATE_ADAPTIVE |
1205 /* ODM_BB_PATH_DIV | */
1206 ODM_BB_ADAPTIVITY |
1207 ODM_BB_CFO_TRACKING |
1208 ODM_BB_ENV_MONITOR;
1209 break;
1210 #endif
1211
1212 #if (RTL8814B_SUPPORT)
1213 case ODM_RTL8814B:
1214 support_ability |=
1215 ODM_BB_DIG |
1216 ODM_BB_RA_MASK |
1217 /*@ODM_BB_DYNAMIC_TXPWR |*/
1218 ODM_BB_FA_CNT |
1219 ODM_BB_RSSI_MONITOR |
1220 ODM_BB_CCK_PD |
1221 /*@ODM_BB_PWR_TRAIN |*/
1222 /*ODM_BB_RATE_ADAPTIVE |*/
1223 ODM_BB_ADAPTIVITY |
1224 ODM_BB_CFO_TRACKING;
1225 /*ODM_BB_ENV_MONITOR;*/
1226 break;
1227 #endif
1228 #if (RTL8723F_SUPPORT)
1229 case ODM_RTL8723F:
1230 support_ability |=
1231 ODM_BB_DIG |
1232 ODM_BB_RA_MASK |
1233 ODM_BB_DYNAMIC_TXPWR |
1234 ODM_BB_FA_CNT |
1235 ODM_BB_RSSI_MONITOR |
1236 ODM_BB_CCK_PD |
1237 ODM_BB_RATE_ADAPTIVE |
1238 /* ODM_BB_PATH_DIV | */
1239 ODM_BB_ADAPTIVITY |
1240 ODM_BB_CFO_TRACKING |
1241 ODM_BB_ENV_MONITOR;
1242 break;
1243 #endif
1244 default:
1245 support_ability |=
1246 ODM_BB_DIG |
1247 ODM_BB_RA_MASK |
1248 /*@ODM_BB_DYNAMIC_TXPWR |*/
1249 ODM_BB_FA_CNT |
1250 ODM_BB_RSSI_MONITOR |
1251 ODM_BB_CCK_PD |
1252 /*@ODM_BB_PWR_TRAIN |*/
1253 ODM_BB_RATE_ADAPTIVE |
1254 ODM_BB_ADAPTIVITY |
1255 ODM_BB_CFO_TRACKING |
1256 ODM_BB_ENV_MONITOR;
1257
1258 pr_debug("[Warning] Supportability Init Warning !!!\n");
1259 break;
1260 }
1261
1262 return support_ability;
1263 }
1264 #endif
1265
1266 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1267 u64 phydm_supportability_init_ap(
1268 void *dm_void)
1269 {
1270 struct dm_struct *dm = (struct dm_struct *)dm_void;
1271 u64 support_ability = 0;
1272
1273 switch (dm->support_ic_type) {
1274 /*@---------------N Series--------------------*/
1275 #if (RTL8188E_SUPPORT)
1276 case ODM_RTL8188E:
1277 support_ability |=
1278 ODM_BB_DIG |
1279 ODM_BB_RA_MASK |
1280 ODM_BB_FA_CNT |
1281 ODM_BB_RSSI_MONITOR |
1282 ODM_BB_CCK_PD |
1283 /*ODM_BB_PWR_TRAIN |*/
1284 ODM_BB_RATE_ADAPTIVE |
1285 ODM_BB_ADAPTIVITY |
1286 ODM_BB_CFO_TRACKING |
1287 ODM_BB_ENV_MONITOR |
1288 ODM_BB_PRIMARY_CCA;
1289 break;
1290 #endif
1291
1292 #if (RTL8192E_SUPPORT)
1293 case ODM_RTL8192E:
1294 support_ability |=
1295 ODM_BB_DIG |
1296 ODM_BB_RA_MASK |
1297 ODM_BB_FA_CNT |
1298 ODM_BB_RSSI_MONITOR |
1299 ODM_BB_CCK_PD |
1300 /*ODM_BB_PWR_TRAIN |*/
1301 ODM_BB_RATE_ADAPTIVE |
1302 ODM_BB_ADAPTIVITY |
1303 ODM_BB_CFO_TRACKING |
1304 ODM_BB_ENV_MONITOR |
1305 ODM_BB_PRIMARY_CCA;
1306 break;
1307 #endif
1308
1309 #if (RTL8723B_SUPPORT)
1310 case ODM_RTL8723B:
1311 support_ability |=
1312 ODM_BB_DIG |
1313 ODM_BB_RA_MASK |
1314 ODM_BB_FA_CNT |
1315 ODM_BB_RSSI_MONITOR |
1316 ODM_BB_CCK_PD |
1317 /*ODM_BB_PWR_TRAIN |*/
1318 ODM_BB_RATE_ADAPTIVE |
1319 ODM_BB_ADAPTIVITY |
1320 ODM_BB_CFO_TRACKING |
1321 ODM_BB_ENV_MONITOR;
1322 break;
1323 #endif
1324
1325 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1326 case ODM_RTL8198F:
1327 support_ability |=
1328 ODM_BB_DIG |
1329 ODM_BB_RA_MASK |
1330 ODM_BB_FA_CNT |
1331 ODM_BB_RSSI_MONITOR |
1332 ODM_BB_CCK_PD |
1333 /*ODM_BB_PWR_TRAIN |*/
1334 /*ODM_BB_RATE_ADAPTIVE |*/
1335 ODM_BB_ADAPTIVITY |
1336 ODM_BB_CFO_TRACKING;
1337 /*ODM_BB_ADAPTIVE_SOML |*/
1338 /*ODM_BB_ENV_MONITOR |*/
1339 /*ODM_BB_LNA_SAT_CHK |*/
1340 /*ODM_BB_PRIMARY_CCA;*/
1341 break;
1342 case ODM_RTL8197F:
1343 support_ability |=
1344 ODM_BB_DIG |
1345 ODM_BB_RA_MASK |
1346 ODM_BB_FA_CNT |
1347 ODM_BB_RSSI_MONITOR |
1348 ODM_BB_CCK_PD |
1349 /*ODM_BB_PWR_TRAIN |*/
1350 ODM_BB_RATE_ADAPTIVE |
1351 ODM_BB_ADAPTIVITY |
1352 ODM_BB_CFO_TRACKING |
1353 ODM_BB_ADAPTIVE_SOML |
1354 ODM_BB_ENV_MONITOR |
1355 ODM_BB_LNA_SAT_CHK |
1356 ODM_BB_PRIMARY_CCA;
1357 break;
1358 #endif
1359
1360 #if (RTL8192F_SUPPORT)
1361 case ODM_RTL8192F:
1362 support_ability |=
1363 ODM_BB_DIG |
1364 ODM_BB_RA_MASK |
1365 ODM_BB_FA_CNT |
1366 ODM_BB_RSSI_MONITOR |
1367 ODM_BB_CCK_PD |
1368 /*ODM_BB_PWR_TRAIN |*/
1369 ODM_BB_RATE_ADAPTIVE |
1370 ODM_BB_ADAPTIVITY |
1371 /*ODM_BB_CFO_TRACKING |*/
1372 ODM_BB_ADAPTIVE_SOML |
1373 /*ODM_BB_PATH_DIV |*/
1374 ODM_BB_ENV_MONITOR |
1375 /*ODM_BB_LNA_SAT_CHK |*/
1376 /*ODM_BB_PRIMARY_CCA |*/
1377 0;
1378 break;
1379 #endif
1380
1381 /*@---------------AC Series-------------------*/
1382
1383 #if (RTL8881A_SUPPORT)
1384 case ODM_RTL8881A:
1385 support_ability |=
1386 ODM_BB_DIG |
1387 ODM_BB_RA_MASK |
1388 ODM_BB_FA_CNT |
1389 ODM_BB_RSSI_MONITOR |
1390 ODM_BB_CCK_PD |
1391 /*ODM_BB_PWR_TRAIN |*/
1392 ODM_BB_RATE_ADAPTIVE |
1393 ODM_BB_ADAPTIVITY |
1394 ODM_BB_CFO_TRACKING |
1395 ODM_BB_ENV_MONITOR;
1396 break;
1397 #endif
1398
1399 #if (RTL8814A_SUPPORT)
1400 case ODM_RTL8814A:
1401 support_ability |=
1402 ODM_BB_DIG |
1403 ODM_BB_RA_MASK |
1404 ODM_BB_FA_CNT |
1405 ODM_BB_RSSI_MONITOR |
1406 ODM_BB_CCK_PD |
1407 /*ODM_BB_PWR_TRAIN |*/
1408 ODM_BB_RATE_ADAPTIVE |
1409 ODM_BB_ADAPTIVITY |
1410 ODM_BB_CFO_TRACKING |
1411 ODM_BB_ENV_MONITOR;
1412 break;
1413 #endif
1414
1415 #if (RTL8822B_SUPPORT)
1416 case ODM_RTL8822B:
1417 support_ability |=
1418 ODM_BB_DIG |
1419 ODM_BB_RA_MASK |
1420 ODM_BB_FA_CNT |
1421 ODM_BB_RSSI_MONITOR |
1422 ODM_BB_CCK_PD |
1423 /*ODM_BB_PWR_TRAIN |*/
1424 /*ODM_BB_ADAPTIVE_SOML |*/
1425 ODM_BB_RATE_ADAPTIVE |
1426 ODM_BB_ADAPTIVITY |
1427 ODM_BB_CFO_TRACKING |
1428 ODM_BB_ENV_MONITOR;
1429 break;
1430 #endif
1431
1432 #if (RTL8821C_SUPPORT)
1433 case ODM_RTL8821C:
1434 support_ability |=
1435 ODM_BB_DIG |
1436 ODM_BB_RA_MASK |
1437 ODM_BB_FA_CNT |
1438 ODM_BB_RSSI_MONITOR |
1439 ODM_BB_CCK_PD |
1440 /*ODM_BB_PWR_TRAIN |*/
1441 ODM_BB_RATE_ADAPTIVE |
1442 ODM_BB_ADAPTIVITY |
1443 ODM_BB_CFO_TRACKING |
1444 ODM_BB_ENV_MONITOR;
1445
1446 break;
1447 #endif
1448
1449 /*@---------------JGR3 Series-------------------*/
1450
1451 #if (RTL8814B_SUPPORT)
1452 case ODM_RTL8814B:
1453 support_ability |=
1454 ODM_BB_DIG |
1455 ODM_BB_RA_MASK |
1456 ODM_BB_FA_CNT |
1457 ODM_BB_RSSI_MONITOR |
1458 ODM_BB_CCK_PD |
1459 /*ODM_BB_PWR_TRAIN |*/
1460 /*ODM_BB_RATE_ADAPTIVE |*/
1461 ODM_BB_ADAPTIVITY |
1462 ODM_BB_CFO_TRACKING |
1463 ODM_BB_ENV_MONITOR;
1464 break;
1465 case ODM_RTL8814C:
1466 support_ability |=
1467 ODM_BB_DIG |
1468 ODM_BB_RA_MASK |
1469 ODM_BB_FA_CNT |
1470 ODM_BB_RSSI_MONITOR |
1471 ODM_BB_CCK_PD |
1472 /*ODM_BB_PWR_TRAIN |*/
1473 /*ODM_BB_RATE_ADAPTIVE |*/
1474 ODM_BB_ADAPTIVITY |
1475 ODM_BB_CFO_TRACKING |
1476 ODM_BB_ENV_MONITOR;
1477 break;
1478 #endif
1479
1480 #if (RTL8197G_SUPPORT)
1481 case ODM_RTL8197G:
1482 support_ability |=
1483 ODM_BB_DIG |
1484 ODM_BB_RA_MASK |
1485 ODM_BB_FA_CNT |
1486 ODM_BB_RSSI_MONITOR |
1487 ODM_BB_CCK_PD |
1488 /*ODM_BB_PWR_TRAIN |*/
1489 ODM_BB_RATE_ADAPTIVE |
1490 ODM_BB_ADAPTIVITY |
1491 ODM_BB_CFO_TRACKING |
1492 ODM_BB_ENV_MONITOR;
1493 break;
1494 #endif
1495
1496 #if (RTL8812F_SUPPORT)
1497 case ODM_RTL8812F:
1498 support_ability |=
1499 ODM_BB_DIG |
1500 ODM_BB_RA_MASK |
1501 ODM_BB_DYNAMIC_TXPWR |
1502 ODM_BB_FA_CNT |
1503 ODM_BB_RSSI_MONITOR |
1504 /*ODM_BB_CCK_PD |*/
1505 /*ODM_BB_PWR_TRAIN |*/
1506 ODM_BB_RATE_ADAPTIVE |
1507 ODM_BB_ADAPTIVITY |
1508 ODM_BB_CFO_TRACKING |
1509 ODM_BB_ENV_MONITOR;
1510 break;
1511 #endif
1512
1513 #if (RTL8723F_SUPPORT)
1514 case ODM_RTL8723F:
1515 support_ability |=
1516 ODM_BB_DIG |
1517 ODM_BB_RA_MASK |
1518 ODM_BB_FA_CNT |
1519 ODM_BB_RSSI_MONITOR |
1520 ODM_BB_CCK_PD |
1521 /*ODM_BB_PWR_TRAIN |*/
1522 ODM_BB_RATE_ADAPTIVE |
1523 ODM_BB_ADAPTIVITY |
1524 ODM_BB_CFO_TRACKING |
1525 ODM_BB_ENV_MONITOR;
1526 break;
1527 #endif
1528 default:
1529 support_ability |=
1530 ODM_BB_DIG |
1531 ODM_BB_RA_MASK |
1532 ODM_BB_FA_CNT |
1533 ODM_BB_RSSI_MONITOR |
1534 ODM_BB_CCK_PD |
1535 /*ODM_BB_PWR_TRAIN |*/
1536 ODM_BB_RATE_ADAPTIVE |
1537 ODM_BB_ADAPTIVITY |
1538 ODM_BB_CFO_TRACKING |
1539 ODM_BB_ENV_MONITOR;
1540
1541 pr_debug("[Warning] Supportability Init Warning !!!\n");
1542 break;
1543 }
1544
1545 return support_ability;
1546 }
1547 #endif
1548
1549 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1550 u64 phydm_supportability_init_iot(
1551 void *dm_void)
1552 {
1553 struct dm_struct *dm = (struct dm_struct *)dm_void;
1554 u64 support_ability = 0;
1555
1556 switch (dm->support_ic_type) {
1557 #if (RTL8710B_SUPPORT)
1558 case ODM_RTL8710B:
1559 support_ability |=
1560 ODM_BB_DIG |
1561 ODM_BB_RA_MASK |
1562 /*ODM_BB_DYNAMIC_TXPWR |*/
1563 ODM_BB_FA_CNT |
1564 ODM_BB_RSSI_MONITOR |
1565 ODM_BB_CCK_PD |
1566 /*ODM_BB_PWR_TRAIN |*/
1567 ODM_BB_RATE_ADAPTIVE |
1568 ODM_BB_CFO_TRACKING |
1569 ODM_BB_ENV_MONITOR;
1570 break;
1571 #endif
1572
1573 #if (RTL8195A_SUPPORT)
1574 case ODM_RTL8195A:
1575 support_ability |=
1576 ODM_BB_DIG |
1577 ODM_BB_RA_MASK |
1578 /*ODM_BB_DYNAMIC_TXPWR |*/
1579 ODM_BB_FA_CNT |
1580 ODM_BB_RSSI_MONITOR |
1581 ODM_BB_CCK_PD |
1582 /*ODM_BB_PWR_TRAIN |*/
1583 ODM_BB_RATE_ADAPTIVE |
1584 ODM_BB_CFO_TRACKING |
1585 ODM_BB_ENV_MONITOR;
1586 break;
1587 #endif
1588
1589 #if (RTL8195B_SUPPORT)
1590 case ODM_RTL8195B:
1591 support_ability |=
1592 ODM_BB_DIG |
1593 ODM_BB_RA_MASK |
1594 /*ODM_BB_DYNAMIC_TXPWR |*/
1595 ODM_BB_FA_CNT |
1596 ODM_BB_RSSI_MONITOR |
1597 ODM_BB_CCK_PD |
1598 /*ODM_BB_PWR_TRAIN |*/
1599 ODM_BB_RATE_ADAPTIVE |
1600 ODM_BB_ADAPTIVITY |
1601 ODM_BB_CFO_TRACKING |
1602 ODM_BB_ENV_MONITOR;
1603 break;
1604 #endif
1605
1606 #if (RTL8721D_SUPPORT)
1607 case ODM_RTL8721D:
1608 support_ability |=
1609 ODM_BB_DIG |
1610 ODM_BB_RA_MASK |
1611 /*ODM_BB_DYNAMIC_TXPWR |*/
1612 ODM_BB_FA_CNT |
1613 ODM_BB_RSSI_MONITOR |
1614 ODM_BB_CCK_PD |
1615 /*ODM_BB_PWR_TRAIN |*/
1616 ODM_BB_RATE_ADAPTIVE |
1617 ODM_BB_ADAPTIVITY |
1618 ODM_BB_CFO_TRACKING |
1619 ODM_BB_ENV_MONITOR;
1620 break;
1621 #endif
1622
1623 #if (RTL8710C_SUPPORT)
1624 case ODM_RTL8710C:
1625 support_ability |=
1626 ODM_BB_DIG |
1627 ODM_BB_RA_MASK |
1628 /*ODM_BB_DYNAMIC_TXPWR |*/
1629 ODM_BB_FA_CNT |
1630 ODM_BB_RSSI_MONITOR |
1631 ODM_BB_CCK_PD |
1632 /*ODM_BB_PWR_TRAIN |*/
1633 ODM_BB_RATE_ADAPTIVE |
1634 ODM_BB_ADAPTIVITY |
1635 ODM_BB_CFO_TRACKING |
1636 ODM_BB_ENV_MONITOR;
1637 break;
1638 #endif
1639 default:
1640 support_ability |=
1641 ODM_BB_DIG |
1642 ODM_BB_RA_MASK |
1643 /*ODM_BB_DYNAMIC_TXPWR |*/
1644 ODM_BB_FA_CNT |
1645 ODM_BB_RSSI_MONITOR |
1646 ODM_BB_CCK_PD |
1647 /*ODM_BB_PWR_TRAIN |*/
1648 ODM_BB_RATE_ADAPTIVE |
1649 ODM_BB_CFO_TRACKING |
1650 ODM_BB_ENV_MONITOR;
1651
1652 pr_debug("[Warning] Supportability Init Warning !!!\n");
1653 break;
1654 }
1655
1656 return support_ability;
1657 }
1658 #endif
1659
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1660 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1661 enum phydm_offload_ability offload_ability)
1662 {
1663 switch (offload_ability) {
1664 case PHYDM_PHY_PARAM_OFFLOAD:
1665 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1666 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1667 break;
1668
1669 case PHYDM_RF_IQK_OFFLOAD:
1670 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1671 break;
1672
1673 case PHYDM_RF_DPK_OFFLOAD:
1674 dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
1675 break;
1676
1677 default:
1678 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1679 break;
1680 }
1681
1682 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1683 dm->fw_offload_ability);
1684 }
1685
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1686 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1687 enum phydm_offload_ability offload_ability)
1688 {
1689 switch (offload_ability) {
1690 case PHYDM_PHY_PARAM_OFFLOAD:
1691 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1692 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1693 break;
1694
1695 case PHYDM_RF_IQK_OFFLOAD:
1696 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1697 break;
1698
1699 case PHYDM_RF_DPK_OFFLOAD:
1700 dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
1701 break;
1702
1703 default:
1704 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1705 break;
1706 }
1707
1708 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1709 dm->fw_offload_ability);
1710 }
1711
phydm_supportability_init(void * dm_void)1712 void phydm_supportability_init(void *dm_void)
1713 {
1714 struct dm_struct *dm = (struct dm_struct *)dm_void;
1715 u64 support_ability;
1716
1717 if (dm->manual_supportability &&
1718 *dm->manual_supportability != 0xffffffff) {
1719 support_ability = *dm->manual_supportability;
1720 } else if (*dm->mp_mode) {
1721 support_ability = 0;
1722 } else {
1723 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1724 support_ability = phydm_supportability_init_win(dm);
1725 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1726 support_ability = phydm_supportability_init_ap(dm);
1727 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1728 support_ability = phydm_supportability_init_ce(dm);
1729 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1730 support_ability = phydm_supportability_init_iot(dm);
1731 #endif
1732
1733 /*@[Config Antenna Diversity]*/
1734 if (IS_FUNC_EN(dm->enable_antdiv))
1735 support_ability |= ODM_BB_ANT_DIV;
1736
1737 /*@[Config TXpath Diversity]*/
1738 if (IS_FUNC_EN(dm->enable_pathdiv))
1739 support_ability |= ODM_BB_PATH_DIV;
1740
1741 /*@[Config Adaptive SOML]*/
1742 if (IS_FUNC_EN(dm->en_adap_soml))
1743 support_ability |= ODM_BB_ADAPTIVE_SOML;
1744
1745 /*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
1746 if(IS_FUNC_EN(&dm->en_tssi_mode) &&
1747 (dm->support_ic_type & ODM_RTL8822C))
1748 support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
1749 /*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
1750 if(IS_FUNC_EN(&dm->en_tssi_mode) &&
1751 (dm->support_ic_type & ODM_RTL8723F))
1752 support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
1753 }
1754 dm->support_ability = support_ability;
1755 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1756 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1757 }
1758
phydm_rfe_init(void * dm_void)1759 void phydm_rfe_init(void *dm_void)
1760 {
1761 struct dm_struct *dm = (struct dm_struct *)dm_void;
1762
1763 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1764 #if (RTL8822B_SUPPORT == 1)
1765 if (dm->support_ic_type == ODM_RTL8822B)
1766 phydm_rfe_8822b_init(dm);
1767 #endif
1768 }
1769
1770 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
phydm_tx_collsion_th_init(void * dm_void)1771 void phydm_tx_collsion_th_init(void *dm_void)
1772 {
1773
1774 struct dm_struct *dm = (struct dm_struct *)dm_void;
1775
1776 #if (RTL8197G_SUPPORT)
1777 if (dm->support_ic_type & ODM_RTL8197G)
1778 phydm_tx_collsion_th_init_8197g(dm);
1779 #endif
1780
1781 #if (RTL8812F_SUPPORT)
1782 if (dm->support_ic_type & ODM_RTL8812F)
1783 phydm_tx_collsion_th_init_8812f(dm);
1784 #endif
1785
1786 }
1787
phydm_tx_collsion_th_set(void * dm_void,u8 val_r2t,u8 val_t2r)1788 void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r)
1789 {
1790 struct dm_struct *dm = (struct dm_struct *)dm_void;
1791
1792 #if (RTL8197G_SUPPORT)
1793 if (dm->support_ic_type & ODM_RTL8197G)
1794 phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r);
1795 #endif
1796
1797 #if (RTL8812F_SUPPORT)
1798 if (dm->support_ic_type & ODM_RTL8812F)
1799 phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r);
1800 #endif
1801
1802 }
1803 #endif
1804
phydm_dm_early_init(struct dm_struct * dm)1805 void phydm_dm_early_init(struct dm_struct *dm)
1806 {
1807 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1808 phydm_init_debug_setting(dm);
1809 #endif
1810 }
1811
odm_dm_init(struct dm_struct * dm)1812 enum phydm_init_result odm_dm_init(struct dm_struct *dm)
1813 {
1814 enum phydm_init_result result = PHYDM_INIT_SUCCESS;
1815
1816 if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
1817 pr_debug("[Warning][%s] Init fail\n", __func__);
1818 return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
1819 }
1820
1821 halrf_init(dm);
1822 phydm_supportability_init(dm);
1823 phydm_pause_func_init(dm);
1824 phydm_rfe_init(dm);
1825 phydm_common_info_self_init(dm);
1826 phydm_rx_phy_status_init(dm);
1827 #ifdef PHYDM_AUTO_DEGBUG
1828 phydm_auto_dbg_engine_init(dm);
1829 #endif
1830 phydm_dig_init(dm);
1831 #ifdef PHYDM_SUPPORT_CCKPD
1832 #ifdef PHYDM_DCC_ENHANCE
1833 phydm_dig_cckpd_coex_init(dm);
1834 #endif
1835 phydm_cck_pd_init(dm);
1836 #endif
1837 phydm_env_monitor_init(dm);
1838 phydm_adaptivity_init(dm);
1839 phydm_ra_info_init(dm);
1840 phydm_rssi_monitor_init(dm);
1841 phydm_cfo_tracking_init(dm);
1842 phydm_rf_init(dm);
1843 phydm_dc_cancellation(dm);
1844 #ifdef PHYDM_TXA_CALIBRATION
1845 phydm_txcurrentcalibration(dm);
1846 phydm_get_pa_bias_offset(dm);
1847 #endif
1848 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1849 odm_antenna_diversity_init(dm);
1850 #endif
1851 #ifdef CONFIG_ADAPTIVE_SOML
1852 phydm_adaptive_soml_init(dm);
1853 #endif
1854 #ifdef CONFIG_PATH_DIVERSITY
1855 phydm_tx_path_diversity_init(dm);
1856 #endif
1857 #ifdef CONFIG_DYNAMIC_TX_TWR
1858 phydm_dynamic_tx_power_init(dm);
1859 #endif
1860 #if (PHYDM_LA_MODE_SUPPORT)
1861 phydm_la_init(dm);
1862 #endif
1863
1864 #ifdef PHYDM_BEAMFORMING_VERSION1
1865 phydm_beamforming_init(dm);
1866 #endif
1867
1868 #if (RTL8188E_SUPPORT)
1869 odm_ra_info_init_all(dm);
1870 #endif
1871 #ifdef PHYDM_PRIMARY_CCA
1872 phydm_primary_cca_init(dm);
1873 #endif
1874 #ifdef CONFIG_PSD_TOOL
1875 phydm_psd_init(dm);
1876 #endif
1877
1878 #ifdef CONFIG_SMART_ANTENNA
1879 phydm_smt_ant_init(dm);
1880 #endif
1881 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1882 phydm_lna_sat_check_init(dm);
1883 #endif
1884 #ifdef CONFIG_MCC_DM
1885 phydm_mcc_init(dm);
1886 #endif
1887
1888 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
1889 phydm_cck_rx_pathdiv_init(dm);
1890 #endif
1891
1892 #ifdef CONFIG_MU_RSOML
1893 phydm_mu_rsoml_init(dm);
1894 #endif
1895
1896 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
1897 phydm_tx_collsion_th_init(dm);
1898 #endif
1899
1900 return result;
1901 }
1902
odm_dm_reset(struct dm_struct * dm)1903 void odm_dm_reset(struct dm_struct *dm)
1904 {
1905 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1906 odm_ant_div_reset(dm);
1907 #endif
1908 phydm_set_edcca_threshold_api(dm);
1909 }
1910
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1911 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1912 char *output, u32 *_out_len)
1913 {
1914 struct dm_struct *dm = (struct dm_struct *)dm_void;
1915 u32 dm_value[10] = {0};
1916 u64 pre_support_ability, one = 1;
1917 u64 comp = 0;
1918 u32 used = *_used;
1919 u32 out_len = *_out_len;
1920 u8 i;
1921
1922 for (i = 0; i < 5; i++) {
1923 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1924 }
1925
1926 pre_support_ability = dm->support_ability;
1927 comp = dm->support_ability;
1928
1929 PDM_SNPF(out_len, used, output + used, out_len - used,
1930 "\n================================\n");
1931
1932 if (dm_value[0] == 100) {
1933 PDM_SNPF(out_len, used, output + used, out_len - used,
1934 "[Supportability] PhyDM Selection\n");
1935 PDM_SNPF(out_len, used, output + used, out_len - used,
1936 "================================\n");
1937 PDM_SNPF(out_len, used, output + used, out_len - used,
1938 "00. (( %s ))DIG\n",
1939 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1940 PDM_SNPF(out_len, used, output + used, out_len - used,
1941 "01. (( %s ))RA_MASK\n",
1942 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1943 PDM_SNPF(out_len, used, output + used, out_len - used,
1944 "02. (( %s ))DYN_TXPWR\n",
1945 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1946 PDM_SNPF(out_len, used, output + used, out_len - used,
1947 "03. (( %s ))FA_CNT\n",
1948 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1949 PDM_SNPF(out_len, used, output + used, out_len - used,
1950 "04. (( %s ))RSSI_MNTR\n",
1951 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1952 PDM_SNPF(out_len, used, output + used, out_len - used,
1953 "05. (( %s ))CCK_PD\n",
1954 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1955 PDM_SNPF(out_len, used, output + used, out_len - used,
1956 "06. (( %s ))ANT_DIV\n",
1957 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1958 PDM_SNPF(out_len, used, output + used, out_len - used,
1959 "07. (( %s ))SMT_ANT\n",
1960 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1961 PDM_SNPF(out_len, used, output + used, out_len - used,
1962 "08. (( %s ))PWR_TRAIN\n",
1963 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1964 PDM_SNPF(out_len, used, output + used, out_len - used,
1965 "09. (( %s ))RA\n",
1966 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1967 PDM_SNPF(out_len, used, output + used, out_len - used,
1968 "10. (( %s ))PATH_DIV\n",
1969 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1970 PDM_SNPF(out_len, used, output + used, out_len - used,
1971 "11. (( %s ))DFS\n",
1972 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1973 PDM_SNPF(out_len, used, output + used, out_len - used,
1974 "12. (( %s ))DYN_ARFR\n",
1975 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1976 PDM_SNPF(out_len, used, output + used, out_len - used,
1977 "13. (( %s ))ADAPTIVITY\n",
1978 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1979 PDM_SNPF(out_len, used, output + used, out_len - used,
1980 "14. (( %s ))CFO_TRACK\n",
1981 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1982 PDM_SNPF(out_len, used, output + used, out_len - used,
1983 "15. (( %s ))ENV_MONITOR\n",
1984 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1985 PDM_SNPF(out_len, used, output + used, out_len - used,
1986 "16. (( %s ))PRI_CCA\n",
1987 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1988 PDM_SNPF(out_len, used, output + used, out_len - used,
1989 "17. (( %s ))ADPTV_SOML\n",
1990 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1991 PDM_SNPF(out_len, used, output + used, out_len - used,
1992 "18. (( %s ))LNA_SAT_CHK\n",
1993 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1994 PDM_SNPF(out_len, used, output + used, out_len - used,
1995 "================================\n");
1996 PDM_SNPF(out_len, used, output + used, out_len - used,
1997 "[Supportability] PhyDM offload ability\n");
1998 PDM_SNPF(out_len, used, output + used, out_len - used,
1999 "================================\n");
2000
2001 PDM_SNPF(out_len, used, output + used, out_len - used,
2002 "00. (( %s ))PHY PARAM OFFLOAD\n",
2003 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
2004 ("V") : (".")));
2005 PDM_SNPF(out_len, used, output + used, out_len - used,
2006 "01. (( %s ))RF IQK OFFLOAD\n",
2007 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
2008 ("V") : (".")));
2009 PDM_SNPF(out_len, used, output + used, out_len - used,
2010 "================================\n");
2011
2012 } else if (dm_value[0] == 101) {
2013 dm->support_ability = 0;
2014 PDM_SNPF(out_len, used, output + used, out_len - used,
2015 "Disable all support_ability components\n");
2016 } else {
2017 if (dm_value[1] == 1) { /* @enable */
2018 dm->support_ability |= (one << dm_value[0]);
2019 } else if (dm_value[1] == 2) {/* @disable */
2020 dm->support_ability &= ~(one << dm_value[0]);
2021 } else {
2022 PDM_SNPF(out_len, used, output + used, out_len - used,
2023 "[Warning!!!] 1:enable, 2:disable\n");
2024 }
2025 }
2026 PDM_SNPF(out_len, used, output + used, out_len - used,
2027 "pre-supportability = 0x%llx\n", pre_support_ability);
2028 PDM_SNPF(out_len, used, output + used, out_len - used,
2029 "Cur-supportability = 0x%llx\n", dm->support_ability);
2030 PDM_SNPF(out_len, used, output + used, out_len - used,
2031 "================================\n");
2032
2033 *_used = used;
2034 *_out_len = out_len;
2035 }
2036
phydm_watchdog_lps_32k(struct dm_struct * dm)2037 void phydm_watchdog_lps_32k(struct dm_struct *dm)
2038 {
2039 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2040
2041 phydm_common_info_self_update(dm);
2042 phydm_rssi_monitor_check(dm);
2043 phydm_dig_lps_32k(dm);
2044 phydm_common_info_self_reset(dm);
2045 }
2046
phydm_watchdog_lps(struct dm_struct * dm)2047 void phydm_watchdog_lps(struct dm_struct *dm)
2048 {
2049 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
2050 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2051
2052 phydm_common_info_self_update(dm);
2053 phydm_rssi_monitor_check(dm);
2054 phydm_basic_dbg_message(dm);
2055 phydm_receiver_blocking(dm);
2056 phydm_false_alarm_counter_statistics(dm);
2057 phydm_dig_by_rssi_lps(dm);
2058 #ifdef PHYDM_SUPPORT_CCKPD
2059 phydm_cck_pd_th(dm);
2060 #endif
2061 phydm_adaptivity(dm);
2062 #ifdef CONFIG_BW_INDICATION
2063 phydm_dyn_bw_indication(dm);
2064 #endif
2065 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
2066 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2067 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
2068 odm_antenna_diversity(dm);
2069 #endif
2070 #endif
2071 phydm_common_info_self_reset(dm);
2072 #endif
2073 }
2074
phydm_watchdog_mp(struct dm_struct * dm)2075 void phydm_watchdog_mp(struct dm_struct *dm)
2076 {
2077 }
2078
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)2079 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
2080 {
2081 struct dm_struct *dm = (struct dm_struct *)dm_void;
2082
2083 if (pause_type == PHYDM_PAUSE) {
2084 dm->disable_phydm_watchdog = 1;
2085 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
2086 } else {
2087 dm->disable_phydm_watchdog = 0;
2088 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
2089 }
2090 }
2091
phydm_pause_func_init(void * dm_void)2092 void phydm_pause_func_init(void *dm_void)
2093 {
2094 struct dm_struct *dm = (struct dm_struct *)dm_void;
2095
2096 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
2097 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2098 dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
2099 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2100 dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
2101 dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
2102 }
2103
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)2104 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
2105 enum phydm_pause_type pause_type,
2106 enum phydm_pause_level pause_lv, u8 val_lehgth,
2107 u32 *val_buf)
2108 {
2109 struct dm_struct *dm = (struct dm_struct *)dm_void;
2110 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
2111 s8 *pause_lv_pre = &dm->s8_dummy;
2112 u32 *bkp_val = &dm->u32_dummy;
2113 u32 ori_val[5] = {0};
2114 u64 pause_func_bitmap = (u64)BIT(pause_func);
2115 u8 i = 0;
2116 u8 en_2rcca = 0;
2117 u8 en_bw40m = 0;
2118 u8 pause_result = PAUSE_FAIL;
2119
2120 PHYDM_DBG(dm, ODM_COMP_API, "\n");
2121 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
2122 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2123 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2124 pause_lv, val_lehgth);
2125
2126 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
2127 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
2128 return PAUSE_FAIL;
2129 }
2130
2131 if (pause_func == F00_DIG) {
2132 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
2133
2134 if (val_lehgth != 1) {
2135 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2136 return PAUSE_FAIL;
2137 }
2138
2139 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
2140 pause_lv_pre = &dm->pause_lv_table.lv_dig;
2141 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
2142 /*@function pointer hook*/
2143 func_t->pause_phydm_handler = phydm_set_dig_val;
2144
2145 #ifdef PHYDM_SUPPORT_CCKPD
2146 } else if (pause_func == F05_CCK_PD) {
2147 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
2148
2149 if (val_lehgth != 1) {
2150 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2151 return PAUSE_FAIL;
2152 }
2153
2154 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
2155 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
2156 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
2157 /*@function pointer hook*/
2158 func_t->pause_phydm_handler = phydm_set_cckpd_val;
2159 #endif
2160
2161 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2162 } else if (pause_func == F06_ANT_DIV) {
2163 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
2164
2165 if (val_lehgth != 1) {
2166 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2167 return PAUSE_FAIL;
2168 }
2169 /*@default antenna*/
2170 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
2171 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
2172 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
2173 /*@function pointer hook*/
2174 func_t->pause_phydm_handler = phydm_set_antdiv_val;
2175
2176 #endif
2177 #ifdef PHYDM_SUPPORT_ADAPTIVITY
2178 } else if (pause_func == F13_ADPTVTY) {
2179 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
2180
2181 if (val_lehgth != 2) {
2182 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
2183 return PAUSE_FAIL;
2184 }
2185
2186 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
2187 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
2188 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
2189 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
2190 /*@function pointer hook*/
2191 func_t->pause_phydm_handler = phydm_set_edcca_val;
2192
2193 #endif
2194 #ifdef CONFIG_ADAPTIVE_SOML
2195 } else if (pause_func == F17_ADPTV_SOML) {
2196 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
2197
2198 if (val_lehgth != 1) {
2199 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2200 return PAUSE_FAIL;
2201 }
2202 /*SOML_ON/OFF*/
2203 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
2204
2205 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
2206 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
2207 /*@function pointer hook*/
2208 func_t->pause_phydm_handler = phydm_set_adsl_val;
2209
2210 #endif
2211 } else {
2212 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
2213 return PAUSE_FAIL;
2214 }
2215
2216 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
2217 pause_lv, *pause_lv_pre);
2218
2219 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
2220 if (pause_lv <= *pause_lv_pre) {
2221 PHYDM_DBG(dm, ODM_COMP_API,
2222 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
2223 return PAUSE_FAIL;
2224 }
2225
2226 if (!(dm->pause_ability & pause_func_bitmap)) {
2227 for (i = 0; i < val_lehgth; i++)
2228 bkp_val[i] = ori_val[i];
2229 }
2230
2231 dm->pause_ability |= pause_func_bitmap;
2232 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2233 dm->pause_ability);
2234
2235 if (pause_type == PHYDM_PAUSE) {
2236 for (i = 0; i < val_lehgth; i++)
2237 PHYDM_DBG(dm, ODM_COMP_API,
2238 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
2239 i, val_buf[i], bkp_val[i]);
2240 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
2241 } else {
2242 for (i = 0; i < val_lehgth; i++)
2243 PHYDM_DBG(dm, ODM_COMP_API,
2244 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
2245 i, bkp_val[i]);
2246 }
2247
2248 *pause_lv_pre = pause_lv;
2249 pause_result = PAUSE_SUCCESS;
2250
2251 } else if (pause_type == PHYDM_RESUME) {
2252 if (pause_lv < *pause_lv_pre) {
2253 PHYDM_DBG(dm, ODM_COMP_API,
2254 "[Resume FAIL] Pre_LV >= Curr_LV\n");
2255 return PAUSE_FAIL;
2256 }
2257
2258 if ((dm->pause_ability & pause_func_bitmap) == 0) {
2259 PHYDM_DBG(dm, ODM_COMP_API,
2260 "[RESUME] No Need to Revert\n");
2261 return PAUSE_SUCCESS;
2262 }
2263
2264 dm->pause_ability &= ~pause_func_bitmap;
2265 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2266 dm->pause_ability);
2267
2268 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
2269
2270 for (i = 0; i < val_lehgth; i++) {
2271 PHYDM_DBG(dm, ODM_COMP_API,
2272 "[RESUME] val_idx[%d]={0x%x}\n", i,
2273 bkp_val[i]);
2274 }
2275
2276 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
2277
2278 pause_result = PAUSE_SUCCESS;
2279 } else {
2280 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
2281 pause_result = PAUSE_FAIL;
2282 }
2283 return pause_result;
2284 }
2285
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2286 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
2287 char *output, u32 *_out_len)
2288 {
2289 struct dm_struct *dm = (struct dm_struct *)dm_void;
2290 char help[] = "-h";
2291 u32 var1[10] = {0};
2292 u32 used = *_used;
2293 u32 out_len = *_out_len;
2294 u32 i;
2295 u8 length = 0;
2296 u32 buf[5] = {0};
2297 u8 set_result = 0;
2298 enum phydm_func_idx func = 0;
2299 enum phydm_pause_type type = 0;
2300 enum phydm_pause_level lv = 0;
2301
2302 if ((strcmp(input[1], help) == 0)) {
2303 PDM_SNPF(out_len, used, output + used, out_len - used,
2304 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
2305
2306 goto out;
2307 }
2308
2309 for (i = 0; i < 10; i++) {
2310 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2311 }
2312
2313 func = (enum phydm_func_idx)var1[0];
2314 type = (enum phydm_pause_type)var1[1];
2315 lv = (enum phydm_pause_level)var1[2];
2316
2317 for (i = 0; i < 5; i++)
2318 buf[i] = var1[3 + i];
2319
2320 if (func == F00_DIG) {
2321 PDM_SNPF(out_len, used, output + used, out_len - used,
2322 "[DIG]\n");
2323 length = 1;
2324
2325 } else if (func == F05_CCK_PD) {
2326 PDM_SNPF(out_len, used, output + used, out_len - used,
2327 "[CCK_PD]\n");
2328 length = 1;
2329 } else if (func == F06_ANT_DIV) {
2330 PDM_SNPF(out_len, used, output + used, out_len - used,
2331 "[Ant_Div]\n");
2332 length = 1;
2333 } else if (func == F13_ADPTVTY) {
2334 PDM_SNPF(out_len, used, output + used, out_len - used,
2335 "[Adaptivity]\n");
2336 length = 2;
2337 } else if (func == F17_ADPTV_SOML) {
2338 PDM_SNPF(out_len, used, output + used, out_len - used,
2339 "[ADSL]\n");
2340 length = 1;
2341 } else {
2342 PDM_SNPF(out_len, used, output + used, out_len - used,
2343 "[Set Function Error]\n");
2344 length = 0;
2345 }
2346
2347 if (length != 0) {
2348 PDM_SNPF(out_len, used, output + used, out_len - used,
2349 "{%s, lv=%d} val = %d, %d}\n",
2350 ((type == PHYDM_PAUSE) ? "Pause" :
2351 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2352 lv, var1[3], var1[4]);
2353
2354 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
2355 }
2356
2357 PDM_SNPF(out_len, used, output + used, out_len - used,
2358 "set_result = %d\n", set_result);
2359
2360 out:
2361 *_used = used;
2362 *_out_len = out_len;
2363 }
2364
phydm_pause_dm_by_asso_pkt(struct dm_struct * dm,enum phydm_pause_type pause_type,u8 rssi)2365 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
2366 enum phydm_pause_type pause_type, u8 rssi)
2367 {
2368 u32 igi_val = rssi + 10;
2369 u32 th_buf[2];
2370
2371 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
2372 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2373 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2374 rssi);
2375
2376 if (pause_type == PHYDM_RESUME) {
2377 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
2378 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2379
2380 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
2381 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2382 } else {
2383 odm_write_dig(dm, (u8)igi_val);
2384 phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
2385 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2386
2387 th_buf[0] = 0xff;
2388 th_buf[1] = 0xff;
2389
2390 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
2391 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2392 }
2393 }
2394
phydm_stop_dm_watchdog_check(void * dm_void)2395 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2396 {
2397 struct dm_struct *dm = (struct dm_struct *)dm_void;
2398
2399 if (dm->disable_phydm_watchdog == 1) {
2400 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2401 return true;
2402 } else {
2403 return false;
2404 }
2405 }
2406
phydm_watchdog(struct dm_struct * dm)2407 void phydm_watchdog(struct dm_struct *dm)
2408 {
2409 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2410
2411 phydm_common_info_self_update(dm);
2412 phydm_phy_info_update(dm);
2413 phydm_rssi_monitor_check(dm);
2414 phydm_basic_dbg_message(dm);
2415 phydm_dm_summary(dm, FIRST_MACID);
2416 #ifdef PHYDM_AUTO_DEGBUG
2417 phydm_auto_dbg_engine(dm);
2418 #endif
2419 phydm_receiver_blocking(dm);
2420
2421 if (phydm_stop_dm_watchdog_check(dm) == true)
2422 return;
2423
2424 phydm_hw_setting(dm);
2425
2426 phydm_env_mntr_result_watchdog(dm);
2427
2428 #ifdef PHYDM_TDMA_DIG_SUPPORT
2429 if (dm->original_dig_restore == 0) {
2430 phydm_tdma_dig_timer_check(dm);
2431 } else
2432 #endif
2433 {
2434 phydm_false_alarm_counter_statistics(dm);
2435 #if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
2436 if (dm->support_ic_type & (ODM_IC_11N_SERIES |
2437 ODM_IC_11AC_SERIES))
2438 phydm_noisy_detection(dm);
2439 #endif
2440
2441 #if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
2442 phydm_dig_cckpd_coex(dm);
2443 #else
2444 phydm_dig(dm);
2445 #ifdef PHYDM_SUPPORT_CCKPD
2446 phydm_cck_pd_th(dm);
2447 #endif
2448 #endif
2449 }
2450
2451 #ifdef PHYDM_HW_IGI
2452 phydm_hwigi(dm);
2453 #endif
2454 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2455 phydm_update_power_training_state(dm);
2456 #endif
2457 phydm_adaptivity(dm);
2458 phydm_ra_info_watchdog(dm);
2459 #ifdef CONFIG_PATH_DIVERSITY
2460 phydm_tx_path_diversity(dm);
2461 #endif
2462 phydm_cfo_tracking(dm);
2463 #ifdef CONFIG_DYNAMIC_TX_TWR
2464 phydm_dynamic_tx_power(dm);
2465 #endif
2466 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2467 odm_antenna_diversity(dm);
2468 #endif
2469 #ifdef CONFIG_ADAPTIVE_SOML
2470 phydm_adaptive_soml(dm);
2471 #endif
2472
2473 #ifdef PHYDM_BEAMFORMING_VERSION1
2474 phydm_beamforming_watchdog(dm);
2475 #endif
2476
2477 halrf_watchdog(dm);
2478 #ifdef PHYDM_PRIMARY_CCA
2479 phydm_primary_cca(dm);
2480 #endif
2481 #ifdef CONFIG_BW_INDICATION
2482 phydm_dyn_bw_indication(dm);
2483 #endif
2484 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2485 odm_dtc(dm);
2486 #endif
2487
2488 phydm_env_mntr_set_watchdog(dm);
2489
2490 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2491 phydm_lna_sat_chk_watchdog(dm);
2492 #endif
2493
2494 #ifdef CONFIG_MCC_DM
2495 phydm_mcc_switch(dm);
2496 #endif
2497
2498 #ifdef CONFIG_MU_RSOML
2499 phydm_mu_rsoml_decision(dm);
2500 #endif
2501
2502 phydm_common_info_self_reset(dm);
2503 }
2504
phydm_fw_dm_ctrl_en(void * dm_void,enum phydm_func_idx fun_idx,boolean enable)2505 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
2506 boolean enable)
2507 {
2508 struct dm_struct *dm = (struct dm_struct *)dm_void;
2509 u8 h2c_val[H2C_MAX_LENGTH] = {0};
2510 u8 para4[4]; /*4 bit*/
2511 u8 para8[4]; /*8 bit*/
2512 u8 i = 0;
2513
2514 for (i = 0; i < 4; i++) {
2515 para4[i] = 0;
2516 para8[i] = 0;
2517 }
2518
2519 switch (fun_idx) {
2520 case F00_DIG:
2521 phydm_fill_fw_dig_info(dm, &enable, para4, para8);
2522 break;
2523 default:
2524 pr_debug("[Warning] %s\n", __func__);
2525 return;
2526 }
2527
2528 h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
2529 h2c_val[1] = para8[0];
2530 h2c_val[2] = para8[1];
2531 h2c_val[3] = para8[2];
2532 h2c_val[4] = para8[3];
2533 h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
2534 h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
2535
2536 PHYDM_DBG(dm, DBG_FW_DM,
2537 "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
2538 fun_idx, enable,
2539 para8[0], para8[1], para8[2], para8[3],
2540 para4[0], para4[1], para4[2], para4[3]);
2541
2542 odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
2543 }
2544
2545 /*@
2546 * Init /.. Fixed HW value. Only init time.
2547 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2548 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2549 u64 value)
2550 {
2551 /* This section is used for init value */
2552 switch (cmn_info) {
2553 /* @Fixed ODM value. */
2554 case ODM_CMNINFO_ABILITY:
2555 dm->support_ability = (u64)value;
2556 break;
2557
2558 case ODM_CMNINFO_RF_TYPE:
2559 dm->rf_type = (u8)value;
2560 break;
2561
2562 case ODM_CMNINFO_PLATFORM:
2563 dm->support_platform = (u8)value;
2564 break;
2565
2566 case ODM_CMNINFO_INTERFACE:
2567 dm->support_interface = (u8)value;
2568 break;
2569
2570 case ODM_CMNINFO_MP_TEST_CHIP:
2571 dm->is_mp_chip = (u8)value;
2572 break;
2573
2574 case ODM_CMNINFO_IC_TYPE:
2575 dm->support_ic_type = (u32)value;
2576 break;
2577
2578 case ODM_CMNINFO_CUT_VER:
2579 dm->cut_version = (u8)value;
2580 break;
2581
2582 case ODM_CMNINFO_FAB_VER:
2583 dm->fab_version = (u8)value;
2584 break;
2585 case ODM_CMNINFO_FW_VER:
2586 dm->fw_version = (u8)value;
2587 break;
2588 case ODM_CMNINFO_FW_SUB_VER:
2589 dm->fw_sub_version = (u8)value;
2590 break;
2591 case ODM_CMNINFO_RFE_TYPE:
2592 #if (RTL8821C_SUPPORT)
2593 if (dm->support_ic_type & ODM_RTL8821C)
2594 dm->rfe_type_expand = (u8)value;
2595 else
2596 #endif
2597 dm->rfe_type = (u8)value;
2598
2599 #ifdef CONFIG_RFE_BY_HW_INFO
2600 phydm_init_hw_info_by_rfe(dm);
2601 #endif
2602 break;
2603
2604 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2605 dm->ant_div_type = (u8)value;
2606 break;
2607
2608 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2609 dm->with_extenal_ant_switch = (u8)value;
2610 break;
2611
2612 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2613 case ODM_CMNINFO_BE_FIX_TX_ANT:
2614 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2615 break;
2616 #endif
2617
2618 case ODM_CMNINFO_BOARD_TYPE:
2619 if (!dm->is_init_hw_info_by_rfe)
2620 dm->board_type = (u8)value;
2621 break;
2622
2623 case ODM_CMNINFO_PACKAGE_TYPE:
2624 if (!dm->is_init_hw_info_by_rfe)
2625 dm->package_type = (u8)value;
2626 break;
2627
2628 case ODM_CMNINFO_EXT_LNA:
2629 if (!dm->is_init_hw_info_by_rfe)
2630 dm->ext_lna = (u8)value;
2631 break;
2632
2633 case ODM_CMNINFO_5G_EXT_LNA:
2634 if (!dm->is_init_hw_info_by_rfe)
2635 dm->ext_lna_5g = (u8)value;
2636 break;
2637
2638 case ODM_CMNINFO_EXT_PA:
2639 if (!dm->is_init_hw_info_by_rfe)
2640 dm->ext_pa = (u8)value;
2641 break;
2642
2643 case ODM_CMNINFO_5G_EXT_PA:
2644 if (!dm->is_init_hw_info_by_rfe)
2645 dm->ext_pa_5g = (u8)value;
2646 break;
2647
2648 case ODM_CMNINFO_GPA:
2649 if (!dm->is_init_hw_info_by_rfe)
2650 dm->type_gpa = (u16)value;
2651 break;
2652
2653 case ODM_CMNINFO_APA:
2654 if (!dm->is_init_hw_info_by_rfe)
2655 dm->type_apa = (u16)value;
2656 break;
2657
2658 case ODM_CMNINFO_GLNA:
2659 if (!dm->is_init_hw_info_by_rfe)
2660 dm->type_glna = (u16)value;
2661 break;
2662
2663 case ODM_CMNINFO_ALNA:
2664 if (!dm->is_init_hw_info_by_rfe)
2665 dm->type_alna = (u16)value;
2666 break;
2667
2668 case ODM_CMNINFO_EXT_TRSW:
2669 if (!dm->is_init_hw_info_by_rfe)
2670 dm->ext_trsw = (u8)value;
2671 break;
2672 case ODM_CMNINFO_EXT_LNA_GAIN:
2673 dm->ext_lna_gain = (u8)value;
2674 break;
2675 case ODM_CMNINFO_PATCH_ID:
2676 dm->iot_table.win_patch_id = (u8)value;
2677 break;
2678 case ODM_CMNINFO_BINHCT_TEST:
2679 dm->is_in_hct_test = (boolean)value;
2680 break;
2681 case ODM_CMNINFO_BWIFI_TEST:
2682 dm->wifi_test = (u8)value;
2683 break;
2684 case ODM_CMNINFO_SMART_CONCURRENT:
2685 dm->is_dual_mac_smart_concurrent = (boolean)value;
2686 break;
2687 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2688 case ODM_CMNINFO_CONFIG_BB_RF:
2689 dm->config_bbrf = (boolean)value;
2690 break;
2691 #endif
2692 case ODM_CMNINFO_IQKPAOFF:
2693 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2694 break;
2695 case ODM_CMNINFO_REGRFKFREEENABLE:
2696 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2697 break;
2698 case ODM_CMNINFO_RFKFREEENABLE:
2699 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2700 break;
2701 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2702 dm->normal_rx_path = (u8)value;
2703 break;
2704 case ODM_CMNINFO_VALID_PATH_SET:
2705 dm->valid_path_set = (u8)value;
2706 break;
2707 case ODM_CMNINFO_EFUSE0X3D8:
2708 dm->efuse0x3d8 = (u8)value;
2709 break;
2710 case ODM_CMNINFO_EFUSE0X3D7:
2711 dm->efuse0x3d7 = (u8)value;
2712 break;
2713 case ODM_CMNINFO_ADVANCE_OTA:
2714 dm->p_advance_ota = (u8)value;
2715 break;
2716
2717 #ifdef CONFIG_PHYDM_DFS_MASTER
2718 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2719 dm->dfs_region_domain = (u8)value;
2720 break;
2721 #endif
2722 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2723 dm->soft_ap_special_setting = (u32)value;
2724 break;
2725
2726 case ODM_CMNINFO_X_CAP_SETTING:
2727 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2728 break;
2729
2730 case ODM_CMNINFO_DPK_EN:
2731 /*@dm->dpk_en = (u1Byte)value;*/
2732 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2733 break;
2734
2735 case ODM_CMNINFO_HP_HWID:
2736 dm->hp_hw_id = (boolean)value;
2737 break;
2738 case ODM_CMNINFO_TSSI_ENABLE:
2739 dm->en_tssi_mode = (u8)value;
2740 break;
2741 case ODM_CMNINFO_DIS_DPD:
2742 dm->en_dis_dpd = (boolean)value;
2743 break;
2744 case ODM_CMNINFO_EN_AUTO_BW_TH:
2745 dm->en_auto_bw_th = (u8)value;
2746 break;
2747 case ODM_CMNINFO_EN_NBI_DETECT:
2748 dm->en_nbi_detect = (boolean)value;
2749 break;
2750 #if (RTL8721D_SUPPORT)
2751 case ODM_CMNINFO_POWER_VOLTAGE:
2752 dm->power_voltage = (u8)value;
2753 break;
2754 case ODM_CMNINFO_ANTDIV_GPIO:
2755 dm->antdiv_gpio = (u8)value;
2756 break;
2757 case ODM_CMNINFO_PEAK_DETECT_MODE:
2758 dm->peak_detect_mode = (u8)value;
2759 break;
2760 #endif
2761 default:
2762 break;
2763 }
2764 }
2765
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2766 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2767 void *value)
2768 {
2769 /* @Hook call by reference pointer. */
2770 switch (cmn_info) {
2771 /* @Dynamic call by reference pointer. */
2772 case ODM_CMNINFO_TX_UNI:
2773 dm->num_tx_bytes_unicast = (u64 *)value;
2774 break;
2775
2776 case ODM_CMNINFO_RX_UNI:
2777 dm->num_rx_bytes_unicast = (u64 *)value;
2778 break;
2779
2780 case ODM_CMNINFO_BAND:
2781 dm->band_type = (u8 *)value;
2782 break;
2783
2784 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2785 dm->sec_ch_offset = (u8 *)value;
2786 break;
2787
2788 case ODM_CMNINFO_SEC_MODE:
2789 dm->security = (u8 *)value;
2790 break;
2791
2792 case ODM_CMNINFO_BW:
2793 dm->band_width = (u8 *)value;
2794 break;
2795
2796 case ODM_CMNINFO_CHNL:
2797 dm->channel = (u8 *)value;
2798 break;
2799
2800 case ODM_CMNINFO_SCAN:
2801 dm->is_scan_in_process = (boolean *)value;
2802 break;
2803
2804 case ODM_CMNINFO_POWER_SAVING:
2805 dm->is_power_saving = (boolean *)value;
2806 break;
2807
2808 case ODM_CMNINFO_TDMA:
2809 dm->is_tdma = (boolean *)value;
2810 break;
2811
2812 case ODM_CMNINFO_ONE_PATH_CCA:
2813 dm->one_path_cca = (u8 *)value;
2814 break;
2815
2816 case ODM_CMNINFO_DRV_STOP:
2817 dm->is_driver_stopped = (boolean *)value;
2818 break;
2819 case ODM_CMNINFO_INIT_ON:
2820 dm->pinit_adpt_in_progress = (boolean *)value;
2821 break;
2822
2823 case ODM_CMNINFO_ANT_TEST:
2824 dm->antenna_test = (u8 *)value;
2825 break;
2826
2827 case ODM_CMNINFO_NET_CLOSED:
2828 dm->is_net_closed = (boolean *)value;
2829 break;
2830
2831 case ODM_CMNINFO_FORCED_RATE:
2832 dm->forced_data_rate = (u16 *)value;
2833 break;
2834 case ODM_CMNINFO_ANT_DIV:
2835 dm->enable_antdiv = (u8 *)value;
2836 break;
2837 case ODM_CMNINFO_PATH_DIV:
2838 dm->enable_pathdiv = (u8 *)value;
2839 break;
2840 case ODM_CMNINFO_ADAPTIVE_SOML:
2841 dm->en_adap_soml = (u8 *)value;
2842 break;
2843 case ODM_CMNINFO_ADAPTIVITY:
2844 dm->edcca_mode = (u8 *)value;
2845 break;
2846
2847 case ODM_CMNINFO_P2P_LINK:
2848 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2849 break;
2850
2851 case ODM_CMNINFO_IS1ANTENNA:
2852 dm->is_1_antenna = (boolean *)value;
2853 break;
2854
2855 case ODM_CMNINFO_RFDEFAULTPATH:
2856 dm->rf_default_path = (u8 *)value;
2857 break;
2858
2859 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2860 dm->is_fcs_mode_enable = (boolean *)value;
2861 break;
2862
2863 case ODM_CMNINFO_HUBUSBMODE:
2864 dm->hub_usb_mode = (u8 *)value;
2865 break;
2866 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2867 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2868 break;
2869 case ODM_CMNINFO_TX_TP:
2870 dm->current_tx_tp = (u32 *)value;
2871 break;
2872 case ODM_CMNINFO_RX_TP:
2873 dm->current_rx_tp = (u32 *)value;
2874 break;
2875 case ODM_CMNINFO_SOUNDING_SEQ:
2876 dm->sounding_seq = (u8 *)value;
2877 break;
2878 #ifdef CONFIG_PHYDM_DFS_MASTER
2879 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2880 dm->dfs_master_enabled = (u8 *)value;
2881 break;
2882 #endif
2883
2884 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2885 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2886 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2887 break;
2888 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2889 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2890 break;
2891 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2892 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2893 break;
2894 #endif
2895
2896 case ODM_CMNINFO_SOFT_AP_MODE:
2897 dm->soft_ap_mode = (u32 *)value;
2898 break;
2899 case ODM_CMNINFO_MP_MODE:
2900 dm->mp_mode = (u8 *)value;
2901 break;
2902 case ODM_CMNINFO_INTERRUPT_MASK:
2903 dm->interrupt_mask = (u32 *)value;
2904 break;
2905 case ODM_CMNINFO_BB_OPERATION_MODE:
2906 dm->bb_op_mode = (u8 *)value;
2907 break;
2908 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2909 dm->manual_supportability = (u32 *)value;
2910 break;
2911 case ODM_CMNINFO_EN_DYM_BW_INDICATION:
2912 dm->dis_dym_bw_indication = (u8 *)value;
2913 break;
2914 #if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
2915 case ODM_ANTI_INTERFERENCE_EN:
2916 dm->anti_interference_en = (u8 *)value;
2917 break;
2918 #endif
2919 default:
2920 /*do nothing*/
2921 break;
2922 }
2923 }
2924
2925 /*@
2926 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2927 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2928 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2929 {
2930 /* This init variable may be changed in run time. */
2931 switch (cmn_info) {
2932 case ODM_CMNINFO_LINK_IN_PROGRESS:
2933 dm->is_link_in_process = (boolean)value;
2934 break;
2935
2936 case ODM_CMNINFO_ABILITY:
2937 dm->support_ability = (u64)value;
2938 break;
2939
2940 case ODM_CMNINFO_RF_TYPE:
2941 dm->rf_type = (u8)value;
2942 break;
2943
2944 case ODM_CMNINFO_WIFI_DIRECT:
2945 dm->is_wifi_direct = (boolean)value;
2946 break;
2947
2948 case ODM_CMNINFO_WIFI_DISPLAY:
2949 dm->is_wifi_display = (boolean)value;
2950 break;
2951
2952 case ODM_CMNINFO_LINK:
2953 dm->is_linked = (boolean)value;
2954 break;
2955
2956 case ODM_CMNINFO_CMW500LINK:
2957 dm->iot_table.is_linked_cmw500 = (boolean)value;
2958 break;
2959
2960 case ODM_CMNINFO_STATION_STATE:
2961 dm->bsta_state = (boolean)value;
2962 break;
2963
2964 case ODM_CMNINFO_RSSI_MIN:
2965 #if 0
2966 dm->rssi_min = (u8)value;
2967 #endif
2968 break;
2969
2970 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2971 dm->rssi_min_by_path = (u8)value;
2972 break;
2973
2974 case ODM_CMNINFO_DBG_COMP:
2975 dm->debug_components = (u64)value;
2976 break;
2977
2978 #ifdef ODM_CONFIG_BT_COEXIST
2979 /* The following is for BT HS mode and BT coexist mechanism. */
2980 case ODM_CMNINFO_BT_ENABLED:
2981 dm->bt_info_table.is_bt_enabled = (boolean)value;
2982 break;
2983
2984 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2985 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2986 break;
2987
2988 case ODM_CMNINFO_BT_HS_RSSI:
2989 dm->bt_info_table.bt_hs_rssi = (u8)value;
2990 break;
2991
2992 case ODM_CMNINFO_BT_OPERATION:
2993 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2994 break;
2995
2996 case ODM_CMNINFO_BT_LIMITED_DIG:
2997 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2998 break;
2999 #endif
3000
3001 case ODM_CMNINFO_AP_TOTAL_NUM:
3002 dm->ap_total_num = (u8)value;
3003 break;
3004
3005 #ifdef CONFIG_PHYDM_DFS_MASTER
3006 case ODM_CMNINFO_DFS_REGION_DOMAIN:
3007 dm->dfs_region_domain = (u8)value;
3008 break;
3009 #endif
3010
3011 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
3012 dm->is_bt_continuous_turn = (boolean)value;
3013 break;
3014 case ODM_CMNINFO_IS_DOWNLOAD_FW:
3015 dm->is_download_fw = (boolean)value;
3016 break;
3017 case ODM_CMNINFO_PHYDM_PATCH_ID:
3018 dm->iot_table.phydm_patch_id = (u32)value;
3019 break;
3020 case ODM_CMNINFO_RRSR_VAL:
3021 dm->dm_ra_table.rrsr_val_init = (u32)value;
3022 break;
3023 case ODM_CMNINFO_LINKED_BF_SUPPORT:
3024 dm->linked_bf_support = (u8)value;
3025 break;
3026 case ODM_CMNINFO_FLATNESS_TYPE:
3027 dm->flatness_type = (u8)value;
3028 break;
3029 case ODM_CMNINFO_TSSI_ENABLE:
3030 dm->en_tssi_mode = (u8)value;
3031 break;
3032 case ODM_CMNINFO_HUAWEI_HWID:
3033 dm->is_dig_low_bond = (boolean)value;
3034 break;
3035 case ODM_CMNINFO_ATHEROS_HWID:
3036 dm->is_R2R_CCA_MASKT_TIME_SHORT = (boolean)value;
3037 break;
3038 default:
3039 break;
3040 }
3041 }
3042
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)3043 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
3044 {
3045 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
3046 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3047 struct ccx_info *ccx_info = &dm->dm_ccx_info;
3048
3049 switch (info_type) {
3050 /*@=== [FA Relative] ===========================================*/
3051 case PHYDM_INFO_FA_OFDM:
3052 return fa_t->cnt_ofdm_fail;
3053
3054 case PHYDM_INFO_FA_CCK:
3055 return fa_t->cnt_cck_fail;
3056
3057 case PHYDM_INFO_FA_TOTAL:
3058 return fa_t->cnt_all;
3059
3060 case PHYDM_INFO_CCA_OFDM:
3061 return fa_t->cnt_ofdm_cca;
3062
3063 case PHYDM_INFO_CCA_CCK:
3064 return fa_t->cnt_cck_cca;
3065
3066 case PHYDM_INFO_CCA_ALL:
3067 return fa_t->cnt_cca_all;
3068
3069 case PHYDM_INFO_CRC32_OK_VHT:
3070 return fa_t->cnt_vht_crc32_ok;
3071
3072 case PHYDM_INFO_CRC32_OK_HT:
3073 return fa_t->cnt_ht_crc32_ok;
3074
3075 case PHYDM_INFO_CRC32_OK_LEGACY:
3076 return fa_t->cnt_ofdm_crc32_ok;
3077
3078 case PHYDM_INFO_CRC32_OK_CCK:
3079 return fa_t->cnt_cck_crc32_ok;
3080
3081 case PHYDM_INFO_CRC32_ERROR_VHT:
3082 return fa_t->cnt_vht_crc32_error;
3083
3084 case PHYDM_INFO_CRC32_ERROR_HT:
3085 return fa_t->cnt_ht_crc32_error;
3086
3087 case PHYDM_INFO_CRC32_ERROR_LEGACY:
3088 return fa_t->cnt_ofdm_crc32_error;
3089
3090 case PHYDM_INFO_CRC32_ERROR_CCK:
3091 return fa_t->cnt_cck_crc32_error;
3092
3093 case PHYDM_INFO_EDCCA_FLAG:
3094 return fa_t->edcca_flag;
3095
3096 case PHYDM_INFO_OFDM_ENABLE:
3097 return fa_t->ofdm_block_enable;
3098
3099 case PHYDM_INFO_CCK_ENABLE:
3100 return fa_t->cck_block_enable;
3101
3102 case PHYDM_INFO_DBG_PORT_0:
3103 return fa_t->dbg_port0;
3104
3105 case PHYDM_INFO_CRC32_OK_HT_AGG:
3106 return fa_t->cnt_ht_crc32_ok_agg;
3107
3108 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
3109 return fa_t->cnt_ht_crc32_error_agg;
3110
3111 /*@=== [DIG] ================================================*/
3112
3113 case PHYDM_INFO_CURR_IGI:
3114 return dig_t->cur_ig_value;
3115
3116 /*@=== [RSSI] ===============================================*/
3117 case PHYDM_INFO_RSSI_MIN:
3118 return (u32)dm->rssi_min;
3119
3120 case PHYDM_INFO_RSSI_MAX:
3121 return (u32)dm->rssi_max;
3122
3123 case PHYDM_INFO_CLM_RATIO:
3124 return (u32)ccx_info->clm_ratio;
3125 case PHYDM_INFO_NHM_RATIO:
3126 return (u32)ccx_info->nhm_ratio;
3127 case PHYDM_INFO_NHM_NOISE_PWR:
3128 return (u32)ccx_info->nhm_level;
3129 case PHYDM_INFO_NHM_PWR:
3130 return (u32)ccx_info->nhm_pwr;
3131 case PHYDM_INFO_NHM_ENV_RATIO:
3132 return (u32)ccx_info->nhm_env_ratio;
3133 case PHYDM_INFO_TXEN_CCK:
3134 return (u32)fa_t->cnt_cck_txen;
3135 case PHYDM_INFO_TXEN_OFDM:
3136 return (u32)fa_t->cnt_ofdm_txen;
3137 case PHYDM_INFO_NHM_IDLE_RATIO:
3138 return (u32)ccx_info->nhm_idle_ratio;
3139 case PHYDM_INFO_NHM_TX_RATIO:
3140 return (u32)ccx_info->nhm_tx_ratio;
3141 default:
3142 return 0xffffffff;
3143 }
3144 }
3145
3146 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)3147 void odm_init_all_work_items(struct dm_struct *dm)
3148 {
3149 void *adapter = dm->adapter;
3150 #if USE_WORKITEM
3151
3152 #ifdef CONFIG_ADAPTIVE_SOML
3153 odm_initialize_work_item(dm,
3154 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
3155 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
3156 (void *)adapter,
3157 "AdaptiveSOMLWorkitem");
3158 #endif
3159
3160 #ifdef ODM_EVM_ENHANCE_ANTDIV
3161 odm_initialize_work_item(dm,
3162 &dm->phydm_evm_antdiv_workitem,
3163 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
3164 (void *)adapter,
3165 "EvmAntdivWorkitem");
3166 #endif
3167
3168 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3169 odm_initialize_work_item(dm,
3170 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
3171 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
3172 (void *)adapter,
3173 "AntennaSwitchWorkitem");
3174 #endif
3175 #if (defined(CONFIG_HL_SMART_ANTENNA))
3176 odm_initialize_work_item(dm,
3177 &dm->dm_sat_table.hl_smart_antenna_workitem,
3178 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
3179 (void *)adapter,
3180 "hl_smart_ant_workitem");
3181
3182 odm_initialize_work_item(dm,
3183 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
3184 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
3185 (void *)adapter,
3186 "hl_smart_ant_decision_workitem");
3187 #endif
3188
3189 odm_initialize_work_item(
3190 dm,
3191 &dm->ra_rpt_workitem,
3192 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
3193 (void *)adapter,
3194 "ra_rpt_workitem");
3195
3196 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3197 odm_initialize_work_item(
3198 dm,
3199 &dm->fast_ant_training_workitem,
3200 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
3201 (void *)adapter,
3202 "fast_ant_training_workitem");
3203 #endif
3204
3205 #endif /*#if USE_WORKITEM*/
3206
3207 #ifdef PHYDM_BEAMFORMING_SUPPORT
3208 odm_initialize_work_item(
3209 dm,
3210 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
3211 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
3212 (void *)adapter,
3213 "txbf_enter_work_item");
3214
3215 odm_initialize_work_item(
3216 dm,
3217 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
3218 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
3219 (void *)adapter,
3220 "txbf_leave_work_item");
3221
3222 odm_initialize_work_item(
3223 dm,
3224 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
3225 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
3226 (void *)adapter,
3227 "txbf_fw_ndpa_work_item");
3228
3229 odm_initialize_work_item(
3230 dm,
3231 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
3232 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
3233 (void *)adapter,
3234 "txbf_clk_work_item");
3235
3236 odm_initialize_work_item(
3237 dm,
3238 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
3239 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
3240 (void *)adapter,
3241 "txbf_rate_work_item");
3242
3243 odm_initialize_work_item(
3244 dm,
3245 &dm->beamforming_info.txbf_info.txbf_status_work_item,
3246 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
3247 (void *)adapter,
3248 "txbf_status_work_item");
3249
3250 odm_initialize_work_item(
3251 dm,
3252 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
3253 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
3254 (void *)adapter,
3255 "txbf_reset_tx_path_work_item");
3256
3257 odm_initialize_work_item(
3258 dm,
3259 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
3260 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
3261 (void *)adapter,
3262 "txbf_get_tx_rate_work_item");
3263 #endif
3264
3265 #if (PHYDM_LA_MODE_SUPPORT == 1)
3266 odm_initialize_work_item(
3267 dm,
3268 &dm->adcsmp.adc_smp_work_item,
3269 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3270 (void *)adapter,
3271 "adc_smp_work_item");
3272
3273 odm_initialize_work_item(
3274 dm,
3275 &dm->adcsmp.adc_smp_work_item_1,
3276 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3277 (void *)adapter,
3278 "adc_smp_work_item_1");
3279 #endif
3280 }
3281
odm_free_all_work_items(struct dm_struct * dm)3282 void odm_free_all_work_items(struct dm_struct *dm)
3283 {
3284 #if USE_WORKITEM
3285
3286 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3287 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
3288 #endif
3289
3290 #ifdef CONFIG_ADAPTIVE_SOML
3291 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
3292 #endif
3293
3294 #ifdef ODM_EVM_ENHANCE_ANTDIV
3295 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
3296 #endif
3297
3298 #if (defined(CONFIG_HL_SMART_ANTENNA))
3299 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
3300 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
3301 #endif
3302
3303 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3304 odm_free_work_item(&dm->fast_ant_training_workitem);
3305 #endif
3306 odm_free_work_item(&dm->ra_rpt_workitem);
3307 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
3308 #endif
3309
3310 #ifdef PHYDM_BEAMFORMING_SUPPORT
3311 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
3312 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
3313 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
3314 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
3315 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
3316 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
3317 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
3318 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
3319 #endif
3320
3321 #if (PHYDM_LA_MODE_SUPPORT == 1)
3322 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
3323 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
3324 #endif
3325 }
3326 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
3327
odm_init_all_timers(struct dm_struct * dm)3328 void odm_init_all_timers(struct dm_struct *dm)
3329 {
3330 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3331 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
3332 #endif
3333 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
3334 #ifdef IS_USE_NEW_TDMA
3335 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
3336 #endif
3337 #endif
3338 #ifdef CONFIG_ADAPTIVE_SOML
3339 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
3340 #endif
3341 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3342 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3343 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
3344 #endif
3345 #endif
3346
3347 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3348 odm_initialize_timer(dm, &dm->sbdcnt_timer,
3349 (void *)phydm_sbd_callback, NULL, "SbdTimer");
3350 #ifdef PHYDM_BEAMFORMING_SUPPORT
3351 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
3352 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
3353 "txbf_fw_ndpa_timer");
3354 #endif
3355 #endif
3356
3357 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3358 #ifdef PHYDM_BEAMFORMING_SUPPORT
3359 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
3360 (void *)beamforming_sw_timer_callback, NULL,
3361 "beamforming_timer");
3362 #endif
3363 #endif
3364 }
3365
odm_cancel_all_timers(struct dm_struct * dm)3366 void odm_cancel_all_timers(struct dm_struct *dm)
3367 {
3368 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3369 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
3370 if (dm->adapter == NULL)
3371 return;
3372 #endif
3373
3374 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3375 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
3376 #endif
3377 #ifdef PHYDM_TDMA_DIG_SUPPORT
3378 #ifdef IS_USE_NEW_TDMA
3379 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
3380 #endif
3381 #endif
3382 #ifdef CONFIG_ADAPTIVE_SOML
3383 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
3384 #endif
3385 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3386 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3387 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
3388 #endif
3389 #endif
3390
3391 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3392 odm_cancel_timer(dm, &dm->sbdcnt_timer);
3393 #ifdef PHYDM_BEAMFORMING_SUPPORT
3394 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3395 #endif
3396 #endif
3397
3398 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3399 #ifdef PHYDM_BEAMFORMING_SUPPORT
3400 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
3401 #endif
3402 #endif
3403 }
3404
odm_release_all_timers(struct dm_struct * dm)3405 void odm_release_all_timers(struct dm_struct *dm)
3406 {
3407 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3408 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
3409 #endif
3410 #ifdef PHYDM_TDMA_DIG_SUPPORT
3411 #ifdef IS_USE_NEW_TDMA
3412 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
3413 #endif
3414 #endif
3415 #ifdef CONFIG_ADAPTIVE_SOML
3416 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
3417 #endif
3418 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3419 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3420 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
3421 #endif
3422 #endif
3423
3424 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3425 odm_release_timer(dm, &dm->sbdcnt_timer);
3426 #ifdef PHYDM_BEAMFORMING_SUPPORT
3427 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3428 #endif
3429 #endif
3430
3431 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3432 #ifdef PHYDM_BEAMFORMING_SUPPORT
3433 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
3434 #endif
3435 #endif
3436 }
3437
3438 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)3439 void odm_init_all_threads(
3440 struct dm_struct *dm)
3441 {
3442 #ifdef TPT_THREAD
3443 k_tpt_task_init(dm->priv);
3444 #endif
3445 }
3446
odm_stop_all_threads(struct dm_struct * dm)3447 void odm_stop_all_threads(
3448 struct dm_struct *dm)
3449 {
3450 #ifdef TPT_THREAD
3451 k_tpt_task_stop(dm->priv);
3452 #endif
3453 }
3454 #endif
3455
3456 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3457 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
3458 * 2012/11/05
3459 */
odm_dtc(struct dm_struct * dm)3460 void odm_dtc(struct dm_struct *dm)
3461 {
3462 #ifdef CONFIG_DM_RESP_TXAGC
3463 /* RSSI higher than this value, start to decade TX power */
3464 #define DTC_BASE 35
3465
3466 /* RSSI lower than this value, start to increase TX power */
3467 #define DTC_DWN_BASE (DTC_BASE - 5)
3468
3469 /* RSSI vs TX power step mapping: decade TX power */
3470 static const u8 dtc_table_down[] = {
3471 DTC_BASE,
3472 (DTC_BASE + 5),
3473 (DTC_BASE + 10),
3474 (DTC_BASE + 15),
3475 (DTC_BASE + 20),
3476 (DTC_BASE + 25)};
3477
3478 /* RSSI vs TX power step mapping: increase TX power */
3479 static const u8 dtc_table_up[] = {
3480 DTC_DWN_BASE,
3481 (DTC_DWN_BASE - 5),
3482 (DTC_DWN_BASE - 10),
3483 (DTC_DWN_BASE - 15),
3484 (DTC_DWN_BASE - 15),
3485 (DTC_DWN_BASE - 20),
3486 (DTC_DWN_BASE - 20),
3487 (DTC_DWN_BASE - 25),
3488 (DTC_DWN_BASE - 25),
3489 (DTC_DWN_BASE - 30),
3490 (DTC_DWN_BASE - 35)};
3491
3492 u8 i;
3493 u8 dtc_steps = 0;
3494 u8 sign;
3495 u8 resp_txagc = 0;
3496
3497 if (dm->rssi_min > DTC_BASE) {
3498 /* need to decade the CTS TX power */
3499 sign = 1;
3500 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
3501 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
3502 break;
3503 else
3504 dtc_steps++;
3505 }
3506 }
3507 #if 0
3508 else if (dm->rssi_min > DTC_DWN_BASE) {
3509 /* needs to increase the CTS TX power */
3510 sign = 0;
3511 dtc_steps = 1;
3512 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3513 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3514 break;
3515 else
3516 dtc_steps++;
3517 }
3518 }
3519 #endif
3520 else {
3521 sign = 0;
3522 dtc_steps = 0;
3523 }
3524
3525 resp_txagc = dtc_steps | (sign << 4);
3526 resp_txagc = resp_txagc | (resp_txagc << 5);
3527 odm_write_1byte(dm, 0x06d9, resp_txagc);
3528
3529 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3530 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3531 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3532 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3533 }
3534
3535 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3536
3537 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3538 void phydm_dc_cancellation(struct dm_struct *dm)
3539 {
3540 #ifdef PHYDM_DC_CANCELLATION
3541 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3542 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3543 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3544 u8 path = RF_PATH_A;
3545 u8 set_result;
3546
3547 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3548 return;
3549 if ((dm->support_ic_type & ODM_RTL8188F) &&
3550 dm->cut_version < ODM_CUT_D)
3551 return;
3552 if ((dm->support_ic_type & ODM_RTL8192F) &&
3553 dm->cut_version == ODM_CUT_A)
3554 return;
3555 if (*dm->band_width == CHANNEL_WIDTH_5)
3556 return;
3557 if (*dm->band_width == CHANNEL_WIDTH_10)
3558 return;
3559
3560 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3561
3562 /*@DC_Estimation (only for 2x2 ic now) */
3563
3564 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3565 if (path > RF_PATH_A &&
3566 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3567 ODM_RTL8710B | ODM_RTL8721D |
3568 ODM_RTL8710C | ODM_RTL8723D))
3569 break;
3570 else if (path > RF_PATH_B &&
3571 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3572 break;
3573 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3574 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3575 return;
3576 }
3577 odm_write_dig(dm, 0x7e);
3578 /*@Disable LNA*/
3579 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3580 ODM_RTL8710C))
3581 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3582 /*Turn off 3-wire*/
3583 phydm_stop_3_wire(dm, PHYDM_SET);
3584 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3585 ODM_RTL8710B)) {
3586 /*set debug port to 0x235*/
3587 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3588 PHYDM_DBG(dm, ODM_COMP_API,
3589 "Set Debug port Fail\n");
3590 return;
3591 }
3592 } else if (dm->support_ic_type & (ODM_RTL8721D |
3593 ODM_RTL8710C)) {
3594 /*set debug port to 0x200*/
3595 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3596 PHYDM_DBG(dm, ODM_COMP_API,
3597 "Set Debug port Fail\n");
3598 return;
3599 }
3600 } else if (dm->support_ic_type & ODM_RTL8821C) {
3601 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3602 /*set debug port to 0x200*/
3603 PHYDM_DBG(dm, ODM_COMP_API,
3604 "Set Debug port Fail\n");
3605 return;
3606 }
3607 phydm_bb_dbg_port_header_sel(dm, 0x0);
3608 } else if (dm->support_ic_type & ODM_RTL8822B) {
3609 if (path == RF_PATH_A &&
3610 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3611 /*set debug port to 0x200*/
3612 PHYDM_DBG(dm, ODM_COMP_API,
3613 "Set Debug port Fail\n");
3614 return;
3615 }
3616 if (path == RF_PATH_B &&
3617 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3618 /*set debug port to 0x200*/
3619 PHYDM_DBG(dm, ODM_COMP_API,
3620 "Set Debug port Fail\n");
3621 return;
3622 }
3623 phydm_bb_dbg_port_header_sel(dm, 0x0);
3624 } else if (dm->support_ic_type & ODM_RTL8192F) {
3625 if (path == RF_PATH_A &&
3626 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3627 /*set debug port to 0x235*/
3628 PHYDM_DBG(dm, ODM_COMP_API,
3629 "Set Debug port Fail\n");
3630 return;
3631 }
3632 if (path == RF_PATH_B &&
3633 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3634 /*set debug port to 0x23d*/
3635 PHYDM_DBG(dm, ODM_COMP_API,
3636 "Set Debug port Fail\n");
3637 return;
3638 }
3639 }
3640
3641 /*@disable CCK DCNF*/
3642 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3643
3644 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3645
3646 phydm_stop_ck320(dm, true); /*stop ck320*/
3647
3648 /* the same debug port both for path-a and path-b*/
3649 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3650
3651 phydm_stop_ck320(dm, false); /*start ck320*/
3652
3653 phydm_release_bb_dbg_port(dm);
3654 /* @Turn on 3-wire*/
3655 phydm_stop_3_wire(dm, PHYDM_REVERT);
3656 /* @Enable LNA*/
3657 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3658 ODM_RTL8710C))
3659 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3660
3661 odm_write_dig(dm, 0x20);
3662
3663 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3664
3665 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3666 }
3667
3668 /*@DC_Cancellation*/
3669 /*@DC compensation to CCK data path*/
3670 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3671 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3672 ODM_RTL8710B)) {
3673 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3674 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3675
3676 /*@Before filling into registers,
3677 *offset should be multiplexed (-1)
3678 */
3679 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3680 (0x400 - offset_i_hex[0]) :
3681 (0x1ff - offset_i_hex[0]);
3682 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3683 (0x400 - offset_q_hex[0]) :
3684 (0x1ff - offset_q_hex[0]);
3685
3686 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3687 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3688 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3689 /* Path-a */
3690 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3691 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3692
3693 /*@Before filling into registers,
3694 *offset should be multiplexed (-1)
3695 */
3696 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3697 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3698
3699 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3700 (0x3c0 & offset_i_hex[0]) >> 6);
3701 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3702 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3703 (0x3c0 & offset_q_hex[0]) >> 6);
3704 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3705
3706 /* Path-b */
3707 if (dm->rf_type > RF_1T1R) {
3708 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3709 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3710
3711 /*@Before filling into registers,
3712 *offset should be multiplexed (-1)
3713 */
3714 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3715 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3716
3717 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3718 (0x3c0 & offset_i_hex[1]) >> 6);
3719 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3720 0x3f & offset_i_hex[1]);
3721 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3722 (0x3c0 & offset_q_hex[1]) >> 6);
3723 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3724 0x3f & offset_q_hex[1]);
3725 }
3726 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3727 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3728 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3729 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3730
3731 /*@Before filling into registers,
3732 *offset should be multiplexed (-1)
3733 */
3734 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3735 (0x400 - offset_i_hex[0]) :
3736 (0xff - offset_i_hex[0]);
3737 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3738 (0x400 - offset_q_hex[0]) :
3739 (0xff - offset_q_hex[0]);
3740 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3741 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3742 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3743
3744 /* Path-b */
3745 if (dm->rf_type > RF_1T1R) {
3746 /* @I:df4[27:18],Q:df4[17:8]*/
3747 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3748 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3749
3750 /*@Before filling into registers,
3751 *offset should be multiplexed (-1)
3752 */
3753 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3754 (0x400 - offset_i_hex[1]) :
3755 (0xff - offset_i_hex[1]);
3756 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3757 (0x400 - offset_q_hex[1]) :
3758 (0xff - offset_q_hex[1]);
3759 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3760 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3761 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3762 }
3763 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
3764 /*judy modified 20180517*/
3765 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3766 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3767
3768 if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1)
3769 || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) {
3770 /*@Discard outliers*/
3771 offset_i_hex[0] = 0x0;
3772 offset_q_hex[0] = 0x0;
3773 } else {
3774 /*@Before filling into registers,
3775 *offset should be multiplexed (-1)
3776 */
3777 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3778 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3779 }
3780 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3781 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3782 }
3783 #endif
3784 }
3785
phydm_receiver_blocking(void * dm_void)3786 void phydm_receiver_blocking(void *dm_void)
3787 {
3788 #ifdef CONFIG_RECEIVER_BLOCKING
3789 struct dm_struct *dm = (struct dm_struct *)dm_void;
3790 u32 chnl = *dm->channel;
3791 u8 bw = *dm->band_width;
3792 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3793
3794 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3795 *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
3796 return;
3797
3798 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3799 dm->support_ic_type & ODM_RTL8192E) {
3800 /*@8188E_T version*/
3801 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3802 goto end;
3803
3804 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3805 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3806 PHYDM_DONT_CARE);
3807 dm->is_rx_blocking_en = true;
3808 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3809 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3810 PHYDM_DONT_CARE);
3811 dm->is_rx_blocking_en = true;
3812 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3813 phydm_nbi_enable(dm, FUNC_DISABLE);
3814 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3815 dm->is_rx_blocking_en = false;
3816 }
3817 return;
3818 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3819 /*@8188E_S version*/
3820 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3821 goto end;
3822
3823 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3824 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3825 PHYDM_DONT_CARE);
3826 dm->is_rx_blocking_en = true;
3827 } else if (dm->is_rx_blocking_en && chnl != 13) {
3828 phydm_nbi_enable(dm, FUNC_DISABLE);
3829 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3830 dm->is_rx_blocking_en = false;
3831 }
3832 return;
3833 }
3834
3835 end:
3836 if (dm->is_rx_blocking_en) {
3837 phydm_nbi_enable(dm, FUNC_DISABLE);
3838 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3839 dm->is_rx_blocking_en = false;
3840 }
3841 #endif
3842 }
3843
phydm_dyn_bw_indication(void * dm_void)3844 void phydm_dyn_bw_indication(void *dm_void)
3845 {
3846 #ifdef CONFIG_BW_INDICATION
3847 struct dm_struct *dm = (struct dm_struct *)dm_void;
3848 u8 en_auto_bw_th = dm->en_auto_bw_th;
3849
3850 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
3851 return;
3852
3853 /*driver decide bw cobime timing*/
3854 if (dm->dis_dym_bw_indication) {
3855 if (*dm->dis_dym_bw_indication)
3856 return;
3857 }
3858
3859 /*check for auto bw*/
3860 if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
3861 phydm_bw_fixed_enable(dm, FUNC_DISABLE);
3862 return;
3863 }
3864
3865 phydm_bw_fixed_setting(dm);
3866 #endif
3867 }
3868
3869