1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
34 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
35 RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
36 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
37 RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
38 RTL8197G_SUPPORT == 1 || RTL8814C_SUPPORT == 1 )
39
_iqk_check_if_reload(void * dm_void)40 void _iqk_check_if_reload(void *dm_void)
41 {
42 struct dm_struct *dm = (struct dm_struct *)dm_void;
43 struct dm_iqk_info *iqk_info = &dm->IQK_info;
44
45 iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
46 }
47
_iqk_page_switch(void * dm_void)48 void _iqk_page_switch(void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51
52 if (dm->support_ic_type == ODM_RTL8821C)
53 odm_write_4byte(dm, 0x1b00, 0xf8000008);
54 else
55 odm_write_4byte(dm, 0x1b00, 0xf800000a);
56 }
57
halrf_psd_log2base(u32 val)58 u32 halrf_psd_log2base(u32 val)
59 {
60 u8 j;
61 u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
62 u32 result, val_fractiond_b = 0;
63 u32 table_fraction[21] = {
64 0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
65 100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
66
67 if (val == 0)
68 return 0;
69
70 tmp = val;
71
72 while (1) {
73 if (tmp == 1)
74 break;
75
76 tmp = (tmp >> 1);
77 shiftcount++;
78 }
79
80 val_integerd_b = shiftcount + 1;
81
82 tmp2 = 1;
83 for (j = 1; j <= val_integerd_b; j++)
84 tmp2 = tmp2 * 2;
85
86 tmp = (val * 100) / tmp2;
87 tindex = tmp / 5;
88
89 if (tindex > 20)
90 tindex = 20;
91
92 val_fractiond_b = table_fraction[tindex];
93
94 result = val_integerd_b * 100 - val_fractiond_b;
95
96 return result;
97 }
98 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
99 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
100 RTL8814C_SUPPORT == 1)
halrf_iqk_xym_enable(struct dm_struct * dm,u8 xym_enable)101 void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)
102 {
103 struct dm_iqk_info *iqk_info = &dm->IQK_info;
104
105 if (xym_enable == 0)
106 iqk_info->xym_read = false;
107 else
108 iqk_info->xym_read = true;
109
110 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ",
111 (iqk_info->xym_read ? "true" : "false"));
112 }
113
114 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_read(void * dm_void,u8 path,u8 xym_type)115 void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)
116 {
117 struct dm_struct *dm = (struct dm_struct *)dm_void;
118 struct dm_iqk_info *iqk_info = &dm->IQK_info;
119 u8 i, start, num;
120 u32 tmp1, tmp2;
121
122 if (!iqk_info->xym_read)
123 return;
124
125 if (*dm->band_width == 0) {
126 start = 3;
127 num = 4;
128 } else if (*dm->band_width == 1) {
129 start = 2;
130 num = 6;
131 } else {
132 start = 0;
133 num = 10;
134 }
135
136 odm_write_4byte(dm, 0x1b00, 0xf8000008);
137 tmp1 = odm_read_4byte(dm, 0x1b1c);
138 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
139
140 odm_write_4byte(dm, 0x1b00, 0xf800000a);
141 tmp2 = odm_read_4byte(dm, 0x1b1c);
142 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
143
144 for (path = 0; path < 2; path++) {
145 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
146 switch (xym_type) {
147 case 0:
148 for (i = 0; i < num; i++) {
149 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
150 odm_write_4byte(dm, 0x1b14, 0x0);
151 iqk_info->rx_xym[path][i] =
152 odm_read_4byte(dm, 0x1b38);
153 }
154 break;
155 case 1:
156 for (i = 0; i < num; i++) {
157 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
158 odm_write_4byte(dm, 0x1b14, 0x0);
159 iqk_info->tx_xym[path][i] =
160 odm_read_4byte(dm, 0x1b38);
161 }
162 break;
163 case 2:
164 for (i = 0; i < 6; i++) {
165 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
166 odm_write_4byte(dm, 0x1b14, 0x0);
167 iqk_info->gs1_xym[path][i] =
168 odm_read_4byte(dm, 0x1b38);
169 }
170 break;
171 case 3:
172 for (i = 0; i < 6; i++) {
173 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
174 odm_write_4byte(dm, 0x1b14, 0x0);
175 iqk_info->gs2_xym[path][i] =
176 odm_read_4byte(dm, 0x1b38);
177 }
178 break;
179 case 4:
180 for (i = 0; i < 6; i++) {
181 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
182 odm_write_4byte(dm, 0x1b14, 0x0);
183 iqk_info->rxk1_xym[path][i] =
184 odm_read_4byte(dm, 0x1b38);
185 }
186 break;
187 }
188 odm_write_4byte(dm, 0x1b38, 0x20000000);
189 odm_write_4byte(dm, 0x1b00, 0xf8000008);
190 odm_write_4byte(dm, 0x1b1c, tmp1);
191 odm_write_4byte(dm, 0x1b00, 0xf800000a);
192 odm_write_4byte(dm, 0x1b1c, tmp2);
193 _iqk_page_switch(dm);
194 }
195 }
196
197 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_show(struct dm_struct * dm,u8 xym_type)198 void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)
199 {
200 u8 num, path, path_num, i;
201 struct dm_iqk_info *iqk_info = &dm->IQK_info;
202
203 if (dm->rf_type == RF_1T1R)
204 path_num = 0x1;
205 else if (dm->rf_type == RF_2T2R)
206 path_num = 0x2;
207 else
208 path_num = 0x4;
209
210 if (*dm->band_width == CHANNEL_WIDTH_20)
211 num = 4;
212 else if (*dm->band_width == CHANNEL_WIDTH_40)
213 num = 6;
214 else
215 num = 10;
216
217 for (path = 0; path < path_num; path++) {
218 switch (xym_type) {
219 case 0:
220 for (i = 0; i < num; i++)
221 RF_DBG(dm, DBG_RF_IQK,
222 "[IQK]%-20s %-2d: 0x%x\n",
223 (path == 0) ? "PATH A RX-XYM " :
224 "PATH B RX-XYM", i,
225 iqk_info->rx_xym[path][i]);
226 break;
227 case 1:
228 for (i = 0; i < num; i++)
229 RF_DBG(dm, DBG_RF_IQK,
230 "[IQK]%-20s %-2d: 0x%x\n",
231 (path == 0) ? "PATH A TX-XYM " :
232 "PATH B TX-XYM", i,
233 iqk_info->tx_xym[path][i]);
234 break;
235 case 2:
236 for (i = 0; i < 6; i++)
237 RF_DBG(dm, DBG_RF_IQK,
238 "[IQK]%-20s %-2d: 0x%x\n",
239 (path == 0) ? "PATH A GS1-XYM " :
240 "PATH B GS1-XYM", i,
241 iqk_info->gs1_xym[path][i]);
242 break;
243 case 3:
244 for (i = 0; i < 6; i++)
245 RF_DBG(dm, DBG_RF_IQK,
246 "[IQK]%-20s %-2d: 0x%x\n",
247 (path == 0) ? "PATH A GS2-XYM " :
248 "PATH B GS2-XYM", i,
249 iqk_info->gs2_xym[path][i]);
250 break;
251 case 4:
252 for (i = 0; i < 6; i++)
253 RF_DBG(dm, DBG_RF_IQK,
254 "[IQK]%-20s %-2d: 0x%x\n",
255 (path == 0) ? "PATH A RXK1-XYM " :
256 "PATH B RXK1-XYM", i,
257 iqk_info->rxk1_xym[path][i]);
258 break;
259 }
260 }
261 }
262
halrf_iqk_xym_dump(void * dm_void)263 void halrf_iqk_xym_dump(void *dm_void)
264 {
265 u32 tmp1, tmp2;
266 struct dm_struct *dm = (struct dm_struct *)dm_void;
267
268 odm_write_4byte(dm, 0x1b00, 0xf8000008);
269 tmp1 = odm_read_4byte(dm, 0x1b1c);
270 odm_write_4byte(dm, 0x1b00, 0xf800000a);
271 tmp2 = odm_read_4byte(dm, 0x1b1c);
272 #if 0
273 /*halrf_iqk_xym_read(dm, xym_type);*/
274 #endif
275 odm_write_4byte(dm, 0x1b00, 0xf8000008);
276 odm_write_4byte(dm, 0x1b1c, tmp1);
277 odm_write_4byte(dm, 0x1b00, 0xf800000a);
278 odm_write_4byte(dm, 0x1b1c, tmp2);
279 _iqk_page_switch(dm);
280 }
281 #endif
halrf_iqk_info_dump(void * dm_void,u32 * _used,char * output,u32 * _out_len)282 void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
283 {
284 struct dm_struct *dm = (struct dm_struct *)dm_void;
285 u32 used = *_used;
286 u32 out_len = *_out_len;
287 u8 rf_path, j, reload_iqk = 0;
288 u32 tmp;
289 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
290 boolean iqk_result[2][NUM][2];
291 struct dm_iqk_info *iqk_info = &dm->IQK_info;
292
293 if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))
294 return;
295
296 /* IQK INFO */
297 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
298 "% IQK Info %");
299 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
300 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
301 "Driver-IQK");
302
303 reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
304 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
305 "reload", (reload_iqk) ? "True" : "False");
306
307 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
308 "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
309 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
310 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
311 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
312 RTL8814C_SUPPORT == 1 )
313 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
314 "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
315 #endif
316
317 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n",
318 "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
319
320 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n",
321 "channel", *dm->channel);
322
323 if (*dm->band_width == CHANNEL_WIDTH_20)
324 PDM_SNPF(out_len, used, output + used, out_len - used,
325 "%-20s: %s\n", "bandwidth", "BW_20");
326 else if (*dm->band_width == CHANNEL_WIDTH_40)
327 PDM_SNPF(out_len, used, output + used, out_len - used,
328 "%-20s: %s\n", "bandwidth", "BW_40");
329 else if (*dm->band_width == CHANNEL_WIDTH_80)
330 PDM_SNPF(out_len, used, output + used, out_len - used,
331 "%-20s: %s\n", "bandwidth", "BW_80");
332 else if (*dm->band_width == CHANNEL_WIDTH_160)
333 PDM_SNPF(out_len, used, output + used, out_len - used,
334 "%-20s: %s\n", "bandwidth", "BW_160");
335 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
336 PDM_SNPF(out_len, used, output + used, out_len - used,
337 "%-20s: %s\n", "bandwidth", "BW_80_80");
338 else
339 PDM_SNPF(out_len, used, output + used, out_len - used,
340 "%-20s: %s\n", "bandwidth", "BW_UNKNOWN");
341
342 PDM_SNPF(out_len, used, output + used, out_len - used,
343 "%-20s: %llu %s\n", "progressing_time",
344 dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
345
346 tmp = odm_read_4byte(dm, 0x1bf0);
347 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
348 for (j = 0; j < 2; j++)
349 iqk_result[0][rf_path][j] = (boolean)
350 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
351
352 PDM_SNPF(out_len, used, output + used, out_len - used,
353 "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
354 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
355 "PATH_A-Tx result",
356 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
357 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
358 "PATH_A-Rx result",
359 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
360 #if (RTL8822B_SUPPORT == 1)
361 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
362 "PATH_B-Tx result",
363 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
364 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
365 "PATH_B-Rx result",
366 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
367 #endif
368 *_used = used;
369 *_out_len = out_len;
370 }
371
halrf_get_fw_version(void * dm_void)372 void halrf_get_fw_version(void *dm_void)
373 {
374 struct dm_struct *dm = (struct dm_struct *)dm_void;
375 struct _hal_rf_ *rf = &dm->rf_table;
376
377 rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;
378 }
379
halrf_iqk_dbg(void * dm_void)380 void halrf_iqk_dbg(void *dm_void)
381 {
382 struct dm_struct *dm = (struct dm_struct *)dm_void;
383 u8 rf_path, j;
384 u32 tmp;
385 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
386 boolean iqk_result[2][NUM][2];
387 struct dm_iqk_info *iqk_info = &dm->IQK_info;
388 struct _hal_rf_ *rf = &dm->rf_table;
389
390 /* IQK INFO */
391 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
392
393 RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
394 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
395 "Driver-IQK");
396
397 if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
398 halrf_get_fw_version(dm);
399 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver);
400 } else {
401 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER);
402 }
403
404 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload",
405 (iqk_info->is_reload) ? "True" : "False");
406
407 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
408 dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
409
410 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel);
411
412 if (*dm->band_width == CHANNEL_WIDTH_20)
413 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20");
414 else if (*dm->band_width == CHANNEL_WIDTH_40)
415 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40");
416 else if (*dm->band_width == CHANNEL_WIDTH_80)
417 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80");
418 else if (*dm->band_width == CHANNEL_WIDTH_160)
419 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160");
420 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
421 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80_80");
422 else
423 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth",
424 "BW_UNKNOWN");
425 #if 0
426 /*
427 * RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n",
428 * "progressing_time",
429 * dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
430 */
431 #endif
432 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden",
433 (iqk_info->rfk_forbidden) ? "True" : "False");
434 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
435 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
436 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
437 RTL8814C_SUPPORT == 1)
438 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
439 (iqk_info->segment_iqk) ? "True" : "False");
440 #endif
441
442 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
443 dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
444
445 tmp = odm_read_4byte(dm, 0x1bf0);
446 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
447 for (j = 0; j < 2; j++)
448 iqk_result[0][rf_path][j] = (boolean)
449 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
450
451 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
452 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8",
453 odm_read_4byte(dm, 0x1be8));
454 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result",
455 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
456 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result",
457 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
458 #if (RTL8822B_SUPPORT == 1)
459 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result",
460 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
461 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result",
462 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
463 #endif
464 }
465
halrf_lck_dbg(struct dm_struct * dm)466 void halrf_lck_dbg(struct dm_struct *dm)
467 {
468 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======");
469 #if 0
470 /*RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
471 * (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));
472 */
473 #endif
474 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
475 dm->rf_calibrate_info.lck_progressing_time, "(ms)");
476 }
phydm_get_iqk_cfir(void * dm_void,u8 idx,u8 path,boolean debug)477 void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)
478 {
479 struct dm_struct *dm = (struct dm_struct *)dm_void;
480
481 switch (dm->support_ic_type) {
482 #if (RTL8822B_SUPPORT == 1)
483 case ODM_RTL8822B:
484 phy_get_iqk_cfir_8822b(dm, idx, path, debug);
485 break;
486 #endif
487 #if (RTL8822C_SUPPORT == 1)
488 case ODM_RTL8822C:
489 phy_get_iqk_cfir_8822c(dm, idx, path, debug);
490 break;
491 #endif
492 #if (RTL8814B_SUPPORT == 1)
493 case ODM_RTL8814B:
494 phy_get_iqk_cfir_8814b(dm, idx, path, debug);
495 break;
496 #endif
497 #if (RTL8814C_SUPPORT == 1)
498 case ODM_RTL8814C:
499 phy_get_iqk_cfir_8814c(dm, idx, path, debug);
500 break;
501 #endif
502
503 default:
504 break;
505 }
506 }
507
508
halrf_iqk_dbg_cfir_backup(void * dm_void)509 void halrf_iqk_dbg_cfir_backup(void *dm_void)
510 {
511 struct dm_struct *dm = (struct dm_struct *)dm_void;
512 struct dm_iqk_info *iqk_info = &dm->IQK_info;
513 u8 path, idx, i;
514
515 switch (dm->support_ic_type) {
516 #if (RTL8822B_SUPPORT == 1)
517 case ODM_RTL8822B:
518 phy_iqk_dbg_cfir_backup_8822b(dm);
519 break;
520 #endif
521 #if (RTL8822C_SUPPORT == 1)
522 case ODM_RTL8822C:
523 phy_iqk_dbg_cfir_backup_8822c(dm);
524 break;
525 #endif
526 #if (RTL8814B_SUPPORT == 1)
527 case ODM_RTL8814B:
528 phy_iqk_dbg_cfir_backup_8814b(dm);
529 break;
530 #endif
531 #if (RTL8814C_SUPPORT == 1)
532 case ODM_RTL8814C:
533 phy_iqk_dbg_cfir_backup_8814c(dm);
534 break;
535 #endif
536
537 default:
538 break;
539 }
540
541 }
542
halrf_iqk_dbg_cfir_backup_update(void * dm_void)543 void halrf_iqk_dbg_cfir_backup_update(void *dm_void)
544 {
545 struct dm_struct *dm = (struct dm_struct *)dm_void;
546 struct dm_iqk_info *iqk = &dm->IQK_info;
547 u8 i, path, idx;
548 u32 bmask13_12 = BIT(13) | BIT(12);
549 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
550 u32 data;
551
552 switch (dm->support_ic_type) {
553 #if (RTL8822B_SUPPORT == 1)
554 case ODM_RTL8822B:
555 phy_iqk_dbg_cfir_backup_update_8822b(dm);
556 break;
557 #endif
558 #if (RTL8822C_SUPPORT == 1)
559 case ODM_RTL8822C:
560 phy_iqk_dbg_cfir_backup_update_8822c(dm);
561 break;
562 #endif
563 #if (RTL8814C_SUPPORT == 1)
564 case ODM_RTL8814C:
565 phy_iqk_dbg_cfir_backup_update_8814c(dm);
566 break;
567 #endif
568
569 default:
570 break;
571 }
572 }
573
halrf_iqk_dbg_cfir_reload(void * dm_void)574 void halrf_iqk_dbg_cfir_reload(void *dm_void)
575 {
576 struct dm_struct *dm = (struct dm_struct *)dm_void;
577 struct dm_iqk_info *iqk = &dm->IQK_info;
578 u8 i, path, idx;
579 u32 bmask13_12 = BIT(13) | BIT(12);
580 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
581 u32 data;
582
583 switch (dm->support_ic_type) {
584 #if (RTL8822B_SUPPORT == 1)
585 case ODM_RTL8822B:
586 phy_iqk_dbg_cfir_reload_8822b(dm);
587 break;
588 #endif
589 #if (RTL8822C_SUPPORT == 1)
590 case ODM_RTL8822C:
591 phy_iqk_dbg_cfir_reload_8822c(dm);
592 break;
593 #endif
594 #if (RTL8814C_SUPPORT == 1)
595 case ODM_RTL8814C:
596 phy_iqk_dbg_cfir_reload_8814c(dm);
597 break;
598 #endif
599
600 default:
601 break;
602 }
603 }
604
halrf_iqk_dbg_cfir_write(void * dm_void,u8 type,u32 path,u32 idx,u32 i,u32 data)605 void halrf_iqk_dbg_cfir_write(void *dm_void, u8 type, u32 path, u32 idx,
606 u32 i, u32 data)
607 {
608 struct dm_struct *dm = (struct dm_struct *)dm_void;
609 struct dm_iqk_info *iqk_info = &dm->IQK_info;
610
611 switch (dm->support_ic_type) {
612 #if (RTL8822B_SUPPORT == 1)
613 case ODM_RTL8822B:
614 phy_iqk_dbg_cfir_write_8822b(dm, type, path, idx, i, data);
615 break;
616 #endif
617 #if (RTL8822C_SUPPORT == 1)
618 case ODM_RTL8822C:
619 phy_iqk_dbg_cfir_write_8822c(dm, type, path, idx, i, data);
620 break;
621 #endif
622 #if (RTL8814C_SUPPORT == 1)
623 case ODM_RTL8814C:
624 phy_iqk_dbg_cfir_write_8814c(dm, type, path, idx, i, data);
625 break;
626 #endif
627
628 default:
629 break;
630 }
631 }
632
halrf_iqk_dbg_cfir_backup_show(void * dm_void)633 void halrf_iqk_dbg_cfir_backup_show(void *dm_void)
634 {
635 struct dm_struct *dm = (struct dm_struct *)dm_void;
636 struct dm_iqk_info *iqk_info = &dm->IQK_info;
637 u8 path, idx, i;
638
639 switch (dm->support_ic_type) {
640 #if (RTL8822B_SUPPORT == 1)
641 case ODM_RTL8822B:
642 phy_iqk_dbg_cfir_backup_8822b(dm);
643 break;
644 #endif
645 #if (RTL8822C_SUPPORT == 1)
646 case ODM_RTL8822C:
647 phy_iqk_dbg_cfir_backup_8822c(dm);
648 break;
649 #endif
650 #if (RTL8814C_SUPPORT == 1)
651 case ODM_RTL8814C:
652 phy_iqk_dbg_cfir_backup_8814c(dm);
653 break;
654 #endif
655
656 default:
657 break;
658 }
659 }
660
halrf_do_imr_test(void * dm_void,u8 flag_imr_test)661 void halrf_do_imr_test(void *dm_void, u8 flag_imr_test)
662 {
663 struct dm_struct *dm = (struct dm_struct *)dm_void;
664
665 if (flag_imr_test != 0x0)
666 switch (dm->support_ic_type) {
667 #if (RTL8822B_SUPPORT == 1)
668 case ODM_RTL8822B:
669 do_imr_test_8822b(dm);
670 break;
671 #endif
672 #if (RTL8821C_SUPPORT == 1)
673 case ODM_RTL8821C:
674 do_imr_test_8821c(dm);
675 break;
676 #endif
677 default:
678 break;
679 }
680 }
681
682 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
683 RTL8814B_SUPPORT == 1 || RTL8814C_SUPPORT == 1)
halrf_iqk_debug(void * dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)684 void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
685 char *output, u32 *_out_len)
686 {
687 struct dm_struct *dm = (struct dm_struct *)dm_void;
688
689 #if 0
690 /*dm_value[0]=0x0: backup from SRAM & show*/
691 /*dm_value[0]=0x1: write backup CFIR to SRAM*/
692 /*dm_value[0]=0x2: reload default CFIR to SRAM*/
693 /*dm_value[0]=0x3: show backup*/
694 /*dm_value[0]=0x10: write backup CFIR real part*/
695 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
696 /*dm_value[0]=0x11: write backup CFIR imag*/
697 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
698 /*dm_value[0]=0x20 :xym_read enable*/
699 /*--> dm_value[1]:0:disable, 1:enable*/
700 /*if dm_value[0]=0x20 = enable, */
701 /*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
702 #endif
703 if (dm_value[0] == 0x0)
704 halrf_iqk_dbg_cfir_backup(dm);
705 else if (dm_value[0] == 0x1)
706 halrf_iqk_dbg_cfir_backup_update(dm);
707 else if (dm_value[0] == 0x2)
708 halrf_iqk_dbg_cfir_reload(dm);
709 else if (dm_value[0] == 0x3)
710 halrf_iqk_dbg_cfir_backup_show(dm);
711 else if (dm_value[0] == 0x10)
712 halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],
713 dm_value[3], dm_value[4]);
714 else if (dm_value[0] == 0x11)
715 halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],
716 dm_value[3], dm_value[4]);
717 else if (dm_value[0] == 0x20)
718 halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
719 else if (dm_value[0] == 0x21)
720 halrf_iqk_xym_show(dm, (u8)dm_value[1]);
721 else if (dm_value[0] == 0x30)
722 halrf_do_imr_test(dm, (u8)dm_value[1]);
723 }
724 #endif
725
halrf_iqk_hwtx_check(void * dm_void,boolean is_check)726 void halrf_iqk_hwtx_check(void *dm_void, boolean is_check)
727 {
728 #if 0
729 struct dm_struct *dm = (struct dm_struct *)dm_void;
730 struct dm_iqk_info *iqk_info = &dm->IQK_info;
731 u32 tmp_b04;
732
733 if (is_check) {
734 iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));
735 } else {
736 if (iqk_info->is_hwtx) {
737 tmp_b04 = odm_read_4byte(dm, 0xb04);
738 odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);
739 odm_write_4byte(dm, 0xb04, tmp_b04);
740 }
741 }
742 #endif
743 }
744 #endif
745
halrf_match_iqk_version(void * dm_void)746 u8 halrf_match_iqk_version(void *dm_void)
747 {
748 struct dm_struct *dm = (struct dm_struct *)dm_void;
749
750 u32 iqk_version = 0;
751 char temp[10] = {0};
752
753 odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));
754 PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
755
756 if (dm->support_ic_type == ODM_RTL8822B) {
757 if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))
758 return 1;
759 else if ((iqk_version <= 0x23) &&
760 (odm_get_hw_img_version(dm) <= 71))
761 return 1;
762 else
763 return 0;
764 }
765
766 if (dm->support_ic_type == ODM_RTL8821C) {
767 if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))
768 return 1;
769 else
770 return 0;
771 }
772
773 return 1;
774 }
775
halrf_rf_lna_setting(void * dm_void,enum halrf_lna_set type)776 void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)
777 {
778 struct dm_struct *dm = (struct dm_struct *)dm_void;
779
780 switch (dm->support_ic_type) {
781 #if (RTL8188E_SUPPORT == 1)
782 case ODM_RTL8188E:
783 halrf_rf_lna_setting_8188e(dm, type);
784 break;
785 #endif
786 #if (RTL8192E_SUPPORT == 1)
787 case ODM_RTL8192E:
788 halrf_rf_lna_setting_8192e(dm, type);
789 break;
790 #endif
791 #if (RTL8192F_SUPPORT == 1)
792 case ODM_RTL8192F:
793 halrf_rf_lna_setting_8192f(dm, type);
794 break;
795 #endif
796
797 #if (RTL8723B_SUPPORT == 1)
798 case ODM_RTL8723B:
799 halrf_rf_lna_setting_8723b(dm, type);
800 break;
801 #endif
802 #if (RTL8812A_SUPPORT == 1)
803 case ODM_RTL8812:
804 halrf_rf_lna_setting_8812a(dm, type);
805 break;
806 #endif
807 #if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
808 case ODM_RTL8881A:
809 case ODM_RTL8821:
810 halrf_rf_lna_setting_8821a(dm, type);
811 break;
812 #endif
813 #if (RTL8822B_SUPPORT == 1)
814 case ODM_RTL8822B:
815 halrf_rf_lna_setting_8822b(dm_void, type);
816 break;
817 #endif
818 #if (RTL8822C_SUPPORT == 1)
819 case ODM_RTL8822C:
820 halrf_rf_lna_setting_8822c(dm_void, type);
821 break;
822 #endif
823 #if (RTL8812F_SUPPORT == 1)
824 case ODM_RTL8812F:
825 halrf_rf_lna_setting_8812f(dm_void, type);
826 break;
827 #endif
828 #if (RTL8821C_SUPPORT == 1)
829 case ODM_RTL8821C:
830 halrf_rf_lna_setting_8821c(dm_void, type);
831 break;
832 #endif
833 #if (RTL8710C_SUPPORT == 1)
834 case ODM_RTL8710C:
835 halrf_rf_lna_setting_8710c(dm_void, type);
836 break;
837 #endif
838 #if (RTL8721D_SUPPORT == 1)
839 case ODM_RTL8721D:
840 halrf_rf_lna_setting_8721d(dm, type);
841 break;
842 #endif
843 #if (RTL8814B_SUPPORT == 1)
844 case ODM_RTL8814B:
845 break;
846 #endif
847 #if (RTL8814C_SUPPORT == 1)
848 case ODM_RTL8814C:
849 break;
850 #endif
851
852 default:
853 break;
854 }
855 }
856
halrf_support_ability_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)857 void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
858 char *output, u32 *_out_len)
859 {
860 struct dm_struct *dm = (struct dm_struct *)dm_void;
861 struct _hal_rf_ *rf = &dm->rf_table;
862 u32 dm_value[10] = {0};
863 u32 used = *_used;
864 u32 out_len = *_out_len;
865 u8 i;
866
867 for (i = 0; i < 5; i++)
868 if (input[i + 1])
869 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
870
871 if (dm_value[0] == 100) {
872 PDM_SNPF(out_len, used, output + used, out_len - used,
873 "\n[RF Supportability]\n");
874 PDM_SNPF(out_len, used, output + used, out_len - used,
875 "00. (( %s ))Power Tracking\n",
876 ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?
877 ("V") : (".")));
878 PDM_SNPF(out_len, used, output + used, out_len - used,
879 "01. (( %s ))IQK\n",
880 ((rf->rf_supportability & HAL_RF_IQK) ? ("V") :
881 (".")));
882 PDM_SNPF(out_len, used, output + used, out_len - used,
883 "02. (( %s ))LCK\n",
884 ((rf->rf_supportability & HAL_RF_LCK) ? ("V") :
885 (".")));
886 PDM_SNPF(out_len, used, output + used, out_len - used,
887 "03. (( %s ))DPK\n",
888 ((rf->rf_supportability & HAL_RF_DPK) ? ("V") :
889 (".")));
890 PDM_SNPF(out_len, used, output + used, out_len - used,
891 "04. (( %s ))HAL_RF_TXGAPK\n",
892 ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") :
893 (".")));
894 PDM_SNPF(out_len, used, output + used, out_len - used,
895 "05. (( %s ))HAL_RF_DACK\n",
896 ((rf->rf_supportability & HAL_RF_DACK) ? ("V") :
897 (".")));
898 PDM_SNPF(out_len, used, output + used, out_len - used,
899 "06. (( %s ))DPK_TRACK\n",
900 ((rf->rf_supportability & HAL_RF_DPK_TRACK) ? ("V") :
901 (".")));
902 #ifdef CONFIG_2G_BAND_SHIFT
903 PDM_SNPF(out_len, used, output + used, out_len - used,
904 "07. (( %s ))HAL_2GBAND_SHIFT\n",
905 ((rf->rf_supportability & HAL_2GBAND_SHIFT) ? ("V") :
906 (".")));
907 #endif
908 PDM_SNPF(out_len, used, output + used, out_len - used,
909 "08. (( %s ))HAL_RF_RXDCK\n",
910 ((rf->rf_supportability & HAL_RF_RXDCK) ? ("V") :
911 (".")));
912
913 } else {
914 if (dm_value[1] == 1) /* enable */
915 rf->rf_supportability |= BIT(dm_value[0]);
916 else if (dm_value[1] == 2) /* disable */
917 rf->rf_supportability &= ~(BIT(dm_value[0]));
918 else
919 PDM_SNPF(out_len, used, output + used, out_len - used,
920 "[Warning!!!] 1:enable, 2:disable\n");
921 }
922 PDM_SNPF(out_len, used, output + used, out_len - used,
923 "\nCurr-RF_supportability = 0x%x\n\n", rf->rf_supportability);
924
925 *_used = used;
926 *_out_len = out_len;
927 }
928
929 #ifdef CONFIG_2G_BAND_SHIFT
halrf_support_band_shift_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)930 void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
931 char *output, u32 *_out_len)
932 {
933 struct dm_struct *dm = (struct dm_struct *)dm_void;
934 struct _hal_rf_ *rf = &dm->rf_table;
935 //u32 band_value[2] = {00};
936 u32 dm_value[10] = {0};
937 u32 used = *_used;
938 u32 out_len = *_out_len;
939 u8 i;
940
941 #if (RTL8192F_SUPPORT == 1)
942 for (i = 0; i < 7; i++)
943 if (input[i + 1])
944 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
945
946 if (!(rf->rf_supportability & HAL_2GBAND_SHIFT)) {
947 PDM_SNPF(out_len, used, output + used, out_len - used,
948 "\nCurr-RF_supportability[07. (( . ))HAL_2GBAND_SHIFT]\nNo RF Band Shift,default: 2.4G!\n");
949 } else {
950 if (dm_value[0] == 01) {
951 rf->rf_shift_band = HAL_RF_2P3;
952 halrf_lck_trigger(dm);
953 PDM_SNPF(out_len, used, output + used, out_len - used,
954 "\n[rf_shift_band] = %d\nRF Band Shift to 2.3G!\n",
955 rf->rf_shift_band);
956 } else if (dm_value[0] == 02) {
957 rf->rf_shift_band = HAL_RF_2P5;
958 halrf_lck_trigger(dm);
959 PDM_SNPF(out_len, used, output + used, out_len - used,
960 "\n[rf_shift_band] = %d\nRF Band Shift to 2.5G!\n",
961 rf->rf_shift_band);
962 } else {
963 rf->rf_shift_band = HAL_RF_2P4;
964 halrf_lck_trigger(dm);
965 PDM_SNPF(out_len, used, output + used, out_len - used,
966 "\n[rf_shift_band] = %d\nNo RF Band Shift,default: 2.4G!\n",
967 rf->rf_shift_band);
968 }
969 }
970 *_used = used;
971 *_out_len = out_len;
972 #endif
973 }
974 #endif
975
halrf_cmn_info_init(void * dm_void,enum halrf_cmninfo_init cmn_info,u32 value)976 void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
977 u32 value)
978 {
979 struct dm_struct *dm = (struct dm_struct *)dm_void;
980 struct _hal_rf_ *rf = &dm->rf_table;
981
982 switch (cmn_info) {
983 case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
984 rf->eeprom_thermal = (u8)value;
985 break;
986 case HALRF_CMNINFO_PWT_TYPE:
987 rf->pwt_type = (u8)value;
988 break;
989 case HALRF_CMNINFO_MP_POWER_TRACKING_TYPE:
990 rf->mp_pwt_type = (u8)value;
991 break;
992 default:
993 break;
994 }
995 }
996
halrf_cmn_info_hook(void * dm_void,enum halrf_cmninfo_hook cmn_info,void * value)997 void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
998 void *value)
999 {
1000 struct dm_struct *dm = (struct dm_struct *)dm_void;
1001 struct _hal_rf_ *rf = &dm->rf_table;
1002
1003 switch (cmn_info) {
1004 case HALRF_CMNINFO_CON_TX:
1005 rf->is_con_tx = (boolean *)value;
1006 break;
1007 case HALRF_CMNINFO_SINGLE_TONE:
1008 rf->is_single_tone = (boolean *)value;
1009 break;
1010 case HALRF_CMNINFO_CARRIER_SUPPRESSION:
1011 rf->is_carrier_suppresion = (boolean *)value;
1012 break;
1013 case HALRF_CMNINFO_MP_RATE_INDEX:
1014 rf->mp_rate_index = (u8 *)value;
1015 break;
1016 case HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY:
1017 rf->manual_rf_supportability = (u32 *)value;
1018 break;
1019 default:
1020 /*do nothing*/
1021 break;
1022 }
1023 }
1024
halrf_cmn_info_set(void * dm_void,u32 cmn_info,u64 value)1025 void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)
1026 {
1027 /* This init variable may be changed in run time. */
1028 struct dm_struct *dm = (struct dm_struct *)dm_void;
1029 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
1030 struct _hal_rf_ *rf = &dm->rf_table;
1031
1032 switch (cmn_info) {
1033 case HALRF_CMNINFO_ABILITY:
1034 rf->rf_supportability = (u32)value;
1035 break;
1036
1037 case HALRF_CMNINFO_DPK_EN:
1038 rf->dpk_en = (u8)value;
1039 break;
1040 case HALRF_CMNINFO_RFK_FORBIDDEN:
1041 dm->IQK_info.rfk_forbidden = (boolean)value;
1042 break;
1043 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
1044 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1045 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
1046 RTL8814C_SUPPORT == 1 )
1047 case HALRF_CMNINFO_IQK_SEGMENT:
1048 dm->IQK_info.segment_iqk = (boolean)value;
1049 break;
1050 #endif
1051 case HALRF_CMNINFO_RATE_INDEX:
1052 rf->p_rate_index = (u32)value;
1053 break;
1054 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
1055 case HALRF_CMNINFO_MP_PSD_POINT:
1056 rf->halrf_psd_data.point = (u32)value;
1057 break;
1058 case HALRF_CMNINFO_MP_PSD_START_POINT:
1059 rf->halrf_psd_data.start_point = (u32)value;
1060 break;
1061 case HALRF_CMNINFO_MP_PSD_STOP_POINT:
1062 rf->halrf_psd_data.stop_point = (u32)value;
1063 break;
1064 case HALRF_CMNINFO_MP_PSD_AVERAGE:
1065 rf->halrf_psd_data.average = (u32)value;
1066 break;
1067 #endif
1068 case HALRF_CMNINFO_POWER_TRACK_CONTROL:
1069 cali_info->txpowertrack_control = (u8)value;
1070 break;
1071 default:
1072 /* do nothing */
1073 break;
1074 }
1075 }
1076
halrf_cmn_info_get(void * dm_void,u32 cmn_info)1077 u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)
1078 {
1079 /* This init variable may be changed in run time. */
1080 struct dm_struct *dm = (struct dm_struct *)dm_void;
1081 struct _hal_rf_ *rf = &dm->rf_table;
1082 u64 return_value = 0;
1083
1084 switch (cmn_info) {
1085 case HALRF_CMNINFO_ABILITY:
1086 return_value = (u32)rf->rf_supportability;
1087 break;
1088 case HALRF_CMNINFO_RFK_FORBIDDEN:
1089 return_value = dm->IQK_info.rfk_forbidden;
1090 break;
1091 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
1092 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1093 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
1094 RTL8814C_SUPPORT == 1)
1095 case HALRF_CMNINFO_IQK_SEGMENT:
1096 return_value = dm->IQK_info.segment_iqk;
1097 break;
1098 case HALRF_CMNINFO_IQK_TIMES:
1099 return_value = dm->IQK_info.iqk_times;
1100 break;
1101 #endif
1102 default:
1103 /* do nothing */
1104 break;
1105 }
1106
1107 return return_value;
1108 }
1109
halrf_supportability_init_mp(void * dm_void)1110 void halrf_supportability_init_mp(void *dm_void)
1111 {
1112 struct dm_struct *dm = (struct dm_struct *)dm_void;
1113 struct _hal_rf_ *rf = &dm->rf_table;
1114
1115 switch (dm->support_ic_type) {
1116 case ODM_RTL8814B:
1117 #if (RTL8814B_SUPPORT == 1)
1118 rf->rf_supportability =
1119 /*HAL_RF_TX_PWR_TRACK |*/
1120 HAL_RF_IQK |
1121 HAL_RF_LCK |
1122 HAL_RF_DPK |
1123 HAL_RF_DACK |
1124 /*HAL_RF_TXGAPK |*/
1125 HAL_RF_DPK_TRACK |
1126 0;
1127 #endif
1128 break;
1129 #if (RTL8822B_SUPPORT == 1)
1130 case ODM_RTL8822B:
1131 rf->rf_supportability =
1132 /*HAL_RF_TX_PWR_TRACK |*/
1133 HAL_RF_IQK |
1134 HAL_RF_LCK |
1135 /*@HAL_RF_DPK |*/
1136 0;
1137 break;
1138 #endif
1139 #if (RTL8822C_SUPPORT == 1)
1140 case ODM_RTL8822C:
1141 rf->rf_supportability =
1142 /*HAL_RF_TX_PWR_TRACK |*/
1143 HAL_RF_IQK |
1144 HAL_RF_LCK |
1145 HAL_RF_DPK |
1146 HAL_RF_DACK |
1147 HAL_RF_DPK_TRACK |
1148 HAL_RF_RXDCK |
1149 HAL_RF_TXGAPK |
1150 0;
1151 break;
1152 #endif
1153 #if (RTL8821C_SUPPORT == 1)
1154 case ODM_RTL8821C:
1155 rf->rf_supportability =
1156 /*HAL_RF_TX_PWR_TRACK |*/
1157 HAL_RF_IQK |
1158 HAL_RF_LCK |
1159 /*@HAL_RF_DPK |*/
1160 /*@HAL_RF_TXGAPK |*/
1161 0;
1162 break;
1163 #endif
1164 #if (RTL8195B_SUPPORT == 1)
1165 case ODM_RTL8195B:
1166 rf->rf_supportability =
1167 /*HAL_RF_TX_PWR_TRACK |*/
1168 HAL_RF_IQK |
1169 HAL_RF_LCK |
1170 HAL_RF_DPK |
1171 /*HAL_RF_TXGAPK |*/
1172 HAL_RF_DPK_TRACK |
1173 0;
1174 break;
1175 #endif
1176 #if (RTL8812F_SUPPORT == 1)
1177 case ODM_RTL8812F:
1178 rf->rf_supportability =
1179 /*HAL_RF_TX_PWR_TRACK |*/
1180 HAL_RF_IQK |
1181 HAL_RF_LCK |
1182 HAL_RF_DPK |
1183 HAL_RF_DACK |
1184 HAL_RF_DPK_TRACK |
1185 0;
1186 break;
1187 #endif
1188
1189 #if (RTL8198F_SUPPORT == 1)
1190 case ODM_RTL8198F:
1191 rf->rf_supportability =
1192 /*HAL_RF_TX_PWR_TRACK |*/
1193 HAL_RF_IQK |
1194 HAL_RF_LCK |
1195 HAL_RF_DPK |
1196 /*@HAL_RF_TXGAPK |*/
1197 0;
1198 break;
1199 #endif
1200
1201 #if (RTL8192F_SUPPORT == 1)
1202 case ODM_RTL8192F:
1203 rf->rf_supportability =
1204 /*HAL_RF_TX_PWR_TRACK |*/
1205 HAL_RF_IQK |
1206 HAL_RF_LCK |
1207 HAL_RF_DPK |
1208 /*@HAL_RF_TXGAPK |*/
1209 #ifdef CONFIG_2G_BAND_SHIFT
1210 /*@HAL_2GBAND_SHIFT |*/
1211 #endif
1212 0;
1213 break;
1214 #endif
1215
1216 #if (RTL8197F_SUPPORT == 1)
1217 case ODM_RTL8197F:
1218 rf->rf_supportability =
1219 /*HAL_RF_TX_PWR_TRACK |*/
1220 HAL_RF_IQK |
1221 HAL_RF_LCK |
1222 HAL_RF_DPK |
1223 /*@HAL_RF_TXGAPK |*/
1224 0;
1225 break;
1226 #endif
1227 #if (RTL8197G_SUPPORT == 1)
1228 case ODM_RTL8197G:
1229 rf->rf_supportability =
1230 /*HAL_RF_TX_PWR_TRACK |*/
1231 HAL_RF_IQK |
1232 /*HAL_RF_LCK |*/
1233 HAL_RF_DPK |
1234 /*@HAL_RF_TXGAPK |*/
1235 HAL_RF_DPK_TRACK |
1236 0;
1237 break;
1238 #endif
1239 #if (RTL8721D_SUPPORT == 1)
1240 case ODM_RTL8721D:
1241 rf->rf_supportability =
1242 HAL_RF_TX_PWR_TRACK |
1243 HAL_RF_IQK |
1244 HAL_RF_LCK |
1245 HAL_RF_DPK |
1246 HAL_RF_DPK_TRACK |
1247 /*@HAL_RF_TXGAPK |*/
1248 0;
1249 break;
1250 #endif
1251 #if (RTL8723F_SUPPORT == 1)
1252 case ODM_RTL8723F:
1253 rf->rf_supportability =
1254 HAL_RF_TX_PWR_TRACK |
1255 HAL_RF_IQK |
1256 HAL_RF_LCK |
1257 HAL_RF_DPK |
1258 HAL_RF_TXGAPK |
1259 HAL_RF_DPK_TRACK |
1260 0;
1261 break;
1262 #endif
1263 case ODM_RTL8814C:
1264 #if (RTL8814C_SUPPORT == 1)
1265 rf->rf_supportability =
1266 /*HAL_RF_TX_PWR_TRACK |*/
1267 HAL_RF_IQK |
1268 HAL_RF_LCK |
1269 HAL_RF_DPK |
1270 HAL_RF_DACK |
1271 HAL_RF_TXGAPK |
1272 HAL_RF_DPK_TRACK |
1273 0;
1274 #endif
1275 break;
1276
1277 default:
1278 rf->rf_supportability =
1279 /*HAL_RF_TX_PWR_TRACK |*/
1280 HAL_RF_IQK |
1281 HAL_RF_LCK |
1282 /*@HAL_RF_DPK |*/
1283 /*@HAL_RF_TXGAPK |*/
1284 0;
1285 break;
1286 }
1287
1288 RF_DBG(dm, DBG_RF_INIT,
1289 "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n",
1290 dm->support_ic_type, rf->rf_supportability);
1291 }
1292
halrf_supportability_init(void * dm_void)1293 void halrf_supportability_init(void *dm_void)
1294 {
1295 struct dm_struct *dm = (struct dm_struct *)dm_void;
1296 struct _hal_rf_ *rf = &dm->rf_table;
1297
1298 switch (dm->support_ic_type) {
1299 case ODM_RTL8814B:
1300 #if (RTL8814B_SUPPORT == 1)
1301 rf->rf_supportability =
1302 HAL_RF_TX_PWR_TRACK |
1303 HAL_RF_IQK |
1304 HAL_RF_LCK |
1305 HAL_RF_DPK |
1306 HAL_RF_DACK |
1307 HAL_RF_DPK_TRACK |
1308 0;
1309 #endif
1310 break;
1311 #if (RTL8822B_SUPPORT == 1)
1312 case ODM_RTL8822B:
1313 rf->rf_supportability =
1314 HAL_RF_TX_PWR_TRACK |
1315 HAL_RF_IQK |
1316 HAL_RF_LCK |
1317 /*@HAL_RF_DPK |*/
1318 0;
1319 break;
1320 #endif
1321 #if (RTL8822C_SUPPORT == 1)
1322 case ODM_RTL8822C:
1323 rf->rf_supportability =
1324 HAL_RF_TX_PWR_TRACK |
1325 HAL_RF_IQK |
1326 HAL_RF_LCK |
1327 HAL_RF_DPK |
1328 HAL_RF_DACK |
1329 HAL_RF_DPK_TRACK |
1330 HAL_RF_RXDCK |
1331 HAL_RF_TXGAPK |
1332 0;
1333 break;
1334 #endif
1335 #if (RTL8821C_SUPPORT == 1)
1336 case ODM_RTL8821C:
1337 rf->rf_supportability =
1338 HAL_RF_TX_PWR_TRACK |
1339 HAL_RF_IQK |
1340 HAL_RF_LCK |
1341 /*@HAL_RF_DPK |*/
1342 /*@HAL_RF_TXGAPK |*/
1343 0;
1344 break;
1345 #endif
1346 #if (RTL8195B_SUPPORT == 1)
1347 case ODM_RTL8195B:
1348 rf->rf_supportability =
1349 HAL_RF_TX_PWR_TRACK |
1350 HAL_RF_IQK |
1351 HAL_RF_LCK |
1352 HAL_RF_DPK |
1353 /*HAL_RF_TXGAPK |*/
1354 HAL_RF_DPK_TRACK |
1355 0;
1356 break;
1357 #endif
1358 #if (RTL8812F_SUPPORT == 1)
1359 case ODM_RTL8812F:
1360 rf->rf_supportability =
1361 HAL_RF_TX_PWR_TRACK |
1362 HAL_RF_IQK |
1363 HAL_RF_LCK |
1364 HAL_RF_DPK |
1365 HAL_RF_DACK |
1366 HAL_RF_DPK_TRACK |
1367 0;
1368 break;
1369 #endif
1370
1371 #if (RTL8198F_SUPPORT == 1)
1372 case ODM_RTL8198F:
1373 rf->rf_supportability =
1374 HAL_RF_TX_PWR_TRACK |
1375 HAL_RF_IQK |
1376 HAL_RF_LCK |
1377 HAL_RF_DPK |
1378 /*@HAL_RF_TXGAPK |*/
1379 0;
1380 break;
1381 #endif
1382
1383 #if (RTL8192F_SUPPORT == 1)
1384 case ODM_RTL8192F:
1385 rf->rf_supportability =
1386 HAL_RF_TX_PWR_TRACK |
1387 HAL_RF_IQK |
1388 HAL_RF_LCK |
1389 HAL_RF_DPK |
1390 /*@HAL_RF_TXGAPK |*/
1391 #ifdef CONFIG_2G_BAND_SHIFT
1392 /*@HAL_2GBAND_SHIFT |*/
1393 #endif
1394 0;
1395 break;
1396 #endif
1397
1398 #if (RTL8197F_SUPPORT == 1)
1399 case ODM_RTL8197F:
1400 rf->rf_supportability =
1401 HAL_RF_TX_PWR_TRACK |
1402 HAL_RF_IQK |
1403 HAL_RF_LCK |
1404 HAL_RF_DPK |
1405 /*@HAL_RF_TXGAPK |*/
1406 0;
1407 break;
1408 #endif
1409 #if (RTL8197G_SUPPORT == 1)
1410 case ODM_RTL8197G:
1411 rf->rf_supportability =
1412 HAL_RF_TX_PWR_TRACK |
1413 HAL_RF_IQK |
1414 /*HAL_RF_LCK |*/
1415 HAL_RF_DPK |
1416 /*@HAL_RF_TXGAPK |*/
1417 HAL_RF_DPK_TRACK |
1418 #ifdef CONFIG_2G_BAND_SHIFT
1419 HAL_2GBAND_SHIFT |
1420 #endif
1421 0;
1422 break;
1423 #endif
1424 #if (RTL8721D_SUPPORT == 1)
1425 case ODM_RTL8721D:
1426 rf->rf_supportability =
1427 HAL_RF_TX_PWR_TRACK |
1428 HAL_RF_IQK |
1429 HAL_RF_LCK |
1430 HAL_RF_DPK |
1431 HAL_RF_DPK_TRACK |
1432 /*@HAL_RF_TXGAPK |*/
1433 0;
1434 break;
1435 #endif
1436 #if (RTL8723F_SUPPORT == 1)
1437 case ODM_RTL8723F:
1438 rf->rf_supportability =
1439 HAL_RF_TX_PWR_TRACK |
1440 HAL_RF_IQK |
1441 HAL_RF_LCK |
1442 HAL_RF_DPK |
1443 HAL_RF_TXGAPK |
1444 HAL_RF_DPK_TRACK |
1445 0;
1446 break;
1447 #endif
1448 case ODM_RTL8814C:
1449 #if (RTL8814C_SUPPORT == 1)
1450 rf->rf_supportability =
1451 HAL_RF_TX_PWR_TRACK |
1452 HAL_RF_IQK |
1453 HAL_RF_LCK |
1454 HAL_RF_DPK |
1455 HAL_RF_DACK |
1456 HAL_RF_DPK_TRACK |
1457 HAL_RF_TXGAPK |
1458 0;
1459 #endif
1460 break;
1461
1462 default:
1463 rf->rf_supportability =
1464 HAL_RF_TX_PWR_TRACK |
1465 HAL_RF_IQK |
1466 HAL_RF_LCK |
1467 /*@HAL_RF_DPK |*/
1468 0;
1469 break;
1470 }
1471
1472 RF_DBG(dm, DBG_RF_INIT,
1473 "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n",
1474 dm->support_ic_type, rf->rf_supportability);
1475 }
1476
halrf_watchdog(void * dm_void)1477 void halrf_watchdog(void *dm_void)
1478 {
1479 struct dm_struct *dm = (struct dm_struct *)dm_void;
1480 struct _hal_rf_ *rf = &dm->rf_table;
1481 #if 0
1482 /*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/
1483 #endif
1484 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
1485 rf->is_tssi_in_progress)
1486 return;
1487
1488 if (!(dm->support_ic_type & ODM_RTL8723F))
1489 phydm_rf_watchdog(dm);
1490
1491 halrf_dpk_track(dm);
1492 #if (RTL8723F_SUPPORT == 1)
1493 if (dm->support_ic_type & ODM_RTL8723F){
1494 halrf_xtal_thermal_track(dm);
1495 halrf_powertracking_thermal(dm);
1496 }
1497 #endif
1498 }
1499
1500 #if 0
1501 void
1502 halrf_iqk_init(
1503 void *dm_void
1504 )
1505 {
1506 struct dm_struct *dm = (struct dm_struct *)dm_void;
1507 struct _hal_rf_ *rf = &dm->rf_table;
1508
1509 switch (dm->support_ic_type) {
1510 #if (RTL8814B_SUPPORT == 1)
1511 case ODM_RTL8814B:
1512 break;
1513 #endif
1514 #if (RTL8822B_SUPPORT == 1)
1515 case ODM_RTL8822B:
1516 _iq_calibrate_8822b_init(dm);
1517 break;
1518 #endif
1519 #if (RTL8822C_SUPPORT == 1)
1520 case ODM_RTL8822C:
1521 _iq_calibrate_8822c_init(dm);
1522 break;
1523 #endif
1524 #if (RTL8821C_SUPPORT == 1)
1525 case ODM_RTL8821C:
1526 break;
1527 #endif
1528
1529 default:
1530 break;
1531 }
1532 }
1533 #endif
1534
halrf_rfk_power_save(void * dm_void,boolean is_power_save)1535 void halrf_rfk_power_save(void *dm_void, boolean is_power_save)
1536 {
1537 struct dm_struct *dm = (struct dm_struct *)dm_void;
1538 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1539
1540 switch (dm->support_ic_type) {
1541 #if (RTL8822C_SUPPORT == 1)
1542 case ODM_RTL8822C:
1543 halrf_rfk_power_save_8822c(dm, is_power_save);
1544 break;
1545 #endif
1546
1547 #if (RTL8723F_SUPPORT == 1)
1548 case ODM_RTL8723F:
1549 halrf_rfk_power_save_8723f(dm, is_power_save);
1550 break;
1551 #endif
1552 #if (RTL8814C_SUPPORT == 1)
1553 case ODM_RTL8814C:
1554 break;
1555 #endif
1556
1557 default:
1558 break;
1559 }
1560 }
1561
1562
1563
halrf_reload_iqk(void * dm_void,boolean reset)1564 void halrf_reload_iqk(void *dm_void, boolean reset)
1565 {
1566 struct dm_struct *dm = (struct dm_struct *)dm_void;
1567 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1568 u8 i, ch;
1569 u32 tmp;
1570 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
1571
1572 halrf_rfk_power_save(dm, false);
1573 switch (dm->support_ic_type) {
1574 #if (RTL8822C_SUPPORT == 1)
1575 case ODM_RTL8822C:
1576 iqk_reload_iqk_8822c(dm, reset);
1577 break;
1578 #endif
1579 #if (RTL8195B_SUPPORT == 1)
1580 case ODM_RTL8195B:
1581 iqk_reload_iqk_8195b(dm, reset);
1582 break;
1583 #endif
1584 #if (RTL8814C_SUPPORT == 1)
1585 case ODM_RTL8814C:
1586 iqk_reload_iqk_8814c(dm, reset);
1587 break;
1588 #endif
1589
1590 default:
1591 break;
1592 }
1593 halrf_rfk_power_save(dm, true);
1594 }
1595
halrf_rfk_handshake(void * dm_void,boolean is_before_k)1596 void halrf_rfk_handshake(void *dm_void, boolean is_before_k)
1597 {
1598 struct dm_struct *dm = (struct dm_struct *)dm_void;
1599
1600 if (!dm->mp_mode)
1601 return;
1602
1603 if (*dm->mp_mode)
1604 return;
1605
1606 switch (dm->support_ic_type) {
1607 #if (RTL8822C_SUPPORT == 1)
1608 case ODM_RTL8822C:
1609 halrf_rfk_handshake_8822c(dm, is_before_k);
1610 break;
1611 #endif
1612 #if (RTL8710C_SUPPORT == 1)
1613 case ODM_RTL8710C:
1614 halrf_rfk_handshake_8710c(dm, is_before_k);
1615 break;
1616 #endif
1617 #if (RTL8723F_SUPPORT == 1)
1618 case ODM_RTL8723F:
1619 halrf_rfk_handshake_8723f(dm, is_before_k);
1620 break;
1621 #endif
1622 #if (RTL8814C_SUPPORT == 1)
1623 case ODM_RTL8814C:
1624 break;
1625 #endif
1626
1627 default:
1628 break;
1629 }
1630 }
1631
halrf_bbreset(void * dm_void)1632 void halrf_bbreset(void *dm_void)
1633 {
1634 struct dm_struct *dm = (struct dm_struct *)dm_void;
1635
1636
1637 switch (dm->support_ic_type) {
1638 #if (RTL8814B_SUPPORT == 1)
1639 case ODM_RTL8814B:
1640 phydm_bb_reset_8814b(dm);
1641 break;
1642 #endif
1643 #if (RTL8814C_SUPPORT == 1)
1644 case ODM_RTL8814C:
1645 phydm_bb_reset_8814c(dm);
1646 break;
1647 #endif
1648
1649 default:
1650 break;
1651 }
1652 }
1653
halrf_rf_k_connect_trigger(void * dm_void,boolean is_recovery,enum halrf_k_segment_time seg_time)1654 void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
1655 enum halrf_k_segment_time seg_time)
1656 {
1657 struct dm_struct *dm = (struct dm_struct *)dm_void;
1658 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1659 struct _hal_rf_ *rf = &dm->rf_table;
1660
1661 if (!dm->mp_mode)
1662 return;
1663
1664 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1665 rf->is_carrier_suppresion) {
1666 if (*dm->mp_mode &
1667 (*rf->is_con_tx || *rf->is_single_tone ||
1668 *rf->is_carrier_suppresion))
1669 return;
1670 }
1671 #if (RTL8723F_SUPPORT == 1)
1672 if(dm->support_ic_type == ODM_RTL8723F)
1673 halrf_dis_cca_8723f(dm, true);
1674 #endif
1675 /*[TX GAP K]*/
1676 halrf_txgapk_trigger(dm);
1677
1678 /*[LOK, IQK]*/
1679 halrf_segment_iqk_trigger(dm, true, seg_time);
1680
1681 /*[TSSI Trk]*/
1682 halrf_tssi_trigger(dm);
1683 /*[DPK]*/
1684 #if 1
1685 if(dpk_info->is_dpk_by_channel == true)
1686 halrf_dpk_trigger(dm);
1687 else
1688 halrf_dpk_reload(dm);
1689 #endif
1690 //ADDA restore to MP_UI setting;
1691 config_halrf_path_adda_setting_trigger(dm);
1692
1693 halrf_spur_compensation(dm);
1694
1695 halrf_bbreset(dm);
1696 #if (RTL8723F_SUPPORT == 1)
1697 if(dm->support_ic_type == ODM_RTL8723F)
1698 halrf_dis_cca_8723f(dm, false);
1699 #endif
1700 }
1701
config_halrf_path_adda_setting_trigger(void * dm_void)1702 void config_halrf_path_adda_setting_trigger(void *dm_void)
1703 {
1704 struct dm_struct *dm = (struct dm_struct *)dm_void;
1705
1706 #if (RTL8814B_SUPPORT == 1)
1707 if (dm->support_ic_type & ODM_RTL8814B)
1708 config_phydm_path_adda_setting_8814b(dm);
1709 #endif
1710 #if (RTL8814C_SUPPORT == 1)
1711 if (dm->support_ic_type & ODM_RTL8814C)
1712 config_phydm_path_adda_setting_8814c(dm);
1713 #endif
1714
1715
1716 }
1717
halrf_dack_restore(void * dm_void)1718 void halrf_dack_restore(void *dm_void)
1719 {
1720 struct dm_struct *dm = (struct dm_struct *)dm_void;
1721 struct _hal_rf_ *rf = &dm->rf_table;
1722
1723 if (!(rf->rf_supportability & HAL_RF_DACK))
1724 return;
1725 switch (dm->support_ic_type) {
1726 #if (RTL8822C_SUPPORT == 1)
1727 case ODM_RTL8822C:
1728 halrf_dack_restore_8822c(dm);
1729 break;
1730 #endif
1731 #if (RTL8814C_SUPPORT == 1)
1732 case ODM_RTL8814C:
1733 //halrf_dack_restore_8814c(dm);
1734 break;
1735 #endif
1736
1737 default:
1738 break;
1739 }
1740 }
halrf_dack_trigger(void * dm_void,boolean force)1741 void halrf_dack_trigger(void *dm_void, boolean force)
1742 {
1743 struct dm_struct *dm = (struct dm_struct *)dm_void;
1744 struct _hal_rf_ *rf = &dm->rf_table;
1745
1746 u64 start_time;
1747
1748 if (!(rf->rf_supportability & HAL_RF_DACK))
1749 return;
1750
1751 start_time = odm_get_current_time(dm);
1752
1753 switch (dm->support_ic_type) {
1754 #if (RTL8822C_SUPPORT == 1)
1755 case ODM_RTL8822C:
1756 halrf_dac_cal_8822c(dm, force);
1757 break;
1758 #endif
1759 #if (RTL8812F_SUPPORT == 1)
1760 case ODM_RTL8812F:
1761 halrf_dac_cal_8812f(dm);
1762 break;
1763 #endif
1764 #if (RTL8814B_SUPPORT == 1)
1765 case ODM_RTL8814B:
1766 halrf_dac_cal_8814b(dm);
1767 break;
1768 #endif
1769 #if (RTL8814C_SUPPORT == 1)
1770 case ODM_RTL8814C:
1771 halrf_dac_cal_8814c(dm);
1772 break;
1773 #endif
1774
1775 default:
1776 break;
1777 }
1778 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
1779 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK progressing_time = %lld ms\n",
1780 rf->dpk_progressing_time);
1781 }
1782
1783
halrf_dack_dbg(void * dm_void)1784 void halrf_dack_dbg(void *dm_void)
1785 {
1786 struct dm_struct *dm = (struct dm_struct *)dm_void;
1787 struct _hal_rf_ *rf = &dm->rf_table;
1788
1789 u64 start_time;
1790
1791 if (!(rf->rf_supportability & HAL_RF_DACK))
1792 return;
1793
1794 switch (dm->support_ic_type) {
1795 #if (RTL8822C_SUPPORT == 1)
1796 case ODM_RTL8822C:
1797 halrf_dack_dbg_8822c(dm);
1798 break;
1799 #endif
1800 default:
1801 break;
1802 }
1803 }
1804
1805
halrf_segment_iqk_trigger(void * dm_void,boolean clear,boolean segment_iqk)1806 void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
1807 boolean segment_iqk)
1808 {
1809 struct dm_struct *dm = (struct dm_struct *)dm_void;
1810 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1811 struct _hal_rf_ *rf = &dm->rf_table;
1812 u64 start_time;
1813
1814 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1815 if (odm_check_power_status(dm) == false)
1816 return;
1817 #endif
1818
1819 if (!dm->mp_mode)
1820 return;
1821
1822 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1823 rf->is_carrier_suppresion) {
1824 if (*dm->mp_mode &
1825 (*rf->is_con_tx || *rf->is_single_tone ||
1826 *rf->is_carrier_suppresion))
1827 return;
1828 }
1829
1830 if (!(rf->rf_supportability & HAL_RF_IQK))
1831 return;
1832
1833 #if DISABLE_BB_RF
1834 return;
1835 #endif
1836 if (iqk_info->rfk_forbidden)
1837 return;
1838
1839 rf->rfk_type = RF01_IQK;
1840 halrf_rfk_handshake(dm, true);
1841
1842 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1843 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1844 dm->rf_calibrate_info.is_iqk_in_progress = true;
1845 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1846 start_time = odm_get_current_time(dm);
1847 dm->IQK_info.segment_iqk = segment_iqk;
1848
1849 halrf_rfk_power_save(dm, false);
1850 switch (dm->support_ic_type) {
1851 #if (RTL8822B_SUPPORT == 1)
1852 case ODM_RTL8822B:
1853 phy_iq_calibrate_8822b(dm, clear, segment_iqk);
1854 break;
1855 #endif
1856 #if (RTL8822C_SUPPORT == 1)
1857 case ODM_RTL8822C:
1858 phy_iq_calibrate_8822c(dm, clear, segment_iqk);
1859 break;
1860 #endif
1861 #if (RTL8821C_SUPPORT == 1)
1862 case ODM_RTL8821C:
1863 phy_iq_calibrate_8821c(dm, clear, segment_iqk);
1864 break;
1865 #endif
1866 #if (RTL8814B_SUPPORT == 1)
1867 case ODM_RTL8814B:
1868 phy_iq_calibrate_8814b(dm, clear, segment_iqk);
1869 break;
1870 #endif
1871 #if (RTL8195B_SUPPORT == 1)
1872 case ODM_RTL8195B:
1873 phy_iq_calibrate_8195b(dm, clear, segment_iqk);
1874 break;
1875 #endif
1876 #if (RTL8710C_SUPPORT == 1)
1877 case ODM_RTL8710C:
1878 phy_iq_calibrate_8710c(dm, clear, segment_iqk);
1879 break;
1880 #endif
1881 #if (RTL8198F_SUPPORT == 1)
1882 case ODM_RTL8198F:
1883 phy_iq_calibrate_8198f(dm, clear, segment_iqk);
1884 break;
1885 #endif
1886 #if (RTL8812F_SUPPORT == 1)
1887 case ODM_RTL8812F:
1888 phy_iq_calibrate_8812f(dm, clear, segment_iqk);
1889 break;
1890 #endif
1891 #if (RTL8197G_SUPPORT == 1)
1892 case ODM_RTL8197G:
1893 phy_iq_calibrate_8197g(dm, clear, segment_iqk);
1894 break;
1895 #endif
1896 #if (RTL8188E_SUPPORT == 1)
1897 case ODM_RTL8188E:
1898 phy_iq_calibrate_8188e(dm, false);
1899 break;
1900 #endif
1901 #if (RTL8188F_SUPPORT == 1)
1902 case ODM_RTL8188F:
1903 phy_iq_calibrate_8188f(dm, false);
1904 break;
1905 #endif
1906 #if (RTL8192E_SUPPORT == 1)
1907 case ODM_RTL8192E:
1908 phy_iq_calibrate_8192e(dm, false);
1909 break;
1910 #endif
1911 #if (RTL8197F_SUPPORT == 1)
1912 case ODM_RTL8197F:
1913 phy_iq_calibrate_8197f(dm, false);
1914 break;
1915 #endif
1916 #if (RTL8192F_SUPPORT == 1)
1917 case ODM_RTL8192F:
1918 phy_iq_calibrate_8192f(dm, false);
1919 break;
1920 #endif
1921 #if (RTL8703B_SUPPORT == 1)
1922 case ODM_RTL8703B:
1923 phy_iq_calibrate_8703b(dm, false);
1924 break;
1925 #endif
1926 #if (RTL8710B_SUPPORT == 1)
1927 case ODM_RTL8710B:
1928 phy_iq_calibrate_8710b(dm, false);
1929 break;
1930 #endif
1931 #if (RTL8723B_SUPPORT == 1)
1932 case ODM_RTL8723B:
1933 phy_iq_calibrate_8723b(dm, false);
1934 break;
1935 #endif
1936 #if (RTL8723D_SUPPORT == 1)
1937 case ODM_RTL8723D:
1938 phy_iq_calibrate_8723d(dm, false);
1939 break;
1940 #endif
1941 #if (RTL8721D_SUPPORT == 1)
1942 case ODM_RTL8721D:
1943 phy_iq_calibrate_8721d(dm, false);
1944 break;
1945 #endif
1946 #if (RTL8812A_SUPPORT == 1)
1947 case ODM_RTL8812:
1948 phy_iq_calibrate_8812a(dm, false);
1949 break;
1950 #endif
1951 #if (RTL8821A_SUPPORT == 1)
1952 case ODM_RTL8821:
1953 phy_iq_calibrate_8821a(dm, false);
1954 break;
1955 #endif
1956 #if (RTL8814A_SUPPORT == 1)
1957 case ODM_RTL8814A:
1958 phy_iq_calibrate_8814a(dm, false);
1959 break;
1960 #endif
1961 #if (RTL8723F_SUPPORT == 1)
1962 case ODM_RTL8723F:
1963 phy_iq_calibrate_8723f(dm, false);
1964 break;
1965 #endif
1966 #if (RTL8814C_SUPPORT == 1)
1967 case ODM_RTL8814C:
1968 phy_iq_calibrate_8814c(dm, clear, segment_iqk);
1969 break;
1970 #endif
1971
1972
1973 default:
1974 break;
1975 }
1976
1977 halrf_rfk_power_save(dm, true);
1978 dm->rf_calibrate_info.iqk_progressing_time =
1979 odm_get_progressing_time(dm, start_time);
1980 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
1981 dm->rf_calibrate_info.iqk_progressing_time);
1982
1983 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1984 dm->rf_calibrate_info.is_iqk_in_progress = false;
1985 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1986
1987 halrf_rfk_handshake(dm, false);
1988 } else {
1989 RF_DBG(dm, DBG_RF_IQK,
1990 "== Return the IQK CMD, because RFKs in Progress ==\n");
1991 }
1992 }
1993
1994
halrf_iqk_trigger(void * dm_void,boolean is_recovery)1995 void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
1996 {
1997 struct dm_struct *dm = (struct dm_struct *)dm_void;
1998 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1999 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2000 struct _hal_rf_ *rf = &dm->rf_table;
2001 u64 start_time;
2002
2003 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2004 if (odm_check_power_status(dm) == false)
2005 return;
2006 #endif
2007
2008 if (!dm->mp_mode)
2009 return;
2010
2011 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2012 rf->is_carrier_suppresion) {
2013 if (*dm->mp_mode &
2014 (*rf->is_con_tx || *rf->is_single_tone ||
2015 *rf->is_carrier_suppresion))
2016 return;
2017 }
2018
2019 if (!(rf->rf_supportability & HAL_RF_IQK))
2020 return;
2021
2022 #if DISABLE_BB_RF
2023 return;
2024 #endif
2025
2026 if (iqk_info->rfk_forbidden)
2027 return;
2028
2029 rf->rfk_type = RF01_IQK;
2030 halrf_rfk_handshake(dm, true);
2031
2032 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
2033 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2034 dm->rf_calibrate_info.is_iqk_in_progress = true;
2035 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2036 start_time = odm_get_current_time(dm);
2037 halrf_rfk_power_save(dm, false);
2038 switch (dm->support_ic_type) {
2039 #if (RTL8188E_SUPPORT == 1)
2040 case ODM_RTL8188E:
2041 phy_iq_calibrate_8188e(dm, is_recovery);
2042 break;
2043 #endif
2044 #if (RTL8188F_SUPPORT == 1)
2045 case ODM_RTL8188F:
2046 phy_iq_calibrate_8188f(dm, is_recovery);
2047 break;
2048 #endif
2049 #if (RTL8192E_SUPPORT == 1)
2050 case ODM_RTL8192E:
2051 phy_iq_calibrate_8192e(dm, is_recovery);
2052 break;
2053 #endif
2054 #if (RTL8197F_SUPPORT == 1)
2055 case ODM_RTL8197F:
2056 phy_iq_calibrate_8197f(dm, is_recovery);
2057 break;
2058 #endif
2059 #if (RTL8192F_SUPPORT == 1)
2060 case ODM_RTL8192F:
2061 phy_iq_calibrate_8192f(dm, is_recovery);
2062 break;
2063 #endif
2064 #if (RTL8703B_SUPPORT == 1)
2065 case ODM_RTL8703B:
2066 phy_iq_calibrate_8703b(dm, is_recovery);
2067 break;
2068 #endif
2069 #if (RTL8710B_SUPPORT == 1)
2070 case ODM_RTL8710B:
2071 phy_iq_calibrate_8710b(dm, is_recovery);
2072 break;
2073 #endif
2074 #if (RTL8723B_SUPPORT == 1)
2075 case ODM_RTL8723B:
2076 phy_iq_calibrate_8723b(dm, is_recovery);
2077 break;
2078 #endif
2079 #if (RTL8723D_SUPPORT == 1)
2080 case ODM_RTL8723D:
2081 phy_iq_calibrate_8723d(dm, is_recovery);
2082 break;
2083 #endif
2084 #if (RTL8721D_SUPPORT == 1)
2085 case ODM_RTL8721D:
2086 phy_iq_calibrate_8721d(dm, is_recovery);
2087 break;
2088 #endif
2089 #if (RTL8812A_SUPPORT == 1)
2090 case ODM_RTL8812:
2091 phy_iq_calibrate_8812a(dm, is_recovery);
2092 break;
2093 #endif
2094 #if (RTL8821A_SUPPORT == 1)
2095 case ODM_RTL8821:
2096 phy_iq_calibrate_8821a(dm, is_recovery);
2097 break;
2098 #endif
2099 #if (RTL8814A_SUPPORT == 1)
2100 case ODM_RTL8814A:
2101 phy_iq_calibrate_8814a(dm, is_recovery);
2102 break;
2103 #endif
2104 #if (RTL8822B_SUPPORT == 1)
2105 case ODM_RTL8822B:
2106 phy_iq_calibrate_8822b(dm, false, false);
2107 break;
2108 #endif
2109 #if (RTL8822C_SUPPORT == 1)
2110 case ODM_RTL8822C:
2111 phy_iq_calibrate_8822c(dm, false, false);
2112 break;
2113 #endif
2114 #if (RTL8821C_SUPPORT == 1)
2115 case ODM_RTL8821C:
2116 phy_iq_calibrate_8821c(dm, false, false);
2117 break;
2118 #endif
2119 #if (RTL8814B_SUPPORT == 1)
2120 case ODM_RTL8814B:
2121 phy_iq_calibrate_8814b(dm, false, false);
2122 break;
2123 #endif
2124 #if (RTL8195B_SUPPORT == 1)
2125 case ODM_RTL8195B:
2126 phy_iq_calibrate_8195b(dm, false, false);
2127 break;
2128 #endif
2129 #if (RTL8710C_SUPPORT == 1)
2130 case ODM_RTL8710C:
2131 phy_iq_calibrate_8710c(dm, false, false);
2132 break;
2133 #endif
2134 #if (RTL8198F_SUPPORT == 1)
2135 case ODM_RTL8198F:
2136 phy_iq_calibrate_8198f(dm, false, false);
2137 break;
2138 #endif
2139 #if (RTL8812F_SUPPORT == 1)
2140 case ODM_RTL8812F:
2141 phy_iq_calibrate_8812f(dm, false, false);
2142 break;
2143 #endif
2144 #if (RTL8197G_SUPPORT == 1)
2145 case ODM_RTL8197G:
2146 phy_iq_calibrate_8197g(dm, false, false);
2147 break;
2148 #endif
2149 #if (RTL8723F_SUPPORT == 1)
2150 case ODM_RTL8723F:
2151 phy_iq_calibrate_8723f(dm, is_recovery);
2152 break;
2153 #endif
2154 #if (RTL8814C_SUPPORT == 1)
2155 case ODM_RTL8814C:
2156 phy_iq_calibrate_8814c(dm, false, false);
2157 break;
2158 #endif
2159
2160 default:
2161 break;
2162 }
2163
2164 halrf_rfk_power_save(dm, true);
2165 rf->iqk_progressing_time = odm_get_progressing_time(dm, start_time);
2166 RF_DBG(dm, DBG_RF_LCK, "[IQK]Trigger IQK progressing_time = %lld ms\n",
2167 rf->iqk_progressing_time);
2168 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2169 dm->rf_calibrate_info.is_iqk_in_progress = false;
2170 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2171
2172 halrf_rfk_handshake(dm, false);
2173 } else {
2174 RF_DBG(dm, DBG_RF_IQK,
2175 "== Return the IQK CMD, because RFKs in Progress ==\n");
2176 }
2177 }
2178
halrf_lck_trigger(void * dm_void)2179 void halrf_lck_trigger(void *dm_void)
2180 {
2181 struct dm_struct *dm = (struct dm_struct *)dm_void;
2182 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2183 struct _hal_rf_ *rf = &dm->rf_table;
2184 u64 start_time;
2185
2186 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2187 if (odm_check_power_status(dm) == false)
2188 return;
2189 #endif
2190
2191 if (!dm->mp_mode)
2192 return;
2193
2194 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2195 rf->is_carrier_suppresion) {
2196 if (*dm->mp_mode &
2197 (*rf->is_con_tx || *rf->is_single_tone ||
2198 *rf->is_carrier_suppresion))
2199 return;
2200 }
2201
2202 if (!(rf->rf_supportability & HAL_RF_LCK))
2203 return;
2204
2205 #if DISABLE_BB_RF
2206 return;
2207 #endif
2208 if (iqk_info->rfk_forbidden)
2209 return;
2210 while (*dm->is_scan_in_process) {
2211 RF_DBG(dm, DBG_RF_LCK, "[LCK]scan is in process, bypass LCK\n");
2212 return;
2213 }
2214
2215 if (!dm->rf_calibrate_info.is_lck_in_progress) {
2216 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2217 dm->rf_calibrate_info.is_lck_in_progress = true;
2218 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2219 start_time = odm_get_current_time(dm);
2220 switch (dm->support_ic_type) {
2221 #if (RTL8188E_SUPPORT == 1)
2222 case ODM_RTL8188E:
2223 phy_lc_calibrate_8188e(dm);
2224 break;
2225 #endif
2226 #if (RTL8188F_SUPPORT == 1)
2227 case ODM_RTL8188F:
2228 phy_lc_calibrate_8188f(dm);
2229 break;
2230 #endif
2231 #if (RTL8192E_SUPPORT == 1)
2232 case ODM_RTL8192E:
2233 phy_lc_calibrate_8192e(dm);
2234 break;
2235 #endif
2236 #if (RTL8197F_SUPPORT == 1)
2237 case ODM_RTL8197F:
2238 phy_lc_calibrate_8197f(dm);
2239 break;
2240 #endif
2241 #if (RTL8192F_SUPPORT == 1)
2242 case ODM_RTL8192F:
2243 phy_lc_calibrate_8192f(dm);
2244 break;
2245 #endif
2246 #if (RTL8703B_SUPPORT == 1)
2247 case ODM_RTL8703B:
2248 phy_lc_calibrate_8703b(dm);
2249 break;
2250 #endif
2251 #if (RTL8710B_SUPPORT == 1)
2252 case ODM_RTL8710B:
2253 phy_lc_calibrate_8710b(dm);
2254 break;
2255 #endif
2256 #if (RTL8721D_SUPPORT == 1)
2257 case ODM_RTL8721D:
2258 phy_lc_calibrate_8721d(dm);
2259 break;
2260 #endif
2261 #if (RTL8723B_SUPPORT == 1)
2262 case ODM_RTL8723B:
2263 phy_lc_calibrate_8723b(dm);
2264 break;
2265 #endif
2266 #if (RTL8723D_SUPPORT == 1)
2267 case ODM_RTL8723D:
2268 phy_lc_calibrate_8723d(dm);
2269 break;
2270 #endif
2271 #if (RTL8812A_SUPPORT == 1)
2272 case ODM_RTL8812:
2273 phy_lc_calibrate_8812a(dm);
2274 break;
2275 #endif
2276 #if (RTL8821A_SUPPORT == 1)
2277 case ODM_RTL8821:
2278 phy_lc_calibrate_8821a(dm);
2279 break;
2280 #endif
2281 #if (RTL8814A_SUPPORT == 1)
2282 case ODM_RTL8814A:
2283 phy_lc_calibrate_8814a(dm);
2284 break;
2285 #endif
2286 #if (RTL8822B_SUPPORT == 1)
2287 case ODM_RTL8822B:
2288 phy_lc_calibrate_8822b(dm);
2289 break;
2290 #endif
2291 #if (RTL8822C_SUPPORT == 1)
2292 case ODM_RTL8822C:
2293 phy_lc_calibrate_8822c(dm);
2294 break;
2295 #endif
2296 #if (RTL8812F_SUPPORT == 1)
2297 case ODM_RTL8812F:
2298 phy_lc_calibrate_8812f(dm);
2299 break;
2300 #endif
2301 #if (RTL8821C_SUPPORT == 1)
2302 case ODM_RTL8821C:
2303 phy_lc_calibrate_8821c(dm);
2304 break;
2305 #endif
2306 #if (RTL8814B_SUPPORT == 1)
2307 case ODM_RTL8814B:
2308 phy_lc_calibrate_8814b(dm);
2309 break;
2310 #endif
2311 #if (RTL8197G_SUPPORT == 1)
2312 case ODM_RTL8197G:
2313 phy_lc_calibrate_8197g(dm);
2314 break;
2315 #endif
2316 #if (RTL8198F_SUPPORT == 1)
2317 case ODM_RTL8198F:
2318 phy_lc_calibrate_8198f(dm);
2319 break;
2320 #endif
2321 #if (RTL8710C_SUPPORT == 1)
2322 case ODM_RTL8710C:
2323 phy_lc_calibrate_8710c(dm);
2324 break;
2325 #endif
2326 #if (RTL8723F_SUPPORT == 1)
2327 case ODM_RTL8723F:
2328 phy_lc_calibrate_8723f(dm);
2329 break;
2330 #endif
2331 #if (RTL8814C_SUPPORT == 1)
2332 case ODM_RTL8814C:
2333 phy_lc_calibrate_8814c(dm);
2334 break;
2335 #endif
2336
2337
2338 default:
2339 break;
2340 }
2341 dm->rf_calibrate_info.lck_progressing_time =
2342 odm_get_progressing_time(dm, start_time);
2343 RF_DBG(dm, DBG_RF_LCK, "[LCK]LCK progressing_time = %lld ms\n",
2344 dm->rf_calibrate_info.lck_progressing_time);
2345 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
2346 halrf_lck_dbg(dm);
2347 #endif
2348 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2349 dm->rf_calibrate_info.is_lck_in_progress = false;
2350 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2351 } else {
2352 RF_DBG(dm, DBG_RF_LCK,
2353 "[LCK]= Return the LCK CMD, because RFK is in Progress =\n");
2354 }
2355 }
2356
halrf_aac_check(struct dm_struct * dm)2357 void halrf_aac_check(struct dm_struct *dm)
2358 {
2359 switch (dm->support_ic_type) {
2360 #if (RTL8821C_SUPPORT == 1)
2361 case ODM_RTL8821C:
2362 #if 0
2363 aac_check_8821c(dm);
2364 #endif
2365 break;
2366 #endif
2367 #if (RTL8822B_SUPPORT == 1)
2368 case ODM_RTL8822B:
2369 #if 1
2370 aac_check_8822b(dm);
2371 #endif
2372 break;
2373 #endif
2374 default:
2375 break;
2376 }
2377 }
2378
halrf_rxdck(void * dm_void)2379 void halrf_rxdck(void *dm_void)
2380 {
2381 struct dm_struct *dm = (struct dm_struct *)dm_void;
2382 struct _hal_rf_ *rf = &dm->rf_table;
2383
2384 if (!(rf->rf_supportability & HAL_RF_RXDCK))
2385 return;
2386
2387 switch (dm->support_ic_type) {
2388 case ODM_RTL8822C:
2389 #if (RTL8822C_SUPPORT == 1)
2390 halrf_rxdck_8822c(dm);
2391 break;
2392 #endif
2393 default:
2394 break;
2395 }
2396 }
2397
halrf_x2k_check(struct dm_struct * dm)2398 void halrf_x2k_check(struct dm_struct *dm)
2399 {
2400
2401 switch (dm->support_ic_type) {
2402 case ODM_RTL8821C:
2403 #if (RTL8821C_SUPPORT == 1)
2404 #endif
2405 break;
2406 case ODM_RTL8822C:
2407 #if (RTL8822C_SUPPORT == 1)
2408 phy_x2_check_8822c(dm);
2409 break;
2410 #endif
2411 case ODM_RTL8812F:
2412 #if (RTL8812F_SUPPORT == 1)
2413 phy_x2_check_8812f(dm);
2414 break;
2415 #endif
2416 case ODM_RTL8723F:
2417 #if (RTL8723F_SUPPORT == 1)
2418 phy_x2_check_8723f(dm);
2419 break;
2420 #endif
2421
2422 default:
2423 break;
2424 }
2425 }
2426
halrf_set_rfsupportability(void * dm_void)2427 void halrf_set_rfsupportability(void *dm_void)
2428 {
2429 struct dm_struct *dm = (struct dm_struct *)dm_void;
2430 struct _hal_rf_ *rf = &dm->rf_table;
2431
2432 if (!dm->mp_mode)
2433 return;
2434
2435 if (rf->manual_rf_supportability &&
2436 *rf->manual_rf_supportability != 0xffffffff) {
2437 rf->rf_supportability = *rf->manual_rf_supportability;
2438 } else if (*dm->mp_mode) {
2439 halrf_supportability_init_mp(dm);
2440 } else {
2441 halrf_supportability_init(dm);
2442 }
2443 }
2444
halrf_rfe_definition(struct dm_struct * dm)2445 void halrf_rfe_definition(struct dm_struct *dm)
2446 {
2447 struct _hal_rf_ *rf = &dm->rf_table;
2448
2449 switch (dm->support_ic_type) {
2450 case ODM_RTL8822C:
2451 #if (RTL8822C_SUPPORT == 1)
2452 if (dm->rfe_type == 21 || dm->rfe_type == 22) {
2453 rf->ext_pa_5g = 1;
2454 rf->ext_lna_5g = 1;
2455 }
2456 break;
2457 #endif
2458 default:
2459 break;
2460 }
2461 }
2462
halrf_init(void * dm_void)2463 void halrf_init(void *dm_void)
2464 {
2465 struct dm_struct *dm = (struct dm_struct *)dm_void;
2466 struct _hal_rf_ *rf = &dm->rf_table;
2467
2468 RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n");
2469 rf->aac_checked = false;
2470 halrf_init_debug_setting(dm);
2471 halrf_set_rfsupportability(dm);
2472 halrf_rfe_definition(dm);
2473 #if 1
2474 /*Init all RF funciton*/
2475 halrf_aac_check(dm);
2476 halrf_dack_trigger(dm, false);
2477 halrf_x2k_check(dm);
2478 #endif
2479
2480 /*power trim, thrmal trim, pa bias*/
2481 phydm_config_new_kfree(dm);
2482
2483 /*TSSI Init*/
2484 halrf_tssi_dck(dm, true);
2485 halrf_tssi_get_efuse(dm);
2486 halrf_tssi_set_de(dm);
2487 #if (RTL8723F_SUPPORT == 1)
2488 halrf_do_tssi(dm);
2489 halrf_rx_port_ctl_8723f(dm);
2490 #endif
2491
2492 /*TX Gap K*/
2493 halrf_txgapk_write_gain_table(dm);
2494 }
2495
halrf_dpk_trigger(void * dm_void)2496 void halrf_dpk_trigger(void *dm_void)
2497 {
2498 struct dm_struct *dm = (struct dm_struct *)dm_void;
2499 struct _hal_rf_ *rf = &dm->rf_table;
2500 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2501 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2502
2503 u64 start_time;
2504
2505 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2506 if (odm_check_power_status(dm) == false)
2507 return;
2508 #endif
2509
2510 if (!dm->mp_mode)
2511 return;
2512
2513 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2514 rf->is_carrier_suppresion) {
2515 if (*dm->mp_mode &
2516 (*rf->is_con_tx || *rf->is_single_tone ||
2517 *rf->is_carrier_suppresion))
2518 return;
2519 }
2520
2521 if (!(rf->rf_supportability & HAL_RF_DPK))
2522 return;
2523
2524 #if DISABLE_BB_RF
2525 return;
2526 #endif
2527
2528 if (iqk_info->rfk_forbidden)
2529 return;
2530
2531 rf->rfk_type = RF03_DPK;
2532 halrf_rfk_handshake(dm, true);
2533
2534 if (!rf->is_dpk_in_progress) {
2535 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2536 rf->is_dpk_in_progress = true;
2537 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2538 start_time = odm_get_current_time(dm);
2539 halrf_rfk_power_save(dm, false);
2540 switch (dm->support_ic_type) {
2541 #if (RTL8822C_SUPPORT == 1)
2542 case ODM_RTL8822C:
2543 do_dpk_8822c(dm);
2544 break;
2545 #endif
2546 #if (RTL8814C_SUPPORT == 1)
2547 case ODM_RTL8814C:
2548 do_dpk_8814c(dm);
2549 break;
2550 #endif
2551
2552 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2553 #if (RTL8197F_SUPPORT == 1)
2554 case ODM_RTL8197F:
2555 do_dpk_8197f(dm);
2556 break;
2557 #endif
2558 #if (RTL8192F_SUPPORT == 1)
2559 case ODM_RTL8192F:
2560 do_dpk_8192f(dm);
2561 break;
2562 #endif
2563
2564 #if (RTL8198F_SUPPORT == 1)
2565 case ODM_RTL8198F:
2566 do_dpk_8198f(dm);
2567 break;
2568 #endif
2569 #if (RTL8812F_SUPPORT == 1)
2570 case ODM_RTL8812F:
2571 do_dpk_8812f(dm);
2572 break;
2573 #endif
2574 #if (RTL8197G_SUPPORT == 1)
2575 case ODM_RTL8197G:
2576 do_dpk_8197g(dm);
2577 break;
2578 #endif
2579
2580 #endif
2581
2582 #if (RTL8814B_SUPPORT == 1)
2583 case ODM_RTL8814B:
2584 do_dpk_8814b(dm);
2585 break;
2586 #endif
2587 #if (RTL8723F_SUPPORT == 1)
2588 case ODM_RTL8723F:
2589 do_dpk_8723f(dm);
2590 break;
2591 #endif
2592
2593 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2594 #if (RTL8195B_SUPPORT == 1)
2595 case ODM_RTL8195B:
2596 do_dpk_8195b(dm);
2597 break;
2598 #endif
2599 #if (RTL8721D_SUPPORT == 1)
2600 case ODM_RTL8721D:
2601 do_dpk_8721d(dm);
2602 break;
2603 #endif
2604
2605 #endif
2606 default:
2607 break;
2608 }
2609 halrf_rfk_power_save(dm, true);
2610 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
2611 RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n",
2612 rf->dpk_progressing_time);
2613
2614 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2615 rf->is_dpk_in_progress = false;
2616 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2617
2618 halrf_rfk_handshake(dm, false);
2619 } else {
2620 RF_DBG(dm, DBG_RF_DPK,
2621 "== Return the DPK CMD, because RFKs in Progress ==\n");
2622 }
2623 }
2624
halrf_set_dpkbychannel(void * dm_void,boolean dpk_by_ch)2625 void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch)
2626 {
2627 struct dm_struct *dm = (struct dm_struct *)dm_void;
2628 struct _hal_rf_ *rf = &dm->rf_table;
2629 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2630 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2631
2632
2633 switch (dm->support_ic_type) {
2634 #if (RTL8814B_SUPPORT == 1)
2635 case ODM_RTL8814B:
2636 dpk_set_dpkbychannel_8814b(dm, dpk_by_ch);
2637 break;
2638 #endif
2639
2640 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2641 #if (RTL8195B_SUPPORT == 1)
2642 case ODM_RTL8195B:
2643 dpk_set_dpkbychannel_8195b(dm,dpk_by_ch);
2644 break;
2645 #endif
2646 #endif
2647 #if (RTL8814C_SUPPORT == 1)
2648 case ODM_RTL8814C:
2649 dpk_set_dpkbychannel_8814c(dm, dpk_by_ch);
2650 break;
2651 #endif
2652
2653 default:
2654 if (dpk_by_ch)
2655 dpk_info->is_dpk_by_channel = 1;
2656 else
2657 dpk_info->is_dpk_by_channel = 0;
2658 break;
2659 }
2660
2661 }
2662
halrf_set_dpkenable(void * dm_void,boolean is_dpk_enable)2663 void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable)
2664 {
2665 struct dm_struct *dm = (struct dm_struct *)dm_void;
2666 struct _hal_rf_ *rf = &dm->rf_table;
2667 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2668 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2669
2670
2671 switch (dm->support_ic_type) {
2672 #if (RTL8814B_SUPPORT == 1)
2673 case ODM_RTL8814B:
2674 dpk_set_is_dpk_enable_8814b(dm, is_dpk_enable);
2675 break;
2676 #endif
2677
2678 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2679 #if (RTL8195B_SUPPORT == 1)
2680 case ODM_RTL8195B:
2681 dpk_set_is_dpk_enable_8195b(dm, is_dpk_enable);
2682 break;
2683 #endif
2684
2685 #if (RTL8721D_SUPPORT == 1)
2686 case ODM_RTL8721D:
2687 dpk_set_is_dpk_enable_8721d(dm, is_dpk_enable);
2688 break;
2689 #endif
2690
2691 #endif
2692 #if (RTL8814C_SUPPORT == 1)
2693 case ODM_RTL8814C:
2694 dpk_set_is_dpk_enable_8814c(dm, is_dpk_enable);
2695 break;
2696 #endif
2697
2698 default:
2699 break;
2700 }
2701
2702 }
halrf_get_dpkbychannel(void * dm_void)2703 boolean halrf_get_dpkbychannel(void *dm_void)
2704 {
2705 struct dm_struct *dm = (struct dm_struct *)dm_void;
2706 struct _hal_rf_ *rf = &dm->rf_table;
2707 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2708 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2709 boolean is_dpk_by_channel = true;
2710
2711 switch (dm->support_ic_type) {
2712 #if (RTL8814B_SUPPORT == 1)
2713 case ODM_RTL8814B:
2714 is_dpk_by_channel = dpk_get_dpkbychannel_8814b(dm);
2715 break;
2716 #endif
2717
2718 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2719 #if (RTL8195B_SUPPORT == 1)
2720 case ODM_RTL8195B:
2721 is_dpk_by_channel = dpk_get_dpkbychannel_8195b(dm);
2722 break;
2723 #endif
2724 #endif
2725
2726 #if (RTL8814C_SUPPORT == 1)
2727 case ODM_RTL8814C:
2728 is_dpk_by_channel = dpk_get_dpkbychannel_8814c(dm);
2729 break;
2730 #endif
2731
2732
2733 default:
2734 break;
2735 }
2736 return is_dpk_by_channel;
2737
2738 }
2739
2740
halrf_get_dpkenable(void * dm_void)2741 boolean halrf_get_dpkenable(void *dm_void)
2742 {
2743 struct dm_struct *dm = (struct dm_struct *)dm_void;
2744 struct _hal_rf_ *rf = &dm->rf_table;
2745 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2746 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2747 boolean is_dpk_enable = true;
2748
2749
2750 switch (dm->support_ic_type) {
2751 #if (RTL8814B_SUPPORT == 1)
2752 case ODM_RTL8814B:
2753 is_dpk_enable = dpk_get_is_dpk_enable_8814b(dm);
2754 break;
2755 #endif
2756
2757 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2758 #if (RTL8195B_SUPPORT == 1)
2759 case ODM_RTL8195B:
2760 is_dpk_enable = dpk_get_is_dpk_enable_8195b(dm);
2761 break;
2762 #endif
2763 #endif
2764 #if (RTL8814C_SUPPORT == 1)
2765 case ODM_RTL8814C:
2766 is_dpk_enable = dpk_get_is_dpk_enable_8814c(dm);
2767 break;
2768 #endif
2769
2770 default:
2771 break;
2772 }
2773 return is_dpk_enable;
2774
2775 }
2776
halrf_dpk_result_check(void * dm_void)2777 u8 halrf_dpk_result_check(void *dm_void)
2778 {
2779 struct dm_struct *dm = (struct dm_struct *)dm_void;
2780 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2781
2782 u8 result = 0;
2783
2784 switch (dm->support_ic_type) {
2785 #if (RTL8822C_SUPPORT == 1)
2786 case ODM_RTL8822C:
2787 if (dpk_info->dpk_path_ok == 0x3)
2788 result = 1;
2789 else
2790 result = 0;
2791 break;
2792 #endif
2793
2794 #if (RTL8195B_SUPPORT == 1)
2795 case ODM_RTL8195B:
2796 if (dpk_info->dpk_path_ok == 0x1)
2797 result = 1;
2798 else
2799 result = 0;
2800 break;
2801 #endif
2802
2803 #if (RTL8721D_SUPPORT == 1)
2804 case ODM_RTL8721D:
2805 if (dpk_info->dpk_path_ok == 0x1)
2806 result = 1;
2807 else
2808 result = 0;
2809 break;
2810 #endif
2811
2812 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2813
2814 #if (RTL8197F_SUPPORT == 1)
2815 case ODM_RTL8197F:
2816 if (dpk_info->dpk_path_ok == 0x3)
2817 result = 1;
2818 else
2819 result = 0;
2820 break;
2821 #endif
2822
2823 #if (RTL8192F_SUPPORT == 1)
2824 case ODM_RTL8192F:
2825 if (dpk_info->dpk_path_ok == 0x3)
2826 result = 1;
2827 else
2828 result = 0;
2829 break;
2830 #endif
2831
2832 #if (RTL8198F_SUPPORT == 1)
2833 case ODM_RTL8198F:
2834 if (dpk_info->dpk_path_ok == 0xf)
2835 result = 1;
2836 else
2837 result = 0;
2838 break;
2839 #endif
2840
2841 #if (RTL8814B_SUPPORT == 1)
2842 case ODM_RTL8814B:
2843 if (dpk_info->dpk_path_ok == 0xf)
2844 result = 1;
2845 else
2846 result = 0;
2847 break;
2848 #endif
2849 #if (RTL8814C_SUPPORT == 1)
2850 case ODM_RTL8814C:
2851 if (dpk_info->dpk_path_ok == 0xf)
2852 result = 1;
2853 else
2854 result = 0;
2855 break;
2856 #endif
2857
2858
2859 #if (RTL8812F_SUPPORT == 1)
2860 case ODM_RTL8812F:
2861 if (dpk_info->dpk_path_ok == 0x3)
2862 result = 1;
2863 else
2864 result = 0;
2865 break;
2866 #endif
2867
2868 #if (RTL8197G_SUPPORT == 1)
2869 case ODM_RTL8197G:
2870 if (dpk_info->dpk_path_ok == 0x3)
2871 result = 1;
2872 else
2873 result = 0;
2874 break;
2875 #endif
2876
2877 #endif
2878 default:
2879 break;
2880 }
2881 return result;
2882 }
2883
halrf_dpk_sram_read(void * dm_void)2884 void halrf_dpk_sram_read(void *dm_void)
2885 {
2886 struct dm_struct *dm = (struct dm_struct *)dm_void;
2887
2888 u8 path, group;
2889
2890 switch (dm->support_ic_type) {
2891 #if (RTL8822C_SUPPORT == 1)
2892 case ODM_RTL8822C:
2893 dpk_coef_read_8822c(dm);
2894 break;
2895 #endif
2896
2897 #if (RTL8195B_SUPPORT == 1)
2898 case ODM_RTL8195B:
2899 dpk_sram_read_8195b(dm);
2900 break;
2901 #endif
2902
2903 #if (RTL8721D_SUPPORT == 1)
2904 case ODM_RTL8721D:
2905 dpk_sram_read_8721d(dm);
2906 break;
2907 #endif
2908
2909 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2910
2911 #if (RTL8197F_SUPPORT == 1)
2912 case ODM_RTL8197F:
2913 dpk_sram_read_8197f(dm);
2914 break;
2915 #endif
2916
2917 #if (RTL8192F_SUPPORT == 1)
2918 case ODM_RTL8192F:
2919 dpk_sram_read_8192f(dm);
2920 break;
2921 #endif
2922
2923 #if (RTL8198F_SUPPORT == 1)
2924 case ODM_RTL8198F:
2925 dpk_sram_read_8198f(dm);
2926 break;
2927 #endif
2928
2929 #if (RTL8814B_SUPPORT == 1)
2930 case ODM_RTL8814B:
2931 dpk_sram_read_8814b(dm);
2932 break;
2933 #endif
2934
2935 #if (RTL8812F_SUPPORT == 1)
2936 case ODM_RTL8812F:
2937 dpk_coef_read_8812f(dm);
2938 break;
2939 #endif
2940
2941 #if (RTL8197G_SUPPORT == 1)
2942 case ODM_RTL8197G:
2943 dpk_sram_read_8197g(dm);
2944 break;
2945 #endif
2946
2947 #if (RTL8814C_SUPPORT == 1)
2948 case ODM_RTL8814C:
2949 dpk_sram_read_8814c(dm);
2950 break;
2951 #endif
2952
2953 #endif
2954
2955 default:
2956 break;
2957 }
2958 }
2959
halrf_dpk_enable_disable(void * dm_void)2960 void halrf_dpk_enable_disable(void *dm_void)
2961 {
2962 struct dm_struct *dm = (struct dm_struct *)dm_void;
2963 struct _hal_rf_ *rf = &dm->rf_table;
2964
2965 if (!(rf->rf_supportability & HAL_RF_DPK))
2966 return;
2967
2968 if (!rf->is_dpk_in_progress) {
2969 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2970 rf->is_dpk_in_progress = true;
2971 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2972
2973 switch (dm->support_ic_type) {
2974 #if (RTL8822C_SUPPORT == 1)
2975 case ODM_RTL8822C:
2976 dpk_enable_disable_8822c(dm);
2977 break;
2978 #endif
2979 #if (RTL8195B_SUPPORT == 1)
2980 case ODM_RTL8195B:
2981 dpk_enable_disable_8195b(dm);
2982 break;
2983 #endif
2984 #if (RTL8721D_SUPPORT == 1)
2985 case ODM_RTL8721D:
2986 phy_dpk_enable_disable_8721d(dm);
2987 break;
2988 #endif
2989
2990 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2991
2992 #if (RTL8197F_SUPPORT == 1)
2993 case ODM_RTL8197F:
2994 phy_dpk_enable_disable_8197f(dm);
2995 break;
2996 #endif
2997 #if (RTL8192F_SUPPORT == 1)
2998 case ODM_RTL8192F:
2999 phy_dpk_enable_disable_8192f(dm);
3000 break;
3001 #endif
3002
3003 #if (RTL8198F_SUPPORT == 1)
3004 case ODM_RTL8198F:
3005 dpk_enable_disable_8198f(dm);
3006 break;
3007 #endif
3008
3009 #if (RTL8814B_SUPPORT == 1)
3010 case ODM_RTL8814B:
3011 dpk_enable_disable_8814b(dm);
3012 break;
3013 #endif
3014
3015 #if (RTL8812F_SUPPORT == 1)
3016 case ODM_RTL8812F:
3017 dpk_enable_disable_8812f(dm);
3018 break;
3019 #endif
3020
3021 #if (RTL8197G_SUPPORT == 1)
3022 case ODM_RTL8197G:
3023 dpk_enable_disable_8197g(dm);
3024 break;
3025 #endif
3026
3027 #if (RTL8723F_SUPPORT == 1)
3028 case ODM_RTL8723F:
3029 dpk_enable_disable_8723f(dm);
3030 break;
3031 #endif
3032 #if (RTL8814C_SUPPORT == 1)
3033 case ODM_RTL8814C:
3034 dpk_enable_disable_8814c(dm);
3035 break;
3036 #endif
3037
3038 #endif
3039 default:
3040 break;
3041 }
3042
3043 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
3044 rf->is_dpk_in_progress = false;
3045 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
3046 } else {
3047 RF_DBG(dm, DBG_RF_DPK,
3048 "== Return the DPK CMD, because RFKs in Progress ==\n");
3049 }
3050 }
3051
halrf_dpk_track(void * dm_void)3052 void halrf_dpk_track(void *dm_void)
3053 {
3054 struct dm_struct *dm = (struct dm_struct *)dm_void;
3055 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3056 struct _hal_rf_ *rf = &dm->rf_table;
3057
3058 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
3059 dm->is_psd_in_process || (dpk_info->dpk_path_ok == 0) ||
3060 !(rf->rf_supportability & HAL_RF_DPK_TRACK) || rf->is_tssi_in_progress
3061 || rf->is_txgapk_in_progress)
3062 return;
3063
3064 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3065 if (*dm->is_fcs_mode_enable)
3066 return;
3067 #endif
3068
3069 switch (dm->support_ic_type) {
3070 #if (RTL8814B_SUPPORT == 1)
3071 case ODM_RTL8814B:
3072 dpk_track_8814b(dm);
3073 break;
3074 #endif
3075
3076 #if (RTL8822C_SUPPORT == 1)
3077 case ODM_RTL8822C:
3078 dpk_track_8822c(dm);
3079 break;
3080 #endif
3081
3082 #if (RTL8195B_SUPPORT == 1)
3083 case ODM_RTL8195B:
3084 dpk_track_8195b(dm);
3085 break;
3086 #endif
3087
3088 #if (RTL8721D_SUPPORT == 1)
3089 case ODM_RTL8721D:
3090 phy_dpk_track_8721d(dm);
3091 break;
3092 #endif
3093
3094 #if (RTL8723F_SUPPORT == 1)
3095 case ODM_RTL8723F:
3096 dpk_track_8723f(dm);
3097 break;
3098 #endif
3099
3100 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3101
3102 #if (RTL8197F_SUPPORT == 1)
3103 case ODM_RTL8197F:
3104 phy_dpk_track_8197f(dm);
3105 break;
3106 #endif
3107
3108 #if (RTL8192F_SUPPORT == 1)
3109 case ODM_RTL8192F:
3110 phy_dpk_track_8192f(dm);
3111 break;
3112 #endif
3113
3114 #if (RTL8198F_SUPPORT == 1)
3115 case ODM_RTL8198F:
3116 dpk_track_8198f(dm);
3117 break;
3118 #endif
3119
3120 #if (RTL8812F_SUPPORT == 1)
3121 case ODM_RTL8812F:
3122 dpk_track_8812f(dm);
3123 break;
3124 #endif
3125
3126 #if (RTL8197G_SUPPORT == 1)
3127 case ODM_RTL8197G:
3128 dpk_track_8197g(dm);
3129 break;
3130 #endif
3131
3132 #endif
3133 #if (RTL8814C_SUPPORT == 1)
3134 case ODM_RTL8814C:
3135 dpk_track_8814c(dm);
3136 break;
3137 #endif
3138
3139 default:
3140 break;
3141 }
3142 }
3143
halrf_set_dpk_track(void * dm_void,u8 enable)3144 void halrf_set_dpk_track(void *dm_void, u8 enable)
3145 {
3146 struct dm_struct *dm = (struct dm_struct *)dm_void;
3147 struct _hal_rf_ *rf = &(dm->rf_table);
3148
3149 if (enable)
3150 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK_TRACK;
3151 else
3152 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
3153 }
3154
halrf_dpk_reload(void * dm_void)3155 void halrf_dpk_reload(void *dm_void)
3156 {
3157 struct dm_struct *dm = (struct dm_struct *)dm_void;
3158 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3159
3160 switch (dm->support_ic_type) {
3161 #if (RTL8195B_SUPPORT == 1)
3162 case ODM_RTL8195B:
3163 if (dpk_info->dpk_path_ok > 0)
3164 dpk_reload_8195b(dm);
3165 break;
3166 #endif
3167 #if (RTL8721D_SUPPORT == 1)
3168 case ODM_RTL8721D:
3169 if (dpk_info->dpk_path_ok > 0)
3170 dpk_reload_8721d(dm);
3171 break;
3172 #endif
3173
3174 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3175
3176 #if (RTL8197F_SUPPORT == 1)
3177 case ODM_RTL8197F:
3178 if (dpk_info->dpk_path_ok > 0)
3179 dpk_reload_8197f(dm);
3180 break;
3181 #endif
3182
3183 #if (RTL8192F_SUPPORT == 1)
3184 case ODM_RTL8192F:
3185 if (dpk_info->dpk_path_ok > 0)
3186 dpk_reload_8192f(dm);
3187
3188 break;
3189 #endif
3190
3191 #if (RTL8198F_SUPPORT == 1)
3192 case ODM_RTL8198F:
3193 if (dpk_info->dpk_path_ok > 0)
3194 dpk_reload_8198f(dm);
3195 break;
3196 #endif
3197
3198 #if (RTL8814B_SUPPORT == 1)
3199 case ODM_RTL8814B:
3200 if (dpk_info->dpk_path_ok > 0)
3201 dpk_reload_8814b(dm);
3202 break;
3203 #endif
3204
3205 #if (RTL8814C_SUPPORT == 1)
3206 case ODM_RTL8814C:
3207 if (dpk_info->dpk_path_ok > 0)
3208 dpk_reload_8814c(dm);
3209 break;
3210 #endif
3211
3212
3213 #endif
3214 default:
3215 break;
3216 }
3217 }
3218
halrf_dpk_switch(void * dm_void,u8 enable)3219 void halrf_dpk_switch(void *dm_void, u8 enable)
3220 {
3221 struct dm_struct *dm = (struct dm_struct *)dm_void;
3222 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3223 struct _hal_rf_ *rf = &dm->rf_table;
3224
3225 if (enable) {
3226 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK;
3227 dpk_info->is_dpk_enable = true;
3228 halrf_dpk_enable_disable(dm);
3229 halrf_dpk_trigger(dm);
3230 halrf_set_dpk_track(dm, 1);
3231 } else {
3232 halrf_set_dpk_track(dm, 0);
3233 dpk_info->is_dpk_enable = false;
3234 halrf_dpk_enable_disable(dm);
3235 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK;
3236 }
3237 }
3238
_halrf_dpk_info_by_chip(void * dm_void,u32 * _used,char * output,u32 * _out_len)3239 void _halrf_dpk_info_by_chip(void *dm_void, u32 *_used, char *output, u32 *_out_len)
3240 {
3241 struct dm_struct *dm = (struct dm_struct *)dm_void;
3242
3243 u32 used = *_used;
3244 u32 out_len = *_out_len;
3245
3246 switch (dm->support_ic_type) {
3247 #if (RTL8822C_SUPPORT == 1)
3248 case ODM_RTL8822C:
3249 dpk_info_by_8822c(dm, &used, output, &out_len);
3250 break;
3251 #endif
3252
3253 #if (RTL8812F_SUPPORT == 1)
3254 case ODM_RTL8812F:
3255 dpk_info_by_8812f(dm, &used, output, &out_len);
3256 break;
3257 #endif
3258
3259 #if (RTL8197G_SUPPORT == 1)
3260 case ODM_RTL8197G:
3261 dpk_info_by_8197g(dm, &used, output, &out_len);
3262 break;
3263 #endif
3264
3265 default:
3266 break;
3267 }
3268
3269 *_used = used;
3270 *_out_len = out_len;
3271 }
3272
_halrf_display_dpk_info(void * dm_void,u32 * _used,char * output,u32 * _out_len)3273 void _halrf_display_dpk_info(void *dm_void, u32 *_used, char *output, u32 *_out_len)
3274 {
3275 struct dm_struct *dm = (struct dm_struct *)dm_void;
3276 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3277 struct _hal_rf_ *rf = &(dm->rf_table);
3278
3279 u32 used = *_used;
3280 u32 out_len = *_out_len;
3281 char *ic_name = NULL;
3282 u8 path;
3283
3284 switch (dm->support_ic_type) {
3285
3286 #if (RTL8822C_SUPPORT)
3287 case ODM_RTL8822C:
3288 ic_name = "8822C";
3289 break;
3290 #endif
3291
3292 #if (RTL8814B_SUPPORT)
3293 case ODM_RTL8814B:
3294 ic_name = "8814B";
3295 break;
3296 #endif
3297
3298 #if (RTL8812F_SUPPORT)
3299 case ODM_RTL8812F:
3300 ic_name = "8812F";
3301 break;
3302 #endif
3303
3304 #if (RTL8198F_SUPPORT)
3305 case ODM_RTL8198F:
3306 ic_name = "8198F";
3307 break;
3308 #endif
3309
3310 #if (RTL8197F_SUPPORT)
3311 case ODM_RTL8197F:
3312 ic_name = "8197F";
3313 break;
3314 #endif
3315
3316 #if (RTL8192F_SUPPORT)
3317 case ODM_RTL8192F:
3318 ic_name = "8192F";
3319 break;
3320 #endif
3321
3322 #if (RTL8197G_SUPPORT)
3323 case ODM_RTL8197G:
3324 ic_name = "8197G";
3325 break;
3326 #endif
3327
3328 #if (RTL8710B_SUPPORT)
3329 case ODM_RTL8721D:
3330 ic_name = "8721D";
3331 break;
3332 #endif
3333
3334 #if (RTL8195B_SUPPORT)
3335 case ODM_RTL8195B:
3336 ic_name = "8195B";
3337 break;
3338 #endif
3339 #if (RTL8814C_SUPPORT)
3340 case ODM_RTL8814C:
3341 ic_name = "8814C";
3342 break;
3343 #endif
3344 default:
3345 break;
3346 }
3347
3348 PDM_SNPF(out_len, used, output + used, out_len - used,
3349 "\n===============[ DPK info %s ]===============\n", ic_name);
3350
3351 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s %s\n",
3352 "DPK type", (dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD) ? "FW" : "Driver",
3353 (dpk_info->is_dpk_by_channel) ? "(By channel)" : "(By group)");
3354
3355 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d (%d)\n",
3356 "FW Ver (Sub Ver)", dm->fw_version, dm->fw_sub_version);
3357
3358 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3359 "DPK Ver", HALRF_DPK_VER);
3360
3361 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3362 "RFK init ver", HALRF_RFK_INIT_VER);
3363
3364 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d (RFE type:%d)\n",
3365 "Ext_PA 2G / 5G", dm->ext_pa, dm->ext_pa_5g, dm->rfe_type);
3366
3367 if ((dpk_info->dpk_ch == 0) && (dpk_info->thermal_dpk[0] == 0)) {
3368 PDM_SNPF(out_len, used, output + used, out_len - used, "\n %-25s\n",
3369 "No DPK had been done before!!!");
3370 return;
3371 }
3372
3373 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
3374 "DPK Cal / OK / Reload", dpk_info->dpk_cal_cnt, dpk_info->dpk_ok_cnt,
3375 dpk_info->dpk_reload_cnt);
3376
3377 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3378 "RFK H2C timeout", (rf->is_rfk_h2c_timeout) ? "Yes" : "No");
3379
3380 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3381 "DPD Reload", (dpk_info->dpk_status & BIT(0)) ? "Yes" : "No");
3382
3383 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3384 "DPD status", dpk_info->is_dpk_enable ? "Enable" : "Disable");
3385
3386 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3387 "DPD track status", (rf->rf_supportability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable");
3388
3389 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %d / %s\n",
3390 "TSSI / Band / CH / BW", dpk_info->is_tssi_mode == 1 ? "On" : "Off",
3391 dpk_info->dpk_band == 0 ? "2G" : "5G", dpk_info->dpk_ch,
3392 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
3393
3394 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %s / %s\n",
3395 "DPK result (path)", dpk_info->dpk_path_ok & BIT(0) ? "OK" : "Fail",
3396 (dm->support_ic_type & ODM_IC_2SS) ? ((dpk_info->dpk_path_ok & BIT(1)) >> 1 ? "OK" : "Fail") : "NA",
3397 (dm->support_ic_type & ODM_IC_3SS) ? ((dpk_info->dpk_path_ok & BIT(2)) >> 2 ? "OK" : "Fail") : "NA",
3398 (dm->support_ic_type & ODM_IC_4SS) ? ((dpk_info->dpk_path_ok & BIT(3)) >> 3 ? "OK" : "Fail") : "NA");
3399 #if 0
3400 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d / %d\n",
3401 "DPK thermal (path)", dpk_info->thermal_dpk[0], dpk_info->thermal_dpk[1],
3402 dpk_info->thermal_dpk[2], dpk_info->thermal_dpk[3]);
3403 #endif
3404 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = ",
3405 "DPK thermal (path)");
3406 for (path = 0; path < KPATH; path++) {
3407 PDM_SNPF(out_len, used, output + used, out_len - used,
3408 path == (KPATH - 1) ? "%d\n" : "%d / ",
3409 dpk_info->thermal_dpk[path]);
3410 }
3411
3412 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3413 "DPK bkup GNT control", dpk_info->gnt_control);
3414
3415 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3416 "DPK bkup GNT value", dpk_info->gnt_value);
3417
3418 _halrf_dpk_info_by_chip(dm, &used, output, &out_len);
3419
3420 *_used = used;
3421 *_out_len = out_len;
3422 }
3423
halrf_dpk_debug_cmd(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3424 void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
3425 char *output, u32 *_out_len)
3426 {
3427 struct dm_struct *dm = (struct dm_struct *)dm_void;
3428 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3429 struct _hal_rf_ *rf = &(dm->rf_table);
3430
3431 char *cmd[5] = {"-h", "on", "off", "info", "switch"};
3432 u32 used = *_used;
3433 u32 out_len = *_out_len;
3434 u8 i;
3435
3436 if ((strcmp(input[2], cmd[4]) != 0)) {
3437 if (!(rf->rf_supportability & HAL_RF_DPK)) {
3438 PDM_SNPF(out_len, used, output + used, out_len - used,
3439 "DPK is Unsupported!!!\n");
3440 return;
3441 }
3442 }
3443
3444 if ((strcmp(input[2], cmd[0]) == 0)) {
3445 for (i = 1; i < 4; i++) {
3446 PDM_SNPF(out_len, used, output + used, out_len - used,
3447 " %s\n", cmd[i]);
3448 }
3449 } else if ((strcmp(input[2], cmd[1]) == 0)) {
3450 PDM_SNPF(out_len, used, output + used, out_len - used,
3451 "DPK is Enabled!!\n");
3452 dpk_info->is_dpk_enable = true;
3453 halrf_dpk_enable_disable(dm);
3454 } else if ((strcmp(input[2], cmd[2]) == 0)){
3455 PDM_SNPF(out_len, used, output + used, out_len - used,
3456 "DPK is Disabled!!\n");
3457 dpk_info->is_dpk_enable = false;
3458 halrf_dpk_enable_disable(dm);
3459 } else if ((strcmp(input[2], cmd[3]) == 0))
3460 _halrf_display_dpk_info(dm, &used, output, &out_len);
3461 else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[1]) == 0)) {
3462 PDM_SNPF(out_len, used, output + used, out_len - used,
3463 "DPK Switch on!!\n");
3464 halrf_dpk_switch(dm, 1);
3465 } else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[2]) == 0)) {
3466 PDM_SNPF(out_len, used, output + used, out_len - used,
3467 "DPK Switch off!!\n");
3468 halrf_dpk_switch(dm, 0);
3469 } else {
3470 PDM_SNPF(out_len, used, output + used, out_len - used,
3471 "DPK Trigger start!!\n");
3472 halrf_dpk_trigger(dm);
3473 PDM_SNPF(out_len, used, output + used, out_len - used,
3474 "DPK Trigger finish!!\n");
3475 }
3476 }
3477
halrf_dpk_c2h_report_transfer(void * dm_void,boolean is_ok,u8 * buf,u8 buf_size)3478 void halrf_dpk_c2h_report_transfer(void *dm_void, boolean is_ok, u8 *buf, u8 buf_size)
3479 {
3480 struct dm_struct *dm = (struct dm_struct *)dm_void;
3481 struct _hal_rf_ *rf = &dm->rf_table;
3482 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3483
3484 if (!(rf->rf_supportability & HAL_RF_DPK))
3485 return;
3486
3487 switch (dm->support_ic_type) {
3488 #if (RTL8822C_SUPPORT == 1)
3489 case ODM_RTL8822C:
3490 dpk_c2h_report_transfer_8822c(dm, is_ok, buf, buf_size);
3491 break;
3492 #endif
3493 default:
3494 break;
3495 }
3496 }
3497
halrf_dpk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3498 void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3499 {
3500 struct dm_struct *dm = (struct dm_struct *)dm_void;
3501 struct _hal_rf_ *rf = &dm->rf_table;
3502 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3503
3504 if (!(rf->rf_supportability & HAL_RF_DPK) || rf->is_dpk_in_progress)
3505 return;
3506
3507 switch (dm->support_ic_type) {
3508 #if (RTL8822C_SUPPORT == 1)
3509 case ODM_RTL8822C:
3510 dpk_info_rsvd_page_8822c(dm, buf, buf_size);
3511 break;
3512 #endif
3513 default:
3514 break;
3515 }
3516 }
3517
halrf_iqk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3518 void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3519 {
3520 struct dm_struct *dm = (struct dm_struct *)dm_void;
3521 struct _hal_rf_ *rf = &dm->rf_table;
3522
3523 if (!(rf->rf_supportability & HAL_RF_IQK))
3524 return;
3525
3526 if (dm->rf_calibrate_info.is_iqk_in_progress)
3527 return;
3528
3529 switch (dm->support_ic_type) {
3530 #if (RTL8822C_SUPPORT == 1)
3531 case ODM_RTL8822C:
3532 iqk_info_rsvd_page_8822c(dm, buf, buf_size);
3533 break;
3534 #endif
3535 #if (RTL8195B_SUPPORT == 1)
3536 case ODM_RTL8195B:
3537 iqk_info_rsvd_page_8195b(dm, buf, buf_size);
3538 break;
3539 #endif
3540
3541 default:
3542 break;
3543 }
3544 }
3545
3546 enum hal_status
halrf_config_rfk_with_header_file(void * dm_void,u32 config_type)3547 halrf_config_rfk_with_header_file(void *dm_void, u32 config_type)
3548 {
3549 struct dm_struct *dm = (struct dm_struct *)dm_void;
3550 enum hal_status result = HAL_STATUS_SUCCESS;
3551 #if 0
3552 #if (RTL8822B_SUPPORT == 1)
3553 if (dm->support_ic_type == ODM_RTL8822B) {
3554 if (config_type == CONFIG_BB_RF_CAL_INIT)
3555 odm_read_and_config_mp_8822b_cal_init(dm);
3556 }
3557 #endif
3558 #endif
3559 #if (RTL8197G_SUPPORT == 1)
3560 if (dm->support_ic_type == ODM_RTL8197G) {
3561 if (config_type == CONFIG_BB_RF_CAL_INIT)
3562 odm_read_and_config_mp_8197g_cal_init(dm);
3563 }
3564 #endif
3565 #if (RTL8198F_SUPPORT == 1)
3566 if (dm->support_ic_type == ODM_RTL8198F) {
3567 if (config_type == CONFIG_BB_RF_CAL_INIT)
3568 odm_read_and_config_mp_8198f_cal_init(dm);
3569 }
3570 #endif
3571 #if (RTL8812F_SUPPORT == 1)
3572 if (dm->support_ic_type == ODM_RTL8812F) {
3573 if (config_type == CONFIG_BB_RF_CAL_INIT)
3574 odm_read_and_config_mp_8812f_cal_init(dm);
3575 }
3576 #endif
3577 #if (RTL8822C_SUPPORT == 1)
3578 if (dm->support_ic_type == ODM_RTL8822C) {
3579 if (config_type == CONFIG_BB_RF_CAL_INIT)
3580 odm_read_and_config_mp_8822c_cal_init(dm);
3581 }
3582 #endif
3583 #if (RTL8814B_SUPPORT == 1)
3584 if (dm->support_ic_type == ODM_RTL8814B) {
3585 if (config_type == CONFIG_BB_RF_CAL_INIT)
3586 odm_read_and_config_mp_8814b_cal_init(dm);
3587 }
3588 #endif
3589 #if (RTL8195B_SUPPORT == 1)
3590 if (dm->support_ic_type == ODM_RTL8195B) {
3591 if (config_type == CONFIG_BB_RF_CAL_INIT)
3592 odm_read_and_config_mp_8195b_cal_init(dm);
3593 }
3594 #endif
3595 #if (RTL8721D_SUPPORT == 1)
3596 if (dm->support_ic_type == ODM_RTL8721D) {
3597 if (config_type == CONFIG_BB_RF_CAL_INIT)
3598 odm_read_and_config_mp_8721d_cal_init(dm);
3599 }
3600 #endif
3601 #if (RTL8723F_SUPPORT == 1)
3602 if (dm->support_ic_type == ODM_RTL8723F) {
3603 if (config_type == CONFIG_BB_RF_CAL_INIT)
3604 odm_read_and_config_mp_8723f_cal_init(dm);
3605 }
3606 #endif
3607 #if (RTL8814C_SUPPORT == 1)
3608 if (dm->support_ic_type == ODM_RTL8814C) {
3609 if (config_type == CONFIG_BB_RF_CAL_INIT)
3610 odm_read_and_config_mp_8814c_cal_init(dm);
3611 }
3612 #endif
3613
3614
3615 #if 1
3616 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
3617 result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, (enum rf_path)0, 0);
3618 RF_DBG(dm, DBG_RF_IQK,"phy param offload end!result = %d", result);
3619 }
3620 #endif
3621 return result;
3622 }
3623
halrf_txgapk_trigger(void * dm_void)3624 void halrf_txgapk_trigger(void *dm_void)
3625 {
3626 struct dm_struct *dm = (struct dm_struct *)dm_void;
3627 struct _hal_rf_ *rf = &dm->rf_table;
3628 u64 start_time = 0x0;
3629
3630 if (!(rf->rf_supportability & HAL_RF_TXGAPK))
3631 return;
3632
3633 rf->rfk_type = RF04_TXGAPK;
3634 halrf_rfk_handshake(dm, true);
3635
3636 start_time = odm_get_current_time(dm);
3637 rf->is_txgapk_in_progress = true;
3638 halrf_rfk_power_save(dm, false);
3639
3640 switch (dm->support_ic_type) {
3641
3642 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
3643 #if (RTL8195B_SUPPORT == 1)
3644 case ODM_RTL8195B:
3645 /*phy_txgap_calibrate_8195b(dm, false);*/
3646 break;
3647 #endif
3648 #if (RTL8721D_SUPPORT == 1)
3649 case ODM_RTL8721D:
3650 /*phy_txgap_calibrate_8721d(dm, false);*/
3651 break;
3652 #endif
3653
3654 #endif
3655
3656 #if (RTL8814B_SUPPORT == 1)
3657 case ODM_RTL8814B:
3658 /*phy_txgap_calibrate_8814b(dm, false);*/
3659 break;
3660 #endif
3661
3662 #if (RTL8814C_SUPPORT == 1)
3663 case ODM_RTL8814C:
3664 halrf_txgapk_8814c(dm);
3665 break;
3666 #endif
3667
3668
3669 #if (RTL8822C_SUPPORT == 1)
3670 case ODM_RTL8822C:
3671 halrf_txgapk_8822c(dm);
3672 break;
3673 #endif
3674
3675 #if (RTL8723F_SUPPORT == 1)
3676 case ODM_RTL8723F:
3677 halrf_txgapk_8723f(dm);
3678 break;
3679 #endif
3680
3681 default:
3682 break;
3683 }
3684 halrf_rfk_power_save(dm, true);
3685 rf->is_txgapk_in_progress = false;
3686
3687 halrf_rfk_handshake(dm, false);
3688
3689 rf->dpk_progressing_time =
3690 odm_get_progressing_time(dm_void, start_time);
3691 RF_DBG(dm, DBG_RF_TXGAPK, "[TGGC]TXGAPK progressing_time = %lld ms\n",
3692 rf->dpk_progressing_time);
3693 }
3694
halrf_spur_compensation(void * dm_void)3695 void halrf_spur_compensation(void *dm_void)
3696 {
3697 struct dm_struct *dm = (struct dm_struct *)dm_void;
3698
3699 switch (dm->support_ic_type) {
3700 #if (RTL8723F_SUPPORT == 1)
3701 case ODM_RTL8723F:
3702 halrf_rfk_power_save(dm, false);
3703 halrf_spur_compensation_8723f(dm);
3704 halrf_rfk_power_save(dm, true);
3705 break;
3706 #endif
3707 default:
3708 break;
3709 }
3710 }
3711
halrf_tssi_get_efuse(void * dm_void)3712 void halrf_tssi_get_efuse(void *dm_void)
3713 {
3714 struct dm_struct *dm = (struct dm_struct *)dm_void;
3715
3716 #if (RTL8822C_SUPPORT == 1)
3717 if (dm->support_ic_type & ODM_RTL8822C) {
3718 halrf_tssi_get_efuse_8822c(dm);
3719 halrf_get_efuse_thermal_pwrtype_8822c(dm);
3720 }
3721 #endif
3722
3723 #if (RTL8812F_SUPPORT == 1)
3724 if (dm->support_ic_type & ODM_RTL8812F) {
3725 halrf_tssi_get_efuse_8812f(dm);
3726 }
3727 #endif
3728
3729 #if (RTL8814B_SUPPORT == 1)
3730 if (dm->support_ic_type & ODM_RTL8814B) {
3731 halrf_tssi_get_efuse_8814b(dm);
3732 halrf_get_efuse_thermal_pwrtype_8814b(dm);
3733 }
3734 #endif
3735
3736 #if (RTL8197G_SUPPORT == 1)
3737 if (dm->support_ic_type & ODM_RTL8197G) {
3738 halrf_tssi_get_efuse_8197g(dm);
3739 }
3740 #endif
3741
3742 #if (RTL8723F_SUPPORT == 1)
3743 if (dm->support_ic_type & ODM_RTL8723F) {
3744 halrf_tssi_get_efuse_8723f(dm);
3745 }
3746 #endif
3747
3748 #if (RTL8814C_SUPPORT == 1)
3749 if (dm->support_ic_type & ODM_RTL8814C) {
3750 halrf_tssi_get_efuse_8814c(dm);
3751 halrf_get_efuse_thermal_pwrtype_8814c(dm);
3752 }
3753 #endif
3754
3755 }
3756
halrf_do_rxbb_dck(void * dm_void)3757 void halrf_do_rxbb_dck(void *dm_void)
3758 {
3759 struct dm_struct *dm = (struct dm_struct *)dm_void;
3760
3761
3762 #if (RTL8814B_SUPPORT == 1)
3763 if (dm->support_ic_type == ODM_RTL8814B)
3764 halrf_do_rxbb_dck_8814b(dm);
3765 #endif
3766 #if (RTL8814C_SUPPORT == 1)
3767 if (dm->support_ic_type == ODM_RTL8814C)
3768 halrf_do_rxbb_dck_8814c(dm);
3769 #endif
3770
3771
3772 }
3773
halrf_do_tssi(void * dm_void)3774 void halrf_do_tssi(void *dm_void)
3775 {
3776 struct dm_struct *dm = (struct dm_struct *)dm_void;
3777
3778 #if (RTL8822C_SUPPORT == 1)
3779 if (dm->support_ic_type == ODM_RTL8822C)
3780 halrf_do_tssi_8822c(dm);
3781 #endif
3782
3783 #if (RTL8812F_SUPPORT == 1)
3784 if (dm->support_ic_type == ODM_RTL8812F)
3785 halrf_do_tssi_8812f(dm);
3786 #endif
3787
3788 #if (RTL8197G_SUPPORT == 1)
3789 if (dm->support_ic_type == ODM_RTL8197G)
3790 halrf_do_tssi_8197g(dm);
3791 #endif
3792
3793 #if (RTL8723F_SUPPORT == 1)
3794 if (dm->support_ic_type == ODM_RTL8723F) {
3795 halrf_rfk_power_save(dm, false);
3796 halrf_do_tssi_8723f(dm);
3797 halrf_rfk_power_save(dm, true);
3798 }
3799 #endif
3800
3801 #if (RTL8814C_SUPPORT == 1)
3802 if (dm->support_ic_type == ODM_RTL8814C)
3803 halrf_tssi_trigger_bit_reset_8814c(dm);
3804 #endif
3805
3806 }
3807
halrf_do_tssi_by_manual(void * dm_void,u8 path)3808 u8 halrf_do_tssi_by_manual(void *dm_void, u8 path)
3809 {
3810 struct dm_struct *dm = (struct dm_struct *)dm_void;
3811
3812 #if (RTL8814B_SUPPORT == 1)
3813 if (dm->support_ic_type & ODM_RTL8814B)
3814 return halrf_do_tssi_8814b(dm, path);
3815 #endif
3816
3817 #if (RTL8814C_SUPPORT == 1)
3818 if (dm->support_ic_type & ODM_RTL8814C)
3819 return halrf_do_tssi_8814c(dm, path);
3820 #endif
3821
3822 return 0;
3823 }
3824
halrf_set_tssi_enable(void * dm_void,boolean enable)3825 void halrf_set_tssi_enable(void *dm_void, boolean enable)
3826 {
3827 struct dm_struct *dm = (struct dm_struct *)dm_void;
3828 struct _hal_rf_ *rf = &(dm->rf_table);
3829
3830 if (enable == 1) {
3831 rf->power_track_type = 4;
3832 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
3833 } else {
3834 rf->power_track_type = 0;
3835 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
3836 }
3837 }
3838
3839
halrf_do_thermal(void * dm_void)3840 void halrf_do_thermal(void *dm_void)
3841 {
3842 struct dm_struct *dm = (struct dm_struct *)dm_void;
3843
3844 #if (RTL8822C_SUPPORT == 1)
3845 if (dm->support_ic_type & ODM_RTL8822C)
3846 halrf_do_thermal_8822c(dm);
3847 #endif
3848 }
3849
3850
3851
halrf_set_tssi_value(void * dm_void,u32 tssi_value)3852 u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value)
3853 {
3854 struct dm_struct *dm = (struct dm_struct *)dm_void;
3855
3856 #if (RTL8822C_SUPPORT == 1)
3857 if (dm->support_ic_type & ODM_RTL8822C)
3858 return halrf_set_tssi_value_8822c(dm, tssi_value);
3859 #endif
3860
3861 #if (RTL8814B_SUPPORT == 1)
3862 if (dm->support_ic_type & ODM_RTL8814B)
3863 return halrf_set_tssi_value_8814b(dm, tssi_value);
3864 #endif
3865 #if (RTL8723F_SUPPORT == 1)
3866 if (dm->support_ic_type & ODM_RTL8723F)
3867 return halrf_tssi_set_de_8723f(dm, tssi_value);
3868 #endif
3869 #if (RTL8814C_SUPPORT == 1)
3870 if (dm->support_ic_type & ODM_RTL8814C)
3871 return halrf_set_tssi_value_8814c(dm, tssi_value);
3872 #endif
3873
3874 return 0;
3875 }
3876
halrf_set_tssi_power(void * dm_void,s8 power)3877 void halrf_set_tssi_power(void *dm_void, s8 power)
3878 {
3879 struct dm_struct *dm = (struct dm_struct *)dm_void;
3880
3881 #if (RTL8822C_SUPPORT == 1)
3882 /*halrf_set_tssi_poewr_8822c(dm, power);*/
3883 #endif
3884 }
3885
halrf_tssi_set_de_for_tx_verify(void * dm_void,u32 tssi_de,u8 path)3886 void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path)
3887 {
3888 struct dm_struct *dm = (struct dm_struct *)dm_void;
3889
3890 #if (RTL8822C_SUPPORT == 1)
3891 if (dm->support_ic_type & ODM_RTL8822C)
3892 halrf_tssi_set_de_for_tx_verify_8822c(dm, tssi_de, path);
3893 #endif
3894
3895 #if (RTL8814B_SUPPORT == 1)
3896 if (dm->support_ic_type & ODM_RTL8814B)
3897 halrf_tssi_set_de_for_tx_verify_8814b(dm, tssi_de, path);
3898 #endif
3899
3900 #if (RTL8812F_SUPPORT == 1)
3901 if (dm->support_ic_type & ODM_RTL8812F)
3902 halrf_tssi_set_de_for_tx_verify_8812f(dm, tssi_de, path);
3903 #endif
3904
3905 #if (RTL8197G_SUPPORT == 1)
3906 if (dm->support_ic_type & ODM_RTL8197G)
3907 halrf_tssi_set_de_for_tx_verify_8197g(dm, tssi_de, path);
3908 #endif
3909
3910 #if (RTL8723F_SUPPORT == 1)
3911 if (dm->support_ic_type & ODM_RTL8723F)
3912 halrf_tssi_set_de_for_tx_verify_8723f(dm, tssi_de, path);
3913 #endif
3914 #if (RTL8814C_SUPPORT == 1)
3915 if (dm->support_ic_type & ODM_RTL8814C)
3916 halrf_tssi_set_de_for_tx_verify_8814c(dm, tssi_de, path);
3917 #endif
3918
3919 }
3920
halrf_tssi_turn_target_power(void * dm_void,s16 power_offset,u8 path)3921 u32 halrf_tssi_turn_target_power(void *dm_void, s16 power_offset, u8 path)
3922 {
3923 struct dm_struct *dm = (struct dm_struct *)dm_void;
3924 u32 pout = 0;
3925
3926 if (dm->mp_mode) {
3927 if (*dm->mp_mode) {
3928 #if (RTL8723F_SUPPORT == 1)
3929 if (dm->support_ic_type & ODM_RTL8723F)
3930 pout = halrf_tssi_set_powerbyrate_pout_8723f(dm, power_offset, path);
3931 #endif
3932 }
3933 }
3934 return pout;
3935 }
3936
halrf_tssi_set_power_offset(void * dm_void,s16 power_offset,u8 path)3937 void halrf_tssi_set_power_offset(void *dm_void, s16 power_offset, u8 path)
3938 {
3939 struct dm_struct *dm = (struct dm_struct *)dm_void;
3940
3941 #if (RTL8723F_SUPPORT == 1)
3942 if (dm->support_ic_type & ODM_RTL8723F)
3943 _halrf_tssi_set_powerlevel_8723f(dm, power_offset, path);
3944 #endif
3945
3946 }
3947
halrf_query_tssi_value(void * dm_void)3948 u32 halrf_query_tssi_value(void *dm_void)
3949 {
3950 struct dm_struct *dm = (struct dm_struct *)dm_void;
3951
3952 #if (RTL8822C_SUPPORT == 1)
3953 if (dm->support_ic_type & ODM_RTL8822C)
3954 return halrf_query_tssi_value_8822c(dm);
3955 #endif
3956
3957 #if (RTL8814B_SUPPORT == 1)
3958 if (dm->support_ic_type & ODM_RTL8814B)
3959 return halrf_query_tssi_value_8814b(dm);
3960 #endif
3961 #if (RTL8814C_SUPPORT == 1)
3962 if (dm->support_ic_type & ODM_RTL8814C)
3963 return halrf_query_tssi_value_8814c(dm);
3964 #endif
3965
3966 return 0;
3967 }
3968
halrf_tssi_cck(void * dm_void)3969 void halrf_tssi_cck(void *dm_void)
3970 {
3971 struct dm_struct *dm = (struct dm_struct *)dm_void;
3972
3973 #if (RTL8822C_SUPPORT == 1)
3974 /*halrf_tssi_cck_8822c(dm);*/
3975 if (dm->support_ic_type & ODM_RTL8822C)
3976 halrf_thermal_cck_8822c(dm);
3977 #endif
3978
3979 }
3980
halrf_thermal_cck(void * dm_void)3981 void halrf_thermal_cck(void *dm_void)
3982 {
3983 struct dm_struct *dm = (struct dm_struct *)dm_void;
3984
3985 #if (RTL8822C_SUPPORT == 1)
3986 if (dm->support_ic_type & ODM_RTL8822C)
3987 halrf_thermal_cck_8822c(dm);
3988 #endif
3989
3990 }
3991
halrf_tssi_set_de(void * dm_void)3992 void halrf_tssi_set_de(void *dm_void)
3993 {
3994 struct dm_struct *dm = (struct dm_struct *)dm_void;
3995
3996 #if (RTL8814B_SUPPORT == 1)
3997 if (dm->support_ic_type & ODM_RTL8814B)
3998 halrf_tssi_set_de_8814b(dm);
3999 #endif
4000 #if (RTL8814C_SUPPORT == 1)
4001 if (dm->support_ic_type & ODM_RTL8814C)
4002 halrf_tssi_set_de_8814c(dm);
4003 #endif
4004
4005 }
4006
halrf_tssi_dck(void * dm_void,u8 direct_do)4007 void halrf_tssi_dck(void *dm_void, u8 direct_do)
4008 {
4009 struct dm_struct *dm = (struct dm_struct *)dm_void;
4010
4011 halrf_rfk_handshake(dm, true);
4012
4013 #if (RTL8814B_SUPPORT == 1)
4014 if (dm->support_ic_type & ODM_RTL8814B) {
4015 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4016 if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
4017 return;
4018 #else
4019 if (dm->rfe_type == 1 || dm->rfe_type == 6)
4020 return;
4021 #endif
4022 halrf_tssi_dck_8814b(dm, direct_do);
4023 }
4024 #endif
4025
4026 #if (RTL8822C_SUPPORT == 1)
4027 if (dm->support_ic_type & ODM_RTL8822C)
4028 halrf_tssi_dck_8822c(dm);
4029 #endif
4030
4031 #if (RTL8812F_SUPPORT == 1)
4032 if (dm->support_ic_type & ODM_RTL8812F)
4033 halrf_tssi_dck_8812f(dm);
4034 #endif
4035
4036 #if (RTL8197G_SUPPORT == 1)
4037 if (dm->support_ic_type == ODM_RTL8197G)
4038 halrf_tssi_dck_8197g(dm);
4039 #endif
4040 #if (RTL8814C_SUPPORT == 1)
4041 if (dm->support_ic_type & ODM_RTL8814C) {
4042 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4043 if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
4044 return;
4045 #else
4046 if (dm->rfe_type == 1 || dm->rfe_type == 6)
4047 return;
4048 #endif
4049 halrf_tssi_dck_8814c(dm, direct_do);
4050 }
4051 #endif
4052
4053
4054 halrf_rfk_handshake(dm, false);
4055
4056 }
4057
halrf_calculate_tssi_codeword(void * dm_void)4058 void halrf_calculate_tssi_codeword(void *dm_void)
4059 {
4060 struct dm_struct *dm = (struct dm_struct *)dm_void;
4061
4062 #if (RTL8814B_SUPPORT == 1)
4063 if (dm->support_ic_type & ODM_RTL8814B)
4064 halrf_calculate_tssi_codeword_8814b(dm, RF_PATH_A);
4065 #endif
4066
4067 #if (RTL8822C_SUPPORT == 1)
4068 if (dm->support_ic_type & ODM_RTL8822C)
4069 halrf_calculate_tssi_codeword_8822c(dm);
4070 #endif
4071 #if (RTL8814C_SUPPORT == 1)
4072 if (dm->support_ic_type & ODM_RTL8814C)
4073 halrf_calculate_tssi_codeword_8814c(dm, RF_PATH_A);
4074 #endif
4075
4076 }
4077
halrf_set_tssi_codeword(void * dm_void)4078 void halrf_set_tssi_codeword(void *dm_void)
4079 {
4080 struct dm_struct *dm = (struct dm_struct *)dm_void;
4081 struct _hal_rf_ *rf = &dm->rf_table;
4082 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
4083 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
4084 #endif
4085
4086 #if (RTL8814B_SUPPORT == 1)
4087 if (dm->support_ic_type & ODM_RTL8814B)
4088 halrf_set_tssi_codeword_8814b(dm, tssi->tssi_codeword);
4089 #endif
4090
4091 #if (RTL8822C_SUPPORT == 1)
4092 if (dm->support_ic_type & ODM_RTL8822C)
4093 halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);
4094 #endif
4095
4096 #if (RTL8814C_SUPPORT == 1)
4097 if (dm->support_ic_type & ODM_RTL8814C)
4098 halrf_set_tssi_codeword_8814c(dm, tssi->tssi_codeword);
4099 #endif
4100
4101 }
4102
halrf_get_tssi_codeword_for_txindex(void * dm_void)4103 u8 halrf_get_tssi_codeword_for_txindex(void *dm_void)
4104 {
4105 struct dm_struct *dm = (struct dm_struct *)dm_void;
4106
4107 #if (RTL8814B_SUPPORT == 1)
4108 if (dm->support_ic_type & ODM_RTL8814B) {
4109 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4110 return 80;
4111 #else
4112 return 60;
4113 #endif
4114 }
4115 #endif
4116
4117 #if (RTL8822C_SUPPORT == 1)
4118 if (dm->support_ic_type & ODM_RTL8822C)
4119 return 64;
4120 #endif
4121
4122 #if (RTL8812F_SUPPORT == 1)
4123 if (dm->support_ic_type & ODM_RTL8812F)
4124 return 100;
4125 #endif
4126
4127 #if (RTL8197G_SUPPORT == 1)
4128 if (dm->support_ic_type & ODM_RTL8197G)
4129 return 100;
4130 #endif
4131 #if (RTL8814C_SUPPORT == 1)
4132 if (dm->support_ic_type & ODM_RTL8814C) {
4133 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4134 return 80;
4135 #else
4136 return 60;
4137 #endif
4138 }
4139 #endif
4140 return 60;
4141 }
4142
halrf_tssi_clean_de(void * dm_void)4143 void halrf_tssi_clean_de(
4144 void *dm_void)
4145 {
4146 struct dm_struct *dm = (struct dm_struct *)dm_void;
4147
4148 #if (RTL8812F_SUPPORT == 1)
4149 if (dm->support_ic_type & ODM_RTL8812F)
4150 halrf_tssi_clean_de_8812f(dm);
4151 #endif
4152
4153 #if (RTL8814B_SUPPORT == 1)
4154 if (dm->support_ic_type & ODM_RTL8814B)
4155 halrf_tssi_clean_de_8814b(dm);
4156 #endif
4157
4158 #if (RTL8197G_SUPPORT == 1)
4159 if (dm->support_ic_type & ODM_RTL8197G)
4160 halrf_tssi_clean_de_8197g(dm);
4161 #endif
4162 #if (RTL8814C_SUPPORT == 1)
4163 if (dm->support_ic_type & ODM_RTL8814C)
4164 halrf_tssi_clean_de_8814c(dm);
4165 #endif
4166 }
4167
halrf_tssi_trigger_de(void * dm_void,u8 path)4168 u32 halrf_tssi_trigger_de(void *dm_void, u8 path)
4169 {
4170 struct dm_struct *dm = (struct dm_struct *)dm_void;
4171
4172 #if (RTL8812F_SUPPORT == 1)
4173 if (dm->support_ic_type & ODM_RTL8812F)
4174 return halrf_tssi_trigger_de_8812f(dm, path);
4175 #endif
4176
4177 #if (RTL8814B_SUPPORT == 1)
4178 if (dm->support_ic_type & ODM_RTL8814B)
4179 return halrf_tssi_trigger_de_8814b(dm, path);
4180 #endif
4181
4182 #if (RTL8197G_SUPPORT == 1)
4183 if (dm->support_ic_type & ODM_RTL8197G)
4184 return halrf_tssi_trigger_de_8197g(dm, path);
4185 #endif
4186
4187 #if (RTL8814C_SUPPORT == 1)
4188 if (dm->support_ic_type & ODM_RTL8814C)
4189 return halrf_tssi_trigger_de_8814c(dm, path);
4190 #endif
4191 return 0;
4192 }
4193
halrf_tssi_get_de(void * dm_void,u8 path)4194 u32 halrf_tssi_get_de(void *dm_void, u8 path)
4195 {
4196 struct dm_struct *dm = (struct dm_struct *)dm_void;
4197
4198 #if (RTL8822C_SUPPORT == 1)
4199 if (dm->support_ic_type & ODM_RTL8822C)
4200 return halrf_tssi_get_de_8822c(dm, path);
4201 #endif
4202
4203 #if (RTL8812F_SUPPORT == 1)
4204 if (dm->support_ic_type & ODM_RTL8812F)
4205 return halrf_tssi_get_de_8812f(dm, path);
4206 #endif
4207
4208 #if (RTL8814B_SUPPORT == 1)
4209 if (dm->support_ic_type & ODM_RTL8814B)
4210 return halrf_tssi_get_de_8814b(dm, path);
4211 #endif
4212
4213 #if (RTL8197G_SUPPORT == 1)
4214 if (dm->support_ic_type & ODM_RTL8197G)
4215 return halrf_tssi_get_de_8197g(dm, path);
4216 #endif
4217 #if (RTL8814C_SUPPORT == 1)
4218 if (dm->support_ic_type & ODM_RTL8814C)
4219 return halrf_tssi_get_de_8814c(dm, path);
4220 #endif
4221 return 0;
4222 }
4223
halrf_get_online_tssi_de(void * dm_void,u8 path,s32 pout)4224 u32 halrf_get_online_tssi_de(void *dm_void, u8 path, s32 pout)
4225 {
4226 struct dm_struct *dm = (struct dm_struct *)dm_void;
4227
4228 #if (RTL8723F_SUPPORT == 1)
4229 if (dm->support_ic_type & ODM_RTL8723F)
4230 return halrf_get_online_tssi_de_8723f(dm, path, pout);
4231 #endif
4232 return 0;
4233 }
4234
halrf_tssi_trigger(void * dm_void)4235 void halrf_tssi_trigger(void *dm_void)
4236 {
4237 struct dm_struct *dm = (struct dm_struct *)dm_void;
4238 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
4239 struct _hal_rf_ *rf = &(dm->rf_table);
4240
4241 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
4242 if (*dm->mp_mode == 1) {
4243 if (cali_info->txpowertrack_control == 0 ||
4244 cali_info->txpowertrack_control == 1) {
4245 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4246 "[TSSI]======>%s MP Mode UI chose thermal tracking. return !!!\n", __func__);
4247 return;
4248 }
4249 } else {
4250 if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
4251 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4252 "[TSSI]======>%s Normal Mode efues is thermal tracking. return !!!\n", __func__);
4253 return;
4254 }
4255 }
4256 #endif
4257
4258 halrf_calculate_tssi_codeword(dm);
4259 halrf_set_tssi_codeword(dm);
4260 halrf_tssi_dck(dm, false);
4261 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4262 halrf_tssi_get_efuse(dm);
4263 #endif
4264 halrf_tssi_set_de(dm);
4265 halrf_do_tssi(dm);
4266 }
4267
halrf_txgapk_write_gain_table(void * dm_void)4268 void halrf_txgapk_write_gain_table(void *dm_void)
4269 {
4270 struct dm_struct *dm = (struct dm_struct *)dm_void;
4271
4272 #if (RTL8822C_SUPPORT == 1)
4273 if (dm->support_ic_type & ODM_RTL8822C)
4274 halrf_txgapk_save_all_tx_gain_table_8822c(dm);
4275 #endif
4276 #if (RTL8814C_SUPPORT == 1)
4277 if (dm->support_ic_type & ODM_RTL8814C)
4278 halrf_txgapk_save_all_tx_gain_table_8814c(dm);
4279 #endif
4280
4281 }
4282
halrf_txgapk_reload_tx_gain(void * dm_void)4283 void halrf_txgapk_reload_tx_gain(void *dm_void)
4284 {
4285 struct dm_struct *dm = (struct dm_struct *)dm_void;
4286
4287 #if (RTL8822C_SUPPORT == 1)
4288 if (dm->support_ic_type & ODM_RTL8822C)
4289 halrf_txgapk_reload_tx_gain_8822c(dm);
4290 #endif
4291 /*
4292 #if (RTL8814C_SUPPORT == 1)
4293 if (dm->support_ic_type & ODM_RTL8814C)
4294 halrf_txgapk_reload_tx_gain_8814c(dm);
4295 #endif
4296 */
4297 }
4298
halrf_txgap_enable_disable(void * dm_void,u8 enable)4299 void halrf_txgap_enable_disable(void *dm_void, u8 enable)
4300 {
4301 struct dm_struct *dm = (struct dm_struct *)dm_void;
4302 struct _hal_rf_ *rf = &(dm->rf_table);
4303
4304 if (enable) {
4305 rf->rf_supportability = rf->rf_supportability | HAL_RF_TXGAPK;
4306 halrf_txgapk_trigger(dm);
4307 } else {
4308 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TXGAPK;
4309 halrf_txgapk_reload_tx_gain(dm);
4310 }
4311 }
4312
4313 #if (RTL8723F_SUPPORT == 1)
_halrf_get_power_offset_by_thermal_8723f(void * dm_void,u8 path,s8 thermal_detla)4314 s8 _halrf_get_power_offset_by_thermal_8723f(void *dm_void, u8 path, s8 thermal_detla)
4315 {
4316 struct dm_struct *dm = (struct dm_struct *)dm_void;
4317 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
4318 u8 channel = *dm->channel;
4319 u8 tx_rate = phydm_get_tx_rate(dm);
4320 s8 power_offset = 0;
4321 u8 i = 0;
4322 u8 thermal_up_a[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_a[DELTA_SWINGIDX_SIZE] = {0};
4323 u8 thermal_up_b[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_b[DELTA_SWINGIDX_SIZE] = {0};
4324 u8 txagc_offset_2g_cck_a_p[] = {
4325 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5,
4326 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4327 u8 txagc_offset_2g_cck_a_n[] = {
4328 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5,
4329 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4330 u8 txagc_offset_2g_cck_b_p[] = {
4331 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5,
4332 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4333 u8 txagc_offset_2g_cck_b_n[] = {
4334 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5,
4335 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4336 u8 txagc_offset_2ga_p[] = {
4337 0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6,
4338 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
4339 u8 txagc_offset_2ga_n[] = {
4340 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,
4341 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4342 u8 txagc_offset_2gb_p[] = {
4343 0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
4344 5, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
4345 u8 txagc_offset_2gb_n[] = {
4346 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,
4347 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4348 u8 txagc_offset_5ga_n[][30] = {
4349 {0, 0, 2, 2, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6,
4350 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8},
4351 {0, 0, 2, 2, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6,
4352 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8},
4353 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6,
4354 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8},
4355 };
4356 u8 txagc_offset_5ga_p[][30] = {
4357 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 8,
4358 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8},
4359 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 8,
4360 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9},
4361 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 6, 6, 6, 6, 7, 7, 8,
4362 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9},
4363 };
4364 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] ======>%s\n", __func__);
4365
4366 if (channel >= 1 && channel <= 14) {
4367 if (IS_CCK_RATE(tx_rate)) {
4368 odm_move_memory(dm, thermal_up_a, txagc_offset_2g_cck_a_p, sizeof(thermal_up_a));
4369 odm_move_memory(dm, thermal_down_a, txagc_offset_2g_cck_a_n, sizeof(thermal_down_a));
4370 odm_move_memory(dm, thermal_up_b, txagc_offset_2g_cck_b_p, sizeof(thermal_up_b));
4371 odm_move_memory(dm, thermal_down_b, txagc_offset_2g_cck_b_n, sizeof(thermal_down_b));
4372 } else {
4373 odm_move_memory(dm, thermal_up_a, txagc_offset_2ga_p, sizeof(thermal_up_a));
4374 odm_move_memory(dm, thermal_down_a, txagc_offset_2ga_n, sizeof(thermal_down_a));
4375 odm_move_memory(dm, thermal_up_b, txagc_offset_2gb_p, sizeof(thermal_up_b));
4376 odm_move_memory(dm, thermal_down_b, txagc_offset_2gb_n, sizeof(thermal_down_b));
4377 }
4378 }
4379
4380 if (channel >= 36 && channel <= 64) {
4381 odm_move_memory(dm, thermal_up_a, txagc_offset_5ga_p[0], sizeof(thermal_up_a));
4382 odm_move_memory(dm, thermal_down_a, txagc_offset_5ga_n[0], sizeof(thermal_down_a));
4383 } else if (channel >= 100 && channel <= 144) {
4384 odm_move_memory(dm, thermal_up_a, txagc_offset_5ga_p[1], sizeof(thermal_up_a));
4385 odm_move_memory(dm, thermal_down_a, txagc_offset_5ga_n[1], sizeof(thermal_down_a));
4386 } else if (channel >= 149 && channel <= 177) {
4387 odm_move_memory(dm, thermal_up_a, txagc_offset_5ga_p[2], sizeof(thermal_up_a));
4388 odm_move_memory(dm, thermal_down_a, txagc_offset_5ga_n[2], sizeof(thermal_down_a));
4389 }
4390
4391 if(thermal_detla < 0) {
4392 if (thermal_detla < -29)
4393 i = 29;
4394 else
4395 i = (u8)(-1 * thermal_detla);
4396
4397 if (path ==0 )
4398 power_offset = thermal_down_a[i];
4399 else
4400 power_offset = thermal_down_b[i];
4401
4402 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] Temp is lower\n");
4403 } else {
4404 if (thermal_detla >= 30)
4405 i = 29;
4406 else
4407 i = thermal_detla;
4408
4409 if (path ==0 )
4410 power_offset = thermal_up_a[i];
4411 else
4412 power_offset = thermal_up_b[i];
4413 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] Temp is higher\n");
4414 }
4415
4416 return power_offset;
4417 }
4418
halrf_powertracking_thermal(void * dm_void)4419 void halrf_powertracking_thermal(void *dm_void)
4420 {
4421 struct dm_struct *dm = (struct dm_struct *)dm_void;
4422 struct _hal_rf_ *rf = &dm->rf_table;
4423 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
4424 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
4425 s8 thermal_value = 0, thermal_detla = 0;
4426 s8 power_offset0 = 0, power_offset1 = 0;
4427 u8 thermal_base = 0, temp[2] = {0};
4428 u8 path;
4429 u8 rate = phydm_get_tx_rate(dm);
4430 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] ======>%s\n", __func__);
4431
4432 if(rf->is_tssi_in_progress == 1)
4433 return;
4434 if (*dm->mp_mode == 1) {
4435 if (cali_info->txpowertrack_control <= 2) {
4436 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] return!! txpowertrack_control = %d\n",
4437 cali_info->txpowertrack_control);
4438 return;
4439 }
4440 } else {
4441 if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
4442 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4443 "[RF][TSSI] ===>is_txpowertracking is false, return!!\n");
4444 return;
4445 }
4446 }
4447
4448 if (odm_get_bb_reg(dm, R_0x4318, BIT30) == 1){
4449 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] return!! txpowertrack_control = %d, 0x4318 = 0x%x\n",
4450 cali_info->txpowertrack_control,odm_get_bb_reg(dm, R_0x4318, MASKDWORD));
4451 return;
4452 }
4453 path = (u8)odm_get_bb_reg(dm, 0x1884, BIT(20));
4454 thermal_base = tssi->thermal_cal;
4455 thermal_value = (s8)odm_get_rf_reg(dm, 0, RF_0x42, 0x7E);/*path0*/
4456 thermal_detla = (s8)(thermal_value - thermal_base);
4457 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][TSSI] thermal_value = 0x%x, thermal_base = 0x%x\n",
4458 thermal_value, thermal_base);
4459 power_offset0 = _halrf_get_power_offset_by_thermal_8723f(dm, 0, thermal_detla);
4460 power_offset1 = _halrf_get_power_offset_by_thermal_8723f(dm, 1, thermal_detla);
4461
4462 if (rate == ODM_MGN_1M || rate == ODM_MGN_2M || rate == ODM_MGN_5_5M || rate == ODM_MGN_11M){
4463 temp[0] = tssi->txagc_offset_thermaltrack[0] -0x18 + 4*(power_offset0);/*s0*/
4464 temp[1] = tssi->txagc_offset_thermaltrack[1] - 0x8 + 4*(power_offset1);/*s1*/
4465 } else {
4466 temp[0] = tssi->txagc_offset_thermaltrack[0] + 4*(power_offset0);
4467 temp[1] = tssi->txagc_offset_thermaltrack[1] + 4*(power_offset1);
4468 }
4469 /*S0:in the same index,cck_pwr-ofdm_pwr=7dB*/
4470 odm_set_bb_reg(dm, R_0x4388, MASKBYTE0, temp[0]);/*s0*/
4471 /*S1:in the same index,cck_pwr-ofdm_pwr=5dB*/
4472 odm_set_bb_reg(dm, R_0x4388, MASKBYTE2, temp[1]);/*s1*/
4473
4474 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][TSSI] current_Path = %d, tx_rate = 0x%x\n", path, rate);
4475 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][TSSI] txagc_offset = 0x%x\n",
4476 tssi->txagc_offset_thermaltrack[path]);
4477 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4478 "[RF][TSSI] thermal_detla = %d, thermal_offset_s0 = 0x%x, thermal_offset_s1 = 0x%x\n",
4479 thermal_detla, power_offset0, power_offset1);
4480 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] 0x4388 = 0x%x\n",
4481 odm_get_bb_reg(dm, R_0x4388, MASKDWORD));
4482
4483
4484 }
halrf_xtal_thermal_track(void * dm_void)4485 void halrf_xtal_thermal_track(void *dm_void)
4486 {
4487 struct dm_struct *dm = (struct dm_struct *)dm_void;
4488 struct _hal_rf_ *rf = &dm->rf_table;
4489 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
4490 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
4491 s8 *delta_swing_table_xtal_up = NULL;
4492 u8 xtal_offset_eanble = 0, i =0;
4493 s8 thermal_value = 0, thermal_detla = 0;
4494 u8 thermal_base = 0;
4495 s8 xtal_table_up[DELTA_SWINGIDX_SIZE] = {0};
4496 s8 xtal_table_down[DELTA_SWINGIDX_SIZE] = {0};
4497 s32 reg_val = 0, crystal_cap = 0;
4498
4499 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4500 "[RF][xtal] ======>%s\n", __func__);
4501
4502 if ( dm->support_ic_type == ODM_RTL8723F) {
4503 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
4504 dm->is_psd_in_process || rf->is_tssi_in_progress ||
4505 !(rf->rf_supportability & HAL_RF_DPK_TRACK) ||
4506 rf->is_txgapk_in_progress)
4507 return;
4508
4509 if(tssi->thermal[0] == 0xff) {
4510 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal 0xFF, return!\n");
4511 return;
4512 } else {
4513 thermal_base = tssi->thermal[0];
4514 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal_base = 0x%x\n", thermal_base);
4515 }
4516
4517 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal_base = 0x%x\n", thermal_base);
4518
4519 thermal_value = (s8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x42, 0x7E); /* 0x42: RF Reg[6:1]*/
4520
4521 thermal_detla = (s8)(thermal_value - thermal_base);
4522
4523 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] cali_info->xtal_offset = 0x%x\n", cali_info->xtal_offset);
4524
4525 cali_info->xtal_offset_last = cali_info->xtal_offset;
4526 /*
4527 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4528 "[RF][Xtal] cali_info->delta_swing_table_xtal_p = %d\n", cali_info->delta_swing_table_xtal_p[2]);
4529 */
4530 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4531 "[RF][Xtal] thermal_value = 0x%x, thermal_detla = 0x%x, xtal_offset_last = 0x%x\n",
4532 thermal_value, thermal_detla, cali_info->xtal_offset_last);
4533 odm_move_memory(dm, xtal_table_up, cali_info->delta_swing_table_xtal_p, sizeof(xtal_table_up));//(void *)
4534 odm_move_memory(dm, xtal_table_down, cali_info->delta_swing_table_xtal_n, sizeof(xtal_table_down));
4535 /*
4536 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4537 "[RF][Xtal] xtal_table_up[1] = %d\n", xtal_table_up[1]);*/
4538 if(thermal_detla < 0) {
4539
4540 if (thermal_detla < -29)
4541 i = 29;
4542 else
4543 i = (u8)(-1 * thermal_detla);
4544 cali_info->xtal_offset = xtal_table_down[i];
4545 } else {
4546
4547 if (thermal_detla >= 30)
4548 i = 29;
4549 else
4550 i = thermal_detla;
4551
4552 cali_info->xtal_offset = xtal_table_up[i];
4553 }
4554
4555 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4556 "[RF][Xtal] xtal_offset = %d\n", cali_info->xtal_offset);
4557 if (cali_info->xtal_offset_last == cali_info->xtal_offset)
4558 xtal_offset_eanble = 0;
4559 else
4560 xtal_offset_eanble = 1;
4561 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4562 "[RF][Xtal] xtal_offset_eanble = %d\n", xtal_offset_eanble);
4563 if (xtal_offset_eanble != 0) {
4564 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
4565 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4566 "[RF][Xtal] R_0x103c[16:10] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x0001FC00));
4567
4568 crystal_cap = dm->dm_cfo_track.crystal_cap_default & 0x7F;
4569 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4570 "[RF][Xtal] DEFAULT crystal_cap = 0x%x\n", crystal_cap);
4571 reg_val = crystal_cap + cali_info->xtal_offset;
4572 if (reg_val > 0x7F)
4573 reg_val = 0x7F;
4574 else if (reg_val < 0)
4575 reg_val = 0x0;
4576
4577 //reg_val = (u32)(odm_get_mac_reg(dm, R_0x103c, 0x0001FC00) + cali_info->xtal_offset);
4578 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4579 "[RF][Xtal] reg_val = 0x%x\n", reg_val);
4580 /* write 0x103c[23:17] = 0x103c[16:10] = crystal_cap */
4581 crystal_cap = reg_val | (reg_val << 7);
4582 odm_set_mac_reg(dm, R_0x103c, 0x00FFFC00, crystal_cap);
4583 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4584 "[RF][Xtal] R_0x103c[16:10] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x0001FC00));
4585 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4586 "[RF][Xtal] R_0x103c[23:17] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x00FE0000));
4587 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
4588 }
4589 //odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, 0x30000, 0x3);
4590 //delay
4591 }
4592 /*RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4593 "[RF][xtal] <======%s\n", __func__);*/
4594 }
4595 #endif
4596
_halrf_dump_subpage(void * dm_void,u32 * _used,char * output,u32 * _out_len,u8 page)4597 void _halrf_dump_subpage(void *dm_void, u32 *_used, char *output, u32 *_out_len, u8 page)
4598 {
4599 struct dm_struct *dm = (struct dm_struct *)dm_void;
4600
4601 u32 used = *_used;
4602 u32 out_len = *_out_len;
4603 u32 addr;
4604
4605 PDM_SNPF(out_len, used, output + used, out_len - used,
4606 "\n===============[ Subpage_%d start]===============\n", page);
4607
4608 RF_DBG(dm, DBG_RF_RFK, " ===============[ Subpage_%d start]===============\n", page);
4609
4610 odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), page);
4611
4612 for (addr = 0x1b00; addr < 0x1c00; addr += 0x10) {
4613 PDM_SNPF(out_len, used, output + used, out_len - used,
4614 " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
4615 odm_get_bb_reg(dm, addr, MASKDWORD),
4616 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
4617 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
4618 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
4619 RF_DBG(dm, DBG_RF_RFK, " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
4620 odm_get_bb_reg(dm, addr, MASKDWORD),
4621 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
4622 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
4623 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
4624 }
4625
4626 *_used = used;
4627 *_out_len = out_len;
4628 }
4629
halrf_dump_rfk_reg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)4630 void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
4631 char *output, u32 *_out_len)
4632 {
4633 struct dm_struct *dm = (struct dm_struct *)dm_void;
4634 struct _hal_rf_ *rf = &dm->rf_table;
4635
4636 char help[] = "-h";
4637 u32 var1[10] = {0};
4638 u32 used = *_used;
4639 u32 out_len = *_out_len;
4640 u32 reg_1b00, supportability;
4641 u8 page;
4642
4643 if (!(dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES))) {
4644 PDM_SNPF(out_len, used, output + used, out_len - used,
4645 "CMD is Unsupported due to IC type!!!\n");
4646 RF_DBG(dm, DBG_RF_RFK, "[RFK] CMD is Unsupported due to IC type!!!\n");
4647 return;
4648 } else if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
4649 dm->is_psd_in_process || rf->is_tssi_in_progress || rf->is_txgapk_in_progress) {
4650 PDM_SNPF(out_len, used, output + used, out_len - used,
4651 "Bypass CMD due to RFK is doing!!!\n");
4652 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to RFK is doing!!!\n");
4653 return;
4654 }
4655
4656 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4657 if (*dm->is_fcs_mode_enable) {
4658 PDM_SNPF(out_len, used, output + used, out_len - used,
4659 "Bypass CMD due to FCS mode!!!\n");
4660 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to FCS mode!!!\n");
4661 return;
4662 }
4663 #endif
4664 supportability = rf->rf_supportability;
4665
4666 /*to avoid DPK track interruption*/
4667 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
4668
4669 reg_1b00 = odm_get_bb_reg(dm, R_0x1b00, MASKDWORD);
4670
4671 if (input[2])
4672 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[0]);
4673
4674 if ((strcmp(input[2], help) == 0))
4675 PDM_SNPF(out_len, used, output + used, out_len - used,
4676 "dump subpage {0:Page0, 1:Page1, 2:Page2, 3:Page3, 4:all}\n");
4677 else if (var1[0] > 4)
4678 PDM_SNPF(out_len, used, output + used, out_len - used,
4679 "Wrong subpage number!!\n");
4680 else if (var1[0] == 4) {
4681 for (page = 0; page < 4; page++)
4682 _halrf_dump_subpage(dm, &used, output, &out_len, page);
4683 } else
4684 _halrf_dump_subpage(dm, &used, output, &out_len, (u8)var1[0]);
4685
4686 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, reg_1b00);
4687
4688 rf->rf_supportability = supportability;
4689
4690 *_used = used;
4691 *_out_len = out_len;
4692 }
4693
4694 /*Golbal function*/
halrf_reload_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)4695 void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
4696 {
4697 struct dm_struct *dm = (struct dm_struct *)dm_void;
4698 u32 i;
4699
4700 for (i = 0; i < num; i++)
4701 odm_write_4byte(dm, bp_reg[i], bp[i]);
4702 }
4703
halrf_reload_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)4704 void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
4705 u8 ss)
4706 {
4707 struct dm_struct *dm = (struct dm_struct *)dm_void;
4708 u32 i, path;
4709
4710 for (i = 0; i < num; i++) {
4711 for (path = 0; path < ss; path++)
4712 odm_set_rf_reg(dm, (enum rf_path)path, bp_reg[i],
4713 MASK20BITS, bp[i][path]);
4714 }
4715 }
4716
halrf_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)4717 void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
4718 {
4719 struct dm_struct *dm = (struct dm_struct *)dm_void;
4720 u32 i;
4721
4722 for (i = 0; i < num; i++)
4723 bp[i] = odm_read_4byte(dm, bp_reg[i]);
4724 }
4725
halrf_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)4726 void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss)
4727 {
4728 struct dm_struct *dm = (struct dm_struct *)dm_void;
4729 u32 i, path;
4730
4731 for (i = 0; i < num; i++) {
4732 for (path = 0; path < ss; path++) {
4733 bp[i][path] =
4734 odm_get_rf_reg(dm, (enum rf_path)path,
4735 bp_reg[i], MASK20BITS);
4736 }
4737 }
4738 }
4739
halrf_swap(void * dm_void,u32 * v1,u32 * v2)4740 void halrf_swap(void *dm_void, u32 *v1, u32 *v2)
4741 {
4742 struct dm_struct *dm = (struct dm_struct *)dm_void;
4743 u32 temp;
4744
4745 temp = *v1;
4746 *v1 = *v2;
4747 *v2 = temp;
4748 }
4749
halrf_bubble(void * dm_void,u32 * v1,u32 * v2)4750 void halrf_bubble(void *dm_void, u32 *v1, u32 *v2)
4751 {
4752 struct dm_struct *dm = (struct dm_struct *)dm_void;
4753 u32 temp;
4754
4755 if (*v1 >= 0x200 && *v2 >= 0x200) {
4756 if (*v1 > *v2)
4757 halrf_swap(dm, v1, v2);
4758 } else if (*v1 < 0x200 && *v2 < 0x200) {
4759 if (*v1 > *v2)
4760 halrf_swap(dm, v1, v2);
4761 } else if (*v1 < 0x200 && *v2 >= 0x200) {
4762 halrf_swap(dm, v1, v2);
4763 }
4764 }
4765
halrf_b_sort(void * dm_void,u32 * iv,u32 * qv)4766 void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv)
4767 {
4768 struct dm_struct *dm = (struct dm_struct *)dm_void;
4769 u32 temp;
4770 u32 i, j;
4771
4772 RF_DBG(dm, DBG_RF_DACK, "[DACK]bubble!!!!!!!!!!!!");
4773 for (i = 0; i < SN - 1; i++) {
4774 for (j = 0; j < (SN - 1 - i) ; j++) {
4775 halrf_bubble(dm, &iv[j], &iv[j + 1]);
4776 halrf_bubble(dm, &qv[j], &qv[j + 1]);
4777 }
4778 }
4779 }
4780
halrf_minmax_compare(void * dm_void,u32 value,u32 * min,u32 * max)4781 void halrf_minmax_compare(void *dm_void, u32 value, u32 *min,
4782 u32 *max)
4783 {
4784 struct dm_struct *dm = (struct dm_struct *)dm_void;
4785
4786 if (value >= 0x200) {
4787 if (*min >= 0x200) {
4788 if (*min > value)
4789 *min = value;
4790 } else {
4791 *min = value;
4792 }
4793 if (*max >= 0x200) {
4794 if (*max < value)
4795 *max = value;
4796 }
4797 } else {
4798 if (*min < 0x200) {
4799 if (*min > value)
4800 *min = value;
4801 }
4802
4803 if (*max >= 0x200) {
4804 *max = value;
4805 } else {
4806 if (*max < value)
4807 *max = value;
4808 }
4809 }
4810 }
4811
halrf_delta(void * dm_void,u32 v1,u32 v2)4812 u32 halrf_delta(void *dm_void, u32 v1, u32 v2)
4813 {
4814 struct dm_struct *dm = (struct dm_struct *)dm_void;
4815
4816 if (v1 >= 0x200 && v2 >= 0x200) {
4817 if (v1 > v2)
4818 return v1 - v2;
4819 else
4820 return v2 - v1;
4821 } else if (v1 >= 0x200 && v2 < 0x200) {
4822 return v2 + (0x400 - v1);
4823 } else if (v1 < 0x200 && v2 >= 0x200) {
4824 return v1 + (0x400 - v2);
4825 }
4826
4827 if (v1 > v2)
4828 return v1 - v2;
4829 else
4830 return v2 - v1;
4831 }
4832
halrf_compare(void * dm_void,u32 value)4833 boolean halrf_compare(void *dm_void, u32 value)
4834 {
4835 struct dm_struct *dm = (struct dm_struct *)dm_void;
4836
4837 boolean fail = false;
4838
4839 if (value >= 0x200 && (0x400 - value) > 0x64)
4840 fail = true;
4841 else if (value < 0x200 && value > 0x64)
4842 fail = true;
4843
4844 if (fail)
4845 RF_DBG(dm, DBG_RF_DACK, "[DACK]overflow!!!!!!!!!!!!!!!");
4846 return fail;
4847 }
4848
halrf_mode(void * dm_void,u32 * i_value,u32 * q_value)4849 void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value)
4850 {
4851 struct dm_struct *dm = (struct dm_struct *)dm_void;
4852 u32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;
4853 u32 p, m, t;
4854 u32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;
4855 u32 i_delta, q_delta;
4856 u8 i, j, ii = 0, qi = 0;
4857 boolean fail = false;
4858
4859 ODM_delay_ms(10);
4860 for (i = 0; i < SN; i++) {
4861 im[i] = 0;
4862 qm[i] = 0;
4863 }
4864 i = 0;
4865 c = 0;
4866 while (i < SN && c < 1000) {
4867 c++;
4868 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4869 iv[i] = (temp & 0x3ff000) >> 12;
4870 qv[i] = temp & 0x3ff;
4871
4872 fail = false;
4873 if (halrf_compare(dm, iv[i]))
4874 fail = true;
4875 if (halrf_compare(dm, qv[i]))
4876 fail = true;
4877 if (!fail)
4878 i++;
4879 }
4880 c = 0;
4881 do {
4882 c++;
4883 i_min = iv[0];
4884 i_max = iv[0];
4885 q_min = qv[0];
4886 q_max = qv[0];
4887 for (i = 0; i < SN; i++) {
4888 halrf_minmax_compare(dm, iv[i], &i_min, &i_max);
4889 halrf_minmax_compare(dm, qv[i], &q_min, &q_max);
4890 }
4891 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_min=0x%x, i_max=0x%x",
4892 i_min, i_max);
4893 RF_DBG(dm, DBG_RF_DACK, "[DACK]q_min=0x%x, q_max=0x%x",
4894 q_min, q_max);
4895 if (i_max < 0x200 && i_min < 0x200)
4896 i_delta = i_max - i_min;
4897 else if (i_max >= 0x200 && i_min >= 0x200)
4898 i_delta = i_max - i_min;
4899 else
4900 i_delta = i_max + (0x400 - i_min);
4901
4902 if (q_max < 0x200 && q_min < 0x200)
4903 q_delta = q_max - q_min;
4904 else if (q_max >= 0x200 && q_min >= 0x200)
4905 q_delta = q_max - q_min;
4906 else
4907 q_delta = q_max + (0x400 - q_min);
4908 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_delta=0x%x, q_delta=0x%x",
4909 i_delta, q_delta);
4910 halrf_b_sort(dm, iv, qv);
4911 if (i_delta > 5 || q_delta > 5) {
4912 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4913 iv[0] = (temp & 0x3ff000) >> 12;
4914 qv[0] = temp & 0x3ff;
4915 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4916 iv[SN - 1] = (temp & 0x3ff000) >> 12;
4917 qv[SN - 1] = temp & 0x3ff;
4918 } else {
4919 break;
4920 }
4921 } while (c < 100);
4922 #if 1
4923 #if 0
4924 for (i = 0; i < SN; i++)
4925 RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
4926 for (i = 0; i < SN; i++)
4927 RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
4928 #endif
4929 /*i*/
4930 m = 0;
4931 p = 0;
4932 for (i = 10; i < SN - 10; i++) {
4933 if (iv[i] > 0x200)
4934 m = (0x400 - iv[i]) + m;
4935 else
4936 p = iv[i] + p;
4937 }
4938
4939 if (p > m) {
4940 t = p - m;
4941 t = t / (SN - 20);
4942 } else {
4943 t = m - p;
4944 t = t / (SN - 20);
4945 if (t != 0x0)
4946 t = 0x400 - t;
4947 }
4948 *i_value = t;
4949 /*q*/
4950 m = 0;
4951 p = 0;
4952 for (i = 10; i < SN - 10; i++) {
4953 if (qv[i] > 0x200)
4954 m = (0x400 - qv[i]) + m;
4955 else
4956 p = qv[i] + p;
4957 }
4958 if (p > m) {
4959 t = p - m;
4960 t = t / (SN - 20);
4961 } else {
4962 t = m - p;
4963 t = t / (SN - 20);
4964 if (t != 0x0)
4965 t = 0x400 - t;
4966 }
4967 *q_value = t;
4968 #endif
4969 }
halrf_delay_10us(u16 v1)4970 void halrf_delay_10us(u16 v1)
4971 {
4972 u16 i = 0;
4973
4974 for (i = 0; i < v1; i++)
4975 ODM_delay_us(10);
4976 }
4977
4978