1 /****************************************************************************** 2 * 3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 #ifndef __INC_HALMAC_REG_8821C_H 17 #define __INC_HALMAC_REG_8821C_H 18 19 #define REG_SYS_ISO_CTRL_8821C 0x0000 20 #define REG_SYS_FUNC_EN_8821C 0x0002 21 #define REG_SYS_PW_CTRL_8821C 0x0004 22 #define REG_SYS_CLK_CTRL_8821C 0x0008 23 #define REG_SYS_EEPROM_CTRL_8821C 0x000A 24 #define REG_EE_VPD_8821C 0x000C 25 #define REG_SYS_SWR_CTRL1_8821C 0x0010 26 #define REG_SYS_SWR_CTRL2_8821C 0x0014 27 #define REG_SYS_SWR_CTRL3_8821C 0x0018 28 #define REG_RSV_CTRL_8821C 0x001C 29 #define REG_RF_CTRL_8821C 0x001F 30 #define REG_AFE_LDO_CTRL_8821C 0x0020 31 #define REG_AFE_CTRL1_8821C 0x0024 32 #define REG_AFE_CTRL2_8821C 0x0028 33 #define REG_AFE_CTRL3_8821C 0x002C 34 #define REG_EFUSE_CTRL_8821C 0x0030 35 #define REG_LDO_EFUSE_CTRL_8821C 0x0034 36 #define REG_PWR_OPTION_CTRL_8821C 0x0038 37 #define REG_CAL_TIMER_8821C 0x003C 38 #define REG_ACLK_MON_8821C 0x003E 39 #define REG_GPIO_MUXCFG_8821C 0x0040 40 #define REG_GPIO_PIN_CTRL_8821C 0x0044 41 #define REG_GPIO_INTM_8821C 0x0048 42 #define REG_LED_CFG_8821C 0x004C 43 #define REG_FSIMR_8821C 0x0050 44 #define REG_FSISR_8821C 0x0054 45 #define REG_HSIMR_8821C 0x0058 46 #define REG_HSISR_8821C 0x005C 47 #define REG_GPIO_EXT_CTRL_8821C 0x0060 48 #define REG_PAD_CTRL1_8821C 0x0064 49 #define REG_WL_BT_PWR_CTRL_8821C 0x0068 50 #define REG_SDM_DEBUG_8821C 0x006C 51 #define REG_SYS_SDIO_CTRL_8821C 0x0070 52 #define REG_HCI_OPT_CTRL_8821C 0x0074 53 #define REG_AFE_CTRL4_8821C 0x0078 54 #define REG_LDO_SWR_CTRL_8821C 0x007C 55 #define REG_MCUFW_CTRL_8821C 0x0080 56 #define REG_MCU_TST_CFG_8821C 0x0084 57 #define REG_HMEBOX_E0_E1_8821C 0x0088 58 #define REG_HMEBOX_E2_E3_8821C 0x008C 59 #define REG_WLLPS_CTRL_8821C 0x0090 60 #define REG_AFE_CTRL5_8821C 0x0094 61 #define REG_GPIO_DEBOUNCE_CTRL_8821C 0x0098 62 #define REG_RPWM2_8821C 0x009C 63 #define REG_SYSON_FSM_MON_8821C 0x00A0 64 #define REG_AFE_CTRL6_8821C 0x00A4 65 #define REG_PMC_DBG_CTRL1_8821C 0x00A8 66 #define REG_AFE_CTRL7_8821C 0x00AC 67 #define REG_HIMR0_8821C 0x00B0 68 #define REG_HISR0_8821C 0x00B4 69 #define REG_HIMR1_8821C 0x00B8 70 #define REG_HISR1_8821C 0x00BC 71 #define REG_DBG_PORT_SEL_8821C 0x00C0 72 #define REG_PAD_CTRL2_8821C 0x00C4 73 #define REG_PMC_DBG_CTRL2_8821C 0x00CC 74 #define REG_BIST_CTRL_8821C 0x00D0 75 #define REG_BIST_RPT_8821C 0x00D4 76 #define REG_MEM_CTRL_8821C 0x00D8 77 #define REG_AFE_CTRL8_8821C 0x00DC 78 #define REG_USB_SIE_INTF_8821C 0x00E0 79 #define REG_PCIE_MIO_INTF_8821C 0x00E4 80 #define REG_PCIE_MIO_INTD_8821C 0x00E8 81 #define REG_WLRF1_8821C 0x00EC 82 #define REG_SYS_CFG1_8821C 0x00F0 83 #define REG_SYS_STATUS1_8821C 0x00F4 84 #define REG_SYS_STATUS2_8821C 0x00F8 85 #define REG_SYS_CFG2_8821C 0x00FC 86 #define REG_SYS_CFG3_8821C 0x1000 87 #define REG_SYS_CFG5_8821C 0x1070 88 #define REG_CPU_DMEM_CON_8821C 0x1080 89 #define REG_BOOT_REASON_8821C 0x1088 90 #define REG_NFCPAD_CTRL_8821C 0x10A8 91 #define REG_HIMR2_8821C 0x10B0 92 #define REG_HISR2_8821C 0x10B4 93 #define REG_HIMR3_8821C 0x10B8 94 #define REG_HISR3_8821C 0x10BC 95 #define REG_SW_MDIO_8821C 0x10C0 96 #define REG_H2C_PKT_READADDR_8821C 0x10D0 97 #define REG_H2C_PKT_WRITEADDR_8821C 0x10D4 98 #define REG_MEM_PWR_CRTL_8821C 0x10D8 99 #define REG_FW_DBG6_8821C 0x10F8 100 #define REG_FW_DBG7_8821C 0x10FC 101 #define REG_CR_8821C 0x0100 102 #define REG_PG_SIZE_8821C 0x0104 103 #define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106 104 #define REG_TSF_CLK_STATE_8821C 0x0108 105 #define REG_TXDMA_PQ_MAP_8821C 0x010C 106 #define REG_TRXFF_BNDY_8821C 0x0114 107 #define REG_PTA_I2C_MBOX_8821C 0x0118 108 #define REG_RXFF_BNDY_8821C 0x011C 109 #define REG_FE1IMR_8821C 0x0120 110 #define REG_FE1ISR_8821C 0x0124 111 #define REG_CPWM_8821C 0x012C 112 #define REG_FWIMR_8821C 0x0130 113 #define REG_FWISR_8821C 0x0134 114 #define REG_FTIMR_8821C 0x0138 115 #define REG_FTISR_8821C 0x013C 116 #define REG_PKTBUF_DBG_CTRL_8821C 0x0140 117 #define REG_PKTBUF_DBG_DATA_L_8821C 0x0144 118 #define REG_PKTBUF_DBG_DATA_H_8821C 0x0148 119 #define REG_CPWM2_8821C 0x014C 120 #define REG_TC0_CTRL_8821C 0x0150 121 #define REG_TC1_CTRL_8821C 0x0154 122 #define REG_TC2_CTRL_8821C 0x0158 123 #define REG_TC3_CTRL_8821C 0x015C 124 #define REG_TC4_CTRL_8821C 0x0160 125 #define REG_TCUNIT_BASE_8821C 0x0164 126 #define REG_TC5_CTRL_8821C 0x0168 127 #define REG_TC6_CTRL_8821C 0x016C 128 #define REG_MBIST_DRF_FAIL_8821C 0x0170 129 #define REG_MBIST_START_PAUSE_8821C 0x0174 130 #define REG_MBIST_DONE_8821C 0x0178 131 #define REG_MBIST_READ_BIST_RPT_8821C 0x017C 132 #define REG_AES_DECRPT_DATA_8821C 0x0180 133 #define REG_AES_DECRPT_CFG_8821C 0x0184 134 #define REG_TMETER_8821C 0x0190 135 #define REG_OSC_32K_CTRL_8821C 0x0194 136 #define REG_32K_CAL_REG1_8821C 0x0198 137 #define REG_C2HEVT_8821C 0x01A0 138 #define REG_C2HEVT_1_8821C 0x01A4 139 #define REG_C2HEVT_2_8821C 0x01A8 140 #define REG_C2HEVT_3_8821C 0x01AC 141 #define REG_SW_DEFINED_PAGE1_8821C 0x01B8 142 #define REG_SW_DEFINED_PAGE2_8821C 0x01BC 143 #define REG_MCUTST_I_8821C 0x01C0 144 #define REG_MCUTST_II_8821C 0x01C4 145 #define REG_FMETHR_8821C 0x01C8 146 #define REG_HMETFR_8821C 0x01CC 147 #define REG_HMEBOX0_8821C 0x01D0 148 #define REG_HMEBOX1_8821C 0x01D4 149 #define REG_HMEBOX2_8821C 0x01D8 150 #define REG_HMEBOX3_8821C 0x01DC 151 #define REG_BB_ACCESS_CTRL_8821C 0x01E8 152 #define REG_BB_ACCESS_DATA_8821C 0x01EC 153 #define REG_HMEBOX_E0_8821C 0x01F0 154 #define REG_HMEBOX_E1_8821C 0x01F4 155 #define REG_HMEBOX_E2_8821C 0x01F8 156 #define REG_HMEBOX_E3_8821C 0x01FC 157 #define REG_CR_EXT_8821C 0x1100 158 #define REG_FWFF_8821C 0x1114 159 #define REG_RXFF_PTR_V1_8821C 0x1118 160 #define REG_RXFF_WTR_V1_8821C 0x111C 161 #define REG_FE2IMR_8821C 0x1120 162 #define REG_FE2ISR_8821C 0x1124 163 #define REG_FE3IMR_8821C 0x1128 164 #define REG_FE3ISR_8821C 0x112C 165 #define REG_FE4IMR_8821C 0x1130 166 #define REG_FE4ISR_8821C 0x1134 167 #define REG_FT1IMR_8821C 0x1138 168 #define REG_FT1ISR_8821C 0x113C 169 #define REG_SPWR0_8821C 0x1140 170 #define REG_SPWR1_8821C 0x1144 171 #define REG_SPWR2_8821C 0x1148 172 #define REG_SPWR3_8821C 0x114C 173 #define REG_POWSEQ_8821C 0x1150 174 #define REG_TC7_CTRL_V1_8821C 0x1158 175 #define REG_TC8_CTRL_V1_8821C 0x115C 176 #define REG_RX_BCN_TBTT_ITVL0_8821C 0x1160 177 #define REG_RX_BCN_TBTT_ITVL1_8821C 0x1164 178 #define REG_IO_WRAP_ERR_FLAG_8821C 0x1170 179 #define REG_SPEED_SENSOR_8821C 0x1180 180 #define REG_SPEED_SENSOR1_8821C 0x1184 181 #define REG_SPEED_SENSOR2_8821C 0x1188 182 #define REG_SPEED_SENSOR3_8821C 0x118C 183 #define REG_SPEED_SENSOR4_8821C 0x1190 184 #define REG_SPEED_SENSOR5_8821C 0x1194 185 #define REG_COUNTER_CTRL_8821C 0x11C4 186 #define REG_COUNTER_THRESHOLD_8821C 0x11C8 187 #define REG_COUNTER_SET_8821C 0x11CC 188 #define REG_COUNTER_OVERFLOW_8821C 0x11D0 189 #define REG_TXDMA_LEN_THRESHOLD_8821C 0x11D4 190 #define REG_RXDMA_LEN_THRESHOLD_8821C 0x11D8 191 #define REG_PCIE_EXEC_TIME_THRESHOLD_8821C 0x11DC 192 #define REG_FT2IMR_8821C 0x11E0 193 #define REG_FT2ISR_8821C 0x11E4 194 #define REG_MSG2_8821C 0x11F0 195 #define REG_MSG3_8821C 0x11F4 196 #define REG_MSG4_8821C 0x11F8 197 #define REG_MSG5_8821C 0x11FC 198 #define REG_FIFOPAGE_CTRL_1_8821C 0x0200 199 #define REG_FIFOPAGE_CTRL_2_8821C 0x0204 200 #define REG_AUTO_LLT_V1_8821C 0x0208 201 #define REG_TXDMA_OFFSET_CHK_8821C 0x020C 202 #define REG_TXDMA_STATUS_8821C 0x0210 203 #define REG_TX_DMA_DBG_8821C 0x0214 204 #define REG_TQPNT1_8821C 0x0218 205 #define REG_TQPNT2_8821C 0x021C 206 #define REG_TQPNT3_8821C 0x0220 207 #define REG_TQPNT4_8821C 0x0224 208 #define REG_RQPN_CTRL_1_8821C 0x0228 209 #define REG_RQPN_CTRL_2_8821C 0x022C 210 #define REG_FIFOPAGE_INFO_1_8821C 0x0230 211 #define REG_FIFOPAGE_INFO_2_8821C 0x0234 212 #define REG_FIFOPAGE_INFO_3_8821C 0x0238 213 #define REG_FIFOPAGE_INFO_4_8821C 0x023C 214 #define REG_FIFOPAGE_INFO_5_8821C 0x0240 215 #define REG_H2C_HEAD_8821C 0x0244 216 #define REG_H2C_TAIL_8821C 0x0248 217 #define REG_H2C_READ_ADDR_8821C 0x024C 218 #define REG_H2C_WR_ADDR_8821C 0x0250 219 #define REG_H2C_INFO_8821C 0x0254 220 #define REG_RXDMA_AGG_PG_TH_8821C 0x0280 221 #define REG_RXPKT_NUM_8821C 0x0284 222 #define REG_RXDMA_STATUS_8821C 0x0288 223 #define REG_RXDMA_DPR_8821C 0x028C 224 #define REG_RXDMA_MODE_8821C 0x0290 225 #define REG_C2H_PKT_8821C 0x0294 226 #define REG_FWFF_C2H_8821C 0x0298 227 #define REG_FWFF_CTRL_8821C 0x029C 228 #define REG_FWFF_PKT_INFO_8821C 0x02A0 229 #define REG_DDMA_CH0SA_8821C 0x1200 230 #define REG_DDMA_CH0DA_8821C 0x1204 231 #define REG_DDMA_CH0CTRL_8821C 0x1208 232 #define REG_DDMA_CH1SA_8821C 0x1210 233 #define REG_DDMA_CH1DA_8821C 0x1214 234 #define REG_DDMA_CH1CTRL_8821C 0x1218 235 #define REG_DDMA_CH2SA_8821C 0x1220 236 #define REG_DDMA_CH2DA_8821C 0x1224 237 #define REG_DDMA_CH2CTRL_8821C 0x1228 238 #define REG_DDMA_CH3SA_8821C 0x1230 239 #define REG_DDMA_CH3DA_8821C 0x1234 240 #define REG_DDMA_CH3CTRL_8821C 0x1238 241 #define REG_DDMA_CH4SA_8821C 0x1240 242 #define REG_DDMA_CH4DA_8821C 0x1244 243 #define REG_DDMA_CH4CTRL_8821C 0x1248 244 #define REG_DDMA_CH5SA_8821C 0x1250 245 #define REG_DDMA_CH5DA_8821C 0x1254 246 #define REG_DDMA_CH5CTRL_8821C 0x1258 247 #define REG_DDMA_INT_MSK_8821C 0x12E0 248 #define REG_DDMA_CHSTATUS_8821C 0x12E8 249 #define REG_DDMA_CHKSUM_8821C 0x12F0 250 #define REG_DDMA_MONITOR_8821C 0x12FC 251 #define REG_PCIE_CTRL_8821C 0x0300 252 #define REG_INT_MIG_8821C 0x0304 253 #define REG_BCNQ_TXBD_DESA_8821C 0x0308 254 #define REG_MGQ_TXBD_DESA_8821C 0x0310 255 #define REG_VOQ_TXBD_DESA_8821C 0x0318 256 #define REG_VIQ_TXBD_DESA_8821C 0x0320 257 #define REG_BEQ_TXBD_DESA_8821C 0x0328 258 #define REG_BKQ_TXBD_DESA_8821C 0x0330 259 #define REG_RXQ_RXBD_DESA_8821C 0x0338 260 #define REG_HI0Q_TXBD_DESA_8821C 0x0340 261 #define REG_HI1Q_TXBD_DESA_8821C 0x0348 262 #define REG_HI2Q_TXBD_DESA_8821C 0x0350 263 #define REG_HI3Q_TXBD_DESA_8821C 0x0358 264 #define REG_HI4Q_TXBD_DESA_8821C 0x0360 265 #define REG_HI5Q_TXBD_DESA_8821C 0x0368 266 #define REG_HI6Q_TXBD_DESA_8821C 0x0370 267 #define REG_HI7Q_TXBD_DESA_8821C 0x0378 268 #define REG_MGQ_TXBD_NUM_8821C 0x0380 269 #define REG_RX_RXBD_NUM_8821C 0x0382 270 #define REG_VOQ_TXBD_NUM_8821C 0x0384 271 #define REG_VIQ_TXBD_NUM_8821C 0x0386 272 #define REG_BEQ_TXBD_NUM_8821C 0x0388 273 #define REG_BKQ_TXBD_NUM_8821C 0x038A 274 #define REG_HI0Q_TXBD_NUM_8821C 0x038C 275 #define REG_HI1Q_TXBD_NUM_8821C 0x038E 276 #define REG_HI2Q_TXBD_NUM_8821C 0x0390 277 #define REG_HI3Q_TXBD_NUM_8821C 0x0392 278 #define REG_HI4Q_TXBD_NUM_8821C 0x0394 279 #define REG_HI5Q_TXBD_NUM_8821C 0x0396 280 #define REG_HI6Q_TXBD_NUM_8821C 0x0398 281 #define REG_HI7Q_TXBD_NUM_8821C 0x039A 282 #define REG_TSFTIMER_HCI_8821C 0x039C 283 #define REG_BD_RWPTR_CLR_8821C 0x039C 284 #define REG_VOQ_TXBD_IDX_8821C 0x03A0 285 #define REG_VIQ_TXBD_IDX_8821C 0x03A4 286 #define REG_BEQ_TXBD_IDX_8821C 0x03A8 287 #define REG_BKQ_TXBD_IDX_8821C 0x03AC 288 #define REG_MGQ_TXBD_IDX_8821C 0x03B0 289 #define REG_RXQ_RXBD_IDX_8821C 0x03B4 290 #define REG_HI0Q_TXBD_IDX_8821C 0x03B8 291 #define REG_HI1Q_TXBD_IDX_8821C 0x03BC 292 #define REG_HI2Q_TXBD_IDX_8821C 0x03C0 293 #define REG_HI3Q_TXBD_IDX_8821C 0x03C4 294 #define REG_HI4Q_TXBD_IDX_8821C 0x03C8 295 #define REG_HI5Q_TXBD_IDX_8821C 0x03CC 296 #define REG_HI6Q_TXBD_IDX_8821C 0x03D0 297 #define REG_HI7Q_TXBD_IDX_8821C 0x03D4 298 #define REG_DBG_SEL_V1_8821C 0x03D8 299 #define REG_PCIE_HRPWM1_V1_8821C 0x03D9 300 #define REG_PCIE_HCPWM1_V1_8821C 0x03DA 301 #define REG_PCIE_CTRL2_8821C 0x03DB 302 #define REG_PCIE_HRPWM2_V1_8821C 0x03DC 303 #define REG_PCIE_HCPWM2_V1_8821C 0x03DE 304 #define REG_PCIE_H2C_MSG_V1_8821C 0x03E0 305 #define REG_PCIE_C2H_MSG_V1_8821C 0x03E4 306 #define REG_DBI_WDATA_V1_8821C 0x03E8 307 #define REG_DBI_RDATA_V1_8821C 0x03EC 308 #define REG_DBI_FLAG_V1_8821C 0x03F0 309 #define REG_MDIO_V1_8821C 0x03F4 310 #define REG_PCIE_MIX_CFG_8821C 0x03F8 311 #define REG_HCI_MIX_CFG_8821C 0x03FC 312 #define REG_STC_INT_CS_8821C 0x1300 313 #define REG_ST_INT_CFG_8821C 0x1304 314 #define REG_CMU_DLY_CTRL_8821C 0x1310 315 #define REG_CMU_DLY_CFG_8821C 0x1314 316 #define REG_H2CQ_TXBD_DESA_8821C 0x1320 317 #define REG_H2CQ_TXBD_NUM_8821C 0x1328 318 #define REG_H2CQ_TXBD_IDX_8821C 0x132C 319 #define REG_H2CQ_CSR_8821C 0x1330 320 #define REG_Q0_INFO_8821C 0x0400 321 #define REG_Q1_INFO_8821C 0x0404 322 #define REG_Q2_INFO_8821C 0x0408 323 #define REG_Q3_INFO_8821C 0x040C 324 #define REG_MGQ_INFO_8821C 0x0410 325 #define REG_HIQ_INFO_8821C 0x0414 326 #define REG_BCNQ_INFO_8821C 0x0418 327 #define REG_TXPKT_EMPTY_8821C 0x041A 328 #define REG_CPU_MGQ_INFO_8821C 0x041C 329 #define REG_FWHW_TXQ_CTRL_8821C 0x0420 330 #define REG_DATAFB_SEL_8821C 0x0423 331 #define REG_BCNQ_BDNY_V1_8821C 0x0424 332 #define REG_LIFETIME_EN_8821C 0x0426 333 #define REG_SPEC_SIFS_8821C 0x0428 334 #define REG_RETRY_LIMIT_8821C 0x042A 335 #define REG_TXBF_CTRL_8821C 0x042C 336 #define REG_DARFRC_8821C 0x0430 337 #define REG_DARFRCH_8821C 0x0434 338 #define REG_RARFRC_8821C 0x0438 339 #define REG_RARFRCH_8821C 0x043C 340 #define REG_RRSR_8821C 0x0440 341 #define REG_ARFR0_8821C 0x0444 342 #define REG_ARFRH0_8821C 0x0448 343 #define REG_ARFR1_V1_8821C 0x044C 344 #define REG_ARFRH1_V1_8821C 0x0450 345 #define REG_CCK_CHECK_8821C 0x0454 346 #define REG_AMPDU_MAX_TIME_V1_8821C 0x0455 347 #define REG_BCNQ1_BDNY_V1_8821C 0x0456 348 #define REG_AMPDU_MAX_LENGTH_8821C 0x0458 349 #define REG_ACQ_STOP_8821C 0x045C 350 #define REG_NDPA_RATE_8821C 0x045D 351 #define REG_TX_HANG_CTRL_8821C 0x045E 352 #define REG_NDPA_OPT_CTRL_8821C 0x045F 353 #define REG_RD_RESP_PKT_TH_8821C 0x0463 354 #define REG_CMDQ_INFO_8821C 0x0464 355 #define REG_Q4_INFO_8821C 0x0468 356 #define REG_Q5_INFO_8821C 0x046C 357 #define REG_Q6_INFO_8821C 0x0470 358 #define REG_Q7_INFO_8821C 0x0474 359 #define REG_WMAC_LBK_BUF_HD_V1_8821C 0x0478 360 #define REG_MGQ_BDNY_V1_8821C 0x047A 361 #define REG_TXRPT_CTRL_8821C 0x047C 362 #define REG_INIRTS_RATE_SEL_8821C 0x0480 363 #define REG_BASIC_CFEND_RATE_8821C 0x0481 364 #define REG_STBC_CFEND_RATE_8821C 0x0482 365 #define REG_DATA_SC_8821C 0x0483 366 #define REG_MACID_SLEEP3_8821C 0x0484 367 #define REG_MACID_SLEEP1_8821C 0x0488 368 #define REG_ARFR2_V1_8821C 0x048C 369 #define REG_ARFRH2_V1_8821C 0x0490 370 #define REG_ARFR3_V1_8821C 0x0494 371 #define REG_ARFRH3_V1_8821C 0x0498 372 #define REG_ARFR4_8821C 0x049C 373 #define REG_ARFRH4_8821C 0x04A0 374 #define REG_ARFR5_8821C 0x04A4 375 #define REG_ARFRH5_8821C 0x04A8 376 #define REG_TXRPT_START_OFFSET_8821C 0x04AC 377 #define REG_POWER_STAGE1_8821C 0x04B4 378 #define REG_POWER_STAGE2_8821C 0x04B8 379 #define REG_SW_AMPDU_BURST_MODE_CTRL_8821C 0x04BC 380 #define REG_PKT_LIFE_TIME_8821C 0x04C0 381 #define REG_STBC_SETTING_8821C 0x04C4 382 #define REG_STBC_SETTING2_8821C 0x04C5 383 #define REG_QUEUE_CTRL_8821C 0x04C6 384 #define REG_SINGLE_AMPDU_CTRL_8821C 0x04C7 385 #define REG_PROT_MODE_CTRL_8821C 0x04C8 386 #define REG_BAR_MODE_CTRL_8821C 0x04CC 387 #define REG_RA_TRY_RATE_AGG_LMT_8821C 0x04CF 388 #define REG_MACID_SLEEP2_8821C 0x04D0 389 #define REG_MACID_SLEEP_8821C 0x04D4 390 #define REG_HW_SEQ0_8821C 0x04D8 391 #define REG_HW_SEQ1_8821C 0x04DA 392 #define REG_HW_SEQ2_8821C 0x04DC 393 #define REG_HW_SEQ3_8821C 0x04DE 394 #define REG_NULL_PKT_STATUS_V1_8821C 0x04E0 395 #define REG_PTCL_ERR_STATUS_8821C 0x04E2 396 #define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3 397 #define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4 398 #define REG_PRECNT_CTRL_8821C 0x04E5 399 #define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8 400 #define REG_PTCL_DBG_8821C 0x04EC 401 #define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4 402 #define REG_DUMMY_PAGE4_V1_8821C 0x04FC 403 #define REG_MOREDATA_8821C 0x04FE 404 #define REG_Q0_Q1_INFO_8821C 0x1400 405 #define REG_Q2_Q3_INFO_8821C 0x1404 406 #define REG_Q4_Q5_INFO_8821C 0x1408 407 #define REG_Q6_Q7_INFO_8821C 0x140C 408 #define REG_MGQ_HIQ_INFO_8821C 0x1410 409 #define REG_CMDQ_BCNQ_INFO_8821C 0x1414 410 #define REG_USEREG_SETTING_8821C 0x1420 411 #define REG_AESIV_SETTING_8821C 0x1424 412 #define REG_BF0_TIME_SETTING_8821C 0x1428 413 #define REG_BF1_TIME_SETTING_8821C 0x142C 414 #define REG_BF_TIMEOUT_EN_8821C 0x1430 415 #define REG_MACID_RELEASE0_8821C 0x1434 416 #define REG_MACID_RELEASE1_8821C 0x1438 417 #define REG_MACID_RELEASE2_8821C 0x143C 418 #define REG_MACID_RELEASE3_8821C 0x1440 419 #define REG_MACID_RELEASE_SETTING_8821C 0x1444 420 #define REG_FAST_EDCA_VOVI_SETTING_8821C 0x1448 421 #define REG_FAST_EDCA_BEBK_SETTING_8821C 0x144C 422 #define REG_MACID_DROP0_8821C 0x1450 423 #define REG_MACID_DROP1_8821C 0x1454 424 #define REG_MACID_DROP2_8821C 0x1458 425 #define REG_MACID_DROP3_8821C 0x145C 426 #define REG_R_MACID_RELEASE_SUCCESS_0_8821C 0x1460 427 #define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464 428 #define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468 429 #define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C 430 #define REG_MGQ_FIFO_WRITE_POINTER_8821C 0x1470 431 #define REG_MGQ_FIFO_READ_POINTER_8821C 0x1472 432 #define REG_MGQ_FIFO_ENABLE_8821C 0x1472 433 #define REG_MGQ_FIFO_RELEASE_INT_MASK_8821C 0x1474 434 #define REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C 0x1476 435 #define REG_MGQ_FIFO_VALID_MAP_8821C 0x1478 436 #define REG_MGQ_FIFO_LIFETIME_8821C 0x147A 437 #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C 438 #define REG_SHCUT_SETTING_8821C 0x1480 439 #define REG_SHCUT_LLC_ETH_TYPE0_8821C 0x1484 440 #define REG_SHCUT_LLC_ETH_TYPE1_8821C 0x1488 441 #define REG_SHCUT_LLC_OUI0_8821C 0x148C 442 #define REG_SHCUT_LLC_OUI1_8821C 0x1490 443 #define REG_SHCUT_LLC_OUI2_8821C 0x1494 444 #define REG_MU_TX_CTL_8821C 0x14C0 445 #define REG_MU_STA_GID_VLD_8821C 0x14C4 446 #define REG_MU_STA_USER_POS_INFO_8821C 0x14C8 447 #define REG_MU_STA_USER_POS_INFO_H_8821C 0x14CC 448 #define REG_MU_TRX_DBG_CNT_8821C 0x14D0 449 #define REG_EDCA_VO_PARAM_8821C 0x0500 450 #define REG_EDCA_VI_PARAM_8821C 0x0504 451 #define REG_EDCA_BE_PARAM_8821C 0x0508 452 #define REG_EDCA_BK_PARAM_8821C 0x050C 453 #define REG_BCNTCFG_8821C 0x0510 454 #define REG_PIFS_8821C 0x0512 455 #define REG_RDG_PIFS_8821C 0x0513 456 #define REG_SIFS_8821C 0x0514 457 #define REG_TSFTR_SYN_OFFSET_8821C 0x0518 458 #define REG_AGGR_BREAK_TIME_8821C 0x051A 459 #define REG_SLOT_8821C 0x051B 460 #define REG_NOA_ON_ERLY_TIME_8821C 0x051C 461 #define REG_NOA_OFF_ERLY_TIME_8821C 0x051D 462 #define REG_TX_PTCL_CTRL_8821C 0x0520 463 #define REG_TXPAUSE_8821C 0x0522 464 #define REG_DIS_TXREQ_CLR_8821C 0x0523 465 #define REG_RD_CTRL_8821C 0x0524 466 #define REG_MBSSID_CTRL_8821C 0x0526 467 #define REG_P2PPS_CTRL_8821C 0x0527 468 #define REG_PKT_LIFETIME_CTRL_8821C 0x0528 469 #define REG_P2PPS_SPEC_STATE_8821C 0x052B 470 #define REG_BAR_TX_CTRL_8821C 0x0530 471 #define REG_P2PON_DIS_TXTIME_8821C 0x0531 472 #define REG_TBTT_PROHIBIT_8821C 0x0540 473 #define REG_P2PPS_STATE_8821C 0x0543 474 #define REG_RD_NAV_NXT_8821C 0x0544 475 #define REG_NAV_PROT_LEN_8821C 0x0546 476 #define REG_BCN_CTRL_8821C 0x0550 477 #define REG_BCN_CTRL_CLINT0_8821C 0x0551 478 #define REG_MBID_NUM_8821C 0x0552 479 #define REG_DUAL_TSF_RST_8821C 0x0553 480 #define REG_MBSSID_BCN_SPACE_8821C 0x0554 481 #define REG_DRVERLYINT_8821C 0x0558 482 #define REG_BCNDMATIM_8821C 0x0559 483 #define REG_ATIMWND_8821C 0x055A 484 #define REG_USTIME_TSF_8821C 0x055C 485 #define REG_BCN_MAX_ERR_8821C 0x055D 486 #define REG_RXTSF_OFFSET_CCK_8821C 0x055E 487 #define REG_RXTSF_OFFSET_OFDM_8821C 0x055F 488 #define REG_TSFTR_8821C 0x0560 489 #define REG_TSFTR_1_8821C 0x0564 490 #define REG_FREERUN_CNT_8821C 0x0568 491 #define REG_FREERUN_CNT_1_8821C 0x056C 492 #define REG_ATIMWND1_V1_8821C 0x0570 493 #define REG_TBTT_PROHIBIT_INFRA_8821C 0x0571 494 #define REG_CTWND_8821C 0x0572 495 #define REG_BCNIVLCUNT_8821C 0x0573 496 #define REG_BCNDROPCTRL_8821C 0x0574 497 #define REG_HGQ_TIMEOUT_PERIOD_8821C 0x0575 498 #define REG_TXCMD_TIMEOUT_PERIOD_8821C 0x0576 499 #define REG_MISC_CTRL_8821C 0x0577 500 #define REG_BCN_CTRL_CLINT1_8821C 0x0578 501 #define REG_BCN_CTRL_CLINT2_8821C 0x0579 502 #define REG_BCN_CTRL_CLINT3_8821C 0x057A 503 #define REG_EXTEND_CTRL_8821C 0x057B 504 #define REG_P2PPS1_SPEC_STATE_8821C 0x057C 505 #define REG_P2PPS1_STATE_8821C 0x057D 506 #define REG_P2PPS2_SPEC_STATE_8821C 0x057E 507 #define REG_P2PPS2_STATE_8821C 0x057F 508 #define REG_PS_TIMER0_8821C 0x0580 509 #define REG_PS_TIMER1_8821C 0x0584 510 #define REG_PS_TIMER2_8821C 0x0588 511 #define REG_TBTT_CTN_AREA_8821C 0x058C 512 #define REG_FORCE_BCN_IFS_8821C 0x058E 513 #define REG_TXOP_MIN_8821C 0x0590 514 #define REG_PRE_BKF_TIME_8821C 0x0592 515 #define REG_CROSS_TXOP_CTRL_8821C 0x0593 516 #define REG_ATIMWND2_8821C 0x05A0 517 #define REG_ATIMWND3_8821C 0x05A1 518 #define REG_ATIMWND4_8821C 0x05A2 519 #define REG_ATIMWND5_8821C 0x05A3 520 #define REG_ATIMWND6_8821C 0x05A4 521 #define REG_ATIMWND7_8821C 0x05A5 522 #define REG_ATIMUGT_8821C 0x05A6 523 #define REG_HIQ_NO_LMT_EN_8821C 0x05A7 524 #define REG_DTIM_COUNTER_ROOT_8821C 0x05A8 525 #define REG_DTIM_COUNTER_VAP1_8821C 0x05A9 526 #define REG_DTIM_COUNTER_VAP2_8821C 0x05AA 527 #define REG_DTIM_COUNTER_VAP3_8821C 0x05AB 528 #define REG_DTIM_COUNTER_VAP4_8821C 0x05AC 529 #define REG_DTIM_COUNTER_VAP5_8821C 0x05AD 530 #define REG_DTIM_COUNTER_VAP6_8821C 0x05AE 531 #define REG_DTIM_COUNTER_VAP7_8821C 0x05AF 532 #define REG_DIS_ATIM_8821C 0x05B0 533 #define REG_EARLY_128US_8821C 0x05B1 534 #define REG_P2PPS1_CTRL_8821C 0x05B2 535 #define REG_P2PPS2_CTRL_8821C 0x05B3 536 #define REG_TIMER0_SRC_SEL_8821C 0x05B4 537 #define REG_NOA_UNIT_SEL_8821C 0x05B5 538 #define REG_P2POFF_DIS_TXTIME_8821C 0x05B7 539 #define REG_MBSSID_BCN_SPACE2_8821C 0x05B8 540 #define REG_MBSSID_BCN_SPACE3_8821C 0x05BC 541 #define REG_ACMHWCTRL_8821C 0x05C0 542 #define REG_ACMRSTCTRL_8821C 0x05C1 543 #define REG_ACMAVG_8821C 0x05C2 544 #define REG_VO_ADMTIME_8821C 0x05C4 545 #define REG_VI_ADMTIME_8821C 0x05C6 546 #define REG_BE_ADMTIME_8821C 0x05C8 547 #define REG_EDCA_RANDOM_GEN_8821C 0x05CC 548 #define REG_TXCMD_NOA_SEL_8821C 0x05CF 549 #define REG_NOA_PARAM_8821C 0x05E0 550 #define REG_NOA_PARAM_1_8821C 0x05E4 551 #define REG_NOA_PARAM_2_8821C 0x05E8 552 #define REG_NOA_PARAM_3_8821C 0x05EC 553 #define REG_P2P_RST_8821C 0x05F0 554 #define REG_SCHEDULER_RST_8821C 0x05F1 555 #define REG_SCH_TXCMD_8821C 0x05F8 556 #define REG_PAGE5_DUMMY_8821C 0x05FC 557 #define REG_CPUMGQ_TX_TIMER_8821C 0x1500 558 #define REG_PS_TIMER_A_8821C 0x1504 559 #define REG_PS_TIMER_B_8821C 0x1508 560 #define REG_PS_TIMER_C_8821C 0x150C 561 #define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C 0x1510 562 #define REG_CPUMGQ_TX_TIMER_EARLY_8821C 0x1514 563 #define REG_PS_TIMER_A_EARLY_8821C 0x1515 564 #define REG_PS_TIMER_B_EARLY_8821C 0x1516 565 #define REG_PS_TIMER_C_EARLY_8821C 0x1517 566 #define REG_CPUMGQ_PARAMETER_8821C 0x1518 567 #define REG_WMAC_CR_8821C 0x0600 568 #define REG_WMAC_FWPKT_CR_8821C 0x0601 569 #define REG_FW_STS_FILTER_8821C 0x0602 570 #define REG_TCR_8821C 0x0604 571 #define REG_RCR_8821C 0x0608 572 #define REG_RX_PKT_LIMIT_8821C 0x060C 573 #define REG_RX_DLK_TIME_8821C 0x060D 574 #define REG_RX_DRVINFO_SZ_8821C 0x060F 575 #define REG_MACID_8821C 0x0610 576 #define REG_MACID_H_8821C 0x0614 577 #define REG_BSSID_8821C 0x0618 578 #define REG_BSSID_H_8821C 0x061C 579 #define REG_MAR_8821C 0x0620 580 #define REG_MAR_H_8821C 0x0624 581 #define REG_MBIDCAMCFG_1_8821C 0x0628 582 #define REG_MBIDCAMCFG_2_8821C 0x062C 583 #define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630 584 #define REG_UDF_THSD_8821C 0x0632 585 #define REG_ZLD_NUM_8821C 0x0633 586 #define REG_STMP_THSD_8821C 0x0634 587 #define REG_WMAC_TXTIMEOUT_8821C 0x0635 588 #define REG_MCU_TEST_2_V1_8821C 0x0636 589 #define REG_USTIME_EDCA_8821C 0x0638 590 #define REG_ACKTO_CCK_8821C 0x0639 591 #define REG_MAC_SPEC_SIFS_8821C 0x063A 592 #define REG_RESP_SIFS_CCK_8821C 0x063C 593 #define REG_RESP_SIFS_OFDM_8821C 0x063E 594 #define REG_ACKTO_8821C 0x0640 595 #define REG_CTS2TO_8821C 0x0641 596 #define REG_EIFS_8821C 0x0642 597 #define REG_RPFM_MAP0_8821C 0x0644 598 #define REG_RPFM_MAP1_V1_8821C 0x0646 599 #define REG_RPFM_CAM_CMD_8821C 0x0648 600 #define REG_RPFM_CAM_RWD_8821C 0x064C 601 #define REG_NAV_CTRL_8821C 0x0650 602 #define REG_BACAMCMD_8821C 0x0654 603 #define REG_BACAMCONTENT_8821C 0x0658 604 #define REG_BACAMCONTENT_H_8821C 0x065C 605 #define REG_LBDLY_8821C 0x0660 606 #define REG_WMAC_BACAM_RPMEN_8821C 0x0661 607 #define REG_TX_RX_8821C 0x0662 608 #define REG_WMAC_BITMAP_CTL_8821C 0x0663 609 #define REG_RXERR_RPT_8821C 0x0664 610 #define REG_WMAC_TRXPTCL_CTL_8821C 0x0668 611 #define REG_WMAC_TRXPTCL_CTL_H_8821C 0x066C 612 #define REG_CAMCMD_8821C 0x0670 613 #define REG_CAMWRITE_8821C 0x0674 614 #define REG_CAMREAD_8821C 0x0678 615 #define REG_CAMDBG_8821C 0x067C 616 #define REG_SECCFG_8821C 0x0680 617 #define REG_RXFILTER_CATEGORY_1_8821C 0x0682 618 #define REG_RXFILTER_ACTION_1_8821C 0x0683 619 #define REG_RXFILTER_CATEGORY_2_8821C 0x0684 620 #define REG_RXFILTER_ACTION_2_8821C 0x0685 621 #define REG_RXFILTER_CATEGORY_3_8821C 0x0686 622 #define REG_RXFILTER_ACTION_3_8821C 0x0687 623 #define REG_RXFLTMAP3_8821C 0x0688 624 #define REG_RXFLTMAP4_8821C 0x068A 625 #define REG_RXFLTMAP5_8821C 0x068C 626 #define REG_RXFLTMAP6_8821C 0x068E 627 #define REG_WOW_CTRL_8821C 0x0690 628 #define REG_NAN_RX_TSF_FILTER_8821C 0x0691 629 #define REG_PS_RX_INFO_8821C 0x0692 630 #define REG_WMMPS_UAPSD_TID_8821C 0x0693 631 #define REG_LPNAV_CTRL_8821C 0x0694 632 #define REG_WKFMCAM_CMD_8821C 0x0698 633 #define REG_WKFMCAM_RWD_8821C 0x069C 634 #define REG_RXFLTMAP0_8821C 0x06A0 635 #define REG_RXFLTMAP1_8821C 0x06A2 636 #define REG_RXFLTMAP2_8821C 0x06A4 637 #define REG_BCN_PSR_RPT_8821C 0x06A8 638 #define REG_FLC_RPC_8821C 0x06AC 639 #define REG_FLC_RPCT_8821C 0x06AD 640 #define REG_FLC_PTS_8821C 0x06AE 641 #define REG_FLC_TRPC_8821C 0x06AF 642 #define REG_RXPKTMON_CTRL_8821C 0x06B0 643 #define REG_STATE_MON_8821C 0x06B4 644 #define REG_ERROR_MON_8821C 0x06B8 645 #define REG_SEARCH_MACID_8821C 0x06BC 646 #define REG_BT_COEX_TABLE_8821C 0x06C0 647 #define REG_BT_COEX_TABLE2_8821C 0x06C4 648 #define REG_BT_COEX_BREAK_TABLE_8821C 0x06C8 649 #define REG_BT_COEX_TABLE_H_8821C 0x06CC 650 #define REG_RXCMD_0_8821C 0x06D0 651 #define REG_RXCMD_1_8821C 0x06D4 652 #define REG_WMAC_RESP_TXINFO_8821C 0x06D8 653 #define REG_BBPSF_CTRL_8821C 0x06DC 654 #define REG_P2P_RX_BCN_NOA_8821C 0x06E0 655 #define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4 656 #define REG_ASSOCIATED_BFMER0_INFO_H_8821C 0x06E8 657 #define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC 658 #define REG_ASSOCIATED_BFMER1_INFO_H_8821C 0x06F0 659 #define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4 660 #define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8 661 #define REG_BCN_PSR_RPT2_8821C 0x1600 662 #define REG_BCN_PSR_RPT3_8821C 0x1604 663 #define REG_BCN_PSR_RPT4_8821C 0x1608 664 #define REG_A1_ADDR_MASK_8821C 0x160C 665 #define REG_MACID2_8821C 0x1620 666 #define REG_MACID2_H_8821C 0x1624 667 #define REG_BSSID2_8821C 0x1628 668 #define REG_BSSID2_H_8821C 0x162C 669 #define REG_MACID3_8821C 0x1630 670 #define REG_MACID3_H_8821C 0x1634 671 #define REG_BSSID3_8821C 0x1638 672 #define REG_BSSID3_H_8821C 0x163C 673 #define REG_MACID4_8821C 0x1640 674 #define REG_MACID4_H_8821C 0x1644 675 #define REG_BSSID4_8821C 0x1648 676 #define REG_BSSID4_H_8821C 0x164C 677 #define REG_NOA_REPORT_8821C 0x1650 678 #define REG_NOA_REPORT_1_8821C 0x1654 679 #define REG_NOA_REPORT_2_8821C 0x1658 680 #define REG_NOA_REPORT_3_8821C 0x165C 681 #define REG_PWRBIT_SETTING_8821C 0x1660 682 #define REG_MU_BF_OPTION_8821C 0x167C 683 #define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D 684 #define REG_WMAC_MU_ARB_8821C 0x167E 685 #define REG_WMAC_MU_OPTION_8821C 0x167F 686 #define REG_WMAC_MU_BF_CTL_8821C 0x1680 687 #define REG_WMAC_MU_BFRPT_PARA_8821C 0x1682 688 #define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684 689 #define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686 690 #define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688 691 #define REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C 0x168A 692 #define REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C 0x168C 693 #define REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C 0x168E 694 #define REG_WMAC_BB_STOP_RX_COUNTER_8821C 0x1690 695 #define REG_WMAC_PLCP_MONITOR_8821C 0x1694 696 #define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698 697 #define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0 698 #define REG_TRANSMIT_ADDRSS_0_H_8821C 0x16A4 699 #define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8 700 #define REG_TRANSMIT_ADDRSS_1_H_8821C 0x16AC 701 #define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0 702 #define REG_TRANSMIT_ADDRSS_2_H_8821C 0x16B4 703 #define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8 704 #define REG_TRANSMIT_ADDRSS_3_H_8821C 0x16BC 705 #define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0 706 #define REG_TRANSMIT_ADDRSS_4_H_8821C 0x16C4 707 #define REG_MACID1_8821C 0x0700 708 #define REG_MACID1_1_8821C 0x0704 709 #define REG_BSSID1_8821C 0x0708 710 #define REG_BSSID1_1_8821C 0x070C 711 #define REG_BCN_PSR_RPT1_8821C 0x0710 712 #define REG_ASSOCIATED_BFMEE_SEL_8821C 0x0714 713 #define REG_SND_PTCL_CTRL_8821C 0x0718 714 #define REG_RX_CSI_RPT_INFO_8821C 0x071C 715 #define REG_NS_ARP_CTRL_8821C 0x0720 716 #define REG_NS_ARP_INFO_8821C 0x0724 717 #define REG_BEAMFORMING_INFO_NSARP_V1_8821C 0x0728 718 #define REG_BEAMFORMING_INFO_NSARP_8821C 0x072C 719 #define REG_IPV6_8821C 0x0730 720 #define REG_IPV6_1_8821C 0x0734 721 #define REG_IPV6_2_8821C 0x0738 722 #define REG_IPV6_3_8821C 0x073C 723 #define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C 0x0750 724 #define REG_WMAC_SWAES_CFG_8821C 0x0760 725 #define REG_BT_COEX_V2_8821C 0x0762 726 #define REG_BT_COEX_8821C 0x0764 727 #define REG_WLAN_ACT_MASK_CTRL_8821C 0x0768 728 #define REG_WLAN_ACT_MASK_CTRL_1_8821C 0x076C 729 #define REG_BT_COEX_ENHANCED_INTR_CTRL_8821C 0x076E 730 #define REG_BT_ACT_STATISTICS_8821C 0x0770 731 #define REG_BT_ACT_STATISTICS_1_8821C 0x0774 732 #define REG_BT_STATISTICS_CONTROL_REGISTER_8821C 0x0778 733 #define REG_BT_STATUS_REPORT_REGISTER_8821C 0x077C 734 #define REG_BT_INTERRUPT_CONTROL_REGISTER_8821C 0x0780 735 #define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C 0x0784 736 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C 0x0785 737 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C 0x0788 738 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C 0x078C 739 #define REG_BT_INTERRUPT_STATUS_REGISTER_8821C 0x078F 740 #define REG_BT_TDMA_TIME_REGISTER_8821C 0x0790 741 #define REG_BT_ACT_REGISTER_8821C 0x0794 742 #define REG_OBFF_CTRL_BASIC_8821C 0x0798 743 #define REG_OBFF_CTRL2_TIMER_8821C 0x079C 744 #define REG_LTR_CTRL_BASIC_8821C 0x07A0 745 #define REG_LTR_CTRL2_TIMER_THRESHOLD_8821C 0x07A4 746 #define REG_LTR_IDLE_LATENCY_V1_8821C 0x07A8 747 #define REG_LTR_ACTIVE_LATENCY_V1_8821C 0x07AC 748 #define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C 0x07B0 749 #define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C 0x07B4 750 #define REG_WMAC_PKTCNT_RWD_8821C 0x07B8 751 #define REG_WMAC_PKTCNT_CTRL_8821C 0x07BC 752 #define REG_IQ_DUMP_8821C 0x07C0 753 #define REG_IQ_DUMP_1_8821C 0x07C4 754 #define REG_IQ_DUMP_2_8821C 0x07C8 755 #define REG_WMAC_FTM_CTL_8821C 0x07CC 756 #define REG_WMAC_IQ_MDPK_FUNC_8821C 0x07CE 757 #define REG_WMAC_OPTION_FUNCTION_8821C 0x07D0 758 #define REG_WMAC_OPTION_FUNCTION_1_8821C 0x07D4 759 #define REG_WMAC_OPTION_FUNCTION_2_8821C 0x07D8 760 #define REG_RX_FILTER_FUNCTION_8821C 0x07DA 761 #define REG_NDP_SIG_8821C 0x07E0 762 #define REG_TXCMD_INFO_FOR_RSP_PKT_8821C 0x07E4 763 #define REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C 0x07E8 764 #define REG_WSEC_OPTION_8821C 0x07EC 765 #define REG_RTS_ADDRESS_0_8821C 0x07F0 766 #define REG_RTS_ADDRESS_0_1_8821C 0x07F4 767 #define REG_RTS_ADDRESS_1_8821C 0x07F8 768 #define REG_RTS_ADDRESS_1_1_8821C 0x07FC 769 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C 0x1700 770 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C 0x1704 771 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C 0x1708 772 #define REG_SDIO_TX_CTRL_8821C 0x10250000 773 #define REG_SDIO_HIMR_8821C 0x10250014 774 #define REG_SDIO_HISR_8821C 0x10250018 775 #define REG_SDIO_RX_REQ_LEN_8821C 0x1025001C 776 #define REG_SDIO_FREE_TXPG_SEQ_V1_8821C 0x1025001F 777 #define REG_SDIO_FREE_TXPG_8821C 0x10250020 778 #define REG_SDIO_FREE_TXPG2_8821C 0x10250024 779 #define REG_SDIO_OQT_FREE_TXPG_V1_8821C 0x10250028 780 #define REG_SDIO_HTSFR_INFO_8821C 0x10250030 781 #define REG_SDIO_HCPWM1_V2_8821C 0x10250038 782 #define REG_SDIO_HCPWM2_V2_8821C 0x1025003A 783 #define REG_SDIO_INDIRECT_REG_CFG_8821C 0x10250040 784 #define REG_SDIO_INDIRECT_REG_DATA_8821C 0x10250044 785 #define REG_SDIO_H2C_8821C 0x10250060 786 #define REG_SDIO_C2H_8821C 0x10250064 787 #define REG_SDIO_HRPWM1_8821C 0x10250080 788 #define REG_SDIO_HRPWM2_8821C 0x10250082 789 #define REG_SDIO_HPS_CLKR_8821C 0x10250084 790 #define REG_SDIO_BUS_CTRL_8821C 0x10250085 791 #define REG_SDIO_HSUS_CTRL_8821C 0x10250086 792 #define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088 793 #define REG_SDIO_CMD_CRC_8821C 0x1025008A 794 #define REG_SDIO_HSISR_8821C 0x10250090 795 #define REG_SDIO_ERR_RPT_8821C 0x102500C0 796 #define REG_SDIO_CMD_ERRCNT_8821C 0x102500C2 797 #define REG_SDIO_DATA_ERRCNT_8821C 0x102500C3 798 #define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4 799 #define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9 800 #define REG_SDIO_DATA_CRC_8821C 0x102500CA 801 #define REG_SDIO_DATA_REPLY_TIME_8821C 0x102500CB 802 803 #endif 804