1 /****************************************************************************** 2 * 3 * Copyright(c) 2018 - 2019 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 #ifndef __INC_HALMAC_REG_8812F_H 17 #define __INC_HALMAC_REG_8812F_H 18 19 #define REG_SYS_ISO_CTRL_8812F 0x0000 20 #define REG_SYS_FUNC_EN_8812F 0x0002 21 #define REG_SYS_PW_CTRL_8812F 0x0004 22 #define REG_SYS_CLK_CTRL_8812F 0x0008 23 #define REG_SYS_EEPROM_CTRL_8812F 0x000A 24 #define REG_EE_VPD_8812F 0x000C 25 #define REG_SYS_SWR_CTRL1_8812F 0x0010 26 #define REG_SYS_SWR_CTRL2_8812F 0x0014 27 #define REG_SYS_SWR_CTRL3_8812F 0x0018 28 #define REG_RSV_CTRL_8812F 0x001C 29 #define REG_RF_CTRL_8812F 0x001F 30 #define REG_AFE_LDO_CTRL_8812F 0x0020 31 #define REG_AFE_CTRL1_8812F 0x0024 32 #define REG_ANAPARSW_POW_MAC_8812F 0x0028 33 #define REG_ANAPARLDO_POW_MAC_8812F 0x0029 34 #define REG_ANAPAR_POW_MAC_8812F 0x002A 35 #define REG_ANAPAR_POW_XTAL_8812F 0x002B 36 #define REG_ANAPARLDO_MAC_8812F 0x002C 37 #define REG_EFUSE_CTRL_8812F 0x0030 38 #define REG_LDO_EFUSE_CTRL_8812F 0x0034 39 #define REG_PWR_OPTION_CTRL_8812F 0x0038 40 #define REG_CAL_TIMER_8812F 0x003C 41 #define REG_ACLK_MON_8812F 0x003E 42 #define REG_GPIO_MUXCFG_2_8812F 0x003F 43 #define REG_GPIO_MUXCFG_8812F 0x0040 44 #define REG_GPIO_PIN_CTRL_8812F 0x0044 45 #define REG_GPIO_INTM_8812F 0x0048 46 #define REG_LED_CFG_8812F 0x004C 47 #define REG_FSIMR_8812F 0x0050 48 #define REG_FSISR_8812F 0x0054 49 #define REG_HSIMR_8812F 0x0058 50 #define REG_HSISR_8812F 0x005C 51 #define REG_GPIO_EXT_CTRL_8812F 0x0060 52 #define REG_PAD_CTRL1_8812F 0x0064 53 #define REG_WL_BT_PWR_CTRL_8812F 0x0068 54 #define REG_SDM_DEBUG_8812F 0x006C 55 #define REG_SYS_SDIO_CTRL_8812F 0x0070 56 #define REG_HCI_OPT_CTRL_8812F 0x0074 57 #define REG_HCI_BG_CTRL_8812F 0x0078 58 #define REG_HCI_LDO_CTRL_8812F 0x007A 59 #define REG_LDO_SWR_CTRL_8812F 0x007C 60 #define REG_MCUFW_CTRL_8812F 0x0080 61 #define REG_MCU_TST_CFG_8812F 0x0084 62 #define REG_HMEBOX_E0_E1_8812F 0x0088 63 #define REG_HMEBOX_E2_E3_8812F 0x008C 64 #define REG_WLLPS_CTRL_8812F 0x0090 65 #define REG_GPIO_DEBOUNCE_CTRL_8812F 0x0098 66 #define REG_RPWM2_8812F 0x009C 67 #define REG_SYSON_FSM_MON_8812F 0x00A0 68 #define REG_PMC_DBG_CTRL1_8812F 0x00A8 69 #define REG_HIMR0_8812F 0x00B0 70 #define REG_HISR0_8812F 0x00B4 71 #define REG_HIMR1_8812F 0x00B8 72 #define REG_HISR1_8812F 0x00BC 73 #define REG_DBG_PORT_SEL_8812F 0x00C0 74 #define REG_PAD_CTRL2_8812F 0x00C4 75 #define REG_PMC_DBG_CTRL2_8812F 0x00CC 76 #define REG_BIST_CTRL_8812F 0x00D0 77 #define REG_BIST_RPT_8812F 0x00D4 78 #define REG_MEM_CTRL_8812F 0x00D8 79 #define REG_USB_SIE_INTF_8812F 0x00E0 80 #define REG_PCIE_MIO_INTF_8812F 0x00E4 81 #define REG_PCIE_MIO_INTD_8812F 0x00E8 82 #define REG_WLRF1_8812F 0x00EC 83 #define REG_SYS_CFG1_8812F 0x00F0 84 #define REG_SYS_STATUS1_8812F 0x00F4 85 #define REG_SYS_STATUS2_8812F 0x00F8 86 #define REG_SYS_CFG2_8812F 0x00FC 87 #define REG_SYS_CFG3_8812F 0x1000 88 #define REG_ANAPARSW_MAC_0_8812F 0x1010 89 #define REG_ANAPARSW_MAC_1_8812F 0x1014 90 #define REG_ANAPAR_MAC_0_8812F 0x1018 91 #define REG_ANAPAR_MAC_1_8812F 0x101C 92 #define REG_ANAPAR_MAC_2_8812F 0x1020 93 #define REG_ANAPAR_XTAL_0_8812F 0x1040 94 #define REG_ANAPAR_XTAL_1_8812F 0x1044 95 #define REG_ANAPAR_XTAL_2_8812F 0x1048 96 #define REG_ANAPAR_XTAL_3_8812F 0x104C 97 #define REG_ANAPAR_XTAL_AACK_0_8812F 0x1054 98 #define REG_ANAPAR_XTAL_AACK_1_8812F 0x1058 99 #define REG_ANAPAR_XTAL_MODE_DECODER_8812F 0x1064 100 #define REG_SYS_CFG5_8812F 0x1070 101 #define REG_REGU_32K_1_8812F 0x1078 102 #define REG_REGU_32K_2_8812F 0x107C 103 #define REG_CPU_DMEM_CON_8812F 0x1080 104 #define REG_BOOT_REASON_8812F 0x1088 105 #define REG_HIMR2_8812F 0x10B0 106 #define REG_HISR2_8812F 0x10B4 107 #define REG_HIMR3_8812F 0x10B8 108 #define REG_HISR3_8812F 0x10BC 109 #define REG_SW_MDIO_8812F 0x10C0 110 #define REG_H2C_PKT_READADDR_8812F 0x10D0 111 #define REG_H2C_PKT_WRITEADDR_8812F 0x10D4 112 #define REG_MEM_PWR_CRTL_8812F 0x10D8 113 #define REG_FW_DBG6_8812F 0x10F8 114 #define REG_FW_DBG7_8812F 0x10FC 115 #define REG_CR_8812F 0x0100 116 #define REG_PG_SIZE_8812F 0x0104 117 #define REG_PKT_BUFF_ACCESS_CTRL_8812F 0x0106 118 #define REG_TSF_CLK_STATE_8812F 0x0108 119 #define REG_TXDMA_PQ_MAP_8812F 0x010C 120 #define REG_TRXFF_BNDY_8812F 0x0114 121 #define REG_PTA_I2C_MBOX_8812F 0x0118 122 #define REG_RXFF_BNDY_8812F 0x011C 123 #define REG_FE1IMR_8812F 0x0120 124 #define REG_FE1ISR_8812F 0x0124 125 #define REG_CPWM_8812F 0x012C 126 #define REG_FWIMR_8812F 0x0130 127 #define REG_FWISR_8812F 0x0134 128 #define REG_FTIMR_8812F 0x0138 129 #define REG_FTISR_8812F 0x013C 130 #define REG_PKTBUF_DBG_CTRL_8812F 0x0140 131 #define REG_PKTBUF_DBG_DATA_L_8812F 0x0144 132 #define REG_PKTBUF_DBG_DATA_H_8812F 0x0148 133 #define REG_CPWM2_8812F 0x014C 134 #define REG_TC0_CTRL_8812F 0x0150 135 #define REG_TC1_CTRL_8812F 0x0154 136 #define REG_TC2_CTRL_8812F 0x0158 137 #define REG_TC3_CTRL_8812F 0x015C 138 #define REG_TC4_CTRL_8812F 0x0160 139 #define REG_TCUNIT_BASE_8812F 0x0164 140 #define REG_TC5_CTRL_8812F 0x0168 141 #define REG_TC6_CTRL_8812F 0x016C 142 #define REG_MBIST_DRF_FAIL_8812F 0x0170 143 #define REG_MBIST_START_PAUSE_8812F 0x0174 144 #define REG_MBIST_DONE_8812F 0x0178 145 #define REG_MBIST_READ_BIST_RPT_8812F 0x017C 146 #define REG_AES_DECRPT_DATA_8812F 0x0180 147 #define REG_AES_DECRPT_CFG_8812F 0x0184 148 #define REG_HIOE_CTRL_8812F 0x0188 149 #define REG_HIOE_CFG_FILE_8812F 0x018C 150 #define REG_TMETER_8812F 0x0190 151 #define REG_OSC_32K_CTRL_8812F 0x0194 152 #define REG_32K_CAL_REG1_8812F 0x0198 153 #define REG_C2HEVT_8812F 0x01A0 154 #define REG_C2HEVT_1_8812F 0x01A4 155 #define REG_C2HEVT_2_8812F 0x01A8 156 #define REG_C2HEVT_3_8812F 0x01AC 157 #define REG_SW_DEFINED_PAGE1_8812F 0x01B8 158 #define REG_SW_DEFINED_PAGE2_8812F 0x01BC 159 #define REG_MCUTST_I_8812F 0x01C0 160 #define REG_MCUTST_II_8812F 0x01C4 161 #define REG_FMETHR_8812F 0x01C8 162 #define REG_HMETFR_8812F 0x01CC 163 #define REG_HMEBOX0_8812F 0x01D0 164 #define REG_HMEBOX1_8812F 0x01D4 165 #define REG_HMEBOX2_8812F 0x01D8 166 #define REG_HMEBOX3_8812F 0x01DC 167 #define REG_BB_ACCESS_CTRL_8812F 0x01E8 168 #define REG_BB_ACCESS_DATA_8812F 0x01EC 169 #define REG_HMEBOX_E0_8812F 0x01F0 170 #define REG_HMEBOX_E1_8812F 0x01F4 171 #define REG_HMEBOX_E2_8812F 0x01F8 172 #define REG_HMEBOX_E3_8812F 0x01FC 173 #define REG_CR_EXT_8812F 0x1100 174 #define REG_FWFF_8812F 0x1114 175 #define REG_RXFF_PTR_V1_8812F 0x1118 176 #define REG_RXFF_WTR_V1_8812F 0x111C 177 #define REG_FE2IMR_8812F 0x1120 178 #define REG_FE2ISR_8812F 0x1124 179 #define REG_FE3IMR_8812F 0x1128 180 #define REG_FE3ISR_8812F 0x112C 181 #define REG_FE4IMR_8812F 0x1130 182 #define REG_FE4ISR_8812F 0x1134 183 #define REG_FT1IMR_8812F 0x1138 184 #define REG_FT1ISR_8812F 0x113C 185 #define REG_SPWR0_8812F 0x1140 186 #define REG_SPWR1_8812F 0x1144 187 #define REG_SPWR2_8812F 0x1148 188 #define REG_SPWR3_8812F 0x114C 189 #define REG_POWSEQ_8812F 0x1150 190 #define REG_TC7_CTRL_V1_8812F 0x1158 191 #define REG_TC8_CTRL_V1_8812F 0x115C 192 #define REG_RX_BCN_TBTT_ITVL0_8812F 0x1160 193 #define REG_RX_BCN_TBTT_ITVL1_8812F 0x1164 194 #define REG_IO_WRAP_ERR_FLAG_8812F 0x1170 195 #define REG_SPEED_SENSOR_8812F 0x1180 196 #define REG_SPEED_SENSOR1_8812F 0x1184 197 #define REG_SPEED_SENSOR2_8812F 0x1188 198 #define REG_SPEED_SENSOR3_8812F 0x118C 199 #define REG_SPEED_SENSOR4_8812F 0x1190 200 #define REG_SPEED_SENSOR5_8812F 0x1194 201 #define REG_COUNTER_CTRL_8812F 0x11C4 202 #define REG_COUNTER_THRESHOLD_8812F 0x11C8 203 #define REG_COUNTER_SET_8812F 0x11CC 204 #define REG_COUNTER_OVERFLOW_8812F 0x11D0 205 #define REG_TXDMA_LEN_THRESHOLD_8812F 0x11D4 206 #define REG_RXDMA_LEN_THRESHOLD_8812F 0x11D8 207 #define REG_PCIE_EXEC_TIME_THRESHOLD_8812F 0x11DC 208 #define REG_FT2IMR_8812F 0x11E0 209 #define REG_FT2ISR_8812F 0x11E4 210 #define REG_MSG2_8812F 0x11F0 211 #define REG_MSG3_8812F 0x11F4 212 #define REG_MSG4_8812F 0x11F8 213 #define REG_MSG5_8812F 0x11FC 214 #define REG_FIFOPAGE_CTRL_1_8812F 0x0200 215 #define REG_FIFOPAGE_CTRL_2_8812F 0x0204 216 #define REG_AUTO_LLT_V1_8812F 0x0208 217 #define REG_TXDMA_OFFSET_CHK_8812F 0x020C 218 #define REG_TXDMA_STATUS_8812F 0x0210 219 #define REG_TX_DMA_DBG_8812F 0x0214 220 #define REG_TQPNT1_8812F 0x0218 221 #define REG_TQPNT2_8812F 0x021C 222 #define REG_TQPNT3_8812F 0x0220 223 #define REG_TQPNT4_8812F 0x0224 224 #define REG_RQPN_CTRL_1_8812F 0x0228 225 #define REG_RQPN_CTRL_2_8812F 0x022C 226 #define REG_FIFOPAGE_INFO_1_8812F 0x0230 227 #define REG_FIFOPAGE_INFO_2_8812F 0x0234 228 #define REG_FIFOPAGE_INFO_3_8812F 0x0238 229 #define REG_FIFOPAGE_INFO_4_8812F 0x023C 230 #define REG_FIFOPAGE_INFO_5_8812F 0x0240 231 #define REG_H2C_HEAD_8812F 0x0244 232 #define REG_H2C_TAIL_8812F 0x0248 233 #define REG_H2C_READ_ADDR_8812F 0x024C 234 #define REG_H2C_WR_ADDR_8812F 0x0250 235 #define REG_H2C_INFO_8812F 0x0254 236 #define REG_PGSUB_CNT_8812F 0x026C 237 #define REG_PGSUB_H_8812F 0x0270 238 #define REG_PGSUB_N_8812F 0x0274 239 #define REG_PGSUB_L_8812F 0x0278 240 #define REG_PGSUB_E_8812F 0x027C 241 #define REG_RXDMA_AGG_PG_TH_8812F 0x0280 242 #define REG_RXPKT_NUM_8812F 0x0284 243 #define REG_RXDMA_STATUS_8812F 0x0288 244 #define REG_RXDMA_DPR_8812F 0x028C 245 #define REG_RXDMA_MODE_8812F 0x0290 246 #define REG_C2H_PKT_8812F 0x0294 247 #define REG_FWFF_C2H_8812F 0x0298 248 #define REG_FWFF_CTRL_8812F 0x029C 249 #define REG_FWFF_PKT_INFO_8812F 0x02A0 250 #define REG_RXPKTNUM_8812F 0x02B0 251 #define REG_RXPKTNUM_TH_8812F 0x02B4 252 #define REG_FW_MSG1_8812F 0x02E0 253 #define REG_FW_MSG2_8812F 0x02E4 254 #define REG_FW_MSG3_8812F 0x02E8 255 #define REG_FW_MSG4_8812F 0x02EC 256 #define REG_DDMA_CH0SA_8812F 0x1200 257 #define REG_DDMA_CH0DA_8812F 0x1204 258 #define REG_DDMA_CH0CTRL_8812F 0x1208 259 #define REG_DDMA_CH1SA_8812F 0x1210 260 #define REG_DDMA_CH1DA_8812F 0x1214 261 #define REG_DDMA_CH1CTRL_8812F 0x1218 262 #define REG_DDMA_CH2SA_8812F 0x1220 263 #define REG_DDMA_CH2DA_8812F 0x1224 264 #define REG_DDMA_CH2CTRL_8812F 0x1228 265 #define REG_DDMA_CH3SA_8812F 0x1230 266 #define REG_DDMA_CH3DA_8812F 0x1234 267 #define REG_DDMA_CH3CTRL_8812F 0x1238 268 #define REG_DDMA_CH4SA_8812F 0x1240 269 #define REG_DDMA_CH4DA_8812F 0x1244 270 #define REG_DDMA_CH4CTRL_8812F 0x1248 271 #define REG_DDMA_CH5SA_8812F 0x1250 272 #define REG_DDMA_CH5DA_8812F 0x1254 273 #define REG_DDMA_CH5CTRL_8812F 0x1258 274 #define REG_DDMA_INT_MSK_8812F 0x12E0 275 #define REG_DDMA_CHSTATUS_8812F 0x12E8 276 #define REG_DDMA_CHKSUM_8812F 0x12F0 277 #define REG_DDMA_MONITOR_8812F 0x12FC 278 #define REG_PCIE_CTRL_8812F 0x0300 279 #define REG_INT_MIG_8812F 0x0304 280 #define REG_BCNQ_TXBD_DESA_8812F 0x0308 281 #define REG_MGQ_TXBD_DESA_8812F 0x0310 282 #define REG_VOQ_TXBD_DESA_8812F 0x0318 283 #define REG_VIQ_TXBD_DESA_8812F 0x0320 284 #define REG_BEQ_TXBD_DESA_8812F 0x0328 285 #define REG_BKQ_TXBD_DESA_8812F 0x0330 286 #define REG_RXQ_RXBD_DESA_8812F 0x0338 287 #define REG_HI0Q_TXBD_DESA_8812F 0x0340 288 #define REG_HI1Q_TXBD_DESA_8812F 0x0348 289 #define REG_HI2Q_TXBD_DESA_8812F 0x0350 290 #define REG_HI3Q_TXBD_DESA_8812F 0x0358 291 #define REG_HI4Q_TXBD_DESA_8812F 0x0360 292 #define REG_HI5Q_TXBD_DESA_8812F 0x0368 293 #define REG_HI6Q_TXBD_DESA_8812F 0x0370 294 #define REG_HI7Q_TXBD_DESA_8812F 0x0378 295 #define REG_MGQ_TXBD_NUM_8812F 0x0380 296 #define REG_RX_RXBD_NUM_8812F 0x0382 297 #define REG_VOQ_TXBD_NUM_8812F 0x0384 298 #define REG_VIQ_TXBD_NUM_8812F 0x0386 299 #define REG_BEQ_TXBD_NUM_8812F 0x0388 300 #define REG_BKQ_TXBD_NUM_8812F 0x038A 301 #define REG_HI0Q_TXBD_NUM_8812F 0x038C 302 #define REG_HI1Q_TXBD_NUM_8812F 0x038E 303 #define REG_HI2Q_TXBD_NUM_8812F 0x0390 304 #define REG_HI3Q_TXBD_NUM_8812F 0x0392 305 #define REG_HI4Q_TXBD_NUM_8812F 0x0394 306 #define REG_HI5Q_TXBD_NUM_8812F 0x0396 307 #define REG_HI6Q_TXBD_NUM_8812F 0x0398 308 #define REG_HI7Q_TXBD_NUM_8812F 0x039A 309 #define REG_TSFTIMER_HCI_8812F 0x039C 310 #define REG_BD_RWPTR_CLR_8812F 0x039C 311 #define REG_VOQ_TXBD_IDX_8812F 0x03A0 312 #define REG_VIQ_TXBD_IDX_8812F 0x03A4 313 #define REG_BEQ_TXBD_IDX_8812F 0x03A8 314 #define REG_BKQ_TXBD_IDX_8812F 0x03AC 315 #define REG_MGQ_TXBD_IDX_8812F 0x03B0 316 #define REG_RXQ_RXBD_IDX_8812F 0x03B4 317 #define REG_HI0Q_TXBD_IDX_8812F 0x03B8 318 #define REG_HI1Q_TXBD_IDX_8812F 0x03BC 319 #define REG_HI2Q_TXBD_IDX_8812F 0x03C0 320 #define REG_HI3Q_TXBD_IDX_8812F 0x03C4 321 #define REG_HI4Q_TXBD_IDX_8812F 0x03C8 322 #define REG_HI5Q_TXBD_IDX_8812F 0x03CC 323 #define REG_HI6Q_TXBD_IDX_8812F 0x03D0 324 #define REG_HI7Q_TXBD_IDX_8812F 0x03D4 325 #define REG_DBG_SEL_V1_8812F 0x03D8 326 #define REG_PCIE_HRPWM1_V1_8812F 0x03D9 327 #define REG_PCIE_HCPWM1_V1_8812F 0x03DA 328 #define REG_PCIE_CTRL2_8812F 0x03DB 329 #define REG_PCIE_HRPWM2_V1_8812F 0x03DC 330 #define REG_PCIE_HCPWM2_V1_8812F 0x03DE 331 #define REG_PCIE_H2C_MSG_V1_8812F 0x03E0 332 #define REG_PCIE_C2H_MSG_V1_8812F 0x03E4 333 #define REG_DBI_WDATA_V1_8812F 0x03E8 334 #define REG_DBI_RDATA_V1_8812F 0x03EC 335 #define REG_DBI_FLAG_V1_8812F 0x03F0 336 #define REG_MDIO_V1_8812F 0x03F4 337 #define REG_PCIE_MIX_CFG_8812F 0x03F8 338 #define REG_HCI_MIX_CFG_8812F 0x03FC 339 #define REG_STC_INT_CS_8812F 0x1300 340 #define REG_ST_INT_CFG_8812F 0x1304 341 #define REG_H2CQ_TXBD_DESA_8812F 0x1320 342 #define REG_H2CQ_TXBD_NUM_8812F 0x1328 343 #define REG_H2CQ_TXBD_IDX_8812F 0x132C 344 #define REG_H2CQ_CSR_8812F 0x1330 345 #define REG_CHANGE_PCIE_SPEED_8812F 0x1350 346 #define REG_DEBUG_STATE1_8812F 0x1354 347 #define REG_DEBUG_STATE2_8812F 0x1358 348 #define REG_DEBUG_STATE3_8812F 0x135C 349 #define REG_CHNL_DMA_CFG_V1_8812F 0x137C 350 #define REG_PCIE_HISR0_V1_8812F 0x13B4 351 #define REG_PCIE_HISR1_V1_8812F 0x13BC 352 #define REG_PCIE_HISR2_V1_8812F 0x23B4 353 #define REG_PCIE_HISR3_V1_8812F 0x23BC 354 #define REG_Q0_INFO_8812F 0x0400 355 #define REG_Q1_INFO_8812F 0x0404 356 #define REG_Q2_INFO_8812F 0x0408 357 #define REG_Q3_INFO_8812F 0x040C 358 #define REG_MGQ_INFO_8812F 0x0410 359 #define REG_HIQ_INFO_8812F 0x0414 360 #define REG_BCNQ_INFO_8812F 0x0418 361 #define REG_TXPKT_EMPTY_8812F 0x041A 362 #define REG_CPU_MGQ_INFO_8812F 0x041C 363 #define REG_FWHW_TXQ_CTRL_8812F 0x0420 364 #define REG_DATAFB_SEL_8812F 0x0423 365 #define REG_BCNQ_BDNY_V1_8812F 0x0424 366 #define REG_LIFETIME_EN_8812F 0x0426 367 #define REG_SPEC_SIFS_8812F 0x0428 368 #define REG_RETRY_LIMIT_8812F 0x042A 369 #define REG_TXBF_CTRL_8812F 0x042C 370 #define REG_DARFRC_8812F 0x0430 371 #define REG_DARFRCH_8812F 0x0434 372 #define REG_RARFRC_8812F 0x0438 373 #define REG_RARFRCH_8812F 0x043C 374 #define REG_RRSR_8812F 0x0440 375 #define REG_ARFR0_8812F 0x0444 376 #define REG_ARFRH0_8812F 0x0448 377 #define REG_ARFR1_V1_8812F 0x044C 378 #define REG_ARFRH1_V1_8812F 0x0450 379 #define REG_CCK_CHECK_8812F 0x0454 380 #define REG_AMPDU_MAX_TIME_V1_8812F 0x0455 381 #define REG_BCNQ1_BDNY_V1_8812F 0x0456 382 #define REG_AMPDU_MAX_LENGTH_HT_8812F 0x0458 383 #define REG_ACQ_STOP_8812F 0x045C 384 #define REG_NDPA_RATE_8812F 0x045D 385 #define REG_TX_HANG_CTRL_8812F 0x045E 386 #define REG_NDPA_OPT_CTRL_8812F 0x045F 387 #define REG_AMPDU_MAX_LENGTH_VHT_8812F 0x0460 388 #define REG_RD_RESP_PKT_TH_8812F 0x0463 389 #define REG_CMDQ_INFO_8812F 0x0464 390 #define REG_Q4_INFO_8812F 0x0468 391 #define REG_Q5_INFO_8812F 0x046C 392 #define REG_Q6_INFO_8812F 0x0470 393 #define REG_Q7_INFO_8812F 0x0474 394 #define REG_WMAC_LBK_BUF_HD_V1_8812F 0x0478 395 #define REG_MGQ_BDNY_V1_8812F 0x047A 396 #define REG_TXRPT_CTRL_8812F 0x047C 397 #define REG_INIRTS_RATE_SEL_8812F 0x0480 398 #define REG_BASIC_CFEND_RATE_8812F 0x0481 399 #define REG_STBC_CFEND_RATE_8812F 0x0482 400 #define REG_DATA_SC_8812F 0x0483 401 #define REG_MACID_SLEEP3_8812F 0x0484 402 #define REG_MACID_SLEEP1_8812F 0x0488 403 #define REG_ARFR2_V1_8812F 0x048C 404 #define REG_ARFRH2_V1_8812F 0x0490 405 #define REG_ARFR3_V1_8812F 0x0494 406 #define REG_ARFRH3_V1_8812F 0x0498 407 #define REG_ARFR4_8812F 0x049C 408 #define REG_ARFRH4_8812F 0x04A0 409 #define REG_ARFR5_8812F 0x04A4 410 #define REG_ARFRH5_8812F 0x04A8 411 #define REG_TXRPT_START_OFFSET_8812F 0x04AC 412 #define REG_RRSR_CTS_8812F 0x04B0 413 #define REG_POWER_STAGE1_8812F 0x04B4 414 #define REG_POWER_STAGE2_8812F 0x04B8 415 #define REG_SW_AMPDU_BURST_MODE_CTRL_8812F 0x04BC 416 #define REG_PKT_LIFE_TIME_8812F 0x04C0 417 #define REG_STBC_SETTING_8812F 0x04C4 418 #define REG_STBC_SETTING2_8812F 0x04C5 419 #define REG_QUEUE_CTRL_8812F 0x04C6 420 #define REG_SINGLE_AMPDU_CTRL_8812F 0x04C7 421 #define REG_PROT_MODE_CTRL_8812F 0x04C8 422 #define REG_BAR_MODE_CTRL_8812F 0x04CC 423 #define REG_RA_TRY_RATE_AGG_LMT_8812F 0x04CF 424 #define REG_MACID_SLEEP2_8812F 0x04D0 425 #define REG_MACID_SLEEP_8812F 0x04D4 426 #define REG_HW_SEQ0_8812F 0x04D8 427 #define REG_HW_SEQ1_8812F 0x04DA 428 #define REG_HW_SEQ2_8812F 0x04DC 429 #define REG_HW_SEQ3_8812F 0x04DE 430 #define REG_NULL_PKT_STATUS_V1_8812F 0x04E0 431 #define REG_PTCL_ERR_STATUS_8812F 0x04E2 432 #define REG_NULL_PKT_STATUS_EXTEND_8812F 0x04E3 433 #define REG_HQMGQ_DROP_8812F 0x04E4 434 #define REG_PRECNT_CTRL_8812F 0x04E5 435 #define REG_BT_POLLUTE_PKT_CNT_8812F 0x04E8 436 #define REG_PTCL_DBG_8812F 0x04EC 437 #define REG_CPUMGQ_TIMER_CTRL2_8812F 0x04F4 438 #define REG_DUMMY_PAGE4_V1_8812F 0x04FC 439 #define REG_MOREDATA_8812F 0x04FE 440 #define REG_Q0_Q1_INFO_8812F 0x1400 441 #define REG_Q2_Q3_INFO_8812F 0x1404 442 #define REG_Q4_Q5_INFO_8812F 0x1408 443 #define REG_Q6_Q7_INFO_8812F 0x140C 444 #define REG_MGQ_HIQ_INFO_8812F 0x1410 445 #define REG_CMDQ_BCNQ_INFO_8812F 0x1414 446 #define REG_LOOPBACK_OPTION_8812F 0x1420 447 #define REG_AESIV_SETTING_8812F 0x1424 448 #define REG_BF0_TIME_SETTING_8812F 0x1428 449 #define REG_BF1_TIME_SETTING_8812F 0x142C 450 #define REG_BF_TIMEOUT_EN_8812F 0x1430 451 #define REG_MACID_RELEASE0_8812F 0x1434 452 #define REG_MACID_RELEASE1_8812F 0x1438 453 #define REG_MACID_RELEASE2_8812F 0x143C 454 #define REG_MACID_RELEASE3_8812F 0x1440 455 #define REG_MACID_RELEASE_SETTING_8812F 0x1444 456 #define REG_FAST_EDCA_VOVI_SETTING_8812F 0x1448 457 #define REG_FAST_EDCA_BEBK_SETTING_8812F 0x144C 458 #define REG_MACID_DROP0_8812F 0x1450 459 #define REG_MACID_DROP1_8812F 0x1454 460 #define REG_MACID_DROP2_8812F 0x1458 461 #define REG_MACID_DROP3_8812F 0x145C 462 #define REG_R_MACID_RELEASE_SUCCESS_0_8812F 0x1460 463 #define REG_R_MACID_RELEASE_SUCCESS_1_8812F 0x1464 464 #define REG_R_MACID_RELEASE_SUCCESS_2_8812F 0x1468 465 #define REG_R_MACID_RELEASE_SUCCESS_3_8812F 0x146C 466 #define REG_MGQ_FIFO_WRITE_POINTER_8812F 0x1470 467 #define REG_MGQ_FIFO_READ_POINTER_8812F 0x1472 468 #define REG_MGQ_FIFO_ENABLE_8812F 0x1472 469 #define REG_MGQ_FIFO_RELEASE_INT_MASK_8812F 0x1474 470 #define REG_MGQ_FIFO_RELEASE_INT_FLAG_8812F 0x1476 471 #define REG_MGQ_FIFO_VALID_MAP_8812F 0x1478 472 #define REG_MGQ_FIFO_LIFETIME_8812F 0x147A 473 #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8812F 0x147C 474 #define REG_SHCUT_SETTING_8812F 0x1480 475 #define REG_SHCUT_LLC_ETH_TYPE0_8812F 0x1484 476 #define REG_SHCUT_LLC_ETH_TYPE1_8812F 0x1488 477 #define REG_SHCUT_LLC_OUI0_8812F 0x148C 478 #define REG_SHCUT_LLC_OUI1_8812F 0x1490 479 #define REG_SHCUT_LLC_OUI2_8812F 0x1494 480 #define REG_MU_TX_CTL_8812F 0x14C0 481 #define REG_MU_STA_GID_VLD_8812F 0x14C4 482 #define REG_MU_STA_USER_POS_INFO_8812F 0x14C8 483 #define REG_MU_STA_USER_POS_INFO_H_8812F 0x14CC 484 #define REG_CHNL_INFO_CTRL_8812F 0x14D0 485 #define REG_CHNL_IDLE_TIME_8812F 0x14D4 486 #define REG_CHNL_BUSY_TIME_8812F 0x14D8 487 #define REG_MU_TRX_DBG_CNT_V1_8812F 0x14DC 488 #define REG_SU_DURATION_8812F 0x14F0 489 #define REG_MU_DURATION_8812F 0x14F2 490 #define REG_HW_NDPA_RTY_LIMIT_8812F 0x14F4 491 #define REG_EDCA_VO_PARAM_8812F 0x0500 492 #define REG_EDCA_VI_PARAM_8812F 0x0504 493 #define REG_EDCA_BE_PARAM_8812F 0x0508 494 #define REG_EDCA_BK_PARAM_8812F 0x050C 495 #define REG_BCNTCFG_8812F 0x0510 496 #define REG_PIFS_8812F 0x0512 497 #define REG_RDG_PIFS_8812F 0x0513 498 #define REG_SIFS_8812F 0x0514 499 #define REG_TSFTR_SYN_OFFSET_8812F 0x0518 500 #define REG_AGGR_BREAK_TIME_8812F 0x051A 501 #define REG_SLOT_8812F 0x051B 502 #define REG_NOA_ON_ERLY_TIME_8812F 0x051C 503 #define REG_NOA_OFF_ERLY_TIME_8812F 0x051D 504 #define REG_TX_PTCL_CTRL_8812F 0x0520 505 #define REG_TXPAUSE_8812F 0x0522 506 #define REG_DIS_TXREQ_CLR_8812F 0x0523 507 #define REG_RD_CTRL_8812F 0x0524 508 #define REG_MBSSID_CTRL_8812F 0x0526 509 #define REG_P2PPS_CTRL_8812F 0x0527 510 #define REG_PKT_LIFETIME_CTRL_8812F 0x0528 511 #define REG_P2PPS_SPEC_STATE_8812F 0x052B 512 #define REG_TXOP_LIMIT_CTRL_8812F 0x052C 513 #define REG_BAR_TX_CTRL_8812F 0x0530 514 #define REG_P2PON_DIS_TXTIME_8812F 0x0531 515 #define REG_CCA_TXEN_CNT_8812F 0x0534 516 #define REG_MAX_INTER_COLLISION_8812F 0x0538 517 #define REG_MAX_INTER_COLLISION_CNT_8812F 0x053C 518 #define REG_TBTT_PROHIBIT_8812F 0x0540 519 #define REG_P2PPS_STATE_8812F 0x0543 520 #define REG_RD_NAV_NXT_8812F 0x0544 521 #define REG_NAV_PROT_LEN_8812F 0x0546 522 #define REG_FTM_PTT_8812F 0x0548 523 #define REG_FTM_TSF_8812F 0x054C 524 #define REG_BCN_CTRL_8812F 0x0550 525 #define REG_BCN_CTRL_CLINT0_8812F 0x0551 526 #define REG_MBID_NUM_8812F 0x0552 527 #define REG_DUAL_TSF_RST_8812F 0x0553 528 #define REG_MBSSID_BCN_SPACE_8812F 0x0554 529 #define REG_DRVERLYINT_8812F 0x0558 530 #define REG_BCNDMATIM_8812F 0x0559 531 #define REG_ATIMWND_8812F 0x055A 532 #define REG_USTIME_TSF_8812F 0x055C 533 #define REG_BCN_MAX_ERR_8812F 0x055D 534 #define REG_RXTSF_OFFSET_CCK_8812F 0x055E 535 #define REG_RXTSF_OFFSET_OFDM_8812F 0x055F 536 #define REG_TSFTR_8812F 0x0560 537 #define REG_TSFTR_1_8812F 0x0564 538 #define REG_FREERUN_CNT_8812F 0x0568 539 #define REG_FREERUN_CNT_1_8812F 0x056C 540 #define REG_ATIMWND1_V1_8812F 0x0570 541 #define REG_TBTT_PROHIBIT_INFRA_8812F 0x0571 542 #define REG_CTWND_8812F 0x0572 543 #define REG_BCNIVLCUNT_8812F 0x0573 544 #define REG_BCNDROPCTRL_8812F 0x0574 545 #define REG_HGQ_TIMEOUT_PERIOD_8812F 0x0575 546 #define REG_TXCMD_TIMEOUT_PERIOD_8812F 0x0576 547 #define REG_MISC_CTRL_8812F 0x0577 548 #define REG_BCN_CTRL_CLINT1_8812F 0x0578 549 #define REG_BCN_CTRL_CLINT2_8812F 0x0579 550 #define REG_BCN_CTRL_CLINT3_8812F 0x057A 551 #define REG_EXTEND_CTRL_8812F 0x057B 552 #define REG_P2PPS1_SPEC_STATE_8812F 0x057C 553 #define REG_P2PPS1_STATE_8812F 0x057D 554 #define REG_P2PPS2_SPEC_STATE_8812F 0x057E 555 #define REG_P2PPS2_STATE_8812F 0x057F 556 #define REG_PS_TIMER0_8812F 0x0580 557 #define REG_PS_TIMER1_8812F 0x0584 558 #define REG_PS_TIMER2_8812F 0x0588 559 #define REG_TBTT_CTN_AREA_8812F 0x058C 560 #define REG_FORCE_BCN_IFS_8812F 0x058E 561 #define REG_TXOP_MIN_8812F 0x0590 562 #define REG_PRE_BKF_TIME_8812F 0x0592 563 #define REG_CROSS_TXOP_CTRL_8812F 0x0593 564 #define REG_RX_TBTT_SHIFT_V1_8812F 0x0598 565 #define REG_ATIMWND2_8812F 0x05A0 566 #define REG_ATIMWND3_8812F 0x05A1 567 #define REG_ATIMWND4_8812F 0x05A2 568 #define REG_ATIMWND5_8812F 0x05A3 569 #define REG_ATIMWND6_8812F 0x05A4 570 #define REG_ATIMWND7_8812F 0x05A5 571 #define REG_ATIMUGT_8812F 0x05A6 572 #define REG_HIQ_NO_LMT_EN_8812F 0x05A7 573 #define REG_DTIM_COUNTER_ROOT_8812F 0x05A8 574 #define REG_DTIM_COUNTER_VAP1_8812F 0x05A9 575 #define REG_DTIM_COUNTER_VAP2_8812F 0x05AA 576 #define REG_DTIM_COUNTER_VAP3_8812F 0x05AB 577 #define REG_DTIM_COUNTER_VAP4_8812F 0x05AC 578 #define REG_DTIM_COUNTER_VAP5_8812F 0x05AD 579 #define REG_DTIM_COUNTER_VAP6_8812F 0x05AE 580 #define REG_DTIM_COUNTER_VAP7_8812F 0x05AF 581 #define REG_DIS_ATIM_8812F 0x05B0 582 #define REG_EARLY_128US_8812F 0x05B1 583 #define REG_P2PPS1_CTRL_8812F 0x05B2 584 #define REG_P2PPS2_CTRL_8812F 0x05B3 585 #define REG_TIMER0_SRC_SEL_8812F 0x05B4 586 #define REG_NOA_UNIT_SEL_8812F 0x05B5 587 #define REG_P2POFF_DIS_TXTIME_8812F 0x05B7 588 #define REG_MBSSID_BCN_SPACE2_8812F 0x05B8 589 #define REG_MBSSID_BCN_SPACE3_8812F 0x05BC 590 #define REG_ACMHWCTRL_8812F 0x05C0 591 #define REG_ACMRSTCTRL_8812F 0x05C1 592 #define REG_ACMAVG_8812F 0x05C2 593 #define REG_VO_ADMTIME_8812F 0x05C4 594 #define REG_VI_ADMTIME_8812F 0x05C6 595 #define REG_BE_ADMTIME_8812F 0x05C8 596 #define REG_MAC_HEADER_NAV_OFFSET_8812F 0x05CA 597 #define REG_DIS_NDPA_NAV_CHECK_8812F 0x05CB 598 #define REG_EDCA_RANDOM_GEN_8812F 0x05CC 599 #define REG_TXCMD_NOA_SEL_8812F 0x05CF 600 #define REG_32K_CLK_SEL_8812F 0x05D0 601 #define REG_EARLYINT_ADJUST_8812F 0x05D4 602 #define REG_BCNERR_CNT_8812F 0x05D8 603 #define REG_BCNERR_CNT_2_8812F 0x05DC 604 #define REG_NOA_PARAM_8812F 0x05E0 605 #define REG_NOA_PARAM_1_8812F 0x05E4 606 #define REG_NOA_PARAM_2_8812F 0x05E8 607 #define REG_NOA_PARAM_3_8812F 0x05EC 608 #define REG_P2P_RST_8812F 0x05F0 609 #define REG_SCHEDULER_RST_8812F 0x05F1 610 #define REG_SCH_DBG_VALUE_8812F 0x05F4 611 #define REG_SCH_TXCMD_8812F 0x05F8 612 #define REG_PAGE5_DUMMY_8812F 0x05FC 613 #define REG_CPUMGQ_TX_TIMER_8812F 0x1500 614 #define REG_PS_TIMER_A_8812F 0x1504 615 #define REG_PS_TIMER_B_8812F 0x1508 616 #define REG_PS_TIMER_C_8812F 0x150C 617 #define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8812F 0x1510 618 #define REG_CPUMGQ_TX_TIMER_EARLY_8812F 0x1514 619 #define REG_PS_TIMER_A_EARLY_8812F 0x1515 620 #define REG_PS_TIMER_B_EARLY_8812F 0x1516 621 #define REG_PS_TIMER_C_EARLY_8812F 0x1517 622 #define REG_CPUMGQ_PARAMETER_8812F 0x1518 623 #define REG_TSF_SYNC_ADJ_8812F 0x1520 624 #define REG_TSF_ADJ_VLAUE_8812F 0x1524 625 #define REG_TSF_ADJ_VLAUE_2_8812F 0x1528 626 #define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8812F 0x156C 627 #define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8812F 0x1570 628 #define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8812F 0x1574 629 #define REG_WMAC_CR_8812F 0x0600 630 #define REG_WMAC_FWPKT_CR_8812F 0x0601 631 #define REG_FW_STS_FILTER_8812F 0x0602 632 #define REG_TCR_8812F 0x0604 633 #define REG_RCR_8812F 0x0608 634 #define REG_RX_PKT_LIMIT_8812F 0x060C 635 #define REG_RX_DLK_TIME_8812F 0x060D 636 #define REG_RX_DRVINFO_SZ_8812F 0x060F 637 #define REG_MACID_8812F 0x0610 638 #define REG_MACID_H_8812F 0x0614 639 #define REG_BSSID_8812F 0x0618 640 #define REG_BSSID_H_8812F 0x061C 641 #define REG_MAR_8812F 0x0620 642 #define REG_MAR_H_8812F 0x0624 643 #define REG_MBIDCAMCFG_1_8812F 0x0628 644 #define REG_MBIDCAMCFG_2_8812F 0x062C 645 #define REG_WMAC_TCR_TSFT_OFS_8812F 0x0630 646 #define REG_UDF_THSD_8812F 0x0632 647 #define REG_ZLD_NUM_8812F 0x0633 648 #define REG_STMP_THSD_8812F 0x0634 649 #define REG_WMAC_TXTIMEOUT_8812F 0x0635 650 #define REG_USTIME_EDCA_8812F 0x0638 651 #define REG_ACKTO_CCK_8812F 0x0639 652 #define REG_MAC_SPEC_SIFS_8812F 0x063A 653 #define REG_RESP_SIFS_CCK_8812F 0x063C 654 #define REG_RESP_SIFS_OFDM_8812F 0x063E 655 #define REG_ACKTO_8812F 0x0640 656 #define REG_CTS2TO_8812F 0x0641 657 #define REG_EIFS_8812F 0x0642 658 #define REG_RPFM_MAP0_8812F 0x0644 659 #define REG_RPFM_MAP1_V1_8812F 0x0646 660 #define REG_RPFM_CAM_CMD_8812F 0x0648 661 #define REG_RPFM_CAM_RWD_8812F 0x064C 662 #define REG_NAV_CTRL_8812F 0x0650 663 #define REG_BACAMCMD_8812F 0x0654 664 #define REG_BACAMCONTENT_8812F 0x0658 665 #define REG_BACAMCONTENT_H_8812F 0x065C 666 #define REG_LBDLY_8812F 0x0660 667 #define REG_WMAC_BACAM_RPMEN_8812F 0x0661 668 #define REG_TX_RX_8812F 0x0662 669 #define REG_WMAC_BITMAP_CTL_8812F 0x0663 670 #define REG_RXERR_RPT_8812F 0x0664 671 #define REG_WMAC_TRXPTCL_CTL_8812F 0x0668 672 #define REG_WMAC_TRXPTCL_CTL_H_8812F 0x066C 673 #define REG_CAMCMD_8812F 0x0670 674 #define REG_CAMWRITE_8812F 0x0674 675 #define REG_CAMREAD_8812F 0x0678 676 #define REG_CAMDBG_8812F 0x067C 677 #define REG_SECCFG_8812F 0x0680 678 #define REG_RXFILTER_CATEGORY_1_8812F 0x0682 679 #define REG_RXFILTER_ACTION_1_8812F 0x0683 680 #define REG_RXFILTER_CATEGORY_2_8812F 0x0684 681 #define REG_RXFILTER_ACTION_2_8812F 0x0685 682 #define REG_RXFILTER_CATEGORY_3_8812F 0x0686 683 #define REG_RXFILTER_ACTION_3_8812F 0x0687 684 #define REG_RXFLTMAP3_8812F 0x0688 685 #define REG_RXFLTMAP4_8812F 0x068A 686 #define REG_RXFLTMAP5_8812F 0x068C 687 #define REG_RXFLTMAP6_8812F 0x068E 688 #define REG_WOW_CTRL_8812F 0x0690 689 #define REG_NAN_RX_TSF_FILTER_8812F 0x0691 690 #define REG_PS_RX_INFO_8812F 0x0692 691 #define REG_WMMPS_UAPSD_TID_8812F 0x0693 692 #define REG_LPNAV_CTRL_8812F 0x0694 693 #define REG_WKFMCAM_CMD_8812F 0x0698 694 #define REG_WKFMCAM_RWD_8812F 0x069C 695 #define REG_RXFLTMAP0_8812F 0x06A0 696 #define REG_RXFLTMAP1_8812F 0x06A2 697 #define REG_RXFLTMAP2_8812F 0x06A4 698 #define REG_BCN_PSR_RPT_8812F 0x06A8 699 #define REG_FLC_RPC_8812F 0x06AC 700 #define REG_FLC_RPCT_8812F 0x06AD 701 #define REG_FLC_PTS_8812F 0x06AE 702 #define REG_FLC_TRPC_8812F 0x06AF 703 #define REG_RXPKTMON_CTRL_8812F 0x06B0 704 #define REG_STATE_MON_8812F 0x06B4 705 #define REG_ERROR_MON_8812F 0x06B8 706 #define REG_SEARCH_MACID_8812F 0x06BC 707 #define REG_BT_COEX_TABLE_8812F 0x06C0 708 #define REG_BT_COEX_TABLE2_8812F 0x06C4 709 #define REG_BT_COEX_BREAK_TABLE_8812F 0x06C8 710 #define REG_BT_COEX_TABLE_H_8812F 0x06CC 711 #define REG_RXCMD_0_8812F 0x06D0 712 #define REG_RXCMD_1_8812F 0x06D4 713 #define REG_WMAC_RESP_TXINFO_8812F 0x06D8 714 #define REG_BBPSF_CTRL_8812F 0x06DC 715 #define REG_P2P_RX_BCN_NOA_8812F 0x06E0 716 #define REG_ASSOCIATED_BFMER0_INFO_8812F 0x06E4 717 #define REG_ASSOCIATED_BFMER0_INFO_H_8812F 0x06E8 718 #define REG_ASSOCIATED_BFMER1_INFO_8812F 0x06EC 719 #define REG_ASSOCIATED_BFMER1_INFO_H_8812F 0x06F0 720 #define REG_TX_CSI_RPT_PARAM_BW20_8812F 0x06F4 721 #define REG_TX_CSI_RPT_PARAM_BW40_8812F 0x06F8 722 #define REG_CSI_PTR_8812F 0x06FC 723 #define REG_BCN_PSR_RPT2_8812F 0x1600 724 #define REG_BCN_PSR_RPT3_8812F 0x1604 725 #define REG_BCN_PSR_RPT4_8812F 0x1608 726 #define REG_A1_ADDR_MASK_8812F 0x160C 727 #define REG_RXPSF_CTRL_8812F 0x1610 728 #define REG_RXPSF_TYPE_CTRL_8812F 0x1614 729 #define REG_CAM_ACCESS_CTRL_8812F 0x1618 730 #define REG_HT_SND_REF_RATE_8812F 0x161C 731 #define REG_MACID2_8812F 0x1620 732 #define REG_MACID2_H_8812F 0x1624 733 #define REG_BSSID2_8812F 0x1628 734 #define REG_BSSID2_H_8812F 0x162C 735 #define REG_MACID3_8812F 0x1630 736 #define REG_MACID3_H_8812F 0x1634 737 #define REG_BSSID3_8812F 0x1638 738 #define REG_BSSID3_H_8812F 0x163C 739 #define REG_MACID4_8812F 0x1640 740 #define REG_MACID4_H_8812F 0x1644 741 #define REG_BSSID4_8812F 0x1648 742 #define REG_BSSID4_H_8812F 0x164C 743 #define REG_NOA_REPORT_8812F 0x1650 744 #define REG_NOA_REPORT_1_8812F 0x1654 745 #define REG_NOA_REPORT_2_8812F 0x1658 746 #define REG_NOA_REPORT_3_8812F 0x165C 747 #define REG_PWRBIT_SETTING_8812F 0x1660 748 #define REG_GENERAL_OPTION_8812F 0x1664 749 #define REG_RXAI_CTRL_8812F 0x1668 750 #define REG_CSI_RRSR_8812F 0x1678 751 #define REG_MU_BF_OPTION_8812F 0x167C 752 #define REG_WMAC_PAUSE_BB_CLR_TH_8812F 0x167D 753 #define REG__WMAC_MULBK_BUF_8812F 0x167E 754 #define REG_WMAC_MU_OPTION_8812F 0x167F 755 #define REG_WMAC_MU_BF_CTL_8812F 0x1680 756 #define REG_WMAC_MU_BFRPT_PARA_8812F 0x1682 757 #define REG_WMAC_ASSOCIATED_MU_BFMEE2_8812F 0x1684 758 #define REG_WMAC_ASSOCIATED_MU_BFMEE3_8812F 0x1686 759 #define REG_WMAC_ASSOCIATED_MU_BFMEE4_8812F 0x1688 760 #define REG_WMAC_ASSOCIATED_MU_BFMEE5_8812F 0x168A 761 #define REG_WMAC_ASSOCIATED_MU_BFMEE6_8812F 0x168C 762 #define REG_WMAC_ASSOCIATED_MU_BFMEE7_8812F 0x168E 763 #define REG_WMAC_BB_STOP_RX_COUNTER_8812F 0x1690 764 #define REG_WMAC_PLCP_MONITOR_8812F 0x1694 765 #define REG_WMAC_PLCP_MONITOR_MUTX_8812F 0x1698 766 #define REG_WMAC_CSIDMA_CFG_8812F 0x169C 767 #define REG_TRANSMIT_ADDRSS_0_8812F 0x16A0 768 #define REG_TRANSMIT_ADDRSS_0_H_8812F 0x16A4 769 #define REG_TRANSMIT_ADDRSS_1_8812F 0x16A8 770 #define REG_TRANSMIT_ADDRSS_1_H_8812F 0x16AC 771 #define REG_TRANSMIT_ADDRSS_2_8812F 0x16B0 772 #define REG_TRANSMIT_ADDRSS_2_H_8812F 0x16B4 773 #define REG_TRANSMIT_ADDRSS_3_8812F 0x16B8 774 #define REG_TRANSMIT_ADDRSS_3_H_8812F 0x16BC 775 #define REG_TRANSMIT_ADDRSS_4_8812F 0x16C0 776 #define REG_TRANSMIT_ADDRSS_4_H_8812F 0x16C4 777 #define REG_SND_AID12_8812F 0x16D0 778 #define REG_SND_PKT_INFO_8812F 0x16D2 779 #define REG_MACID1_8812F 0x0700 780 #define REG_MACID1_1_8812F 0x0704 781 #define REG_BSSID1_8812F 0x0708 782 #define REG_BSSID1_1_8812F 0x070C 783 #define REG_BCN_PSR_RPT1_8812F 0x0710 784 #define REG_ASSOCIATED_BFMEE_SEL_8812F 0x0714 785 #define REG_SND_PTCL_CTRL_8812F 0x0718 786 #define REG_RX_CSI_RPT_INFO_8812F 0x071C 787 #define REG_NS_ARP_CTRL_8812F 0x0720 788 #define REG_NS_ARP_INFO_8812F 0x0724 789 #define REG_BEAMFORMING_INFO_NSARP_V1_8812F 0x0728 790 #define REG_BEAMFORMING_INFO_NSARP_8812F 0x072C 791 #define REG_IPV6_8812F 0x0730 792 #define REG_IPV6_1_8812F 0x0734 793 #define REG_IPV6_2_8812F 0x0738 794 #define REG_IPV6_3_8812F 0x073C 795 #define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8812F 0x0750 796 #define REG_WMAC_SWAES_DIO_B63_B32_8812F 0x0754 797 #define REG_WMAC_SWAES_DIO_B95_B64_8812F 0x0758 798 #define REG_WMAC_SWAES_DIO_B127_B96_8812F 0x075C 799 #define REG_WMAC_SWAES_CFG_8812F 0x0760 800 #define REG_BT_COEX_V2_8812F 0x0762 801 #define REG_BT_COEX_8812F 0x0764 802 #define REG_WLAN_ACT_MASK_CTRL_8812F 0x0768 803 #define REG_WLAN_ACT_MASK_CTRL_1_8812F 0x076C 804 #define REG_BT_COEX_ENHANCED_INTR_CTRL_8812F 0x076E 805 #define REG_BT_ACT_STATISTICS_8812F 0x0770 806 #define REG_BT_ACT_STATISTICS_1_8812F 0x0774 807 #define REG_BT_STATISTICS_CONTROL_REGISTER_8812F 0x0778 808 #define REG_BT_STATUS_REPORT_REGISTER_8812F 0x077C 809 #define REG_BT_INTERRUPT_CONTROL_REGISTER_8812F 0x0780 810 #define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8812F 0x0784 811 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8812F 0x0785 812 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8812F 0x0788 813 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8812F 0x078C 814 #define REG_BT_INTERRUPT_STATUS_REGISTER_8812F 0x078F 815 #define REG_BT_TDMA_TIME_REGISTER_8812F 0x0790 816 #define REG_BT_ACT_REGISTER_8812F 0x0794 817 #define REG_OBFF_CTRL_BASIC_8812F 0x0798 818 #define REG_OBFF_CTRL2_TIMER_8812F 0x079C 819 #define REG_LTR_CTRL_BASIC_8812F 0x07A0 820 #define REG_LTR_CTRL2_TIMER_THRESHOLD_8812F 0x07A4 821 #define REG_LTR_IDLE_LATENCY_V1_8812F 0x07A8 822 #define REG_LTR_ACTIVE_LATENCY_V1_8812F 0x07AC 823 #define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8812F 0x07B0 824 #define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8812F 0x07B4 825 #define REG_WMAC_PKTCNT_RWD_8812F 0x07B8 826 #define REG_WMAC_PKTCNT_CTRL_8812F 0x07BC 827 #define REG_IQ_DUMP_8812F 0x07C0 828 #define REG_IQ_DUMP_1_8812F 0x07C4 829 #define REG_IQ_DUMP_2_8812F 0x07C8 830 #define REG_WMAC_FTM_CTL_8812F 0x07CC 831 #define REG_WMAC_IQ_MDPK_FUNC_8812F 0x07CE 832 #define REG_WMAC_OPTION_FUNCTION_8812F 0x07D0 833 #define REG_WMAC_OPTION_FUNCTION_1_8812F 0x07D4 834 #define REG_WMAC_OPTION_FUNCTION_2_8812F 0x07D8 835 #define REG_RX_FILTER_FUNCTION_8812F 0x07DA 836 #define REG_NDP_SIG_8812F 0x07E0 837 #define REG_TXCMD_INFO_FOR_RSP_PKT_8812F 0x07E4 838 #define REG_TXCMD_INFO_FOR_RSP_PKT_1_8812F 0x07E8 839 #define REG_WSEC_OPTION_8812F 0x07EC 840 #define REG_RTS_ADDRESS_0_8812F 0x07F0 841 #define REG_RTS_ADDRESS_0_1_8812F 0x07F4 842 #define REG_RTS_ADDRESS_1_8812F 0x07F8 843 #define REG_RTS_ADDRESS_1_1_8812F 0x07FC 844 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8812F 0x1700 845 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8812F 0x1704 846 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8812F 0x1708 847 #define REG_SDIO_TX_CTRL_8812F 0x10250000 848 #define REG_SDIO_CMD11_VOL_SWITCH_8812F 0x10250004 849 #define REG_SDIO_CTRL_8812F 0x10250005 850 #define REG_SDIO_DRIVING_8812F 0x10250006 851 #define REG_SDIO_MONITOR_8812F 0x10250008 852 #define REG_SDIO_MONITOR_2_8812F 0x1025000C 853 #define REG_SDIO_CTRL_2_8812F 0x10250010 854 #define REG_SDIO_HIMR_8812F 0x10250014 855 #define REG_SDIO_HISR_8812F 0x10250018 856 #define REG_SDIO_RX_REQ_LEN_8812F 0x1025001C 857 #define REG_SDIO_FREE_TXPG_SEQ_V1_8812F 0x1025001F 858 #define REG_SDIO_FREE_TXPG_8812F 0x10250020 859 #define REG_SDIO_FREE_TXPG2_8812F 0x10250024 860 #define REG_SDIO_OQT_FREE_TXPG_V1_8812F 0x10250028 861 #define REG_SDIO_TXPKT_EMPTY_8812F 0x1025002C 862 #define REG_SDIO_HTSFR_INFO_8812F 0x10250030 863 #define REG_SDIO_HCPWM1_V2_8812F 0x10250038 864 #define REG_SDIO_HCPWM2_V2_8812F 0x1025003A 865 #define REG_SDIO_INDIRECT_REG_CFG_8812F 0x10250040 866 #define REG_SDIO_INDIRECT_REG_DATA_8812F 0x10250044 867 #define REG_SDIO_H2C_8812F 0x10250060 868 #define REG_SDIO_C2H_8812F 0x10250064 869 #define REG_SDIO_HRPWM1_8812F 0x10250080 870 #define REG_SDIO_HRPWM2_8812F 0x10250082 871 #define REG_SDIO_HPS_CLKR_8812F 0x10250084 872 #define REG_SDIO_BUS_CTRL_8812F 0x10250085 873 #define REG_SDIO_HSUS_CTRL_8812F 0x10250086 874 #define REG_SDIO_RESPONSE_TIMER_8812F 0x10250088 875 #define REG_SDIO_CMD_CRC_8812F 0x1025008A 876 #define REG_SDIO_HSISR_8812F 0x10250090 877 #define REG_SDIO_HSIMR_8812F 0x10250091 878 #define REG_SDIO_DIOERR_RPT_8812F 0x102500C0 879 #define REG_SDIO_CMD_ERRCNT_8812F 0x102500C2 880 #define REG_SDIO_DATA_ERRCNT_8812F 0x102500C3 881 #define REG_SDIO_CMD_ERR_CONTENT_8812F 0x102500C4 882 #define REG_SDIO_CRC_ERR_IDX_8812F 0x102500C9 883 #define REG_SDIO_DATA_CRC_8812F 0x102500CA 884 #define REG_SDIO_TRANS_FIFO_STATUS_8812F 0x102500CC 885 886 #endif 887