1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef _RTW_SRESET_H_ 16*4882a593Smuzhiyun #define _RTW_SRESET_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* #include <drv_types.h> */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum { 21*4882a593Smuzhiyun SRESET_TGP_NULL = 0, 22*4882a593Smuzhiyun SRESET_TGP_XMIT_STATUS = 1, 23*4882a593Smuzhiyun SRESET_TGP_LINK_STATUS = 2, 24*4882a593Smuzhiyun SRESET_TGP_INFO = 99, 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct sreset_priv { 28*4882a593Smuzhiyun _mutex silentreset_mutex; 29*4882a593Smuzhiyun u8 silent_reset_inprogress; 30*4882a593Smuzhiyun u8 Wifi_Error_Status; 31*4882a593Smuzhiyun systime last_tx_time; 32*4882a593Smuzhiyun systime last_tx_complete_time; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun s32 dbg_trigger_point; 35*4882a593Smuzhiyun u64 self_dect_tx_cnt; 36*4882a593Smuzhiyun u64 self_dect_rx_cnt; 37*4882a593Smuzhiyun u64 self_dect_fw_cnt; 38*4882a593Smuzhiyun u64 tx_dma_status_cnt; 39*4882a593Smuzhiyun u64 rx_dma_status_cnt; 40*4882a593Smuzhiyun u8 rx_cnt; 41*4882a593Smuzhiyun u8 self_dect_fw; 42*4882a593Smuzhiyun u8 self_dect_case; 43*4882a593Smuzhiyun u16 last_mac_rxff_ptr; 44*4882a593Smuzhiyun u8 dbg_sreset_ctrl; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define WIFI_STATUS_SUCCESS 0 50*4882a593Smuzhiyun #define USB_VEN_REQ_CMD_FAIL BIT0 51*4882a593Smuzhiyun #define USB_READ_PORT_FAIL BIT1 52*4882a593Smuzhiyun #define USB_WRITE_PORT_FAIL BIT2 53*4882a593Smuzhiyun #define WIFI_MAC_TXDMA_ERROR BIT3 54*4882a593Smuzhiyun #define WIFI_TX_HANG BIT4 55*4882a593Smuzhiyun #define WIFI_RX_HANG BIT5 56*4882a593Smuzhiyun #define WIFI_IF_NOT_EXIST BIT6 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun void sreset_init_value(_adapter *padapter); 59*4882a593Smuzhiyun void sreset_reset_value(_adapter *padapter); 60*4882a593Smuzhiyun u8 sreset_get_wifi_status(_adapter *padapter); 61*4882a593Smuzhiyun void sreset_set_wifi_error_status(_adapter *padapter, u32 status); 62*4882a593Smuzhiyun void sreset_set_trigger_point(_adapter *padapter, s32 tgp); 63*4882a593Smuzhiyun bool sreset_inprogress(_adapter *padapter); 64*4882a593Smuzhiyun void sreset_reset(_adapter *padapter); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif 67