xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/rtw_io.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #ifndef _RTW_IO_H_
17*4882a593Smuzhiyun #define _RTW_IO_H_
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define NUM_IOREQ		8
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #ifdef PLATFORM_LINUX
22*4882a593Smuzhiyun 	#define MAX_PROT_SZ	(64-16)
23*4882a593Smuzhiyun #endif
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define _IOREADY			0
26*4882a593Smuzhiyun #define _IO_WAIT_COMPLETE   1
27*4882a593Smuzhiyun #define _IO_WAIT_RSP        2
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* IO COMMAND TYPE */
30*4882a593Smuzhiyun #define _IOSZ_MASK_		(0x7F)
31*4882a593Smuzhiyun #define _IO_WRITE_		BIT(7)
32*4882a593Smuzhiyun #define _IO_FIXED_		BIT(8)
33*4882a593Smuzhiyun #define _IO_BURST_		BIT(9)
34*4882a593Smuzhiyun #define _IO_BYTE_		BIT(10)
35*4882a593Smuzhiyun #define _IO_HW_			BIT(11)
36*4882a593Smuzhiyun #define _IO_WORD_		BIT(12)
37*4882a593Smuzhiyun #define _IO_SYNC_		BIT(13)
38*4882a593Smuzhiyun #define _IO_CMDMASK_	(0x1F80)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun 	For prompt mode accessing, caller shall free io_req
43*4882a593Smuzhiyun 	Otherwise, io_handler will free io_req
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* IO STATUS TYPE */
49*4882a593Smuzhiyun #define _IO_ERR_		BIT(2)
50*4882a593Smuzhiyun #define _IO_SUCCESS_	BIT(1)
51*4882a593Smuzhiyun #define _IO_DONE_		BIT(0)
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define IO_RD32			(_IO_SYNC_ | _IO_WORD_)
55*4882a593Smuzhiyun #define IO_RD16			(_IO_SYNC_ | _IO_HW_)
56*4882a593Smuzhiyun #define IO_RD8			(_IO_SYNC_ | _IO_BYTE_)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define IO_RD32_ASYNC	(_IO_WORD_)
59*4882a593Smuzhiyun #define IO_RD16_ASYNC	(_IO_HW_)
60*4882a593Smuzhiyun #define IO_RD8_ASYNC	(_IO_BYTE_)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define IO_WR32			(_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
63*4882a593Smuzhiyun #define IO_WR16			(_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
64*4882a593Smuzhiyun #define IO_WR8			(_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define IO_WR32_ASYNC	(_IO_WRITE_ | _IO_WORD_)
67*4882a593Smuzhiyun #define IO_WR16_ASYNC	(_IO_WRITE_ | _IO_HW_)
68*4882a593Smuzhiyun #define IO_WR8_ASYNC	(_IO_WRITE_ | _IO_BYTE_)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	Only Sync. burst accessing is provided.
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define IO_WR_BURST(x)		(_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
77*4882a593Smuzhiyun #define IO_RD_BURST(x)		(_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /* below is for the intf_option bit defition... */
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define _INTF_ASYNC_	BIT(0)	/* support async io */
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun struct intf_priv;
86*4882a593Smuzhiyun struct intf_hdl;
87*4882a593Smuzhiyun struct io_queue;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun struct _io_ops {
90*4882a593Smuzhiyun 	u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
91*4882a593Smuzhiyun 	u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
92*4882a593Smuzhiyun 	u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
95*4882a593Smuzhiyun 	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
96*4882a593Smuzhiyun 	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
97*4882a593Smuzhiyun 	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
100*4882a593Smuzhiyun 	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
101*4882a593Smuzhiyun 	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
104*4882a593Smuzhiyun 	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	void (*_sync_irp_protocol_rw)(struct io_queue *pio_q);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
111*4882a593Smuzhiyun 	u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	u32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
116*4882a593Smuzhiyun 	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
119*4882a593Smuzhiyun 	u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
120*4882a593Smuzhiyun #ifdef CONFIG_SDIO_INDIRECT_ACCESS
121*4882a593Smuzhiyun 	u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
122*4882a593Smuzhiyun 	u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
123*4882a593Smuzhiyun 	u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
124*4882a593Smuzhiyun 	int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
125*4882a593Smuzhiyun 	int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
126*4882a593Smuzhiyun 	int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
127*4882a593Smuzhiyun #endif /* CONFIG_SDIO_INDIRECT_ACCESS */
128*4882a593Smuzhiyun #endif
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun struct io_req {
133*4882a593Smuzhiyun 	_list	list;
134*4882a593Smuzhiyun 	u32	addr;
135*4882a593Smuzhiyun 	volatile u32	val;
136*4882a593Smuzhiyun 	u32	command;
137*4882a593Smuzhiyun 	u32	status;
138*4882a593Smuzhiyun 	u8	*pbuf;
139*4882a593Smuzhiyun 	_sema	sema;
140*4882a593Smuzhiyun 	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);
141*4882a593Smuzhiyun 	u8 *cnxt;
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun struct	intf_hdl {
145*4882a593Smuzhiyun 	_adapter *padapter;
146*4882a593Smuzhiyun 	struct dvobj_priv *pintf_dev;/*	pointer to &(padapter->dvobjpriv); */
147*4882a593Smuzhiyun 	struct _io_ops	io_ops;
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun struct reg_protocol_rd {
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #ifdef CONFIG_LITTLE_ENDIAN
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* DW1 */
155*4882a593Smuzhiyun 	u32		NumOfTrans:4;
156*4882a593Smuzhiyun 	u32		Reserved1:4;
157*4882a593Smuzhiyun 	u32		Reserved2:24;
158*4882a593Smuzhiyun 	/* DW2 */
159*4882a593Smuzhiyun 	u32		ByteCount:7;
160*4882a593Smuzhiyun 	u32		WriteEnable:1;		/* 0:read, 1:write */
161*4882a593Smuzhiyun 	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
162*4882a593Smuzhiyun 	u32		BurstMode:1;
163*4882a593Smuzhiyun 	u32		Byte1Access:1;
164*4882a593Smuzhiyun 	u32		Byte2Access:1;
165*4882a593Smuzhiyun 	u32		Byte4Access:1;
166*4882a593Smuzhiyun 	u32		Reserved3:3;
167*4882a593Smuzhiyun 	u32		Reserved4:16;
168*4882a593Smuzhiyun 	/* DW3 */
169*4882a593Smuzhiyun 	u32		BusAddress;
170*4882a593Smuzhiyun 	/* DW4 */
171*4882a593Smuzhiyun 	/* u32		Value; */
172*4882a593Smuzhiyun #else
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	/* DW1 */
176*4882a593Smuzhiyun 	u32 Reserved1:4;
177*4882a593Smuzhiyun 	u32 NumOfTrans:4;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	u32 Reserved2:24;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	/* DW2 */
182*4882a593Smuzhiyun 	u32 WriteEnable:1;
183*4882a593Smuzhiyun 	u32 ByteCount:7;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	u32 Reserved3:3;
187*4882a593Smuzhiyun 	u32 Byte4Access:1;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	u32 Byte2Access:1;
190*4882a593Smuzhiyun 	u32 Byte1Access:1;
191*4882a593Smuzhiyun 	u32 BurstMode:1;
192*4882a593Smuzhiyun 	u32 FixOrContinuous:1;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	u32 Reserved4:16;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	/* DW3 */
197*4882a593Smuzhiyun 	u32		BusAddress;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	/* DW4 */
200*4882a593Smuzhiyun 	/* u32		Value; */
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun #endif
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun struct reg_protocol_wt {
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun #ifdef CONFIG_LITTLE_ENDIAN
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* DW1 */
213*4882a593Smuzhiyun 	u32		NumOfTrans:4;
214*4882a593Smuzhiyun 	u32		Reserved1:4;
215*4882a593Smuzhiyun 	u32		Reserved2:24;
216*4882a593Smuzhiyun 	/* DW2 */
217*4882a593Smuzhiyun 	u32		ByteCount:7;
218*4882a593Smuzhiyun 	u32		WriteEnable:1;		/* 0:read, 1:write */
219*4882a593Smuzhiyun 	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
220*4882a593Smuzhiyun 	u32		BurstMode:1;
221*4882a593Smuzhiyun 	u32		Byte1Access:1;
222*4882a593Smuzhiyun 	u32		Byte2Access:1;
223*4882a593Smuzhiyun 	u32		Byte4Access:1;
224*4882a593Smuzhiyun 	u32		Reserved3:3;
225*4882a593Smuzhiyun 	u32		Reserved4:16;
226*4882a593Smuzhiyun 	/* DW3 */
227*4882a593Smuzhiyun 	u32		BusAddress;
228*4882a593Smuzhiyun 	/* DW4 */
229*4882a593Smuzhiyun 	u32		Value;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun #else
232*4882a593Smuzhiyun 	/* DW1 */
233*4882a593Smuzhiyun 	u32 Reserved1:4;
234*4882a593Smuzhiyun 	u32 NumOfTrans:4;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	u32 Reserved2:24;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	/* DW2 */
239*4882a593Smuzhiyun 	u32 WriteEnable:1;
240*4882a593Smuzhiyun 	u32 ByteCount:7;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	u32 Reserved3:3;
243*4882a593Smuzhiyun 	u32 Byte4Access:1;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	u32 Byte2Access:1;
246*4882a593Smuzhiyun 	u32 Byte1Access:1;
247*4882a593Smuzhiyun 	u32 BurstMode:1;
248*4882a593Smuzhiyun 	u32 FixOrContinuous:1;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	u32 Reserved4:16;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	/* DW3 */
253*4882a593Smuzhiyun 	u32		BusAddress;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	/* DW4 */
256*4882a593Smuzhiyun 	u32		Value;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun #endif
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
262*4882a593Smuzhiyun #define MAX_CONTINUAL_IO_ERR 4
263*4882a593Smuzhiyun #endif
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
266*4882a593Smuzhiyun #define MAX_CONTINUAL_IO_ERR 4
267*4882a593Smuzhiyun #endif
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
270*4882a593Smuzhiyun #define SD_IO_TRY_CNT (8)
271*4882a593Smuzhiyun #define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
272*4882a593Smuzhiyun #endif
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun #ifdef CONFIG_GSPI_HCI
275*4882a593Smuzhiyun #define SD_IO_TRY_CNT (8)
276*4882a593Smuzhiyun #define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
277*4882a593Smuzhiyun #endif
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj);
281*4882a593Smuzhiyun void rtw_reset_continual_io_error(struct dvobj_priv *dvobj);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun /*
284*4882a593Smuzhiyun Below is the data structure used by _io_handler
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun */
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun struct io_queue {
289*4882a593Smuzhiyun 	_lock	lock;
290*4882a593Smuzhiyun 	_list	free_ioreqs;
291*4882a593Smuzhiyun 	_list		pending;		/* The io_req list that will be served in the single protocol read/write.	 */
292*4882a593Smuzhiyun 	_list		processing;
293*4882a593Smuzhiyun 	u8	*free_ioreqs_buf; /* 4-byte aligned */
294*4882a593Smuzhiyun 	u8	*pallocated_free_ioreqs_buf;
295*4882a593Smuzhiyun 	struct	intf_hdl	intf;
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun struct io_priv {
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	_adapter *padapter;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	struct intf_hdl intf;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
307*4882a593Smuzhiyun extern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue);
308*4882a593Smuzhiyun extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);
312*4882a593Smuzhiyun extern struct io_req *alloc_ioreq(struct io_queue *pio_q);
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);
315*4882a593Smuzhiyun extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
318*4882a593Smuzhiyun extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun extern u8 _rtw_read8(_adapter *adapter, u32 addr);
321*4882a593Smuzhiyun extern u16 _rtw_read16(_adapter *adapter, u32 addr);
322*4882a593Smuzhiyun extern u32 _rtw_read32(_adapter *adapter, u32 addr);
323*4882a593Smuzhiyun extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
324*4882a593Smuzhiyun extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
325*4882a593Smuzhiyun extern void _rtw_read_port_cancel(_adapter *adapter);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
329*4882a593Smuzhiyun extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
330*4882a593Smuzhiyun extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
331*4882a593Smuzhiyun extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
334*4882a593Smuzhiyun u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr);
335*4882a593Smuzhiyun #ifdef CONFIG_SDIO_INDIRECT_ACCESS
336*4882a593Smuzhiyun u8 _rtw_sd_iread8(_adapter *adapter, u32 addr);
337*4882a593Smuzhiyun u16 _rtw_sd_iread16(_adapter *adapter, u32 addr);
338*4882a593Smuzhiyun u32 _rtw_sd_iread32(_adapter *adapter, u32 addr);
339*4882a593Smuzhiyun int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val);
340*4882a593Smuzhiyun int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val);
341*4882a593Smuzhiyun int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val);
342*4882a593Smuzhiyun #endif /* CONFIG_SDIO_INDIRECT_ACCESS */
343*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);
346*4882a593Smuzhiyun extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);
347*4882a593Smuzhiyun extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
350*4882a593Smuzhiyun extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
351*4882a593Smuzhiyun u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);
352*4882a593Smuzhiyun extern void _rtw_write_port_cancel(_adapter *adapter);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun #ifdef DBG_IO
355*4882a593Smuzhiyun u32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
356*4882a593Smuzhiyun u32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
357*4882a593Smuzhiyun bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
358*4882a593Smuzhiyun bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun void dbg_rtw_reg_read_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line);
361*4882a593Smuzhiyun void dbg_rtw_reg_write_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
364*4882a593Smuzhiyun extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);
365*4882a593Smuzhiyun extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
368*4882a593Smuzhiyun extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
369*4882a593Smuzhiyun extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
370*4882a593Smuzhiyun extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line);
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
373*4882a593Smuzhiyun u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
374*4882a593Smuzhiyun #ifdef CONFIG_SDIO_INDIRECT_ACCESS
375*4882a593Smuzhiyun u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line);
376*4882a593Smuzhiyun u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line);
377*4882a593Smuzhiyun u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line);
378*4882a593Smuzhiyun int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
379*4882a593Smuzhiyun int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
380*4882a593Smuzhiyun int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
381*4882a593Smuzhiyun #endif /* CONFIG_SDIO_INDIRECT_ACCESS */
382*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun #define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)
385*4882a593Smuzhiyun #define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)
386*4882a593Smuzhiyun #define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)
387*4882a593Smuzhiyun #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
388*4882a593Smuzhiyun #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
389*4882a593Smuzhiyun #define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun #define  rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)
392*4882a593Smuzhiyun #define  rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)
393*4882a593Smuzhiyun #define  rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)
394*4882a593Smuzhiyun #define  rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun #define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
397*4882a593Smuzhiyun #define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
398*4882a593Smuzhiyun #define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem)
401*4882a593Smuzhiyun #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)
402*4882a593Smuzhiyun #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
403*4882a593Smuzhiyun #define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
406*4882a593Smuzhiyun #define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__)
407*4882a593Smuzhiyun #ifdef CONFIG_SDIO_INDIRECT_ACCESS
408*4882a593Smuzhiyun #define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__)
409*4882a593Smuzhiyun #define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__)
410*4882a593Smuzhiyun #define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__)
411*4882a593Smuzhiyun #define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__)
412*4882a593Smuzhiyun #define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__)
413*4882a593Smuzhiyun #define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__)
414*4882a593Smuzhiyun #endif /* CONFIG_SDIO_INDIRECT_ACCESS */
415*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun #else /* DBG_IO */
418*4882a593Smuzhiyun #define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
419*4882a593Smuzhiyun #define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
420*4882a593Smuzhiyun #define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
421*4882a593Smuzhiyun #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
422*4882a593Smuzhiyun #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
423*4882a593Smuzhiyun #define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun #define  rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
426*4882a593Smuzhiyun #define  rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
427*4882a593Smuzhiyun #define  rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
428*4882a593Smuzhiyun #define  rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun #define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
431*4882a593Smuzhiyun #define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
432*4882a593Smuzhiyun #define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))
435*4882a593Smuzhiyun #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
436*4882a593Smuzhiyun #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
437*4882a593Smuzhiyun #define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
440*4882a593Smuzhiyun #define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr))
441*4882a593Smuzhiyun #ifdef CONFIG_SDIO_INDIRECT_ACCESS
442*4882a593Smuzhiyun #define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr))
443*4882a593Smuzhiyun #define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr))
444*4882a593Smuzhiyun #define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr))
445*4882a593Smuzhiyun #define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val))
446*4882a593Smuzhiyun #define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val))
447*4882a593Smuzhiyun #define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val))
448*4882a593Smuzhiyun #endif /* CONFIG_SDIO_INDIRECT_ACCESS */
449*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun #endif /* DBG_IO */
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun /* ioreq */
456*4882a593Smuzhiyun extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);
457*4882a593Smuzhiyun extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);
458*4882a593Smuzhiyun extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);
459*4882a593Smuzhiyun extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);
460*4882a593Smuzhiyun extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);
461*4882a593Smuzhiyun extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,
465*4882a593Smuzhiyun 	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
466*4882a593Smuzhiyun extern uint async_read16(_adapter *adapter, u32 addr,  u8 *pbuff,
467*4882a593Smuzhiyun 	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
468*4882a593Smuzhiyun extern uint async_read32(_adapter *adapter, u32 addr,  u8 *pbuff,
469*4882a593Smuzhiyun 	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
472*4882a593Smuzhiyun extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun extern void async_write8(_adapter *adapter, u32 addr, u8 val,
475*4882a593Smuzhiyun 	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
476*4882a593Smuzhiyun extern void async_write16(_adapter *adapter, u32 addr, u16 val,
477*4882a593Smuzhiyun 	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
478*4882a593Smuzhiyun extern void async_write32(_adapter *adapter, u32 addr, u32 val,
479*4882a593Smuzhiyun 	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
482*4882a593Smuzhiyun extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops));
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun extern uint alloc_io_queue(_adapter *adapter);
489*4882a593Smuzhiyun extern void free_io_queue(_adapter *adapter);
490*4882a593Smuzhiyun extern void async_bus_io(struct io_queue *pio_q);
491*4882a593Smuzhiyun extern void bus_sync_io(struct io_queue *pio_q);
492*4882a593Smuzhiyun extern u32 _ioreq2rwmem(struct io_queue *pio_q);
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun /*
495*4882a593Smuzhiyun #define RTL_R8(reg)		rtw_read8(padapter, reg)
496*4882a593Smuzhiyun #define RTL_R16(reg)            rtw_read16(padapter, reg)
497*4882a593Smuzhiyun #define RTL_R32(reg)            rtw_read32(padapter, reg)
498*4882a593Smuzhiyun #define RTL_W8(reg, val8)       rtw_write8(padapter, reg, val8)
499*4882a593Smuzhiyun #define RTL_W16(reg, val16)     rtw_write16(padapter, reg, val16)
500*4882a593Smuzhiyun #define RTL_W32(reg, val32)     rtw_write32(padapter, reg, val32)
501*4882a593Smuzhiyun */
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun /*
504*4882a593Smuzhiyun #define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
505*4882a593Smuzhiyun #define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
506*4882a593Smuzhiyun #define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun #define RTL_WRITE_BB(reg, val32)	phy_SetUsbBBReg(padapter, reg, val32)
509*4882a593Smuzhiyun #define RTL_READ_BB(reg)	phy_QueryUsbBBReg(padapter, reg)
510*4882a593Smuzhiyun */
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun #define PlatformEFIOWrite1Byte(_a, _b, _c)		\
513*4882a593Smuzhiyun 	rtw_write8(_a, _b, _c)
514*4882a593Smuzhiyun #define PlatformEFIOWrite2Byte(_a, _b, _c)		\
515*4882a593Smuzhiyun 	rtw_write16(_a, _b, _c)
516*4882a593Smuzhiyun #define PlatformEFIOWrite4Byte(_a, _b, _c)		\
517*4882a593Smuzhiyun 	rtw_write32(_a, _b, _c)
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun #define PlatformEFIORead1Byte(_a, _b)		\
520*4882a593Smuzhiyun 	rtw_read8(_a, _b)
521*4882a593Smuzhiyun #define PlatformEFIORead2Byte(_a, _b)		\
522*4882a593Smuzhiyun 	rtw_read16(_a, _b)
523*4882a593Smuzhiyun #define PlatformEFIORead4Byte(_a, _b)		\
524*4882a593Smuzhiyun 	rtw_read32(_a, _b)
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun #endif /* _RTL8711_IO_H_ */
527