1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8814A_HAL_H__ 16*4882a593Smuzhiyun #define __RTL8814A_HAL_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* #include "hal_com.h" */ 19*4882a593Smuzhiyun #include "hal_data.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* include HAL Related header after HAL Related compiling flags */ 22*4882a593Smuzhiyun #include "rtl8814a_spec.h" 23*4882a593Smuzhiyun #include "rtl8814a_rf.h" 24*4882a593Smuzhiyun #include "rtl8814a_dm.h" 25*4882a593Smuzhiyun #include "rtl8814a_recv.h" 26*4882a593Smuzhiyun #include "rtl8814a_xmit.h" 27*4882a593Smuzhiyun #include "rtl8814a_cmd.h" 28*4882a593Smuzhiyun #include "rtl8814a_led.h" 29*4882a593Smuzhiyun #include "Hal8814PwrSeq.h" 30*4882a593Smuzhiyun #include "Hal8814PhyReg.h" 31*4882a593Smuzhiyun #include "Hal8814PhyCfg.h" 32*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT 33*4882a593Smuzhiyun #include "rtl8814a_sreset.h" 34*4882a593Smuzhiyun #endif /* DBG_CONFIG_ERROR_DETECT */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun enum { 37*4882a593Smuzhiyun VOLTAGE_V25 = 0x03, 38*4882a593Smuzhiyun LDOE25_SHIFT = 28 , 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun /* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/ 41*4882a593Smuzhiyun #define FW_SIZE 0x18000 42*4882a593Smuzhiyun #define FW_START_ADDRESS 0x1000 43*4882a593Smuzhiyun typedef struct _RT_FIRMWARE_8814 { 44*4882a593Smuzhiyun FIRMWARE_SOURCE eFWSource; 45*4882a593Smuzhiyun #ifdef CONFIG_EMBEDDED_FWIMG 46*4882a593Smuzhiyun u8 *szFwBuffer; 47*4882a593Smuzhiyun #else 48*4882a593Smuzhiyun u8 szFwBuffer[FW_SIZE]; 49*4882a593Smuzhiyun #endif 50*4882a593Smuzhiyun u32 ulFwLength; 51*4882a593Smuzhiyun } RT_FIRMWARE_8814, *PRT_FIRMWARE_8814; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PAGE_SIZE_TX_8814 PAGE_SIZE_128 54*4882a593Smuzhiyun /* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8814 55*4882a593Smuzhiyun * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define BCNQ_PAGE_NUM_8814 (MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + 6) /*0x08*/ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define Rtl8814A_NIC_PWR_ON_FLOW rtl8814A_power_on_flow 60*4882a593Smuzhiyun #define Rtl8814A_NIC_RF_OFF_FLOW rtl8814A_radio_off_flow 61*4882a593Smuzhiyun #define Rtl8814A_NIC_DISABLE_FLOW rtl8814A_card_disable_flow 62*4882a593Smuzhiyun #define Rtl8814A_NIC_ENABLE_FLOW rtl8814A_card_enable_flow 63*4882a593Smuzhiyun #define Rtl8814A_NIC_SUSPEND_FLOW rtl8814A_suspend_flow 64*4882a593Smuzhiyun #define Rtl8814A_NIC_RESUME_FLOW rtl8814A_resume_flow 65*4882a593Smuzhiyun #define Rtl8814A_NIC_PDN_FLOW rtl8814A_hwpdn_flow 66*4882a593Smuzhiyun #define Rtl8814A_NIC_LPS_ENTER_FLOW rtl8814A_enter_lps_flow 67*4882a593Smuzhiyun #define Rtl8814A_NIC_LPS_LEAVE_FLOW rtl8814A_leave_lps_flow 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* ***************************************************** 70*4882a593Smuzhiyun * New Firmware Header(8-byte alinment required) 71*4882a593Smuzhiyun * ***************************************************** 72*4882a593Smuzhiyun * --- LONG WORD 0 ---- */ 73*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SIGNATURE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) 74*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_CATEGORY_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */ 75*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_FUNCTION_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ 76*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_VERSION_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */ 77*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SUB_VER_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */ 78*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SUB_IDX_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) /* FW Subversion Index */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* --- LONG WORD 1 ---- */ 81*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SVN_IDX_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 32)/* The SVN entry index */ 82*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD1_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 32) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* --- LONG WORD 2 ---- */ 85*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MONTH_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 8) /* Release time Month field */ 86*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_DATE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 8, 8) /* Release time Date field */ 87*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_HOUR_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 16, 8)/* Release time Hour field */ 88*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MINUTE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 24, 8)/* Release time Minute field */ 89*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_YEAR_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 16)/* Release time Year field */ 90*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_FOUNDRY_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 16, 8)/* Release time Foundry field */ 91*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD2_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 24, 8) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* --- LONG WORD 3 ---- */ 94*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MEM_UASGE_DL_FROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 1) 95*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_FROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 1, 1) 96*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_LOADER_3081(__FwHdr)LE_BITS_TO_4BYTE(__FwHdr+24, 2, 1) 97*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MEM_UASGE_IRAM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 3, 1) 98*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MEM_UASGE_ERAM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 4, 1) 99*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MEM_UASGE_RSVD4_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 5, 3) 100*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD3_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 8, 8) 101*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_BOOT_LOADER_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 16, 16) 102*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD5_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* --- LONG WORD 4 ---- */ 105*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 0, 32) 106*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_FW_CFG_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 0, 16) 107*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_FW_ATTR_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 16, 16) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* --- LONG WORD 5 ---- */ 110*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_IROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+40, 0, 32) 111*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_EROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+44, 0, 32) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* --- LONG WORD 6 ---- */ 114*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_IRAM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+48, 0, 32) 115*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_ERAM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+52, 0, 32) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* --- LONG WORD 7 ---- */ 118*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD6_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+56, 0, 32) 119*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD7_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+60, 0, 32) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * 2013/08/16 MH MOve from SDIO.h for common use. 125*4882a593Smuzhiyun * */ 126*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) 127*4882a593Smuzhiyun #define TRX_SHARE_MODE_8814A 0 /* TRX Buffer Share Index */ 128*4882a593Smuzhiyun #define BASIC_RXFF_SIZE_8814A 24576/* Basic RXFF Size is 24K = 24*1024 Unit: Byte */ 129*4882a593Smuzhiyun #define TRX_SHARE_BUFF_UNIT_8814A 65536/* TRX Share Buffer unit Size 64K = 64*1024 Unit: Byte */ 130*4882a593Smuzhiyun #define TRX_SHARE_BUFF_UNIT_PAGE_8814A (TRX_SHARE_BUFF_UNIT_8814A/PAGE_SIZE_8814A)/* 512 Pages */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* Origin: */ 133*4882a593Smuzhiyun #define HPQ_PGNUM_8814A 0x20 /* High Queue */ 134*4882a593Smuzhiyun #define LPQ_PGNUM_8814A 0x20 /* Low Queue */ 135*4882a593Smuzhiyun #define NPQ_PGNUM_8814A 0x20 /* Normal Queue */ 136*4882a593Smuzhiyun #define EPQ_PGNUM_8814A 0x20 /* Extra Queue */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #else /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */ 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define HPQ_PGNUM_8814A 20 141*4882a593Smuzhiyun #define NPQ_PGNUM_8814A 20 142*4882a593Smuzhiyun #define LPQ_PGNUM_8814A 20 /* 1972 */ 143*4882a593Smuzhiyun #define EPQ_PGNUM_8814A 20 144*4882a593Smuzhiyun #define BCQ_PGNUM_8814A 32 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 149*4882a593Smuzhiyun #define WOWLAN_PAGE_NUM_8814 0x06 150*4882a593Smuzhiyun #else 151*4882a593Smuzhiyun #define WOWLAN_PAGE_NUM_8814 0x00 152*4882a593Smuzhiyun #endif 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define PAGE_SIZE_8814A 128/* TXFF Page Size, Unit: Byte */ 155*4882a593Smuzhiyun #define MAX_RX_DMA_BUFFER_SIZE_8814A 0x5C00 /* BASIC_RXFF_SIZE_8814A + TRX_SHARE_MODE_8814A * TRX_SHARE_BUFF_UNIT_8814A */ /* Basic RXFF Size + ShareBuffer Size */ 156*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_8814A TXPKT_PGNUM_8814A /* Need to enlarge boundary, by KaiYuan */ 157*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_WOWLAN_8814A TXPKT_PGNUM_8814A /* TODO: 20130415 KaiYuan Check this value later */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_DEBUG 160*4882a593Smuzhiyun #define RX_DMA_RESERVED_SIZE_8814A 0x100 /* 256B, reserved for c2h debug message */ 161*4882a593Smuzhiyun #else 162*4882a593Smuzhiyun #define RX_DMA_RESERVED_SIZE_8814A 0x0 /* 0B */ 163*4882a593Smuzhiyun #endif 164*4882a593Smuzhiyun #define RX_DMA_BOUNDARY_8814A (MAX_RX_DMA_BUFFER_SIZE_8814A - RX_DMA_RESERVED_SIZE_8814A - 1) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define TOTAL_PGNUM_8814A 2048 167*4882a593Smuzhiyun #define TXPKT_PGNUM_8814A (2048 - BCNQ_PAGE_NUM_8814-WOWLAN_PAGE_NUM_8814) 168*4882a593Smuzhiyun #define PUB_PGNUM_8814A (TXPKT_PGNUM_8814A-HPQ_PGNUM_8814A-NPQ_PGNUM_8814A-LPQ_PGNUM_8814A-EPQ_PGNUM_8814A) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* Note: For WMM Normal Chip Setting ,modify later */ 171*4882a593Smuzhiyun #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A TX_PAGE_BOUNDARY_8814A 172*4882a593Smuzhiyun #define WMM_NORMAL_TX_PAGE_BOUNDARY_8814A (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A + 1) 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define DRIVER_EARLY_INT_TIME_8814 0x05 175*4882a593Smuzhiyun #define BCN_DMA_ATIME_INT_TIME_8814 0x02 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define EFUSE_MAX_SECTION_JAGUAR 64 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define HWSET_MAX_SIZE_8814A 512 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define EFUSE_REAL_CONTENT_LEN_8814A 1024 185*4882a593Smuzhiyun #define EFUSE_MAX_BANK_8814A 2 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define EFUSE_MAP_LEN_8814A 512 188*4882a593Smuzhiyun #define EFUSE_MAX_SECTION_8814A 64 189*4882a593Smuzhiyun #define EFUSE_MAX_WORD_UNIT_8814A 4 190*4882a593Smuzhiyun #define EFUSE_PROTECT_BYTES_BANK_8814A 16 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define EFUSE_IC_ID_OFFSET_8814A 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ 193*4882a593Smuzhiyun #define AVAILABLE_EFUSE_ADDR_8814A(addr) (addr < EFUSE_REAL_CONTENT_LEN_8814A) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /*------------------------------------------------------------------------- 196*4882a593Smuzhiyun Chip specific 197*4882a593Smuzhiyun -------------------------------------------------------------------------*/ 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* pic buffer descriptor */ 200*4882a593Smuzhiyun #if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */ 201*4882a593Smuzhiyun #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 202*4882a593Smuzhiyun #define TX_DESC_NUM_8814A TX_BD_NUM /* 128 */ 203*4882a593Smuzhiyun #define RX_DESC_NUM_8814A PCI_MAX_RX_COUNT /* 128 */ 204*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 205*4882a593Smuzhiyun #define BE_QUEUE_TX_DESC_NUM_8814A (TX_BD_NUM<<1) /* 256 */ 206*4882a593Smuzhiyun #else 207*4882a593Smuzhiyun #define BE_QUEUE_TX_DESC_NUM_8814A (TX_BD_NUM+(TX_BD_NUM>>1)) /* 192 */ 208*4882a593Smuzhiyun #endif 209*4882a593Smuzhiyun #else 210*4882a593Smuzhiyun #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 211*4882a593Smuzhiyun #define TX_DESC_NUM_8814A 128 /* 1024//2048 change by ylb 20130624 */ 212*4882a593Smuzhiyun #define RX_DESC_NUM_8814A 128 /* 1024 //512 change by ylb 20130624 */ 213*4882a593Smuzhiyun #endif 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section 216*4882a593Smuzhiyun * 9bytes + 1byt + 5bytes and pre 1byte. 217*4882a593Smuzhiyun * For worst case: 218*4882a593Smuzhiyun * | 1byte|----8bytes----|1byte|--5bytes--| 219*4882a593Smuzhiyun * | | Reserved(14bytes) | 220*4882a593Smuzhiyun * */ 221*4882a593Smuzhiyun #define EFUSE_OOB_PROTECT_BYTES 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun #ifdef CONFIG_FILE_FWIMG 224*4882a593Smuzhiyun extern char *rtw_fw_file_path; 225*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 226*4882a593Smuzhiyun extern char *rtw_fw_wow_file_path; 227*4882a593Smuzhiyun #endif 228*4882a593Smuzhiyun #ifdef CONFIG_MP_INCLUDED 229*4882a593Smuzhiyun extern char *rtw_fw_mp_bt_file_path; 230*4882a593Smuzhiyun #endif /* CONFIG_MP_INCLUDED */ 231*4882a593Smuzhiyun #endif /* CONFIG_FILE_FWIMG */ 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /* rtl8814_hal_init.c */ 234*4882a593Smuzhiyun s32 FirmwareDownload8814A(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw); 235*4882a593Smuzhiyun void InitializeFirmwareVars8814(PADAPTER padapter); 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun void 238*4882a593Smuzhiyun Hal_InitEfuseVars_8814A( 239*4882a593Smuzhiyun PADAPTER Adapter 240*4882a593Smuzhiyun ); 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun s32 InitLLTTable8814A( 243*4882a593Smuzhiyun PADAPTER Adapter 244*4882a593Smuzhiyun ); 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun void InitRDGSetting8814A(PADAPTER padapter); 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* void CheckAutoloadState8812A(PADAPTER padapter); */ 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* EFuse */ 252*4882a593Smuzhiyun u8 GetEEPROMSize8814A(PADAPTER padapter); 253*4882a593Smuzhiyun void hal_InitPGData_8814A( 254*4882a593Smuzhiyun PADAPTER padapter, 255*4882a593Smuzhiyun u8 *PROMContent 256*4882a593Smuzhiyun ); 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun void hal_ReadPROMVersion8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 259*4882a593Smuzhiyun void hal_ReadTxPowerInfo8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 260*4882a593Smuzhiyun void hal_ReadBoardType8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 261*4882a593Smuzhiyun void hal_ReadThermalMeter_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 262*4882a593Smuzhiyun void hal_ReadChannelPlan8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 263*4882a593Smuzhiyun void hal_EfuseParseXtal_8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 264*4882a593Smuzhiyun void hal_ReadAntennaDiversity8814A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail); 265*4882a593Smuzhiyun void hal_Read_TRX_antenna_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 266*4882a593Smuzhiyun void hal_ReadAmplifierType_8814A( 267*4882a593Smuzhiyun PADAPTER Adapter 268*4882a593Smuzhiyun ); 269*4882a593Smuzhiyun void hal_ReadPAType_8814A( 270*4882a593Smuzhiyun PADAPTER Adapter, 271*4882a593Smuzhiyun u8 *PROMContent, 272*4882a593Smuzhiyun BOOLEAN AutoloadFail, 273*4882a593Smuzhiyun u8 *pPAType, 274*4882a593Smuzhiyun u8 *pLNAType 275*4882a593Smuzhiyun ); 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun void hal_GetRxGainOffset_8814A( 278*4882a593Smuzhiyun PADAPTER Adapter, 279*4882a593Smuzhiyun u8 *PROMContent, 280*4882a593Smuzhiyun BOOLEAN AutoloadFail 281*4882a593Smuzhiyun ); 282*4882a593Smuzhiyun void Hal_EfuseParseKFreeData_8814A( 283*4882a593Smuzhiyun PADAPTER Adapter, 284*4882a593Smuzhiyun u8 *PROMContent, 285*4882a593Smuzhiyun BOOLEAN AutoloadFail); 286*4882a593Smuzhiyun void hal_ReadRFEType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 287*4882a593Smuzhiyun void hal_EfuseParseBTCoexistInfo8814A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun /* void hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 290*4882a593Smuzhiyun * int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); */ 291*4882a593Smuzhiyun void hal_ReadRemoteWakeup_8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 292*4882a593Smuzhiyun u8 MgntQuery_NssTxRate(u16 Rate); 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); */ 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 297*4882a593Smuzhiyun void Hal_DetectWoWMode(PADAPTER pAdapter); 298*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun void _InitBeaconParameters_8814A(PADAPTER padapter); 301*4882a593Smuzhiyun void SetBeaconRelatedRegisters8814A(PADAPTER padapter); 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun void ReadRFType8814A(PADAPTER padapter); 304*4882a593Smuzhiyun void InitDefaultValue8814A(PADAPTER padapter); 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun u8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); 307*4882a593Smuzhiyun void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); 308*4882a593Smuzhiyun u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); 309*4882a593Smuzhiyun u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); 310*4882a593Smuzhiyun void rtl8814_set_hal_ops(struct hal_ops *pHalFunc); 311*4882a593Smuzhiyun void init_hal_spec_8814a(_adapter *adapter); 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun void rtl8814_start_thread(PADAPTER padapter); 314*4882a593Smuzhiyun void rtl8814_stop_thread(PADAPTER padapter); 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 318*4882a593Smuzhiyun BOOLEAN InterruptRecognized8814AE(PADAPTER Adapter); 319*4882a593Smuzhiyun void UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); 320*4882a593Smuzhiyun void InitMAC_TRXBD_8814AE(PADAPTER Adapter); 321*4882a593Smuzhiyun void rtl8814ae_reset_desc_ring(_adapter *padapter); 322*4882a593Smuzhiyun u16 get_txbd_rw_reg(u16 ff_hwaddr); 323*4882a593Smuzhiyun #endif 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST 326*4882a593Smuzhiyun void rtl8814a_combo_card_WifiOnlyHwInit(PADAPTER Adapter); 327*4882a593Smuzhiyun #endif 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun #endif /* __RTL8188E_HAL_H__ */ 330