xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/rtl8812a_hal.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __RTL8812A_HAL_H__
16*4882a593Smuzhiyun #define __RTL8812A_HAL_H__
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* #include "hal_com.h" */
19*4882a593Smuzhiyun #include "hal_data.h"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* include HAL Related header after HAL Related compiling flags */
22*4882a593Smuzhiyun #include "rtl8812a_spec.h"
23*4882a593Smuzhiyun #include "rtl8812a_rf.h"
24*4882a593Smuzhiyun #include "rtl8812a_dm.h"
25*4882a593Smuzhiyun #include "rtl8812a_recv.h"
26*4882a593Smuzhiyun #include "rtl8812a_xmit.h"
27*4882a593Smuzhiyun #include "rtl8812a_cmd.h"
28*4882a593Smuzhiyun #include "rtl8812a_led.h"
29*4882a593Smuzhiyun #include "Hal8812PwrSeq.h"
30*4882a593Smuzhiyun #include "Hal8821APwrSeq.h" /* for 8821A/8811A */
31*4882a593Smuzhiyun #include "Hal8812PhyReg.h"
32*4882a593Smuzhiyun #include "Hal8812PhyCfg.h"
33*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT
34*4882a593Smuzhiyun #include "rtl8812a_sreset.h"
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* ---------------------------------------------------------------------
38*4882a593Smuzhiyun  *		RTL8812 Power Configuration CMDs for PCIe interface
39*4882a593Smuzhiyun  * --------------------------------------------------------------------- */
40*4882a593Smuzhiyun #define Rtl8812_NIC_PWR_ON_FLOW				rtl8812_power_on_flow
41*4882a593Smuzhiyun #define Rtl8812_NIC_RF_OFF_FLOW				rtl8812_radio_off_flow
42*4882a593Smuzhiyun #define Rtl8812_NIC_DISABLE_FLOW				rtl8812_card_disable_flow
43*4882a593Smuzhiyun #define Rtl8812_NIC_ENABLE_FLOW				rtl8812_card_enable_flow
44*4882a593Smuzhiyun #define Rtl8812_NIC_SUSPEND_FLOW				rtl8812_suspend_flow
45*4882a593Smuzhiyun #define Rtl8812_NIC_RESUME_FLOW				rtl8812_resume_flow
46*4882a593Smuzhiyun #define Rtl8812_NIC_PDN_FLOW					rtl8812_hwpdn_flow
47*4882a593Smuzhiyun #define Rtl8812_NIC_LPS_ENTER_FLOW			rtl8812_enter_lps_flow
48*4882a593Smuzhiyun #define Rtl8812_NIC_LPS_LEAVE_FLOW				rtl8812_leave_lps_flow
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* ---------------------------------------------------------------------
51*4882a593Smuzhiyun  *		RTL8821 Power Configuration CMDs for PCIe interface
52*4882a593Smuzhiyun  * --------------------------------------------------------------------- */
53*4882a593Smuzhiyun #define Rtl8821A_NIC_PWR_ON_FLOW				rtl8821A_power_on_flow
54*4882a593Smuzhiyun #define Rtl8821A_NIC_RF_OFF_FLOW				rtl8821A_radio_off_flow
55*4882a593Smuzhiyun #define Rtl8821A_NIC_DISABLE_FLOW				rtl8821A_card_disable_flow
56*4882a593Smuzhiyun #define Rtl8821A_NIC_ENABLE_FLOW				rtl8821A_card_enable_flow
57*4882a593Smuzhiyun #define Rtl8821A_NIC_SUSPEND_FLOW				rtl8821A_suspend_flow
58*4882a593Smuzhiyun #define Rtl8821A_NIC_RESUME_FLOW				rtl8821A_resume_flow
59*4882a593Smuzhiyun #define Rtl8821A_NIC_PDN_FLOW					rtl8821A_hwpdn_flow
60*4882a593Smuzhiyun #define Rtl8821A_NIC_LPS_ENTER_FLOW			rtl8821A_enter_lps_flow
61*4882a593Smuzhiyun #define Rtl8821A_NIC_LPS_LEAVE_FLOW			rtl8821A_leave_lps_flow
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #if 1 /* download firmware related data structure */
65*4882a593Smuzhiyun #define FW_SIZE_8812			0x8000 /* Compatible with RTL8723 Maximal RAM code size 24K.   modified to 32k, TO compatible with 92d maximal fw size 32k */
66*4882a593Smuzhiyun #define FW_START_ADDRESS		0x1000
67*4882a593Smuzhiyun #define FW_END_ADDRESS		0x5FFF
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun typedef struct _RT_FIRMWARE_8812 {
72*4882a593Smuzhiyun 	FIRMWARE_SOURCE	eFWSource;
73*4882a593Smuzhiyun #ifdef CONFIG_EMBEDDED_FWIMG
74*4882a593Smuzhiyun 	u8			*szFwBuffer;
75*4882a593Smuzhiyun #else
76*4882a593Smuzhiyun 	u8			szFwBuffer[FW_SIZE_8812];
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun 	u32			ulFwLength;
79*4882a593Smuzhiyun } RT_FIRMWARE_8812, *PRT_FIRMWARE_8812;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun  * This structure must be cared byte-ordering
83*4882a593Smuzhiyun  *
84*4882a593Smuzhiyun  * Added by tynli. 2009.12.04. */
85*4882a593Smuzhiyun #define IS_FW_HEADER_EXIST_8812(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x9500)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define IS_FW_HEADER_EXIST_8821(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x2100)
88*4882a593Smuzhiyun /* *****************************************************
89*4882a593Smuzhiyun  *					Firmware Header(8-byte alinment required)
90*4882a593Smuzhiyun  * *****************************************************
91*4882a593Smuzhiyun  * --- LONG WORD 0 ---- */
92*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SIGNATURE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
93*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_CATEGORY_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
94*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_FUNCTION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
95*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_VERSION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
96*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SUB_VER_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
97*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD1_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /* --- LONG WORD 1 ---- */
100*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MONTH_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
101*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_DATE_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
102*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_HOUR_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
103*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MINUTE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
104*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_ROMCODE_SIZE_8812(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
105*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD2_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* --- LONG WORD 2 ---- */
108*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SVN_IDX_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
109*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD3_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* --- LONG WORD 3 ---- */
112*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD4_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
113*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD5_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun #endif /* download firmware related data structure */
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define DRIVER_EARLY_INT_TIME_8812		0x05
119*4882a593Smuzhiyun #define BCN_DMA_ATIME_INT_TIME_8812		0x02
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /* for 8812
122*4882a593Smuzhiyun  * TX 128K, RX 16K, Page size 512B for TX, 128B for RX */
123*4882a593Smuzhiyun #define MAX_RX_DMA_BUFFER_SIZE_8812	0x3E80 /* RX 16K */
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
126*4882a593Smuzhiyun 	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
127*4882a593Smuzhiyun #else
128*4882a593Smuzhiyun 	#define RESV_FMWF	0
129*4882a593Smuzhiyun #endif
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_DEBUG
132*4882a593Smuzhiyun 	#define RX_DMA_RESERVED_SIZE_8812	0x100	/* 256B, reserved for c2h debug message */
133*4882a593Smuzhiyun #else
134*4882a593Smuzhiyun 	#define RX_DMA_RESERVED_SIZE_8812	0x0	/* 0B */
135*4882a593Smuzhiyun #endif
136*4882a593Smuzhiyun #define RX_DMA_BOUNDARY_8812		(MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1)
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun #define PAGE_SIZE_TX_8812A PAGE_SIZE_512
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A
141*4882a593Smuzhiyun  * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
142*4882a593Smuzhiyun #define BCNQ_PAGE_NUM_8812		(MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun /* For WoWLan , more reserved page
145*4882a593Smuzhiyun  * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6
146*4882a593Smuzhiyun  * NS offload: 1 NDP info: 1
147*4882a593Smuzhiyun  */
148*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
149*4882a593Smuzhiyun 	#define WOWLAN_PAGE_NUM_8812	0x08
150*4882a593Smuzhiyun #else
151*4882a593Smuzhiyun 	#define WOWLAN_PAGE_NUM_8812	0x00
152*4882a593Smuzhiyun #endif
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMER_FW_NDPA
156*4882a593Smuzhiyun 	#define FW_NDPA_PAGE_NUM	0x02
157*4882a593Smuzhiyun #else
158*4882a593Smuzhiyun 	#define FW_NDPA_PAGE_NUM	0x00
159*4882a593Smuzhiyun #endif
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun #ifdef DBG_FW_DEBUG_MSG_PKT
162*4882a593Smuzhiyun 	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x01
163*4882a593Smuzhiyun #else
164*4882a593Smuzhiyun 	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x00
165*4882a593Smuzhiyun #endif /*DBG_FW_DEBUG_MSG_PKT*/
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define TX_TOTAL_PAGE_NUMBER_8812	(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812)
168*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_8812			(TX_TOTAL_PAGE_NUMBER_8812 + 1)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_WOWLAN_8812		(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1)
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812	TX_TOTAL_PAGE_NUMBER_8812
173*4882a593Smuzhiyun #define WMM_NORMAL_TX_PAGE_BOUNDARY_8812		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 + 1)
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun /* For Normal Chip Setting
176*4882a593Smuzhiyun  * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8812 */
177*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_LPQ_8812				0x10
178*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_HPQ_8812			0x10
179*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_NPQ_8812			0x00
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_HPQ_8812		0x30
182*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_LPQ_8812		0x20
183*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_NPQ_8812		0x20
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun /* for 8821A
187*4882a593Smuzhiyun  * TX 64K, RX 16K, Page size 256B for TX, 128B for RX */
188*4882a593Smuzhiyun #define PAGE_SIZE_TX_8821A					256
189*4882a593Smuzhiyun #define PAGE_SIZE_RX_8821A					128
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun #define MAX_RX_DMA_BUFFER_SIZE_8821			0x3E80 /* RX 16K */
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_DEBUG
194*4882a593Smuzhiyun 	#define RX_DMA_RESERVED_SIZE_8821	0x100	/* 256B, reserved for c2h debug message */
195*4882a593Smuzhiyun #else
196*4882a593Smuzhiyun 	#define RX_DMA_RESERVED_SIZE_8821	0x0	/* 0B */
197*4882a593Smuzhiyun #endif
198*4882a593Smuzhiyun #define RX_DMA_BOUNDARY_8821		(MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1)
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A
201*4882a593Smuzhiyun  * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun #define BCNQ_PAGE_NUM_8821		(MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun /* For WoWLan , more reserved page
207*4882a593Smuzhiyun  * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */
208*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
209*4882a593Smuzhiyun 	#define WOWLAN_PAGE_NUM_8821	0x06
210*4882a593Smuzhiyun #else
211*4882a593Smuzhiyun 	#define WOWLAN_PAGE_NUM_8821	0x00
212*4882a593Smuzhiyun #endif
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun #define TX_TOTAL_PAGE_NUMBER_8821	(0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)
215*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_8821				(TX_TOTAL_PAGE_NUMBER_8821 + 1)
216*4882a593Smuzhiyun /* #define TX_PAGE_BOUNDARY_WOWLAN_8821		0xE0 */
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821	TX_TOTAL_PAGE_NUMBER_8821
219*4882a593Smuzhiyun #define WMM_NORMAL_TX_PAGE_BOUNDARY_8821		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 + 1)
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun /* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
223*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_LPQ_8821			0x08/* 0x10 */
224*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_HPQ_8821		0x08/* 0x10 */
225*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_NPQ_8821		0x00
226*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_EPQ_8821			0x04
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_HPQ_8821		0x30
229*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_LPQ_8821		0x20
230*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_NPQ_8821		0x20
231*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_EPQ_8821		0x00
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun #define MCC_NORMAL_PAGE_NUM_HPQ_8821		0x10
234*4882a593Smuzhiyun #define MCC_NORMAL_PAGE_NUM_LPQ_8821		0x10
235*4882a593Smuzhiyun #define MCC_NORMAL_PAGE_NUM_NPQ_8821		0x10
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun #define	EFUSE_HIDDEN_812AU					0
238*4882a593Smuzhiyun #define	EFUSE_HIDDEN_812AU_VS				1
239*4882a593Smuzhiyun #define	EFUSE_HIDDEN_812AU_VL				2
240*4882a593Smuzhiyun #define	EFUSE_HIDDEN_812AU_VN				3
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun #if 0
243*4882a593Smuzhiyun #define EFUSE_REAL_CONTENT_LEN_JAGUAR		1024
244*4882a593Smuzhiyun #define HWSET_MAX_SIZE_JAGUAR					1024
245*4882a593Smuzhiyun #else
246*4882a593Smuzhiyun #define EFUSE_REAL_CONTENT_LEN_JAGUAR		512
247*4882a593Smuzhiyun #define HWSET_MAX_SIZE_JAGUAR					512
248*4882a593Smuzhiyun #endif
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun #define EFUSE_MAX_BANK_8812A					2
251*4882a593Smuzhiyun #define EFUSE_MAP_LEN_JAGUAR					512
252*4882a593Smuzhiyun #define EFUSE_MAX_SECTION_JAGUAR				64
253*4882a593Smuzhiyun #define EFUSE_MAX_WORD_UNIT_JAGUAR			4
254*4882a593Smuzhiyun #define EFUSE_IC_ID_OFFSET_JAGUAR				506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
255*4882a593Smuzhiyun #define AVAILABLE_EFUSE_ADDR_8812(addr)	(addr < EFUSE_REAL_CONTENT_LEN_JAGUAR)
256*4882a593Smuzhiyun /* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
257*4882a593Smuzhiyun  * 9bytes + 1byt + 5bytes and pre 1byte.
258*4882a593Smuzhiyun  * For worst case:
259*4882a593Smuzhiyun  * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */
260*4882a593Smuzhiyun #define EFUSE_OOB_PROTECT_BYTES_JAGUAR		18	/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
261*4882a593Smuzhiyun #define EFUSE_PROTECT_BYTES_BANK_JAGUAR		16
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun #define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
264*4882a593Smuzhiyun #define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun /* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun /* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
269*4882a593Smuzhiyun #define HAL_EFUSE_MEMORY
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /* ********************************************************
272*4882a593Smuzhiyun  *			EFUSE for BT definition
273*4882a593Smuzhiyun  * ******************************************************** */
274*4882a593Smuzhiyun #define BANK_NUM			2
275*4882a593Smuzhiyun #define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
276*4882a593Smuzhiyun #define EFUSE_BT_REAL_CONTENT_LEN	\
277*4882a593Smuzhiyun 	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
278*4882a593Smuzhiyun #define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
279*4882a593Smuzhiyun #define EFUSE_BT_MAX_SECTION		(EFUSE_BT_MAP_LEN / 8)
280*4882a593Smuzhiyun #define EFUSE_PROTECT_BYTES_BANK	16
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun #define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_BT_REAL_CONTENT_LEN)
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun #ifdef CONFIG_FILE_FWIMG
285*4882a593Smuzhiyun extern char *rtw_fw_file_path;
286*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
287*4882a593Smuzhiyun extern char *rtw_fw_wow_file_path;
288*4882a593Smuzhiyun #endif
289*4882a593Smuzhiyun #ifdef CONFIG_MP_INCLUDED
290*4882a593Smuzhiyun extern char *rtw_fw_mp_bt_file_path;
291*4882a593Smuzhiyun #endif
292*4882a593Smuzhiyun #endif
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun /* rtl8812_hal_init.c */
296*4882a593Smuzhiyun void	_8051Reset8812(PADAPTER padapter);
297*4882a593Smuzhiyun s32	FirmwareDownload8812(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
298*4882a593Smuzhiyun void	InitializeFirmwareVars8812(PADAPTER padapter);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun s32	_LLTWrite_8812A(PADAPTER Adapter, u32 address, u32 data);
301*4882a593Smuzhiyun s32	InitLLTTable8812A(PADAPTER padapter, u8 txpktbuf_bndy);
302*4882a593Smuzhiyun void InitRDGSetting8812A(PADAPTER padapter);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun void CheckAutoloadState8812A(PADAPTER padapter);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun /* EFuse */
307*4882a593Smuzhiyun u8	GetEEPROMSize8812A(PADAPTER padapter);
308*4882a593Smuzhiyun void InitPGData8812A(PADAPTER padapter);
309*4882a593Smuzhiyun void	Hal_EfuseParseIDCode8812A(PADAPTER padapter, u8 *hwinfo);
310*4882a593Smuzhiyun void	Hal_ReadPROMVersion8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
311*4882a593Smuzhiyun void	Hal_ReadTxPowerInfo8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
312*4882a593Smuzhiyun void	Hal_ReadBoardType8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
313*4882a593Smuzhiyun void	Hal_ReadThermalMeter_8812A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
314*4882a593Smuzhiyun void	Hal_ReadChannelPlan8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
315*4882a593Smuzhiyun void	Hal_EfuseParseXtal_8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
316*4882a593Smuzhiyun void	Hal_ReadAntennaDiversity8812A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
317*4882a593Smuzhiyun void	Hal_ReadAmplifierType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
318*4882a593Smuzhiyun void	Hal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
319*4882a593Smuzhiyun void	Hal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
320*4882a593Smuzhiyun void	Hal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
321*4882a593Smuzhiyun void	hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
322*4882a593Smuzhiyun #ifdef CONFIG_MP_INCLUDED
323*4882a593Smuzhiyun int	FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
324*4882a593Smuzhiyun #endif
325*4882a593Smuzhiyun void	Hal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter);
328*4882a593Smuzhiyun void Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
331*4882a593Smuzhiyun void Hal_DetectWoWMode(PADAPTER pAdapter);
332*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun void _InitBeaconParameters_8812A(PADAPTER padapter);
335*4882a593Smuzhiyun void SetBeaconRelatedRegisters8812A(PADAPTER padapter);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun void ReadRFType8812A(PADAPTER padapter);
338*4882a593Smuzhiyun void InitDefaultValue8821A(PADAPTER padapter);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun u8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
341*4882a593Smuzhiyun void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
342*4882a593Smuzhiyun u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
343*4882a593Smuzhiyun u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
344*4882a593Smuzhiyun void rtl8812_set_hal_ops(struct hal_ops *pHalFunc);
345*4882a593Smuzhiyun void init_hal_spec_8812a(_adapter *adapter);
346*4882a593Smuzhiyun void init_hal_spec_8821a(_adapter *adapter);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen);
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun void rtl8812_start_thread(PADAPTER padapter);
351*4882a593Smuzhiyun void rtl8812_stop_thread(PADAPTER padapter);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
354*4882a593Smuzhiyun BOOLEAN	InterruptRecognized8812AE(PADAPTER Adapter);
355*4882a593Smuzhiyun void	UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
356*4882a593Smuzhiyun void	InitTRXDescHwAddress8812AE(PADAPTER Adapter);
357*4882a593Smuzhiyun #endif
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
360*4882a593Smuzhiyun void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
361*4882a593Smuzhiyun #endif
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun void
364*4882a593Smuzhiyun Hal_PatchwithJaguar_8812(
365*4882a593Smuzhiyun 		PADAPTER				Adapter,
366*4882a593Smuzhiyun 		RT_MEDIA_STATUS		MediaStatus
367*4882a593Smuzhiyun );
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun #endif /* __RTL8188E_HAL_H__ */
370