xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/rtl8192f_hal.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __RTL8192F_HAL_H__
16*4882a593Smuzhiyun #define __RTL8192F_HAL_H__
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "hal_data.h"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include "rtl8192f_spec.h"
21*4882a593Smuzhiyun #include "rtl8192f_rf.h"
22*4882a593Smuzhiyun #include "rtl8192f_dm.h"
23*4882a593Smuzhiyun #include "rtl8192f_recv.h"
24*4882a593Smuzhiyun #include "rtl8192f_xmit.h"
25*4882a593Smuzhiyun #include "rtl8192f_cmd.h"
26*4882a593Smuzhiyun #include "rtl8192f_led.h"
27*4882a593Smuzhiyun #include "Hal8192FPwrSeq.h"
28*4882a593Smuzhiyun #include "Hal8192FPhyReg.h"
29*4882a593Smuzhiyun #include "Hal8192FPhyCfg.h"
30*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT
31*4882a593Smuzhiyun #include "rtl8192f_sreset.h"
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun #ifdef CONFIG_LPS_POFF
34*4882a593Smuzhiyun 	#include "rtl8192f_lps_poff.h"
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define FW_8192F_SIZE		0x8000
38*4882a593Smuzhiyun #define FW_8192F_START_ADDRESS	0x4000
39*4882a593Smuzhiyun #define FW_8192F_END_ADDRESS	0x5000 /* brian_zhang@realsil.com.cn */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\
42*4882a593Smuzhiyun 	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0)
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun typedef struct _RT_FIRMWARE {
45*4882a593Smuzhiyun 	FIRMWARE_SOURCE	eFWSource;
46*4882a593Smuzhiyun #ifdef CONFIG_EMBEDDED_FWIMG
47*4882a593Smuzhiyun 	u8			*szFwBuffer;
48*4882a593Smuzhiyun #else
49*4882a593Smuzhiyun 	u8			szFwBuffer[FW_8192F_SIZE];
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun 	u32			ulFwLength;
52*4882a593Smuzhiyun } RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun  * This structure must be cared byte-ordering
56*4882a593Smuzhiyun  *
57*4882a593Smuzhiyun  * Added by tynli. 2009.12.04. */
58*4882a593Smuzhiyun typedef struct _RT_8192F_FIRMWARE_HDR {
59*4882a593Smuzhiyun 	/* 8-byte alinment required */
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	/* --- LONG WORD 0 ---- */
62*4882a593Smuzhiyun 	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
63*4882a593Smuzhiyun 	u8		Category;	/* AP/NIC and USB/PCI */
64*4882a593Smuzhiyun 	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
65*4882a593Smuzhiyun 	u16		Version;		/* FW Version */
66*4882a593Smuzhiyun 	u16		Subversion;	/* FW Subversion, default 0x00 */
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	/* --- LONG WORD 1 ---- */
69*4882a593Smuzhiyun 	u8		Month;	/* Release time Month field */
70*4882a593Smuzhiyun 	u8		Date;	/* Release time Date field */
71*4882a593Smuzhiyun 	u8		Hour;	/* Release time Hour field */
72*4882a593Smuzhiyun 	u8		Minute;	/* Release time Minute field */
73*4882a593Smuzhiyun 	u16		RamCodeSize;	/* The size of RAM code */
74*4882a593Smuzhiyun 	u16		Rsvd2;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	/* --- LONG WORD 2 ---- */
77*4882a593Smuzhiyun 	u32		SvnIdx;	/* The SVN entry index */
78*4882a593Smuzhiyun 	u32		Rsvd3;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* --- LONG WORD 3 ---- */
81*4882a593Smuzhiyun 	u32		Rsvd4;
82*4882a593Smuzhiyun 	u32		Rsvd5;
83*4882a593Smuzhiyun } RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR;
84*4882a593Smuzhiyun #define DRIVER_EARLY_INT_TIME_8192F		0x05
85*4882a593Smuzhiyun #define BCN_DMA_ATIME_INT_TIME_8192F		0x02
86*4882a593Smuzhiyun /* for 8192F
87*4882a593Smuzhiyun  * TX 64K, RX 16K, Page size 256B for TX*/
88*4882a593Smuzhiyun #define PAGE_SIZE_TX_8192F			256
89*4882a593Smuzhiyun #define PAGE_SIZE_RX_8192F			8
90*4882a593Smuzhiyun #define TX_DMA_SIZE_8192F			0x10000/* 64K(TX) */
91*4882a593Smuzhiyun #define RX_DMA_SIZE_8192F			0x4000/* 16K(RX) */
92*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
93*4882a593Smuzhiyun 	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
94*4882a593Smuzhiyun #else
95*4882a593Smuzhiyun 	#define RESV_FMWF	0
96*4882a593Smuzhiyun #endif
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_DEBUG
99*4882a593Smuzhiyun 	#define RX_DMA_RESERVED_SIZE_8192F	0x100	/* 256B, reserved for c2h debug message */
100*4882a593Smuzhiyun #else
101*4882a593Smuzhiyun 	#define RX_DMA_RESERVED_SIZE_8192F	0xc0	/* 192B, reserved for tx report 24*8=192*/
102*4882a593Smuzhiyun #endif
103*4882a593Smuzhiyun #define RX_DMA_BOUNDARY_8192F\
104*4882a593Smuzhiyun 	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1)
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* Note: We will divide number of page equally for each queue other than public queue! */
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /* For General Reserved Page Number(Beacon Queue is reserved page)
110*4882a593Smuzhiyun  * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F
111*4882a593Smuzhiyun  * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
112*4882a593Smuzhiyun #define BCNQ_PAGE_NUM_8192F		(MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* For WoWLan , more reserved page
116*4882a593Smuzhiyun  * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
117*4882a593Smuzhiyun  * NS offload: 2 NDP info: 1
118*4882a593Smuzhiyun  */
119*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
120*4882a593Smuzhiyun 	#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
121*4882a593Smuzhiyun 	#define WOWLAN_KEEP_ALIVE_PAGE 0x02 /*for keep alive packet*/
122*4882a593Smuzhiyun 	#else
123*4882a593Smuzhiyun 	#define WOWLAN_KEEP_ALIVE_PAGE	0x00
124*4882a593Smuzhiyun 	#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
125*4882a593Smuzhiyun 	/* 7 pages for wow rsvd page + 2 pages for pattern */
126*4882a593Smuzhiyun 	#define WOWLAN_PAGE_NUM_8192F	(0x09 + WOWLAN_KEEP_ALIVE_PAGE)
127*4882a593Smuzhiyun #else
128*4882a593Smuzhiyun 	#define WOWLAN_PAGE_NUM_8192F	0x00
129*4882a593Smuzhiyun #endif
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun #ifdef CONFIG_WOW_PATTERN_IN_TXFIFO
132*4882a593Smuzhiyun 	/* REG_TXBUF_WKCAM_OFFSET 0x1B1[15:0] */
133*4882a593Smuzhiyun 	#define WKCAM_OFFSET_BIT_MASK 0xFFFF
134*4882a593Smuzhiyun 	#define WKCAM_OFFSET_BIT_MASK_OFFSET 0
135*4882a593Smuzhiyun #endif
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun #ifdef CONFIG_PNO_SUPPORT
138*4882a593Smuzhiyun 	#undef WOWLAN_PAGE_NUM_8192F
139*4882a593Smuzhiyun 	#define WOWLAN_PAGE_NUM_8192F	0x15
140*4882a593Smuzhiyun #endif
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #ifdef CONFIG_AP_WOWLAN
143*4882a593Smuzhiyun 	#define AP_WOWLAN_PAGE_NUM_8192F	0x02
144*4882a593Smuzhiyun #endif
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #ifdef DBG_LA_MODE
147*4882a593Smuzhiyun 	#define LA_MODE_PAGE_NUM 0xE0
148*4882a593Smuzhiyun #endif
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun #define MAX_RX_DMA_BUFFER_SIZE_8192F	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #ifdef DBG_LA_MODE
153*4882a593Smuzhiyun 	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - LA_MODE_PAGE_NUM)
154*4882a593Smuzhiyun #else
155*4882a593Smuzhiyun 	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F)
156*4882a593Smuzhiyun #endif
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_8192F		(TX_TOTAL_PAGE_NUMBER_8192F + 1)
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \
161*4882a593Smuzhiyun 	TX_TOTAL_PAGE_NUMBER_8192F
162*4882a593Smuzhiyun #define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \
163*4882a593Smuzhiyun 	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1)
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /* For Normal Chip Setting
166*4882a593Smuzhiyun  * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */
167*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_HPQ_8192F		0x8
168*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_LPQ_8192F		0x8
169*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_NPQ_8192F		0x8
170*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_EPQ_8192F		0x00
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun /* Note: For Normal Chip Setting, modify later */
173*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_HPQ_8192F		0x30
174*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_LPQ_8192F		0x20
175*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_NPQ_8192F		0x20
176*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_EPQ_8192F		0x00
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun #include "HalVerDef.h"
180*4882a593Smuzhiyun #include "hal_com.h"
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun #define HAL_EFUSE_MEMORY
185*4882a593Smuzhiyun #define HWSET_MAX_SIZE_8192F                512
186*4882a593Smuzhiyun #define EFUSE_REAL_CONTENT_LEN_8192F        512
187*4882a593Smuzhiyun #define EFUSE_MAP_LEN_8192F                 512
188*4882a593Smuzhiyun #define EFUSE_MAX_SECTION_8192F            64
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun /* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
191*4882a593Smuzhiyun #define EFUSE_IC_ID_OFFSET			506
192*4882a593Smuzhiyun #define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8192F)
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun #define EFUSE_ACCESS_ON		0x69
195*4882a593Smuzhiyun #define EFUSE_ACCESS_OFF	0x00
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun /* ********************************************************
198*4882a593Smuzhiyun  *			EFUSE for BT definition
199*4882a593Smuzhiyun  * ******************************************************** */
200*4882a593Smuzhiyun #define BANK_NUM			1
201*4882a593Smuzhiyun #define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
202*4882a593Smuzhiyun #define EFUSE_BT_REAL_CONTENT_LEN	1536/*512 * 3 */
203*4882a593Smuzhiyun /*	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/
204*4882a593Smuzhiyun #define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
205*4882a593Smuzhiyun #define EFUSE_BT_MAX_SECTION		128 /* 1024/8 */
206*4882a593Smuzhiyun #define EFUSE_PROTECT_BYTES_BANK	16
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun typedef enum tag_Package_Definition {
209*4882a593Smuzhiyun 	PACKAGE_DEFAULT,
210*4882a593Smuzhiyun 	PACKAGE_QFN32,
211*4882a593Smuzhiyun 	PACKAGE_QFN40,
212*4882a593Smuzhiyun 	PACKAGE_QFN46
213*4882a593Smuzhiyun } PACKAGE_TYPE_E;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun #define INCLUDE_MULTI_FUNC_BT(_Adapter) \
216*4882a593Smuzhiyun 	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
217*4882a593Smuzhiyun #define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
218*4882a593Smuzhiyun 	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #ifdef CONFIG_FILE_FWIMG
221*4882a593Smuzhiyun 	extern char *rtw_fw_file_path;
222*4882a593Smuzhiyun 	extern char *rtw_fw_wow_file_path;
223*4882a593Smuzhiyun 	#ifdef CONFIG_MP_INCLUDED
224*4882a593Smuzhiyun 		extern char *rtw_fw_mp_bt_file_path;
225*4882a593Smuzhiyun 	#endif /* CONFIG_MP_INCLUDED */
226*4882a593Smuzhiyun #endif /* CONFIG_FILE_FWIMG */
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun /* rtl8192f_hal_init.c */
229*4882a593Smuzhiyun s32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
230*4882a593Smuzhiyun void rtl8192f_FirmwareSelfReset(PADAPTER padapter);
231*4882a593Smuzhiyun void rtl8192f_InitializeFirmwareVars(PADAPTER padapter);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun void rtl8192f_InitAntenna_Selection(PADAPTER padapter);
234*4882a593Smuzhiyun void rtl8192f_DeinitAntenna_Selection(PADAPTER padapter);
235*4882a593Smuzhiyun void rtl8192f_CheckAntenna_Selection(PADAPTER padapter);
236*4882a593Smuzhiyun void rtl8192f_init_default_value(PADAPTER padapter);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun s32 rtl8192f_InitLLTTable(PADAPTER padapter);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
241*4882a593Smuzhiyun s32 CardDisableWithoutHWSM(PADAPTER padapter);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /* EFuse */
244*4882a593Smuzhiyun u8 GetEEPROMSize8192F(PADAPTER padapter);
245*4882a593Smuzhiyun void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
246*4882a593Smuzhiyun void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
247*4882a593Smuzhiyun void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,
248*4882a593Smuzhiyun 					u8 *PROMContent, BOOLEAN AutoLoadFail);
249*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
250*4882a593Smuzhiyun void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,
251*4882a593Smuzhiyun 				       u8 *hwinfo, BOOLEAN AutoLoadFail);
252*4882a593Smuzhiyun #endif /* CONFIG_BT_COEXIST */
253*4882a593Smuzhiyun void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,
254*4882a593Smuzhiyun 				   u8 *hwinfo, BOOLEAN AutoLoadFail);
255*4882a593Smuzhiyun void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,
256*4882a593Smuzhiyun 				  u8 *hwinfo, BOOLEAN AutoLoadFail);
257*4882a593Smuzhiyun void Hal_EfuseParseCustomerID_8192F(PADAPTER padapter,
258*4882a593Smuzhiyun 				    u8 *hwinfo, BOOLEAN AutoLoadFail);
259*4882a593Smuzhiyun void Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter,
260*4882a593Smuzhiyun 		u8 *hwinfo, BOOLEAN AutoLoadFail);
261*4882a593Smuzhiyun void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,
262*4882a593Smuzhiyun 			      u8 *hwinfo, u8 AutoLoadFail);
263*4882a593Smuzhiyun void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,
264*4882a593Smuzhiyun 				      u8 *hwinfo, u8 AutoLoadFail);
265*4882a593Smuzhiyun void Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
266*4882a593Smuzhiyun 				 u8 *hwinfo, BOOLEAN	AutoLoadFail);
267*4882a593Smuzhiyun void Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
268*4882a593Smuzhiyun 				   u8	*PROMContent, BOOLEAN AutoloadFail);
269*4882a593Smuzhiyun u8	Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
270*4882a593Smuzhiyun void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);
271*4882a593Smuzhiyun void init_hal_spec_8192f(_adapter *adapter);
272*4882a593Smuzhiyun u8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
273*4882a593Smuzhiyun void GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
274*4882a593Smuzhiyun u8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
275*4882a593Smuzhiyun u8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun /* register */
278*4882a593Smuzhiyun void rtl8192f_InitBeaconParameters(PADAPTER padapter);
279*4882a593Smuzhiyun void rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun void _InitMacAPLLSetting_8192F(PADAPTER Adapter);
282*4882a593Smuzhiyun void _8051Reset8192F(PADAPTER padapter);
283*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
284*4882a593Smuzhiyun 	void Hal_DetectWoWMode(PADAPTER pAdapter);
285*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun void rtl8192f_start_thread(_adapter *padapter);
288*4882a593Smuzhiyun void rtl8192f_stop_thread(_adapter *padapter);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
291*4882a593Smuzhiyun 	void rtl8192fs_init_checkbthang_workqueue(_adapter *adapter);
292*4882a593Smuzhiyun 	void rtl8192fs_free_checkbthang_workqueue(_adapter *adapter);
293*4882a593Smuzhiyun 	void rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter);
294*4882a593Smuzhiyun 	void rtl8192fs_hal_check_bt_hang(_adapter *adapter);
295*4882a593Smuzhiyun #endif
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
298*4882a593Smuzhiyun 	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
299*4882a593Smuzhiyun #endif
300*4882a593Smuzhiyun #ifdef CONFIG_MP_INCLUDED
301*4882a593Smuzhiyun int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
302*4882a593Smuzhiyun #endif
303*4882a593Smuzhiyun void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun u8 MRateToHwRate8192F(u8 rate);
306*4882a593Smuzhiyun u8 HwRateToMRate8192F(u8 rate);
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
309*4882a593Smuzhiyun 	void check_bt_status_work(void *data);
310*4882a593Smuzhiyun #endif
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun #ifdef CONFIG_AMPDU_PRETX_CD
316*4882a593Smuzhiyun void rtl8192f_pretx_cd_config(_adapter *adapter);
317*4882a593Smuzhiyun #endif
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
320*4882a593Smuzhiyun 	BOOLEAN	InterruptRecognized8192FE(PADAPTER Adapter);
321*4882a593Smuzhiyun 	void	UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
322*4882a593Smuzhiyun 	void InitMAC_TRXBD_8192FE(PADAPTER Adapter);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	u16 get_txbd_rw_reg(u16 ff_hwaddr);
325*4882a593Smuzhiyun #endif
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun #endif
328