1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8188E_SPEC_H__ 16*4882a593Smuzhiyun #define __RTL8188E_SPEC_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* ************************************************************ 20*4882a593Smuzhiyun * 8188E Regsiter offset definition 21*4882a593Smuzhiyun * ************************************************************ */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* ************************************************************ 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * ************************************************************ */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* ----------------------------------------------------- 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * 0x0000h ~ 0x00FFh System Configuration 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * ----------------------------------------------------- */ 33*4882a593Smuzhiyun #define REG_BB_PAD_CTRL 0x0064 34*4882a593Smuzhiyun #define REG_HMEBOX_E0 0x0088 35*4882a593Smuzhiyun #define REG_HMEBOX_E1 0x008A 36*4882a593Smuzhiyun #define REG_HMEBOX_E2 0x008C 37*4882a593Smuzhiyun #define REG_HMEBOX_E3 0x008E 38*4882a593Smuzhiyun #define REG_HMEBOX_EXT_0 0x01F0 39*4882a593Smuzhiyun #define REG_HMEBOX_EXT_1 0x01F4 40*4882a593Smuzhiyun #define REG_HMEBOX_EXT_2 0x01F8 41*4882a593Smuzhiyun #define REG_HMEBOX_EXT_3 0x01FC 42*4882a593Smuzhiyun #define REG_HIMR_88E 0x00B0 /* RTL8188E */ 43*4882a593Smuzhiyun #define REG_HISR_88E 0x00B4 /* RTL8188E */ 44*4882a593Smuzhiyun #define REG_HIMRE_88E 0x00B8 /* RTL8188E */ 45*4882a593Smuzhiyun #define REG_HISRE_88E 0x00BC /* RTL8188E */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define REG_DBI_WDATA_8188E 0x0348 /* DBI Write data */ 48*4882a593Smuzhiyun #define REG_DBI_RDATA_8188E 0x034C /* DBI Read data */ 49*4882a593Smuzhiyun #define REG_DBI_ADDR_8188E 0x0350 /* DBI Address */ 50*4882a593Smuzhiyun #define REG_DBI_FLAG_8188E 0x0352 /* DBI Read/Write Flag */ 51*4882a593Smuzhiyun #define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */ 52*4882a593Smuzhiyun #define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */ 53*4882a593Smuzhiyun #define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define REG_MACID_NO_LINK_0 0x0484 56*4882a593Smuzhiyun #define REG_MACID_NO_LINK_1 0x0488 57*4882a593Smuzhiyun #define REG_MACID_PAUSE_0 0x048c 58*4882a593Smuzhiyun #define REG_MACID_PAUSE_1 0x0490 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* ----------------------------------------------------- 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun * 0x0100h ~ 0x01FFh MACTOP General Configuration 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * ----------------------------------------------------- */ 65*4882a593Smuzhiyun #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 66*4882a593Smuzhiyun #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 67*4882a593Smuzhiyun #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 68*4882a593Smuzhiyun #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* ----------------------------------------------------- 71*4882a593Smuzhiyun * 72*4882a593Smuzhiyun * 0x0200h ~ 0x027Fh TXDMA Configuration 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun * ----------------------------------------------------- */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* ----------------------------------------------------- 77*4882a593Smuzhiyun * 78*4882a593Smuzhiyun * 0x0280h ~ 0x02FFh RXDMA Configuration 79*4882a593Smuzhiyun * 80*4882a593Smuzhiyun * ----------------------------------------------------- */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* ----------------------------------------------------- 83*4882a593Smuzhiyun * 84*4882a593Smuzhiyun * 0x0300h ~ 0x03FFh PCIe 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun * ----------------------------------------------------- */ 87*4882a593Smuzhiyun #define REG_PCIE_HRPWM_8188E 0x0361 /* PCIe RPWM */ 88*4882a593Smuzhiyun #define REG_PCIE_HCPWM_8188E 0x0363 /* PCIe CPWM */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* ----------------------------------------------------- 91*4882a593Smuzhiyun * 92*4882a593Smuzhiyun * 0x0400h ~ 0x047Fh Protocol Configuration 93*4882a593Smuzhiyun * 94*4882a593Smuzhiyun * ----------------------------------------------------- */ 95*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 96*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_LOW 0x01a4 97*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_HIGH 0x01a8 98*4882a593Smuzhiyun #endif 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* ----------------------------------------------------- 101*4882a593Smuzhiyun * 102*4882a593Smuzhiyun * 0x0500h ~ 0x05FFh EDCA Configuration 103*4882a593Smuzhiyun * 104*4882a593Smuzhiyun * ----------------------------------------------------- */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* ----------------------------------------------------- 107*4882a593Smuzhiyun * 108*4882a593Smuzhiyun * 0x0600h ~ 0x07FFh WMAC Configuration 109*4882a593Smuzhiyun * 110*4882a593Smuzhiyun * ----------------------------------------------------- */ 111*4882a593Smuzhiyun #ifdef CONFIG_RF_POWER_TRIM 112*4882a593Smuzhiyun #define EEPROM_RF_GAIN_OFFSET 0xC1 113*4882a593Smuzhiyun #define EEPROM_RF_GAIN_VAL 0xF6 114*4882a593Smuzhiyun #define EEPROM_THERMAL_OFFSET 0xF5 115*4882a593Smuzhiyun #endif /*CONFIG_RF_POWER_TRIM*/ 116*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 117*4882a593Smuzhiyun * 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) 118*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 119*4882a593Smuzhiyun * IOL config for REG_FDHM0(Reg0x88) */ 120*4882a593Smuzhiyun #define CMD_INIT_LLT BIT0 121*4882a593Smuzhiyun #define CMD_READ_EFUSE_MAP BIT1 122*4882a593Smuzhiyun #define CMD_EFUSE_PATCH BIT2 123*4882a593Smuzhiyun #define CMD_IOCONFIG BIT3 124*4882a593Smuzhiyun #define CMD_INIT_LLT_ERR BIT4 125*4882a593Smuzhiyun #define CMD_READ_EFUSE_MAP_ERR BIT5 126*4882a593Smuzhiyun #define CMD_EFUSE_PATCH_ERR BIT6 127*4882a593Smuzhiyun #define CMD_IOCONFIG_ERR BIT7 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* ----------------------------------------------------- 130*4882a593Smuzhiyun * 131*4882a593Smuzhiyun * Redifine register definition for compatibility 132*4882a593Smuzhiyun * 133*4882a593Smuzhiyun * ----------------------------------------------------- */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* TODO: use these definition when using REG_xxx naming rule. 136*4882a593Smuzhiyun * NOTE: DO NOT Remove these definition. Use later. */ 137*4882a593Smuzhiyun #define ISR_88E REG_HISR_88E 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 140*4882a593Smuzhiyun /* #define IMR_RX_MASK (IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */ 141*4882a593Smuzhiyun #define IMR_TX_MASK (IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 144*4882a593Smuzhiyun #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E) 145*4882a593Smuzhiyun #else 146*4882a593Smuzhiyun #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E) 147*4882a593Smuzhiyun #endif 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define RT_AC_INT_MASKS (IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E) 150*4882a593Smuzhiyun #endif 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 153*4882a593Smuzhiyun * 8192C EEPROM/EFUSE share register definition. 154*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ 157*4882a593Smuzhiyun #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #endif /* __RTL8188E_SPEC_H__ */ 160