1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun * more details.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __HAL_COMMON_H__
16*4882a593Smuzhiyun #define __HAL_COMMON_H__
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "HalVerDef.h"
19*4882a593Smuzhiyun #include "hal_pg.h"
20*4882a593Smuzhiyun #include "hal_phy.h"
21*4882a593Smuzhiyun #include "hal_phy_reg.h"
22*4882a593Smuzhiyun #include "hal_com_reg.h"
23*4882a593Smuzhiyun #include "hal_com_phycfg.h"
24*4882a593Smuzhiyun #include "../hal/hal_com_c2h.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*------------------------------ Tx Desc definition Macro ------------------------*/
27*4882a593Smuzhiyun /* #pragma mark -- Tx Desc related definition. -- */
28*4882a593Smuzhiyun /* ----------------------------------------------------------------------------
29*4882a593Smuzhiyun * -----------------------------------------------------------
30*4882a593Smuzhiyun * Rate
31*4882a593Smuzhiyun * -----------------------------------------------------------
32*4882a593Smuzhiyun * CCK Rates, TxHT = 0 */
33*4882a593Smuzhiyun #define DESC_RATE1M 0x00
34*4882a593Smuzhiyun #define DESC_RATE2M 0x01
35*4882a593Smuzhiyun #define DESC_RATE5_5M 0x02
36*4882a593Smuzhiyun #define DESC_RATE11M 0x03
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* OFDM Rates, TxHT = 0 */
39*4882a593Smuzhiyun #define DESC_RATE6M 0x04
40*4882a593Smuzhiyun #define DESC_RATE9M 0x05
41*4882a593Smuzhiyun #define DESC_RATE12M 0x06
42*4882a593Smuzhiyun #define DESC_RATE18M 0x07
43*4882a593Smuzhiyun #define DESC_RATE24M 0x08
44*4882a593Smuzhiyun #define DESC_RATE36M 0x09
45*4882a593Smuzhiyun #define DESC_RATE48M 0x0a
46*4882a593Smuzhiyun #define DESC_RATE54M 0x0b
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* MCS Rates, TxHT = 1 */
49*4882a593Smuzhiyun #define DESC_RATEMCS0 0x0c
50*4882a593Smuzhiyun #define DESC_RATEMCS1 0x0d
51*4882a593Smuzhiyun #define DESC_RATEMCS2 0x0e
52*4882a593Smuzhiyun #define DESC_RATEMCS3 0x0f
53*4882a593Smuzhiyun #define DESC_RATEMCS4 0x10
54*4882a593Smuzhiyun #define DESC_RATEMCS5 0x11
55*4882a593Smuzhiyun #define DESC_RATEMCS6 0x12
56*4882a593Smuzhiyun #define DESC_RATEMCS7 0x13
57*4882a593Smuzhiyun #define DESC_RATEMCS8 0x14
58*4882a593Smuzhiyun #define DESC_RATEMCS9 0x15
59*4882a593Smuzhiyun #define DESC_RATEMCS10 0x16
60*4882a593Smuzhiyun #define DESC_RATEMCS11 0x17
61*4882a593Smuzhiyun #define DESC_RATEMCS12 0x18
62*4882a593Smuzhiyun #define DESC_RATEMCS13 0x19
63*4882a593Smuzhiyun #define DESC_RATEMCS14 0x1a
64*4882a593Smuzhiyun #define DESC_RATEMCS15 0x1b
65*4882a593Smuzhiyun #define DESC_RATEMCS16 0x1C
66*4882a593Smuzhiyun #define DESC_RATEMCS17 0x1D
67*4882a593Smuzhiyun #define DESC_RATEMCS18 0x1E
68*4882a593Smuzhiyun #define DESC_RATEMCS19 0x1F
69*4882a593Smuzhiyun #define DESC_RATEMCS20 0x20
70*4882a593Smuzhiyun #define DESC_RATEMCS21 0x21
71*4882a593Smuzhiyun #define DESC_RATEMCS22 0x22
72*4882a593Smuzhiyun #define DESC_RATEMCS23 0x23
73*4882a593Smuzhiyun #define DESC_RATEMCS24 0x24
74*4882a593Smuzhiyun #define DESC_RATEMCS25 0x25
75*4882a593Smuzhiyun #define DESC_RATEMCS26 0x26
76*4882a593Smuzhiyun #define DESC_RATEMCS27 0x27
77*4882a593Smuzhiyun #define DESC_RATEMCS28 0x28
78*4882a593Smuzhiyun #define DESC_RATEMCS29 0x29
79*4882a593Smuzhiyun #define DESC_RATEMCS30 0x2A
80*4882a593Smuzhiyun #define DESC_RATEMCS31 0x2B
81*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS0 0x2C
82*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS1 0x2D
83*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS2 0x2E
84*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS3 0x2F
85*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS4 0x30
86*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS5 0x31
87*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS6 0x32
88*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS7 0x33
89*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS8 0x34
90*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS9 0x35
91*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS0 0x36
92*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS1 0x37
93*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS2 0x38
94*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS3 0x39
95*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS4 0x3A
96*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS5 0x3B
97*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS6 0x3C
98*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS7 0x3D
99*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS8 0x3E
100*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS9 0x3F
101*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS0 0x40
102*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS1 0x41
103*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS2 0x42
104*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS3 0x43
105*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS4 0x44
106*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS5 0x45
107*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS6 0x46
108*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS7 0x47
109*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS8 0x48
110*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS9 0x49
111*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS0 0x4A
112*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS1 0x4B
113*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS2 0x4C
114*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS3 0x4D
115*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS4 0x4E
116*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS5 0x4F
117*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS6 0x50
118*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS7 0x51
119*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS8 0x52
120*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS9 0x53
121*4882a593Smuzhiyun #define DESC_RATE_NUM 0x54
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #define IS_CCK_HRATE(_rate) ((_rate) <= DESC_RATE11M)
124*4882a593Smuzhiyun #define IS_OFDM_HRATE(_rate) ((_rate) >= DESC_RATE6M && (_rate) <= DESC_RATE54M)
125*4882a593Smuzhiyun #define IS_LEGACY_HRATE(_rate) ((_rate) <= DESC_RATE54M)
126*4882a593Smuzhiyun #define IS_HT_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS31)
127*4882a593Smuzhiyun #define IS_VHT_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define IS_HT1SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS7)
130*4882a593Smuzhiyun #define IS_HT2SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS8 && (_rate) <= DESC_RATEMCS15)
131*4882a593Smuzhiyun #define IS_HT3SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS16 && (_rate) <= DESC_RATEMCS23)
132*4882a593Smuzhiyun #define IS_HT4SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS24 && (_rate) <= DESC_RATEMCS31)
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #define IS_VHT1SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS1MCS9)
135*4882a593Smuzhiyun #define IS_VHT2SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS2MCS0 && (_rate) <= DESC_RATEVHTSS2MCS9)
136*4882a593Smuzhiyun #define IS_VHT3SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS3MCS0 && (_rate) <= DESC_RATEVHTSS3MCS9)
137*4882a593Smuzhiyun #define IS_VHT4SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS4MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #define IS_1SS_HRATE(_rate) (IS_CCK_HRATE((_rate)) || IS_OFDM_HRATE((_rate)) || IS_HT1SS_HRATE((_rate)) || IS_VHT1SS_HRATE((_rate)))
140*4882a593Smuzhiyun #define IS_2SS_HRATE(_rate) (IS_HT2SS_HRATE((_rate)) || IS_VHT2SS_HRATE((_rate)))
141*4882a593Smuzhiyun #define IS_3SS_HRATE(_rate) (IS_HT3SS_HRATE((_rate)) || IS_VHT3SS_HRATE((_rate)))
142*4882a593Smuzhiyun #define IS_4SS_HRATE(_rate) (IS_HT4SS_HRATE((_rate)) || IS_VHT4SS_HRATE((_rate)))
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #define HRARE_SS_NUM(_rate) (IS_1SS_HRATE(_rate) ? 1 : (IS_2SS_HRATE(_rate) ? 2 : (IS_3SS_HRATE(_rate) ? 3 : (IS_4SS_HRATE(_rate) ? 4 : 0))))
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun extern const char * const _HDATA_RATE[];
147*4882a593Smuzhiyun #define HDATA_RATE(rate) ((rate) >= DESC_RATE_NUM ? _HDATA_RATE[DESC_RATE_NUM] : _HDATA_RATE[rate])
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun enum {
150*4882a593Smuzhiyun UP_LINK,
151*4882a593Smuzhiyun DOWN_LINK,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun typedef enum _RT_MEDIA_STATUS {
154*4882a593Smuzhiyun RT_MEDIA_DISCONNECT = 0,
155*4882a593Smuzhiyun RT_MEDIA_CONNECT = 1
156*4882a593Smuzhiyun } RT_MEDIA_STATUS;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define MAX_DLFW_PAGE_SIZE 4096 /* @ page : 4k bytes */
159*4882a593Smuzhiyun typedef enum _FIRMWARE_SOURCE {
160*4882a593Smuzhiyun FW_SOURCE_IMG_FILE = 0,
161*4882a593Smuzhiyun FW_SOURCE_HEADER_FILE = 1, /* from header file */
162*4882a593Smuzhiyun } FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun typedef enum _CH_SW_USE_CASE {
165*4882a593Smuzhiyun CH_SW_USE_CASE_TDLS = 0,
166*4882a593Smuzhiyun CH_SW_USE_CASE_MCC = 1
167*4882a593Smuzhiyun } CH_SW_USE_CASE;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun typedef enum _WAKEUP_REASON{
170*4882a593Smuzhiyun RX_PAIRWISEKEY = 0x01,
171*4882a593Smuzhiyun RX_GTK = 0x02,
172*4882a593Smuzhiyun RX_FOURWAY_HANDSHAKE = 0x03,
173*4882a593Smuzhiyun RX_DISASSOC = 0x04,
174*4882a593Smuzhiyun RX_DEAUTH = 0x08,
175*4882a593Smuzhiyun RX_ARP_REQUEST = 0x09,
176*4882a593Smuzhiyun FW_DECISION_DISCONNECT = 0x10,
177*4882a593Smuzhiyun RX_MAGIC_PKT = 0x21,
178*4882a593Smuzhiyun RX_UNICAST_PKT = 0x22,
179*4882a593Smuzhiyun RX_PATTERN_PKT = 0x23,
180*4882a593Smuzhiyun RTD3_SSID_MATCH = 0x24,
181*4882a593Smuzhiyun RX_REALWOW_V2_WAKEUP_PKT = 0x30,
182*4882a593Smuzhiyun RX_REALWOW_V2_ACK_LOST = 0x31,
183*4882a593Smuzhiyun ENABLE_FAIL_DMA_IDLE = 0x40,
184*4882a593Smuzhiyun ENABLE_FAIL_DMA_PAUSE = 0x41,
185*4882a593Smuzhiyun RTIME_FAIL_DMA_IDLE = 0x42,
186*4882a593Smuzhiyun RTIME_FAIL_DMA_PAUSE = 0x43,
187*4882a593Smuzhiyun RX_PNO = 0x55,
188*4882a593Smuzhiyun #ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
189*4882a593Smuzhiyun WOW_KEEPALIVE_ACK_TIMEOUT = 0x60,
190*4882a593Smuzhiyun WOW_KEEPALIVE_WAKE = 0x61,
191*4882a593Smuzhiyun #endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
192*4882a593Smuzhiyun AP_OFFLOAD_WAKEUP = 0x66,
193*4882a593Smuzhiyun CLK_32K_UNLOCK = 0xFD,
194*4882a593Smuzhiyun CLK_32K_LOCK = 0xFE
195*4882a593Smuzhiyun }WAKEUP_REASON;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun typedef enum _BCN_EARLY_INT_CASE{
198*4882a593Smuzhiyun TDLS_BCN_ERLY_ON,
199*4882a593Smuzhiyun TDLS_BCN_ERLY_OFF
200*4882a593Smuzhiyun }BCN_EARLY_INT_CASE;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /*
203*4882a593Smuzhiyun * Queue Select Value in TxDesc
204*4882a593Smuzhiyun * */
205*4882a593Smuzhiyun #define QSLT_BK 0x2/* 0x01 */
206*4882a593Smuzhiyun #define QSLT_BE 0x0
207*4882a593Smuzhiyun #define QSLT_VI 0x5/* 0x4 */
208*4882a593Smuzhiyun #define QSLT_VO 0x7/* 0x6 */
209*4882a593Smuzhiyun #define QSLT_BEACON 0x10
210*4882a593Smuzhiyun #define QSLT_HIGH 0x11
211*4882a593Smuzhiyun #define QSLT_MGNT 0x12
212*4882a593Smuzhiyun #define QSLT_CMD 0x13
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
215*4882a593Smuzhiyun * #define MAX_TX_QUEUE 9 */
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun #define TX_SELE_HQ BIT(0) /* High Queue */
218*4882a593Smuzhiyun #define TX_SELE_LQ BIT(1) /* Low Queue */
219*4882a593Smuzhiyun #define TX_SELE_NQ BIT(2) /* Normal Queue */
220*4882a593Smuzhiyun #define TX_SELE_EQ BIT(3) /* Extern Queue */
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun #define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
223*4882a593Smuzhiyun #define PageNum_256(_Len) (u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))
224*4882a593Smuzhiyun #define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))
225*4882a593Smuzhiyun #define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun struct dbg_rx_counter {
228*4882a593Smuzhiyun u32 rx_pkt_ok;
229*4882a593Smuzhiyun u32 rx_pkt_crc_error;
230*4882a593Smuzhiyun u32 rx_pkt_drop;
231*4882a593Smuzhiyun u32 rx_ofdm_fa;
232*4882a593Smuzhiyun u32 rx_cck_fa;
233*4882a593Smuzhiyun u32 rx_ht_fa;
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun u8 rtw_hal_get_port(_adapter *adapter);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun #ifdef CONFIG_MBSSID_CAM
239*4882a593Smuzhiyun /*#define DBG_MBID_CAM_DUMP*/
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun void rtw_mbid_cam_init(struct dvobj_priv *dvobj);
242*4882a593Smuzhiyun void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);
243*4882a593Smuzhiyun void rtw_mbid_cam_reset(_adapter *adapter);
244*4882a593Smuzhiyun u8 rtw_get_max_mbid_cam_id(_adapter *adapter);
245*4882a593Smuzhiyun u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
246*4882a593Smuzhiyun int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
247*4882a593Smuzhiyun int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
248*4882a593Smuzhiyun void rtw_mi_set_mbid_cam(_adapter *adapter);
249*4882a593Smuzhiyun u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
250*4882a593Smuzhiyun void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);
251*4882a593Smuzhiyun void rtw_mbid_cam_enable(_adapter *adapter);
252*4882a593Smuzhiyun #endif
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun #ifdef CONFIG_MI_WITH_MBSSID_CAM
255*4882a593Smuzhiyun void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
256*4882a593Smuzhiyun void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
257*4882a593Smuzhiyun #ifdef CONFIG_SWTIMER_BASED_TXBCN
258*4882a593Smuzhiyun u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
259*4882a593Smuzhiyun #endif
260*4882a593Smuzhiyun void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
261*4882a593Smuzhiyun #endif
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
264*4882a593Smuzhiyun void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
265*4882a593Smuzhiyun void rtw_reset_mac_rx_counters(_adapter *padapter);
266*4882a593Smuzhiyun void rtw_reset_phy_rx_counters(_adapter *padapter);
267*4882a593Smuzhiyun void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun #ifdef DBG_RX_COUNTER_DUMP
270*4882a593Smuzhiyun #define DUMP_DRV_RX_COUNTER BIT0
271*4882a593Smuzhiyun #define DUMP_MAC_RX_COUNTER BIT1
272*4882a593Smuzhiyun #define DUMP_PHY_RX_COUNTER BIT2
273*4882a593Smuzhiyun #define DUMP_DRV_TRX_COUNTER_DATA BIT3
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);
276*4882a593Smuzhiyun void rtw_dump_rx_counters(_adapter *padapter);
277*4882a593Smuzhiyun #endif
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun void dump_chip_info(HAL_VERSION ChipVersion);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun #define BAND_CAP_2G BIT0
282*4882a593Smuzhiyun #define BAND_CAP_5G BIT1
283*4882a593Smuzhiyun #define BAND_CAP_BIT_NUM 2
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun #define BW_CAP_5M BIT0
286*4882a593Smuzhiyun #define BW_CAP_10M BIT1
287*4882a593Smuzhiyun #define BW_CAP_20M BIT2
288*4882a593Smuzhiyun #define BW_CAP_40M BIT3
289*4882a593Smuzhiyun #define BW_CAP_80M BIT4
290*4882a593Smuzhiyun #define BW_CAP_160M BIT5
291*4882a593Smuzhiyun #define BW_CAP_80_80M BIT6
292*4882a593Smuzhiyun #define BW_CAP_BIT_NUM 7
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun #define PROTO_CAP_11B BIT0
295*4882a593Smuzhiyun #define PROTO_CAP_11G BIT1
296*4882a593Smuzhiyun #define PROTO_CAP_11N BIT2
297*4882a593Smuzhiyun #define PROTO_CAP_11AC BIT3
298*4882a593Smuzhiyun #define PROTO_CAP_BIT_NUM 4
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun #define WL_FUNC_P2P BIT0
301*4882a593Smuzhiyun #define WL_FUNC_MIRACAST BIT1
302*4882a593Smuzhiyun #define WL_FUNC_TDLS BIT2
303*4882a593Smuzhiyun #define WL_FUNC_FTM BIT3
304*4882a593Smuzhiyun #define WL_FUNC_BIT_NUM 4
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun #define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */
307*4882a593Smuzhiyun #define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/
308*4882a593Smuzhiyun #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun int hal_spec_init(_adapter *adapter);
311*4882a593Smuzhiyun void dump_hal_spec(void *sel, _adapter *adapter);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun bool hal_chk_band_cap(_adapter *adapter, u8 cap);
314*4882a593Smuzhiyun bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
315*4882a593Smuzhiyun bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
316*4882a593Smuzhiyun bool hal_is_band_support(_adapter *adapter, u8 band);
317*4882a593Smuzhiyun bool hal_is_bw_support(_adapter *adapter, u8 bw);
318*4882a593Smuzhiyun bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
319*4882a593Smuzhiyun bool hal_is_mimo_support(_adapter *adapter);
320*4882a593Smuzhiyun u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun bool hal_chk_wl_func(_adapter *adapter, u8 func);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun void hal_com_config_channel_plan(
325*4882a593Smuzhiyun PADAPTER padapter,
326*4882a593Smuzhiyun char *hw_alpha2,
327*4882a593Smuzhiyun u8 hw_chplan,
328*4882a593Smuzhiyun char *sw_alpha2,
329*4882a593Smuzhiyun u8 sw_chplan,
330*4882a593Smuzhiyun BOOLEAN AutoLoadFail
331*4882a593Smuzhiyun );
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
334*4882a593Smuzhiyun #ifdef RTW_HALMAC
335*4882a593Smuzhiyun void rtw_hal_hw_port_enable(_adapter *adapter);
336*4882a593Smuzhiyun void rtw_hal_hw_port_disable(_adapter *adapter);
337*4882a593Smuzhiyun #endif
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun BOOLEAN
340*4882a593Smuzhiyun HAL_IsLegalChannel(
341*4882a593Smuzhiyun PADAPTER Adapter,
342*4882a593Smuzhiyun u32 Channel
343*4882a593Smuzhiyun );
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun u8 MRateToHwRate(enum MGN_RATE rate);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun u8 hw_rate_to_m_rate(u8 hw_rate);
348*4882a593Smuzhiyun #ifdef CONFIG_RTW_DEBUG
349*4882a593Smuzhiyun void dump_hw_rate_map_test(void *sel);
350*4882a593Smuzhiyun #endif
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun void HalSetBrateCfg(
353*4882a593Smuzhiyun PADAPTER Adapter,
354*4882a593Smuzhiyun u8 *mBratesOS,
355*4882a593Smuzhiyun u16 *pBrateCfg);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun BOOLEAN
358*4882a593Smuzhiyun Hal_MappingOutPipe(
359*4882a593Smuzhiyun PADAPTER pAdapter,
360*4882a593Smuzhiyun u8 NumOutPipe
361*4882a593Smuzhiyun );
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun void rtw_dump_fw_info(void *sel, _adapter *adapter);
364*4882a593Smuzhiyun void rtw_restore_hw_port_cfg(_adapter *adapter);
365*4882a593Smuzhiyun void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
366*4882a593Smuzhiyun void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun void rtw_init_hal_com_default_value(PADAPTER Adapter);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_REG
371*4882a593Smuzhiyun void c2h_evt_clear(_adapter *adapter);
372*4882a593Smuzhiyun s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
373*4882a593Smuzhiyun #endif
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_PKT
376*4882a593Smuzhiyun void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);
377*4882a593Smuzhiyun void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);
378*4882a593Smuzhiyun #endif
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);
383*4882a593Smuzhiyun s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);
384*4882a593Smuzhiyun s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);
385*4882a593Smuzhiyun void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /* access HW only */
388*4882a593Smuzhiyun u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
389*4882a593Smuzhiyun void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
390*4882a593Smuzhiyun void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
391*4882a593Smuzhiyun void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
392*4882a593Smuzhiyun void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);
393*4882a593Smuzhiyun bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
398*4882a593Smuzhiyun u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
399*4882a593Smuzhiyun void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
400*4882a593Smuzhiyun void rtw_hal_rcr_set_chk_bssid_act_non(_adapter *adapter);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun void rtw_iface_enable_tsf_update(_adapter *adapter);
403*4882a593Smuzhiyun void rtw_iface_disable_tsf_update(_adapter *adapter);
404*4882a593Smuzhiyun void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
405*4882a593Smuzhiyun void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun #if CONFIG_TX_AC_LIFETIME
408*4882a593Smuzhiyun #define TX_ACLT_CONF_DEFAULT 0
409*4882a593Smuzhiyun #define TX_ACLT_CONF_AP_M2U 1
410*4882a593Smuzhiyun #define TX_ACLT_CONF_MESH 2
411*4882a593Smuzhiyun #define TX_ACLT_CONF_NUM 3
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun extern const char *const _tx_aclt_conf_str[];
414*4882a593Smuzhiyun #define tx_aclt_conf_str(conf) (((conf) >= TX_ACLT_CONF_NUM) ? _tx_aclt_conf_str[TX_ACLT_CONF_NUM] : _tx_aclt_conf_str[(conf)])
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun struct tx_aclt_conf_t {
417*4882a593Smuzhiyun u8 en;
418*4882a593Smuzhiyun u32 vo_vi;
419*4882a593Smuzhiyun u32 be_bk;
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj);
423*4882a593Smuzhiyun void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num);
424*4882a593Smuzhiyun void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj);
425*4882a593Smuzhiyun void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num);
426*4882a593Smuzhiyun void rtw_hal_update_tx_aclt(_adapter *adapter);
427*4882a593Smuzhiyun #endif
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun void hw_var_port_switch(_adapter *adapter);
430*4882a593Smuzhiyun void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val);
431*4882a593Smuzhiyun u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
432*4882a593Smuzhiyun void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
433*4882a593Smuzhiyun void rtw_hal_check_rxfifo_full(_adapter *adapter);
434*4882a593Smuzhiyun void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
437*4882a593Smuzhiyun u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun u32
440*4882a593Smuzhiyun MapCharToHexDigit(
441*4882a593Smuzhiyun char chTmp
442*4882a593Smuzhiyun );
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun BOOLEAN
445*4882a593Smuzhiyun GetHexValueFromString(
446*4882a593Smuzhiyun char *szStr,
447*4882a593Smuzhiyun u32 *pu4bVal,
448*4882a593Smuzhiyun u32 *pu4bMove
449*4882a593Smuzhiyun );
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun BOOLEAN
452*4882a593Smuzhiyun GetFractionValueFromString(
453*4882a593Smuzhiyun char *szStr,
454*4882a593Smuzhiyun u8 *pInteger,
455*4882a593Smuzhiyun u8 *pFraction,
456*4882a593Smuzhiyun u32 *pu4bMove
457*4882a593Smuzhiyun );
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun BOOLEAN
460*4882a593Smuzhiyun IsCommentString(
461*4882a593Smuzhiyun char *szStr
462*4882a593Smuzhiyun );
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun BOOLEAN
465*4882a593Smuzhiyun ParseQualifiedString(
466*4882a593Smuzhiyun char *In,
467*4882a593Smuzhiyun u32 *Start,
468*4882a593Smuzhiyun char *Out,
469*4882a593Smuzhiyun char LeftQualifier,
470*4882a593Smuzhiyun char RightQualifier
471*4882a593Smuzhiyun );
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun BOOLEAN
474*4882a593Smuzhiyun GetU1ByteIntegerFromStringInDecimal(
475*4882a593Smuzhiyun char *Str,
476*4882a593Smuzhiyun u8 *pInt
477*4882a593Smuzhiyun );
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun BOOLEAN
480*4882a593Smuzhiyun isAllSpaceOrTab(
481*4882a593Smuzhiyun u8 *data,
482*4882a593Smuzhiyun u8 size
483*4882a593Smuzhiyun );
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun void linked_info_dump(_adapter *padapter, u8 benable);
486*4882a593Smuzhiyun #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
487*4882a593Smuzhiyun void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
488*4882a593Smuzhiyun void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
489*4882a593Smuzhiyun #endif
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun #ifdef DBG_RX_DFRAME_RAW_DATA
492*4882a593Smuzhiyun void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
493*4882a593Smuzhiyun #endif
494*4882a593Smuzhiyun void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
495*4882a593Smuzhiyun #define HWSET_MAX_SIZE 1024
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun #ifdef CONFIG_EFUSE_CONFIG_FILE
498*4882a593Smuzhiyun u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
499*4882a593Smuzhiyun u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
500*4882a593Smuzhiyun #endif /* CONFIG_EFUSE_CONFIG_FILE */
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun int hal_efuse_macaddr_offset(_adapter *adapter);
503*4882a593Smuzhiyun int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
504*4882a593Smuzhiyun void rtw_dump_cur_efuse(PADAPTER padapter);
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun #ifdef CONFIG_RF_POWER_TRIM
507*4882a593Smuzhiyun void rtw_bb_rf_gain_offset(_adapter *padapter);
508*4882a593Smuzhiyun #endif /*CONFIG_RF_POWER_TRIM*/
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
511*4882a593Smuzhiyun u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
514*4882a593Smuzhiyun u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
515*4882a593Smuzhiyun #ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
516*4882a593Smuzhiyun void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx);
517*4882a593Smuzhiyun #endif
518*4882a593Smuzhiyun void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
519*4882a593Smuzhiyun u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun #ifdef CONFIG_TSF_RESET_OFFLOAD
522*4882a593Smuzhiyun int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
523*4882a593Smuzhiyun #endif
524*4882a593Smuzhiyun u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun #ifdef CONFIG_TDLS
527*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW
528*4882a593Smuzhiyun s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
529*4882a593Smuzhiyun #endif
530*4882a593Smuzhiyun #endif
531*4882a593Smuzhiyun #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
532*4882a593Smuzhiyun s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);
533*4882a593Smuzhiyun #endif
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun #ifdef CONFIG_GPIO_API
538*4882a593Smuzhiyun u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);
539*4882a593Smuzhiyun int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);
540*4882a593Smuzhiyun int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);
541*4882a593Smuzhiyun int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));
542*4882a593Smuzhiyun int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);
543*4882a593Smuzhiyun #endif
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
546*4882a593Smuzhiyun void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
547*4882a593Smuzhiyun void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
550*4882a593Smuzhiyun void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
551*4882a593Smuzhiyun void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
552*4882a593Smuzhiyun void rtw_hal_set_input_gpio(_adapter *padapter, u8 index);
553*4882a593Smuzhiyun #define GPIO_OUTPUT_LOW 0
554*4882a593Smuzhiyun #define GPIO_OUTPUT_HIGH 1
555*4882a593Smuzhiyun #endif
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
558*4882a593Smuzhiyun extern char *rtw_phy_file_path;
559*4882a593Smuzhiyun extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
560*4882a593Smuzhiyun #define GetLineFromBuffer(buffer) strsep(&buffer, "\r\n")
561*4882a593Smuzhiyun #endif
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun void update_IOT_info(_adapter *padapter);
564*4882a593Smuzhiyun #ifdef CONFIG_RTS_FULL_BW
565*4882a593Smuzhiyun void rtw_set_rts_bw(_adapter *padapter);
566*4882a593Smuzhiyun #endif/*CONFIG_RTS_FULL_BW*/
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun void ResumeTxBeacon(_adapter *padapter);
569*4882a593Smuzhiyun void StopTxBeacon(_adapter *padapter);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY
572*4882a593Smuzhiyun u8 rtw_hal_antdiv_before_linked(_adapter *padapter);
573*4882a593Smuzhiyun void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
574*4882a593Smuzhiyun #endif
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun #ifdef DBG_SEC_CAM_MOVE
577*4882a593Smuzhiyun void rtw_hal_move_sta_gk_to_dk(_adapter *adapter);
578*4882a593Smuzhiyun void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);
579*4882a593Smuzhiyun #endif
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun #ifdef CONFIG_LPS_PG
582*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
583*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
584*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
585*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
586*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
587*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/
588*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
589*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
590*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
591*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
592*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
593*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
594*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
595*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
596*4882a593Smuzhiyun enum lps_pg_hdl_id {
597*4882a593Smuzhiyun LPS_PG_INFO_CFG = 0,
598*4882a593Smuzhiyun LPS_PG_REDLEMEM,
599*4882a593Smuzhiyun LPS_PG_PHYDM_DIS,
600*4882a593Smuzhiyun LPS_PG_PHYDM_EN,
601*4882a593Smuzhiyun };
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter);
604*4882a593Smuzhiyun u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
605*4882a593Smuzhiyun #endif
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
608*4882a593Smuzhiyun void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);
609*4882a593Smuzhiyun void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,
610*4882a593Smuzhiyun u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap);
613*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
614*4882a593Smuzhiyun struct rtl_wow_pattern {
615*4882a593Smuzhiyun u16 crc;
616*4882a593Smuzhiyun u8 type;
617*4882a593Smuzhiyun u32 mask[4];
618*4882a593Smuzhiyun };
619*4882a593Smuzhiyun void rtw_wow_pattern_cam_dump(_adapter *adapter);
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
622*4882a593Smuzhiyun #ifdef CONFIG_WOW_PATTERN_HW_CAM
623*4882a593Smuzhiyun void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context);
624*4882a593Smuzhiyun #endif
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun struct rtw_ndp_info {
627*4882a593Smuzhiyun u8 enable:1;
628*4882a593Smuzhiyun u8 check_remote_ip:1; /* Need to Check Sender IP or not */
629*4882a593Smuzhiyun u8 rsvd:6;
630*4882a593Smuzhiyun u8 num_of_target_ip; /* Number of Check IP which NA query IP */
631*4882a593Smuzhiyun u8 target_link_addr[6]; /* DUT's MAC address */
632*4882a593Smuzhiyun u8 remote_ipv6_addr[16]; /* Just respond IP */
633*4882a593Smuzhiyun u8 target_ipv6_addr[16]; /* target IP */
634*4882a593Smuzhiyun };
635*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \
636*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)
637*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \
638*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)
639*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \
640*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)
641*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \
642*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)
643*4882a593Smuzhiyun #endif /*CONFIG_WOWLAN*/
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun #ifdef CONFIG_PROC_DEBUG
646*4882a593Smuzhiyun void rtw_dump_phy_cap(void *sel, _adapter *adapter);
647*4882a593Smuzhiyun #endif
648*4882a593Smuzhiyun void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);
649*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_FIFO_DUMP
650*4882a593Smuzhiyun void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);
651*4882a593Smuzhiyun #endif
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
654*4882a593Smuzhiyun s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
655*4882a593Smuzhiyun s32 rtw_set_default_port_id(_adapter *adapter);
656*4882a593Smuzhiyun s32 rtw_set_ps_rsvd_page(_adapter *adapter);
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun #define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)
659*4882a593Smuzhiyun #define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /*void rtw_search_default_port(_adapter *adapter);*/
662*4882a593Smuzhiyun #endif
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS
665*4882a593Smuzhiyun #ifdef RTW_HALMAC
666*4882a593Smuzhiyun void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);
667*4882a593Smuzhiyun #endif
668*4882a593Smuzhiyun #endif
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun #ifdef RTW_CHANNEL_SWITCH_OFFLOAD
671*4882a593Smuzhiyun void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw);
672*4882a593Smuzhiyun #endif
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun s16 translate_dbm_to_percentage(s16 signal);
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_MULTI_BCN
677*4882a593Smuzhiyun void rtw_ap_multi_bcn_cfg(_adapter *adapter);
678*4882a593Smuzhiyun #endif
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun #ifdef CONFIG_SWTIMER_BASED_TXBCN
681*4882a593Smuzhiyun #ifdef CONFIG_BCN_RECOVERY
682*4882a593Smuzhiyun u8 rtw_ap_bcn_recovery(_adapter *padapter);
683*4882a593Smuzhiyun #endif
684*4882a593Smuzhiyun #ifdef CONFIG_BCN_XMIT_PROTECT
685*4882a593Smuzhiyun u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
686*4882a593Smuzhiyun #endif
687*4882a593Smuzhiyun #endif /*CONFIG_SWTIMER_BASED_TXBCN*/
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun #ifdef CONFIG_FW_HANDLE_TXBCN
690*4882a593Smuzhiyun void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
691*4882a593Smuzhiyun void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
692*4882a593Smuzhiyun #endif
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
695*4882a593Smuzhiyun enum bb_path *tx, enum bb_path *rx);
696*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING
697*4882a593Smuzhiyun #ifdef RTW_BEAMFORMING_VERSION_2
698*4882a593Smuzhiyun void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
699*4882a593Smuzhiyun #endif
700*4882a593Smuzhiyun #endif
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun u8 phy_get_capable_tx_num(_adapter *adapter, enum MGN_RATE rate);
703*4882a593Smuzhiyun u8 phy_get_current_tx_num(_adapter *adapter, enum MGN_RATE rate);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun #ifdef CONFIG_RTL8812A
706*4882a593Smuzhiyun u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );
707*4882a593Smuzhiyun #endif
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun #ifdef CONFIG_PROTSEL_PORT
710*4882a593Smuzhiyun void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel);
711*4882a593Smuzhiyun bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len);
712*4882a593Smuzhiyun void rtw_leave_protsel_port(_adapter *padapter);
713*4882a593Smuzhiyun #else
rtw_enter_protsel_port(_adapter * padapter,u8 port_sel)714*4882a593Smuzhiyun static inline void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel) {}
rtw_assert_protsel_port(_adapter * padapter,u32 addr,u8 len)715*4882a593Smuzhiyun static inline bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len) {return true; }
rtw_leave_protsel_port(_adapter * padapter)716*4882a593Smuzhiyun static inline void rtw_leave_protsel_port(_adapter *padapter) {}
717*4882a593Smuzhiyun #endif
718*4882a593Smuzhiyun #ifdef CONFIG_PROTSEL_ATIMDTIM
719*4882a593Smuzhiyun void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel);
720*4882a593Smuzhiyun bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len);
721*4882a593Smuzhiyun void rtw_leave_protsel_atimdtim(_adapter *padapter);
722*4882a593Smuzhiyun #else
rtw_enter_protsel_atimdtim(_adapter * padapter,u8 port_sel)723*4882a593Smuzhiyun static inline void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel) {}
rtw_assert_protsel_atimdtim(_adapter * padapter,u32 addr,u8 len)724*4882a593Smuzhiyun static inline bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len) {return true; }
rtw_leave_protsel_atimdtim(_adapter * padapter)725*4882a593Smuzhiyun static inline void rtw_leave_protsel_atimdtim(_adapter *padapter) {}
726*4882a593Smuzhiyun #endif
727*4882a593Smuzhiyun #ifdef CONFIG_PROTSEL_MACSLEEP
728*4882a593Smuzhiyun void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel);
729*4882a593Smuzhiyun bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len);
730*4882a593Smuzhiyun void rtw_leave_protsel_macsleep(_adapter *padapter);
731*4882a593Smuzhiyun #else
rtw_enter_protsel_macsleep(_adapter * padapter,u8 port_sel)732*4882a593Smuzhiyun static inline void rtw_enter_protsel_macsleep(_adapter *padapter, u8 port_sel) {}
rtw_assert_protsel_macsleep(_adapter * padapter,u32 addr,u8 len)733*4882a593Smuzhiyun static inline bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len) {return true; }
rtw_leave_protsel_macsleep(_adapter * padapter)734*4882a593Smuzhiyun static inline void rtw_leave_protsel_macsleep(_adapter *padapter) {}
735*4882a593Smuzhiyun #endif
736*4882a593Smuzhiyun #endif /* __HAL_COMMON_H__ */
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