1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __HALPWRSEQCMD_H__ 16*4882a593Smuzhiyun #define __HALPWRSEQCMD_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <drv_types.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /*---------------------------------------------*/ 21*4882a593Smuzhiyun /* 3 The value of cmd: 4 bits 22*4882a593Smuzhiyun *---------------------------------------------*/ 23*4882a593Smuzhiyun #define PWR_CMD_READ 0x00 24*4882a593Smuzhiyun /* offset: the read register offset 25*4882a593Smuzhiyun * msk: the mask of the read value 26*4882a593Smuzhiyun * value: N/A, left by 0 27*4882a593Smuzhiyun * note: dirver shall implement this function by read & msk */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PWR_CMD_WRITE 0x01 30*4882a593Smuzhiyun /* offset: the read register offset 31*4882a593Smuzhiyun * msk: the mask of the write bits 32*4882a593Smuzhiyun * value: write value 33*4882a593Smuzhiyun * note: driver shall implement this cmd by read & msk after write */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define PWR_CMD_POLLING 0x02 36*4882a593Smuzhiyun /* offset: the read register offset 37*4882a593Smuzhiyun * msk: the mask of the polled value 38*4882a593Smuzhiyun * value: the value to be polled, masked by the msd field. 39*4882a593Smuzhiyun * note: driver shall implement this cmd by 40*4882a593Smuzhiyun * do { 41*4882a593Smuzhiyun * if( (Read(offset) & msk) == (value & msk) ) 42*4882a593Smuzhiyun * break; 43*4882a593Smuzhiyun * } while(not timeout); */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define PWR_CMD_DELAY 0x03 46*4882a593Smuzhiyun /* offset: the value to delay 47*4882a593Smuzhiyun * msk: N/A 48*4882a593Smuzhiyun * value: the unit of delay, 0: us, 1: ms */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define PWR_CMD_END 0x04 51*4882a593Smuzhiyun /* offset: N/A 52*4882a593Smuzhiyun * msk: N/A 53*4882a593Smuzhiyun * value: N/A */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /*---------------------------------------------*/ 56*4882a593Smuzhiyun /* 3 The value of base: 4 bits 57*4882a593Smuzhiyun *--------------------------------------------- 58*4882a593Smuzhiyun * define the base address of each block */ 59*4882a593Smuzhiyun #define PWR_BASEADDR_MAC 0x00 60*4882a593Smuzhiyun #define PWR_BASEADDR_USB 0x01 61*4882a593Smuzhiyun #define PWR_BASEADDR_PCIE 0x02 62*4882a593Smuzhiyun #define PWR_BASEADDR_SDIO 0x03 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /*---------------------------------------------*/ 65*4882a593Smuzhiyun /* 3 The value of interface_msk: 4 bits 66*4882a593Smuzhiyun *---------------------------------------------*/ 67*4882a593Smuzhiyun #define PWR_INTF_SDIO_MSK BIT(0) 68*4882a593Smuzhiyun #define PWR_INTF_USB_MSK BIT(1) 69*4882a593Smuzhiyun #define PWR_INTF_PCI_MSK BIT(2) 70*4882a593Smuzhiyun #define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /*---------------------------------------------*/ 73*4882a593Smuzhiyun /* 3 The value of fab_msk: 4 bits 74*4882a593Smuzhiyun *---------------------------------------------*/ 75*4882a593Smuzhiyun #define PWR_FAB_TSMC_MSK BIT(0) 76*4882a593Smuzhiyun #define PWR_FAB_UMC_MSK BIT(1) 77*4882a593Smuzhiyun #define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /*---------------------------------------------*/ 80*4882a593Smuzhiyun /* 3 The value of cut_msk: 8 bits 81*4882a593Smuzhiyun *---------------------------------------------*/ 82*4882a593Smuzhiyun #define PWR_CUT_TESTCHIP_MSK BIT(0) 83*4882a593Smuzhiyun #define PWR_CUT_A_MSK BIT(1) 84*4882a593Smuzhiyun #define PWR_CUT_B_MSK BIT(2) 85*4882a593Smuzhiyun #define PWR_CUT_C_MSK BIT(3) 86*4882a593Smuzhiyun #define PWR_CUT_D_MSK BIT(4) 87*4882a593Smuzhiyun #define PWR_CUT_E_MSK BIT(5) 88*4882a593Smuzhiyun #define PWR_CUT_F_MSK BIT(6) 89*4882a593Smuzhiyun #define PWR_CUT_G_MSK BIT(7) 90*4882a593Smuzhiyun #define PWR_CUT_ALL_MSK 0xFF 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun typedef enum _PWRSEQ_CMD_DELAY_UNIT_ { 94*4882a593Smuzhiyun PWRSEQ_DELAY_US, 95*4882a593Smuzhiyun PWRSEQ_DELAY_MS, 96*4882a593Smuzhiyun } PWRSEQ_DELAY_UNIT; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun typedef struct _WL_PWR_CFG_ { 99*4882a593Smuzhiyun u16 offset; 100*4882a593Smuzhiyun u8 cut_msk; 101*4882a593Smuzhiyun u8 fab_msk:4; 102*4882a593Smuzhiyun u8 interface_msk:4; 103*4882a593Smuzhiyun u8 base:4; 104*4882a593Smuzhiyun u8 cmd:4; 105*4882a593Smuzhiyun u8 msk; 106*4882a593Smuzhiyun u8 value; 107*4882a593Smuzhiyun } WLAN_PWR_CFG, *PWLAN_PWR_CFG; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define GET_PWR_CFG_OFFSET(__PWR_CMD) ((__PWR_CMD).offset) 111*4882a593Smuzhiyun #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) ((__PWR_CMD).cut_msk) 112*4882a593Smuzhiyun #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) ((__PWR_CMD).fab_msk) 113*4882a593Smuzhiyun #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) ((__PWR_CMD).interface_msk) 114*4882a593Smuzhiyun #define GET_PWR_CFG_BASE(__PWR_CMD) ((__PWR_CMD).base) 115*4882a593Smuzhiyun #define GET_PWR_CFG_CMD(__PWR_CMD) ((__PWR_CMD).cmd) 116*4882a593Smuzhiyun #define GET_PWR_CFG_MASK(__PWR_CMD) ((__PWR_CMD).msk) 117*4882a593Smuzhiyun #define GET_PWR_CFG_VALUE(__PWR_CMD) ((__PWR_CMD).value) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* ******************************************************************************** 121*4882a593Smuzhiyun * Prototype of protected function. 122*4882a593Smuzhiyun * ******************************************************************************** */ 123*4882a593Smuzhiyun u8 HalPwrSeqCmdParsing( 124*4882a593Smuzhiyun PADAPTER padapter, 125*4882a593Smuzhiyun u8 CutVersion, 126*4882a593Smuzhiyun u8 FabVersion, 127*4882a593Smuzhiyun u8 InterfaceType, 128*4882a593Smuzhiyun WLAN_PWR_CFG PwrCfgCmd[]); 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #endif 131