xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/Hal8814PhyCfg.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __INC_HAL8814PHYCFG_H__
16*4882a593Smuzhiyun #define __INC_HAL8814PHYCFG_H__
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /*--------------------------Define Parameters-------------------------------*/
20*4882a593Smuzhiyun #define LOOP_LIMIT				5
21*4882a593Smuzhiyun #define MAX_STALL_TIME			50		/* us */
22*4882a593Smuzhiyun #define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
23*4882a593Smuzhiyun #define MAX_TXPWR_IDX_NMODE_92S	63
24*4882a593Smuzhiyun #define Reset_Cnt_Limit			3
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
28*4882a593Smuzhiyun 	#define MAX_AGGR_NUM	0x0B
29*4882a593Smuzhiyun #else
30*4882a593Smuzhiyun 	#define MAX_AGGR_NUM	0x07
31*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /*--------------------------Define Parameters-------------------------------*/
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /*------------------------------Define structure----------------------------*/
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* BB/RF related */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define	SIC_ENABLE				0
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /*------------------------------Define structure----------------------------*/
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /*------------------------Export global variable----------------------------*/
47*4882a593Smuzhiyun /*------------------------Export global variable----------------------------*/
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /*------------------------Export Marco Definition---------------------------*/
51*4882a593Smuzhiyun /*------------------------Export Marco Definition---------------------------*/
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /*--------------------------Exported Function prototype---------------------*/
55*4882a593Smuzhiyun /* 1. BB register R/W API */
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun extern	u32
58*4882a593Smuzhiyun PHY_QueryBBReg8814A(PADAPTER	Adapter,
59*4882a593Smuzhiyun 			u32		RegAddr,
60*4882a593Smuzhiyun 			u32		BitMask);
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun void
64*4882a593Smuzhiyun PHY_SetBBReg8814A(PADAPTER	Adapter,
65*4882a593Smuzhiyun 			u32		RegAddr,
66*4882a593Smuzhiyun 			u32		BitMask,
67*4882a593Smuzhiyun 			u32		Data);
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun extern	u32
71*4882a593Smuzhiyun PHY_QueryRFReg8814A(PADAPTER			Adapter,
72*4882a593Smuzhiyun 			enum rf_path	eRFPath,
73*4882a593Smuzhiyun 			u32			RegAddr,
74*4882a593Smuzhiyun 			u32			BitMask);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun void
78*4882a593Smuzhiyun PHY_SetRFReg8814A(PADAPTER			Adapter,
79*4882a593Smuzhiyun 			enum rf_path		eRFPath,
80*4882a593Smuzhiyun 			u32				RegAddr,
81*4882a593Smuzhiyun 			u32				BitMask,
82*4882a593Smuzhiyun 			u32				Data);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
85*4882a593Smuzhiyun s32
86*4882a593Smuzhiyun phy_BB8814A_Config_ParaFile(
87*4882a593Smuzhiyun 		PADAPTER	Adapter
88*4882a593Smuzhiyun );
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun void
91*4882a593Smuzhiyun PHY_ConfigBB_8814A(
92*4882a593Smuzhiyun 		PADAPTER	Adapter
93*4882a593Smuzhiyun );
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun void
97*4882a593Smuzhiyun phy_ADC_CLK_8814A(
98*4882a593Smuzhiyun 		PADAPTER	Adapter
99*4882a593Smuzhiyun );
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun s32
102*4882a593Smuzhiyun PHY_RFConfig8814A(
103*4882a593Smuzhiyun 		PADAPTER	Adapter
104*4882a593Smuzhiyun );
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun  * RF Power setting
108*4882a593Smuzhiyun  *
109*4882a593Smuzhiyun  * BOOLEAN	PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state	eRFPowerState); */
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* 1 5. Tx  Power setting API */
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun void
114*4882a593Smuzhiyun PHY_SetTxPowerLevel8814(
115*4882a593Smuzhiyun 		PADAPTER		Adapter,
116*4882a593Smuzhiyun 		u8			Channel
117*4882a593Smuzhiyun );
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun u8
120*4882a593Smuzhiyun phy_get_tx_power_index_8814a(
121*4882a593Smuzhiyun 		PADAPTER		Adapter,
122*4882a593Smuzhiyun 		enum rf_path		RFPath,
123*4882a593Smuzhiyun 		u8				Rate,
124*4882a593Smuzhiyun 		enum channel_width BandWidth,
125*4882a593Smuzhiyun 		u8				Channel
126*4882a593Smuzhiyun );
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun void
129*4882a593Smuzhiyun PHY_SetTxPowerIndex_8814A(
130*4882a593Smuzhiyun 		PADAPTER		Adapter,
131*4882a593Smuzhiyun 		u32				PowerIndex,
132*4882a593Smuzhiyun 		enum rf_path		RFPath,
133*4882a593Smuzhiyun 		u8				Rate
134*4882a593Smuzhiyun );
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun u32
137*4882a593Smuzhiyun PHY_GetTxBBSwing_8814A(
138*4882a593Smuzhiyun 		PADAPTER	Adapter,
139*4882a593Smuzhiyun 		BAND_TYPE	Band,
140*4882a593Smuzhiyun 		enum rf_path	RFPath
141*4882a593Smuzhiyun );
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /* 1 6. Channel setting API */
146*4882a593Smuzhiyun #if 0
147*4882a593Smuzhiyun void
148*4882a593Smuzhiyun PHY_SwChnlTimerCallback8814A(
149*4882a593Smuzhiyun 		struct timer_list		*p_timer
150*4882a593Smuzhiyun );
151*4882a593Smuzhiyun #endif
152*4882a593Smuzhiyun void
153*4882a593Smuzhiyun PHY_SwChnlWorkItemCallback8814A(
154*4882a593Smuzhiyun 		void *pContext
155*4882a593Smuzhiyun );
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun void
159*4882a593Smuzhiyun HAL_HandleSwChnl8814A(
160*4882a593Smuzhiyun 		PADAPTER	pAdapter,
161*4882a593Smuzhiyun 		u8		channel
162*4882a593Smuzhiyun );
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun void
165*4882a593Smuzhiyun PHY_SwChnlSynchronously8814A(PADAPTER		pAdapter,
166*4882a593Smuzhiyun 				u8			channel);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun void
169*4882a593Smuzhiyun PHY_HandleSwChnlAndSetBW8814A(
170*4882a593Smuzhiyun 		PADAPTER			Adapter,
171*4882a593Smuzhiyun 		BOOLEAN				bSwitchChannel,
172*4882a593Smuzhiyun 		BOOLEAN				bSetBandWidth,
173*4882a593Smuzhiyun 		u8					ChannelNum,
174*4882a593Smuzhiyun 		enum channel_width	ChnlWidth,
175*4882a593Smuzhiyun 		u8					ChnlOffsetOf40MHz,
176*4882a593Smuzhiyun 		u8					ChnlOffsetOf80MHz,
177*4882a593Smuzhiyun 		u8					CenterFrequencyIndex1
178*4882a593Smuzhiyun );
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun BOOLEAN
182*4882a593Smuzhiyun PHY_QueryRFPathSwitch_8814A(PADAPTER	pAdapter);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun #if (USE_WORKITEM)
187*4882a593Smuzhiyun void
188*4882a593Smuzhiyun RtCheckForHangWorkItemCallback8814A(
189*4882a593Smuzhiyun 		void *pContext
190*4882a593Smuzhiyun );
191*4882a593Smuzhiyun #endif
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun BOOLEAN
194*4882a593Smuzhiyun SetAntennaConfig8814A(
195*4882a593Smuzhiyun 		PADAPTER	Adapter,
196*4882a593Smuzhiyun 		u8		DefaultAnt
197*4882a593Smuzhiyun );
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun void
200*4882a593Smuzhiyun PHY_SetRFEReg8814A(
201*4882a593Smuzhiyun 		PADAPTER		Adapter,
202*4882a593Smuzhiyun 		BOOLEAN		bInit,
203*4882a593Smuzhiyun 		u8		Band
204*4882a593Smuzhiyun );
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun s32
208*4882a593Smuzhiyun PHY_SwitchWirelessBand8814A(
209*4882a593Smuzhiyun 		PADAPTER		 Adapter,
210*4882a593Smuzhiyun 		u8		Band
211*4882a593Smuzhiyun );
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun void
214*4882a593Smuzhiyun PHY_SetIO_8814A(
215*4882a593Smuzhiyun 	PADAPTER		pAdapter
216*4882a593Smuzhiyun );
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun void
219*4882a593Smuzhiyun PHY_SetSwChnlBWMode8814(
220*4882a593Smuzhiyun 		PADAPTER			Adapter,
221*4882a593Smuzhiyun 		u8					channel,
222*4882a593Smuzhiyun 		enum channel_width	Bandwidth,
223*4882a593Smuzhiyun 		u8					Offset40,
224*4882a593Smuzhiyun 		u8					Offset80
225*4882a593Smuzhiyun );
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun s32 PHY_MACConfig8814(PADAPTER Adapter);
228*4882a593Smuzhiyun int PHY_BBConfig8814(PADAPTER	Adapter);
229*4882a593Smuzhiyun void PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER	pAdapter, u32 ulAntennaRx);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun /*--------------------------Exported Function prototype---------------------*/
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun /*--------------------------Exported Function prototype---------------------*/
236*4882a593Smuzhiyun #endif /* __INC_HAL8192CPHYCFG_H */
237