1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2012 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __INC_HAL8192EPHYCFG_H__ 16*4882a593Smuzhiyun #define __INC_HAL8192EPHYCFG_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /*--------------------------Define Parameters-------------------------------*/ 20*4882a593Smuzhiyun #define LOOP_LIMIT 5 21*4882a593Smuzhiyun #define MAX_STALL_TIME 50 /* us */ 22*4882a593Smuzhiyun #define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ 23*4882a593Smuzhiyun #define MAX_TXPWR_IDX_NMODE_92S 63 24*4882a593Smuzhiyun #define Reset_Cnt_Limit 3 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 27*4882a593Smuzhiyun #define MAX_AGGR_NUM 0x0B 28*4882a593Smuzhiyun #else 29*4882a593Smuzhiyun #define MAX_AGGR_NUM 0x07 30*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /*--------------------------Define Parameters-------------------------------*/ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /*------------------------------Define structure----------------------------*/ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* BB/RF related */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /*------------------------------Define structure----------------------------*/ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /*------------------------Export global variable----------------------------*/ 43*4882a593Smuzhiyun /*------------------------Export global variable----------------------------*/ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /*------------------------Export Marco Definition---------------------------*/ 47*4882a593Smuzhiyun /*------------------------Export Marco Definition---------------------------*/ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /*--------------------------Exported Function prototype---------------------*/ 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * BB and RF register read/write 53*4882a593Smuzhiyun * */ 54*4882a593Smuzhiyun u32 PHY_QueryBBReg8192E(PADAPTER Adapter, 55*4882a593Smuzhiyun u32 RegAddr, 56*4882a593Smuzhiyun u32 BitMask); 57*4882a593Smuzhiyun void PHY_SetBBReg8192E(PADAPTER Adapter, 58*4882a593Smuzhiyun u32 RegAddr, 59*4882a593Smuzhiyun u32 BitMask, 60*4882a593Smuzhiyun u32 Data); 61*4882a593Smuzhiyun u32 PHY_QueryRFReg8192E(PADAPTER Adapter, 62*4882a593Smuzhiyun enum rf_path eRFPath, 63*4882a593Smuzhiyun u32 RegAddr, 64*4882a593Smuzhiyun u32 BitMask); 65*4882a593Smuzhiyun void PHY_SetRFReg8192E(PADAPTER Adapter, 66*4882a593Smuzhiyun enum rf_path eRFPath, 67*4882a593Smuzhiyun u32 RegAddr, 68*4882a593Smuzhiyun u32 BitMask, 69*4882a593Smuzhiyun u32 Data); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * Initialization related function 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun * MAC/BB/RF HAL config */ 75*4882a593Smuzhiyun int PHY_MACConfig8192E(PADAPTER Adapter); 76*4882a593Smuzhiyun int PHY_BBConfig8192E(PADAPTER Adapter); 77*4882a593Smuzhiyun int PHY_RFConfig8192E(PADAPTER Adapter); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* RF config */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * BB TX Power R/W 84*4882a593Smuzhiyun * */ 85*4882a593Smuzhiyun void PHY_SetTxPowerLevel8192E(PADAPTER Adapter, u8 channel); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun void 88*4882a593Smuzhiyun PHY_SetTxPowerIndex_8192E( 89*4882a593Smuzhiyun PADAPTER Adapter, 90*4882a593Smuzhiyun u32 PowerIndex, 91*4882a593Smuzhiyun enum rf_path RFPath, 92*4882a593Smuzhiyun u8 Rate 93*4882a593Smuzhiyun ); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * channel switch related funciton 97*4882a593Smuzhiyun * */ 98*4882a593Smuzhiyun void 99*4882a593Smuzhiyun PHY_SetSwChnlBWMode8192E( 100*4882a593Smuzhiyun PADAPTER Adapter, 101*4882a593Smuzhiyun u8 channel, 102*4882a593Smuzhiyun enum channel_width Bandwidth, 103*4882a593Smuzhiyun u8 Offset40, 104*4882a593Smuzhiyun u8 Offset80 105*4882a593Smuzhiyun ); 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun void 108*4882a593Smuzhiyun PHY_SetRFEReg_8192E( 109*4882a593Smuzhiyun PADAPTER Adapter 110*4882a593Smuzhiyun ); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun void 113*4882a593Smuzhiyun phy_SpurCalibration_8192E( 114*4882a593Smuzhiyun PADAPTER Adapter, 115*4882a593Smuzhiyun enum spur_cal_method method 116*4882a593Smuzhiyun ); 117*4882a593Smuzhiyun void PHY_SpurCalibration_8192E( PADAPTER Adapter); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #ifdef CONFIG_SPUR_CAL_NBI 120*4882a593Smuzhiyun void 121*4882a593Smuzhiyun phy_SpurCalibration_8192E_NBI( 122*4882a593Smuzhiyun PADAPTER Adapter 123*4882a593Smuzhiyun ); 124*4882a593Smuzhiyun #endif 125*4882a593Smuzhiyun /* 126*4882a593Smuzhiyun * BB/MAC/RF other monitor API 127*4882a593Smuzhiyun * */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun void 130*4882a593Smuzhiyun phy_set_rf_path_switch_8192e( 131*4882a593Smuzhiyun struct dm_struct *phydm, 132*4882a593Smuzhiyun bool bMain 133*4882a593Smuzhiyun ); 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /*--------------------------Exported Function prototype---------------------*/ 136*4882a593Smuzhiyun #endif /* __INC_HAL8192CPHYCFG_H */ 137