1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTL8723D_PHYCFG_C_
16
17 #include <rtl8723d_hal.h>
18
19
20 /*---------------------------Define Local Constant---------------------------*/
21 /* Channel switch:The size of command tables for switch channel*/
22 #define MAX_PRECMD_CNT 16
23 #define MAX_RFDEPENDCMD_CNT 16
24 #define MAX_POSTCMD_CNT 16
25
26 #define MAX_DOZE_WAITING_TIMES_9x 64
27
28 /*---------------------------Define Local Constant---------------------------*/
29
30
31 /*------------------------Define global variable-----------------------------*/
32
33 /*------------------------Define local variable------------------------------*/
34
35
36 /*--------------------Define export function prototype-----------------------*/
37 /* Please refer to header file
38 *--------------------Define export function prototype-----------------------*/
39
40 /*----------------------------Function Body----------------------------------*/
41 /*
42 * 1. BB register R/W API
43 * */
44
45 /**
46 * Function: phy_CalculateBitShift
47 *
48 * OverView: Get shifted position of the BitMask
49 *
50 * Input:
51 * u32 BitMask,
52 *
53 * Output: none
54 * Return: u32 Return the shift bit bit position of the mask
55 */
56 static u32
phy_CalculateBitShift(u32 BitMask)57 phy_CalculateBitShift(
58 u32 BitMask
59 )
60 {
61 u32 i;
62
63 for (i = 0; i <= 31; i++) {
64 if (((BitMask >> i) & 0x1) == 1)
65 break;
66 }
67
68 return i;
69 }
70
71
72 /**
73 * Function: PHY_QueryBBReg
74 *
75 * OverView: Read "sepcific bits" from BB register
76 *
77 * Input:
78 * PADAPTER Adapter,
79 * u32 RegAddr,
80 * u32 BitMask
81 *
82 * Output: None
83 * Return: u32 Data
84 * Note: This function is equal to "GetRegSetting" in PHY programming guide
85 */
86 u32
PHY_QueryBBReg_8723D(PADAPTER Adapter,u32 RegAddr,u32 BitMask)87 PHY_QueryBBReg_8723D(
88 PADAPTER Adapter,
89 u32 RegAddr,
90 u32 BitMask
91 )
92 {
93 u32 ReturnValue = 0, OriginalValue, BitShift;
94 u16 BBWaitCounter = 0;
95
96 #if (DISABLE_BB_RF == 1)
97 return 0;
98 #endif
99
100
101 OriginalValue = rtw_read32(Adapter, RegAddr);
102 BitShift = phy_CalculateBitShift(BitMask);
103 ReturnValue = (OriginalValue & BitMask) >> BitShift;
104
105 return ReturnValue;
106
107 }
108
109
110 /**
111 * Function: PHY_SetBBReg
112 *
113 * OverView: Write "Specific bits" to BB register (page 8~)
114 *
115 * Input:
116 * PADAPTER Adapter,
117 * u32 RegAddr,
118 * u32 BitMask
119 *
120 * u32 Data
121 *
122 *
123 * Output: None
124 * Return: None
125 * Note: This function is equal to "PutRegSetting" in PHY programming guide
126 */
127
128 void
PHY_SetBBReg_8723D(PADAPTER Adapter,u32 RegAddr,u32 BitMask,u32 Data)129 PHY_SetBBReg_8723D(
130 PADAPTER Adapter,
131 u32 RegAddr,
132 u32 BitMask,
133 u32 Data
134 )
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
137 /* u16 BBWaitCounter = 0; */
138 u32 OriginalValue, BitShift;
139
140 #if (DISABLE_BB_RF == 1)
141 return;
142 #endif
143
144
145 if (BitMask != bMaskDWord) { /* if not "double word" write */
146 OriginalValue = rtw_read32(Adapter, RegAddr);
147 BitShift = phy_CalculateBitShift(BitMask);
148 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
149 }
150
151 rtw_write32(Adapter, RegAddr, Data);
152
153 }
154
155
156 /*
157 * 2. RF register R/W API
158 * */
159 static u32
phy_RFSerialRead_8723D(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset)160 phy_RFSerialRead_8723D(
161 PADAPTER Adapter,
162 enum rf_path eRFPath,
163 u32 Offset
164 )
165 {
166 u32 retValue = 0;
167 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
168 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
169 u32 NewOffset;
170 u32 tmplong, tmplong2;
171 u8 RfPiEnable = 0;
172 u32 MaskforPhySet = 0;
173 int i = 0;
174
175 _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
176 /* */
177 /* Make sure RF register offset is correct */
178 /* */
179 Offset &= 0xff;
180
181 NewOffset = Offset;
182
183 if (eRFPath == RF_PATH_A) {
184 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
185 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
186 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
187 } else {
188 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
189 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
190 phy_set_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
191 }
192
193 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
194 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
195 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
196
197 rtw_udelay_os(10);
198
199 for (i = 0; i < 2; i++)
200 rtw_udelay_os(MAX_STALL_TIME);
201 rtw_udelay_os(10);
202
203 if (eRFPath == RF_PATH_A)
204 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT(8));
205 else if (eRFPath == RF_PATH_B)
206 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT(8));
207
208 if (RfPiEnable) {
209 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
210 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
211
212 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
213 } else {
214 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
215 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
216
217 /* RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
218 }
219 _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
220 return retValue;
221
222 }
223
224 /**
225 * Function: phy_RFSerialWrite_8723D
226 *
227 * OverView: Write data to RF register (page 8~)
228 *
229 * Input:
230 * PADAPTER Adapter,
231 enum rf_path eRFPath,
232 * u32 Offset,
233 * u32 Data
234 *
235 *
236 * Output: None
237 * Return: None
238 * Note: Threre are three types of serial operations:
239 * 1. Software serial write
240 * 2. Hardware LSSI-Low Speed Serial Interface
241 * 3. Hardware HSSI-High speed
242 * serial write. Driver need to implement (1) and (2).
243 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
244 *
245 * Note: For RF8256 only
246 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
247 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
248 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
249 * programming guide" for more details.
250 * Thus, we define a sub-finction for RTL8526 register address conversion
251 * ===========================================================
252 * Register Mode RegCTL[1] RegCTL[0] Note
253 * (Reg00[12]) (Reg00[10])
254 * ===========================================================
255 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
256 * ------------------------------------------------------------------
257 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
258 * ------------------------------------------------------------------
259 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
260 * ------------------------------------------------------------------
261 *
262 * 2008/09/02 MH Add 92S RF definition
263 *
264 *
265 *
266 */
267 static void
phy_RFSerialWrite_8723D(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset,u32 Data)268 phy_RFSerialWrite_8723D(
269 PADAPTER Adapter,
270 enum rf_path eRFPath,
271 u32 Offset,
272 u32 Data
273 )
274 {
275 u32 DataAndAddr = 0;
276 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
277 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
278 u32 NewOffset;
279
280 Offset &= 0xff;
281
282 /* */
283 /* Shadow Update */
284 /* */
285 /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
286
287 /* */
288 /* Switch page for 8256 RF IC */
289 /* */
290 NewOffset = Offset;
291
292 /* */
293 /* Put write addr in [5:0] and write data in [31:16] */
294 /* */
295 /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
296 DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
297
298 /* */
299 /* Write Operation */
300 /* */
301 phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
302 /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
303
304 }
305
306
307 /**
308 * Function: PHY_QueryRFReg
309 *
310 * OverView: Query "Specific bits" to RF register (page 8~)
311 *
312 * Input:
313 * PADAPTER Adapter,
314 enum rf_path eRFPath,
315 * u32 RegAddr,
316 * u32 BitMask
317 *
318 *
319 * Output: None
320 * Return: u32 Readback value
321 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
322 */
323 u32
PHY_QueryRFReg_8723D(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)324 PHY_QueryRFReg_8723D(
325 PADAPTER Adapter,
326 enum rf_path eRFPath,
327 u32 RegAddr,
328 u32 BitMask
329 )
330 {
331 u32 Original_Value, Readback_Value, BitShift;
332
333 #if (DISABLE_BB_RF == 1)
334 return 0;
335 #endif
336
337 Original_Value = phy_RFSerialRead_8723D(Adapter, eRFPath, RegAddr);
338
339 BitShift = phy_CalculateBitShift(BitMask);
340 Readback_Value = (Original_Value & BitMask) >> BitShift;
341
342 return Readback_Value;
343 }
344
345 /**
346 * Function: PHY_SetRFReg
347 *
348 * OverView: Write "Specific bits" to RF register (page 8~)
349 *
350 * Input:
351 * PADAPTER Adapter,
352 * RF_PATH eRFPath,
353 * u32 RegAddr,
354 * u32 BitMask
355 *
356 * u32 Data
357 *
358 *
359 * Output: None
360 * Return: None
361 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
362 */
363 void
PHY_SetRFReg_8723D(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)364 PHY_SetRFReg_8723D(
365 PADAPTER Adapter,
366 enum rf_path eRFPath,
367 u32 RegAddr,
368 u32 BitMask,
369 u32 Data
370 )
371 {
372 u32 Original_Value, BitShift;
373
374 #if (DISABLE_BB_RF == 1)
375 return;
376 #endif
377
378 /* RF data is 12 bits only */
379 if (BitMask != bRFRegOffsetMask) {
380 Original_Value = phy_RFSerialRead_8723D(Adapter, eRFPath, RegAddr);
381 BitShift = phy_CalculateBitShift(BitMask);
382 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
383 }
384
385 phy_RFSerialWrite_8723D(Adapter, eRFPath, RegAddr, Data);
386 }
387
388
389 /*
390 * 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
391 * */
392
393
394 /*-----------------------------------------------------------------------------
395 * Function: PHY_MACConfig8192C
396 *
397 * Overview: Condig MAC by header file or parameter file.
398 *
399 * Input: NONE
400 *
401 * Output: NONE
402 *
403 * Return: NONE
404 *
405 * Revised History:
406 * When Who Remark
407 * 08/12/2008 MHC Create Version 0.
408 *
409 *---------------------------------------------------------------------------*/
PHY_MACConfig8723D(PADAPTER Adapter)410 s32 PHY_MACConfig8723D(PADAPTER Adapter)
411 {
412 int rtStatus = _SUCCESS;
413 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
414
415 /* */
416 /* Config MAC */
417 /* */
418 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
419 rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
420 if (rtStatus == _FAIL)
421 #endif
422 {
423 #ifdef CONFIG_EMBEDDED_FWIMG
424 odm_config_mac_with_header_file(&pHalData->odmpriv);
425 rtStatus = _SUCCESS;
426 #endif/* CONFIG_EMBEDDED_FWIMG */
427 }
428
429 return rtStatus;
430 }
431
432 /**
433 * Function: phy_InitBBRFRegisterDefinition
434 *
435 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
436 *
437 * Input:
438 * PADAPTER Adapter,
439 *
440 * Output: None
441 * Return: None
442 * Note: The initialization value is constant and it should never be changes
443 */
444 static void
phy_InitBBRFRegisterDefinition(PADAPTER Adapter)445 phy_InitBBRFRegisterDefinition(
446 PADAPTER Adapter
447 )
448 {
449 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
450
451 /* RF Interface Sowrtware Control */
452 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
453 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
454
455 /* RF Interface Output (and Enable) */
456 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
457 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
458
459 /* RF Interface (Output and) Enable */
460 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
461 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
462
463 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
464 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
465
466 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
467 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */
468
469 /* Tranceiver Readback LSSI/HSPI mode */
470 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
471 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
472 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
473 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
474
475 }
476
477 static int
phy_BB8723d_Config_ParaFile(PADAPTER Adapter)478 phy_BB8723d_Config_ParaFile(
479 PADAPTER Adapter
480 )
481 {
482 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
483 int rtStatus = _SUCCESS;
484
485 /* */
486 /* 1. Read PHY_REG.TXT BB INIT!! */
487 /* */
488 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
489 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
490 #endif
491 {
492 #ifdef CONFIG_EMBEDDED_FWIMG
493 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
494 rtStatus = _FAIL;
495 #endif
496 }
497
498 if (rtStatus != _SUCCESS) {
499 RTW_INFO("%s():Write BB Reg Fail!!", __func__);
500 goto phy_BB8190_Config_ParaFile_Fail;
501 }
502
503 #if MP_DRIVER == 1
504 if (Adapter->registrypriv.mp_mode == 1) {
505 /*20160504, Suggested by jessica_wang. To Fix CCK ACPR issue*/
506 phy_set_bb_reg(Adapter, 0xCE0, BIT1|BIT0, 0);/*RXHP=low corner*/
507 phy_set_bb_reg(Adapter, 0xC3C, 0xFF, 0xCC);/*make sure low rate sensitivity*/
508 }
509 #endif /* #if (MP_DRIVER == 1) */
510
511 /* */
512 /* 2. Read BB AGC table Initialization */
513 /* */
514 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
515 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
516 #endif
517 {
518 #ifdef CONFIG_EMBEDDED_FWIMG
519 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
520 rtStatus = _FAIL;
521 #endif
522 }
523
524 if (rtStatus != _SUCCESS) {
525 RTW_INFO("%s():AGC Table Fail\n", __func__);
526 goto phy_BB8190_Config_ParaFile_Fail;
527 }
528
529 phy_BB8190_Config_ParaFile_Fail:
530
531 return rtStatus;
532 }
533
534
535 int
PHY_BBConfig8723D(PADAPTER Adapter)536 PHY_BBConfig8723D(
537 PADAPTER Adapter
538 )
539 {
540 int rtStatus = _SUCCESS;
541 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
542 u16 RegVal;
543 u8 TmpU1B = 0;
544 u8 value8;
545
546 phy_InitBBRFRegisterDefinition(Adapter);
547
548 /* Enable BB and RF */
549 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
550 RegVal |= FEN_EN_25_1 | FEN_BB_GLB_RSTn | FEN_BBRSTB;
551 rtw_write16(Adapter, REG_SYS_FUNC_EN, RegVal);
552
553 rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
554
555 #if defined(CONFIG_PCI_HCI)
556 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
557 #endif
558
559 #ifdef CONFIG_USB_HCI
560 /* To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23. */
561 PlatformEFIOWrite1Byte(Adapter, REG_LDOHCI12_CTRL, 0x0f);
562 PlatformEFIOWrite1Byte(Adapter, 0x15, 0xe9);
563 #endif
564
565 rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
566
567 /*
568 * Config BB and AGC
569 */
570 rtStatus = phy_BB8723d_Config_ParaFile(Adapter);
571
572 if (rtw_phydm_set_crystal_cap(Adapter, pHalData->crystal_cap) == _FALSE) {
573 RTW_ERR("Init crystal_cap failed\n");
574 rtw_warn_on(1);
575 rtStatus = _FAIL;
576 }
577
578 return rtStatus;
579 }
580 #if 0
581 /* Block & Path enable */
582 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
583 #define bOFDMEN_Jaguar 0x20000000
584 #define bCCKEN_Jaguar 0x10000000
585 #define rRxPath_Jaguar 0x808 /* Rx antenna */
586 #define bRxPath_Jaguar 0xff
587 #define rTxPath_Jaguar 0x80c /* Tx antenna */
588 #define bTxPath_Jaguar 0x0fffffff
589 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
590 #define bCCK_RX_Jaguar 0x0c000000
591 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
592 void
593 PHY_BB8723D_Config_1T(
594 PADAPTER Adapter
595 )
596 {
597 /* BB OFDM RX Path_A */
598 phy_set_bb_reg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
599 /* BB OFDM TX Path_A */
600 phy_set_bb_reg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
601 /* BB CCK R/Rx Path_A */
602 phy_set_bb_reg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
603 /* MCS support */
604 phy_set_bb_reg(Adapter, 0x8bc, 0xc0000060, 0x4);
605 /* RF Path_B HSSI OFF */
606 phy_set_bb_reg(Adapter, 0xe00, 0xf, 0x4);
607 /* RF Path_B Power Down */
608 phy_set_bb_reg(Adapter, 0xe90, bMaskDWord, 0);
609 /* ADDA Path_B OFF */
610 phy_set_bb_reg(Adapter, 0xe60, bMaskDWord, 0);
611 phy_set_bb_reg(Adapter, 0xe64, bMaskDWord, 0);
612 }
613 #endif
614
615 int
PHY_RFConfig8723D(PADAPTER Adapter)616 PHY_RFConfig8723D(
617 PADAPTER Adapter
618 )
619 {
620 int rtStatus = _SUCCESS;
621 int cnt;
622
623 /* */
624 /* RF config */
625 /* */
626 rtStatus = PHY_RF6052_Config8723D(Adapter);
627 /* 20151207 LCK done at RadioA table */
628 /* PHY_BB8723D_Config_1T(Adapter); */
629
630 /* poll LCK triggered by Radio A table */
631 for (cnt = 0; cnt < 100; cnt++) {
632 if (phy_query_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
633 break;
634 rtw_mdelay_os(10);
635 }
636
637 if (cnt == 100)
638 RTW_WARN("LCK timeout\n");
639 RTW_INFO("LCK cnt=%d\n", cnt);
640
641 return rtStatus;
642 }
643
644 /*-----------------------------------------------------------------------------
645 * Function: PHY_ConfigRFWithParaFile()
646 *
647 * Overview: This function read RF parameters from general file format, and do RF 3-wire
648 *
649 * Input: PADAPTER Adapter
650 * ps1Byte pFileName
651 * enum rf_path eRFPath
652 *
653 * Output: NONE
654 *
655 * Return: RT_STATUS_SUCCESS: configuration file exist
656 *
657 * Note: Delay may be required for RF configuration
658 *---------------------------------------------------------------------------*/
659 int
PHY_ConfigRFWithParaFile_8723D(PADAPTER Adapter,u8 * pFileName,enum rf_path eRFPath)660 PHY_ConfigRFWithParaFile_8723D(
661 PADAPTER Adapter,
662 u8 *pFileName,
663 enum rf_path eRFPath
664 )
665 {
666 return _SUCCESS;
667 }
668
669 /**************************************************************************************************************
670 * Description:
671 * The low-level interface to set TxAGC , called by both MP and Normal Driver.
672 *
673 * <20120830, Kordan>
674 **************************************************************************************************************/
675
676 void
PHY_SetTxPowerIndex_8723D(PADAPTER Adapter,u32 PowerIndex,enum rf_path RFPath,u8 Rate)677 PHY_SetTxPowerIndex_8723D(
678 PADAPTER Adapter,
679 u32 PowerIndex,
680 enum rf_path RFPath,
681 u8 Rate
682 )
683 {
684 if (RFPath == RF_PATH_A || RFPath == RF_PATH_B) {
685 switch (Rate) {
686 case MGN_1M:
687 phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
688 break;
689 case MGN_2M:
690 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
691 break;
692 case MGN_5_5M:
693 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
694 break;
695 case MGN_11M:
696 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
697 break;
698
699 case MGN_6M:
700 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
701 break;
702 case MGN_9M:
703 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
704 break;
705 case MGN_12M:
706 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
707 break;
708 case MGN_18M:
709 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
710 break;
711
712 case MGN_24M:
713 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
714 break;
715 case MGN_36M:
716 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
717 break;
718 case MGN_48M:
719 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
720 break;
721 case MGN_54M:
722 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
723 break;
724
725 case MGN_MCS0:
726 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
727 break;
728 case MGN_MCS1:
729 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
730 break;
731 case MGN_MCS2:
732 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
733 break;
734 case MGN_MCS3:
735 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
736 break;
737
738 case MGN_MCS4:
739 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
740 break;
741 case MGN_MCS5:
742 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
743 break;
744 case MGN_MCS6:
745 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
746 break;
747 case MGN_MCS7:
748 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
749 break;
750
751 default:
752 RTW_INFO("Invalid Rate!!\n");
753 break;
754 }
755 }
756 }
757
758 void
PHY_SetTxPowerLevel8723D(PADAPTER Adapter,u8 Channel)759 PHY_SetTxPowerLevel8723D(
760 PADAPTER Adapter,
761 u8 Channel
762 )
763 {
764 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
765 u8 cur_antenna;
766 enum rf_path RFPath = RF_PATH_A;
767
768 #ifdef CONFIG_ANTENNA_DIVERSITY
769 rtw_hal_get_odm_var(Adapter, HAL_ODM_ANTDIV_SELECT, &cur_antenna, NULL);
770
771 if (pHalData->AntDivCfg) /* antenna diversity Enable */
772 RFPath = ((cur_antenna == MAIN_ANT) ? RF_PATH_A : RF_PATH_B);
773 else /* antenna diversity disable */
774 #endif
775 RFPath = pHalData->ant_path;
776
777
778
779 phy_set_tx_power_level_by_path(Adapter, Channel, RFPath);
780
781 }
782
783 /* <20160217, Jessica> A workaround to eliminate the 2472MHz & 2484MHz spur of 8723D. */
784 void
phy_SpurCalibration_8723D(PADAPTER pAdapter,u8 ToChannel,u8 threshold)785 phy_SpurCalibration_8723D(
786 PADAPTER pAdapter,
787 u8 ToChannel,
788 u8 threshold
789 )
790 {
791 u32 freq[2] = {0xFCCD, 0xFF9A}; /* {chnl 13, 14} */
792 u8 idx = 0xFF;
793 u8 b_doNotch = FALSE;
794 u8 initial_gain;
795
796 /* add for notch */
797 u32 wlan_channel, CurrentChannel;
798 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
799 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
800
801 /* check threshold */
802 if (threshold <= 0x0)
803 threshold = 0x16;
804
805 RTW_DBG("===>phy_SpurCalibration_8723D: Channel = %d\n", ToChannel);
806
807 if (ToChannel == 13)
808 idx = 0;
809 else if (ToChannel == 14)
810 idx = 1;
811
812 /* If current channel=13,14 */
813 if (idx < 0xFF) {
814 initial_gain = (u8)(odm_get_bb_reg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
815 odm_pause_dig(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, 0x30);
816 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0); /* disable 3-wire */
817
818 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* Setup PSD */
819 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD */
820
821 rtw_msleep_os(30);
822
823 if (phy_query_bb_reg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
824 b_doNotch = TRUE;
825
826 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
827 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0); /* enable 3-wire */
828 odm_pause_dig(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, NONE);
829 }
830
831 /* --- Notch Filter --- Asked by Rock */
832 if (b_doNotch) {
833 CurrentChannel = odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
834 wlan_channel = CurrentChannel & 0x0f; /* Get center frequency */
835
836 switch (wlan_channel) { /* Set notch filter */
837 case 13:
838 odm_set_bb_reg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0xB);
839 odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x1); /* enable notch filter */
840 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x04000000);
841 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
842 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
843 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
844 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x1); /* enable CSI mask */
845 break;
846 case 14:
847 odm_set_bb_reg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x5);
848 odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x1); /* enable notch filter */
849 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
850 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
851 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
852 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00080000);
853 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x1); /* enable CSI mask */
854 break;
855 default:
856 odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x0); /* disable notch filter */
857 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x0); /* disable CSI mask function */
858 break;
859 } /* switch(wlan_channel) */
860 return;
861 }
862
863 odm_set_bb_reg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x1f);
864 odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x0); /* disable notch filter */
865 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
866 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
867 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
868 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
869 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x0); /* disable CSI mask */
870 }
871
872 void
phy_SetRegBW_8723D(PADAPTER Adapter,enum channel_width CurrentBW)873 phy_SetRegBW_8723D(
874 PADAPTER Adapter,
875 enum channel_width CurrentBW
876 )
877 {
878 u16 RegRfMod_BW, u2tmp = 0;
879
880 RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723D);
881
882 switch (CurrentBW) {
883 case CHANNEL_WIDTH_20:
884 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
885 break;
886
887 case CHANNEL_WIDTH_40:
888 u2tmp = RegRfMod_BW | BIT(7);
889 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
890 break;
891
892 case CHANNEL_WIDTH_80:
893 u2tmp = RegRfMod_BW | BIT(8);
894 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
895 break;
896
897 default:
898 RTW_INFO("phy_PostSetBWMode8723D(): unknown Bandwidth: %#X\n", CurrentBW);
899 break;
900 }
901 }
902
903 u8
phy_GetSecondaryChnl_8723D(PADAPTER Adapter)904 phy_GetSecondaryChnl_8723D(
905 PADAPTER Adapter
906 )
907 {
908 u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
909 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
910
911 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
912 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
913 SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
914 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
915 SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
916
917
918 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
919 SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
920 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
921 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
922 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
923 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
924 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
925 SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
926
927 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
928
929 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
930 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
931 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
932 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
933
934 }
935
936 return (SCSettingOf40 << 4) | SCSettingOf20;
937 }
938
939 void
phy_PostSetBwMode8723D(PADAPTER padapter)940 phy_PostSetBwMode8723D(
941 PADAPTER padapter
942 )
943 {
944 u8 SubChnlNum = 0;
945 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
946
947 /* 2 Set Reg668 Reg440 BW */
948 phy_SetRegBW_8723D(padapter, pHalData->current_channel_bw);
949
950 /* 3 Set Reg483 */
951 SubChnlNum = phy_GetSecondaryChnl_8723D(padapter);
952 rtw_write8(padapter, REG_DATA_SC_8723D, SubChnlNum);
953
954 switch (pHalData->current_channel_bw) {
955 /* 20 MHz channel*/
956 case CHANNEL_WIDTH_20:
957 /*
958 0x800[0]=1'b0
959 0x900[0]=1'b0
960 0x954[19]=1'b1
961 0x954[27:24]= 10
962 */
963 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bRFMOD, 0x0);
964 phy_set_bb_reg(padapter, rFPGA1_RFMOD, bRFMOD, 0x0);
965 phy_set_bb_reg(padapter, rBBrx_DFIR, BIT(19), 1);
966 phy_set_bb_reg(padapter, rBBrx_DFIR,
967 (BIT(27) | BIT(26) | BIT(25) | BIT(24)), 0xa);
968 break;
969 /* 40 MHz channel*/
970 case CHANNEL_WIDTH_40:
971 /*
972 0x800[0]=1'b1
973 0x900[0]=1'b1
974 0x954[19]=1'b0
975 0x954[23:20]=2'b11(For ACPR)
976 0xa00[4]=1/0
977 */
978 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bRFMOD, 0x1);
979 phy_set_bb_reg(padapter, rFPGA1_RFMOD, bRFMOD, 0x1);
980 phy_set_bb_reg(padapter, rBBrx_DFIR, BIT(19), 0);
981 phy_set_bb_reg(padapter, rCCK0_System, bCCKSideBand,
982 (pHalData->nCur40MhzPrimeSC >> 1));
983
984 break;
985 default:
986 break;
987 }
988
989 /*3<3>Set RF related register */
990 PHY_RF6052SetBandwidth8723D(padapter, pHalData->current_channel_bw);
991 }
992
993 void
phy_SwChnl8723D(PADAPTER pAdapter)994 phy_SwChnl8723D(
995 PADAPTER pAdapter
996 )
997 {
998 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
999 u8 channelToSW = pHalData->current_channel;
1000 u8 i = 0;
1001
1002 if (pHalData->rf_chip == RF_PSEUDO_11N) {
1003 RTW_WARN("phy_SwChnl8723D: return for PSEUDO\n");
1004 return;
1005 }
1006
1007 pHalData->RfRegChnlVal[0] =
1008 ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
1009 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
1010 0x3FF, pHalData->RfRegChnlVal[0]);
1011 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_CHNLBW,
1012 0x3FF, pHalData->RfRegChnlVal[0]);
1013
1014 phy_SpurCalibration_8723D(pAdapter, channelToSW, 0x16);
1015
1016 /* 2.4G CCK TX DFIR */
1017 /* 2016.01.20 Suggest from RS BB mingzhi*/
1018 if (channelToSW >= 1 && channelToSW <= 13) {
1019 if (pHalData->need_restore == _TRUE) {
1020 for (i = 0 ; i < 3 ; i++) {
1021 phy_set_bb_reg(pAdapter,
1022 pHalData->RegForRecover[i].offset,
1023 bMaskDWord,
1024 pHalData->RegForRecover[i].value);
1025 }
1026 pHalData->need_restore = _FALSE;
1027 }
1028 } else if (channelToSW == 14) {
1029 pHalData->need_restore = _TRUE;
1030 phy_set_bb_reg(pAdapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
1031 phy_set_bb_reg(pAdapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
1032 phy_set_bb_reg(pAdapter, 0xAAC, bMaskDWord, 0x00003667);
1033 }
1034
1035 RTW_DBG("===>phy_SwChnl8723D: Channel = %d\n", channelToSW);
1036 }
1037
1038 void
phy_SwChnlAndSetBwMode8723D(PADAPTER Adapter)1039 phy_SwChnlAndSetBwMode8723D(
1040 PADAPTER Adapter
1041 )
1042 {
1043 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1044
1045 if (Adapter->bNotifyChannelChange) {
1046 RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
1047 __func__,
1048 pHalData->bSwChnl,
1049 pHalData->current_channel,
1050 pHalData->bSetChnlBW,
1051 pHalData->current_channel_bw);
1052 }
1053
1054 if (RTW_CANNOT_RUN(Adapter))
1055 return;
1056
1057 if (pHalData->bSwChnl) {
1058 phy_SwChnl8723D(Adapter);
1059 pHalData->bSwChnl = _FALSE;
1060 }
1061
1062 if (pHalData->bSetChnlBW) {
1063 phy_PostSetBwMode8723D(Adapter);
1064 pHalData->bSetChnlBW = _FALSE;
1065 }
1066
1067 if (pHalData->bNeedIQK == _TRUE) {
1068 if (pHalData->neediqk_24g == _TRUE) {
1069
1070 halrf_iqk_trigger(&pHalData->odmpriv, _FALSE);
1071 pHalData->bIQKInitialized = _TRUE;
1072 pHalData->neediqk_24g = _FALSE;
1073 }
1074 pHalData->bNeedIQK = _FALSE;
1075 }
1076
1077 rtw_hal_set_tx_power_level(Adapter, pHalData->current_channel);
1078 }
1079
1080 void
PHY_HandleSwChnlAndSetBW8723D(PADAPTER Adapter,BOOLEAN bSwitchChannel,BOOLEAN bSetBandWidth,u8 ChannelNum,enum channel_width ChnlWidth,EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,u8 CenterFrequencyIndex1)1081 PHY_HandleSwChnlAndSetBW8723D(
1082 PADAPTER Adapter,
1083 BOOLEAN bSwitchChannel,
1084 BOOLEAN bSetBandWidth,
1085 u8 ChannelNum,
1086 enum channel_width ChnlWidth,
1087 EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,
1088 EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,
1089 u8 CenterFrequencyIndex1
1090 )
1091 {
1092 /* static BOOLEAN bInitialzed = _FALSE; */
1093 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1094 u8 tmpChannel = pHalData->current_channel;
1095 enum channel_width tmpBW = pHalData->current_channel_bw;
1096 u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
1097 u8 tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
1098 u8 tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
1099 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1100
1101 /* RTW_INFO("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n",bSwitchChannel,bSetBandWidth); */
1102
1103 /* check is swchnl or setbw */
1104 if (!bSwitchChannel && !bSetBandWidth) {
1105 RTW_INFO("PHY_HandleSwChnlAndSetBW8812: not switch channel and not set bandwidth\n");
1106 return;
1107 }
1108
1109 /* skip change for channel or bandwidth is the same */
1110 if (bSwitchChannel) {
1111 /* if(pHalData->current_channel != ChannelNum) */
1112 {
1113 if (HAL_IsLegalChannel(Adapter, ChannelNum))
1114 pHalData->bSwChnl = _TRUE;
1115 }
1116 }
1117
1118 if (bSetBandWidth) {
1119 #if 0
1120 if (bInitialzed == _FALSE) {
1121 bInitialzed = _TRUE;
1122 pHalData->bSetChnlBW = _TRUE;
1123 } else if ((pHalData->current_channel_bw != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
1124 pHalData->bSetChnlBW = _TRUE;
1125 #else
1126 pHalData->bSetChnlBW = _TRUE;
1127 #endif
1128 }
1129
1130 if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
1131 /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1132 return;
1133 }
1134
1135
1136 if (pHalData->bSwChnl) {
1137 pHalData->current_channel = ChannelNum;
1138 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
1139 }
1140
1141
1142 if (pHalData->bSetChnlBW) {
1143 pHalData->current_channel_bw = ChnlWidth;
1144 #if 0
1145 if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_LOWER)
1146 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1147 else if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_UPPER)
1148 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1149 else
1150 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1151
1152 if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_LOWER)
1153 pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1154 else if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_UPPER)
1155 pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1156 else
1157 pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1158 #else
1159 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
1160 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
1161 #endif
1162
1163 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1164 }
1165
1166 /* Switch workitem or set timer to do switch channel or setbandwidth operation */
1167 if (!RTW_CANNOT_RUN(Adapter))
1168 phy_SwChnlAndSetBwMode8723D(Adapter);
1169 else {
1170 if (pHalData->bSwChnl) {
1171 pHalData->current_channel = tmpChannel;
1172 pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
1173 }
1174 if (pHalData->bSetChnlBW) {
1175 pHalData->current_channel_bw = tmpBW;
1176 pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1177 pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1178 pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1179 }
1180 }
1181
1182 /* RTW_INFO("Channel %d ChannelBW %d ",pHalData->current_channel, pHalData->current_channel_bw); */
1183 /* RTW_INFO("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); */
1184 /* RTW_INFO("CenterFrequencyIndex1 %d\n",pHalData->CurrentCenterFrequencyIndex1); */
1185
1186 /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1187
1188 }
1189
1190 void
PHY_SetSwChnlBWMode8723D(PADAPTER Adapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)1191 PHY_SetSwChnlBWMode8723D(
1192 PADAPTER Adapter,
1193 u8 channel,
1194 enum channel_width Bandwidth,
1195 u8 Offset40,
1196 u8 Offset80
1197 )
1198 {
1199 /* RTW_INFO("%s()===>\n",__FUNCTION__); */
1200
1201 PHY_HandleSwChnlAndSetBW8723D(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
1202
1203 /* RTW_INFO("<==%s()\n",__FUNCTION__); */
1204 }
1205