1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) Semiconductor - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "Hal8723DPwrSeq.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun drivers should parse below arrays and do the corresponding actions 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun /* 3 Power on Array */ 24*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = { 25*4882a593Smuzhiyun RTL8723D_TRANS_CARDEMU_TO_ACT 26*4882a593Smuzhiyun RTL8723D_TRANS_END 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 3Radio off GPIO Array */ 30*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS] = { 31*4882a593Smuzhiyun RTL8723D_TRANS_ACT_TO_CARDEMU 32*4882a593Smuzhiyun RTL8723D_TRANS_END 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 3Card Disable Array */ 36*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS] = { 37*4882a593Smuzhiyun RTL8723D_TRANS_ACT_TO_CARDEMU 38*4882a593Smuzhiyun RTL8723D_TRANS_CARDEMU_TO_CARDDIS 39*4882a593Smuzhiyun RTL8723D_TRANS_END 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 3 Card Enable Array */ 43*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = { 44*4882a593Smuzhiyun RTL8723D_TRANS_CARDDIS_TO_CARDEMU 45*4882a593Smuzhiyun RTL8723D_TRANS_CARDEMU_TO_ACT 46*4882a593Smuzhiyun RTL8723D_TRANS_END 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 3Suspend Array */ 50*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS] = { 51*4882a593Smuzhiyun RTL8723D_TRANS_ACT_TO_CARDEMU 52*4882a593Smuzhiyun RTL8723D_TRANS_CARDEMU_TO_SUS 53*4882a593Smuzhiyun RTL8723D_TRANS_END 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 3 Resume Array */ 57*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = { 58*4882a593Smuzhiyun RTL8723D_TRANS_SUS_TO_CARDEMU 59*4882a593Smuzhiyun RTL8723D_TRANS_CARDEMU_TO_ACT 60*4882a593Smuzhiyun RTL8723D_TRANS_END 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 3HWPDN Array */ 66*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS] = { 67*4882a593Smuzhiyun RTL8723D_TRANS_ACT_TO_CARDEMU 68*4882a593Smuzhiyun RTL8723D_TRANS_CARDEMU_TO_PDN 69*4882a593Smuzhiyun RTL8723D_TRANS_END 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 3 Enter LPS */ 73*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS] = { 74*4882a593Smuzhiyun /* FW behavior */ 75*4882a593Smuzhiyun RTL8723D_TRANS_ACT_TO_LPS 76*4882a593Smuzhiyun RTL8723D_TRANS_END 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 3 Leave LPS */ 80*4882a593Smuzhiyun WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = { 81*4882a593Smuzhiyun /* FW behavior */ 82*4882a593Smuzhiyun RTL8723D_TRANS_LPS_TO_ACT 83*4882a593Smuzhiyun RTL8723D_TRANS_END 84*4882a593Smuzhiyun }; 85