1 /****************************************************************************** 2 * 3 * Copyright(c) 2016 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 /***************************************************************************** 16 * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. 17 * 18 * Module: __INC_HAL8723DREG_H 19 * 20 * 21 * Note: 1. Define Mac register address and corresponding bit mask map 22 * 23 * 24 * Export: Constants, macro, functions(API), global variables(None). 25 * 26 * Abbrev: 27 * 28 * History: 29 * data Who Remark 30 * 31 *****************************************************************************/ 32 #ifndef __INC_HAL8723DREG_H 33 #define __INC_HAL8723DREG_H 34 35 /************************************************************* 36 * 37 ************************************************************/ 38 39 /* ----------------------------------------------------- 40 * 41 * 0x0000h ~ 0x00FFh System Configuration 42 * 43 * ----------------------------------------------------- 44 */ 45 #define REG_SYS_ISO_CTRL_8723D 0x0000 /* 2 Byte */ 46 #define REG_SYS_FUNC_EN_8723D 0x0002 /* 2 Byte */ 47 #define REG_SYS_PW_CTRL_8723D 0x0004 /* 4 Byte */ 48 #define REG_SYS_CLKR_8723D 0x0008 /* 2 Byte */ 49 #define REG_SYS_EEPROM_CTRL_8723D 0x000A /* 2 Byte */ 50 #define REG_EE_VPD_8723D 0x000C /* 2 Byte */ 51 #define REG_SYS_SWR_CTRL1_8723D 0x0010 /* 1 Byte */ 52 #define REG_SYS_SWR_CTRL2_8723D 0x0014 /* 1 Byte */ 53 #define REG_SYS_SWR_CTRL3_8723D 0x0018 /* 4 Byte */ 54 #define REG_RSV_CTRL_8723D 0x001C /* 3 Byte */ 55 #define REG_RF_CTRL_8723D 0x001F /* 1 Byte */ 56 #define REG_AFE_CTRL1_8723D 0x0024 /* 4 Byte */ 57 #define REG_AFE_CTRL2_8723D 0x0028 /* 4 Byte */ 58 #define REG_AFE_CTRL3_8723D 0x002c /* 4 Byte */ 59 #define REG_EFUSE_CTRL_8723D 0x0030 60 #define REG_LDO_EFUSE_CTRL_8723D 0x0034 61 #define REG_PWR_DATA_8723D 0x0038 62 #define REG_CAL_TIMER_8723D 0x003C 63 #define REG_ACLK_MON_8723D 0x003E 64 #define REG_GPIO_MUXCFG_8723D 0x0040 65 #define REG_GPIO_IO_SEL_8723D 0x0042 66 #define REG_MAC_PINMUX_CFG_8723D 0x0043 /* ?????? */ 67 #define REG_GPIO_PIN_CTRL_8723D 0x0044 68 #define REG_GPIO_INTM_8723D 0x0048 69 #define BIT_REG_LED_CFG_8723D 0x004C 70 #define REG_LEDCFG2_8723D 0x004E /* ?????? */ 71 #define REG_FSIMR_8723D 0x0050 72 #define REG_FSISR_8723D 0x0054 73 #define REG_HSIMR_8723D 0x0058 74 #define REG_HSISR_8723D 0x005c 75 #define REG_GPIO_EXT_CTRL_8723D 0x0060 76 #define REG_MULTI_FUNC_CTRL_8723D 0x0068 77 #define REG_GPIO_STATUS_8723D 0x006C 78 #define REG_SDIO_CTRL_8723D 0x0070 79 #define REG_HCI_OPT_CTRL_8723D 0x0074 80 #define REG_AFE_CTRL4_8723D 0x0078 81 #define REG_LDO_SWR_CTRL_8723D 0x007C 82 #define REG_8051FW_CTRL_8723D 0x0080 83 #define REG_FW_DBG_STATUS_8723D 0x0088 84 #define REG_FW_DBG_CTRL_8723D 0x008F 85 #define REG_WLLPS_CTRL_8723D 0x0090 86 #define REG_HIMR0_8723D 0x00B0 87 #define REG_HISR0_8723D 0x00B4 88 #define REG_HIMR1_8723D 0x00B8 89 #define REG_HISR1_8723D 0x00BC 90 #define REG_PMC_DBG_CTRL2_8723D 0x00CC 91 #define REG_EFUSE_BURN_GNT_8723D 0x00CF 92 #define REG_XTAL_AAC_8723D 0x00EC 93 #define REG_SYS_CFG1_8723D 0x00F0 94 #define REG_SYS_CFG2_8723D 0x00FC 95 #define REG_ROM_VERSION 0x00FD 96 97 /* ----------------------------------------------------- 98 * 99 * 0x0100h ~ 0x01FFh MACTOP General Configuration 100 * 101 * ----------------------------------------------------- 102 */ 103 #define REG_CR_8723D 0x0100 104 #define REG_PBP_8723D 0x0104 /* ?????? */ 105 #define REG_PKT_BUFF_ACCESS_CTRL_8723D 0x0106 /* ?????? */ 106 #define REG_TRXDMA_CTRL_8723D 0x010C 107 #define REG_TRXFF_BNDY_8723D 0x0114 108 #define REG_RXFF_PTR_8723D 0x011C 109 #define REG_CPWM_8723D 0x012C 110 #define REG_FWIMR_8723D 0x0130 111 #define REG_FWISR_8723D 0x0134 112 #define REG_FTIMR_8723D 0x0138 113 #define REG_PKTBUF_DBG_CTRL_8723D 0x0140 114 #define REG_RXPKTBUF_CTRL_8723D 0x0142 /* ?????? */ 115 #define REG_PKTBUF_DBG_DATA_L_8723D 0x0144 116 #define REG_PKTBUF_DBG_DATA_H_8723D 0x0148 117 118 #define REG_TC0_CTRL_8723D 0x0150 119 #define REG_TC1_CTRL_8723D 0x0154 120 #define REG_TC2_CTRL_8723D 0x0158 121 #define REG_TC3_CTRL_8723D 0x015C 122 #define REG_TC4_CTRL_8723D 0x0160 123 #define REG_TCUNIT_BASE_8723D 0x0164 124 #define REG_RSVD3_8723D 0x0168 /* ????? */ 125 126 #define REG_C2HEVT_MSG_NORMAL_8723D 0x01A0 /* ?????? */ 127 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 /* ?????? */ 128 #define reg_c2h_evt_cmd_content_88xx 0x01A2 /* ?????? */ 129 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE /* ?????? */ 130 #define REG_C2HEVT_CLEAR_8723D 0x01AF /* ?????? */ 131 #define REG_MCUTST_1_8723D 0x01C0 132 #define REG_MCUTST_2_8723D 0x01C4 133 #define REG_MCUTST_WOWLAN_8723D 0x01C7 /* ?????? */ 134 #define REG_FMETHR_8723D 0x01C8 135 #define REG_HMETFR_8723D 0x01CC 136 #define REG_HMEBOX_0_8723D 0x01D0 137 #define REG_HMEBOX_1_8723D 0x01D4 138 #define REG_HMEBOX_2_8723D 0x01D8 139 #define REG_HMEBOX_3_8723D 0x01DC 140 #define REG_LLT_INIT_8723D 0x01E0 141 #define REG_HMEBOX_EXT0_8723D 0x01F0 /* ?????? */ 142 #define REG_HMEBOX_EXT1_8723D 0x01F4 /* ?????? */ 143 #define REG_HMEBOX_EXT2_8723D 0x01F8 /* ?????? */ 144 #define REG_HMEBOX_EXT3_8723D 0x01FC /* ?????? */ 145 146 /* ----------------------------------------------------- 147 * 148 * 0x0200h ~ 0x027Fh TXDMA Configuration 149 * 150 * ----------------------------------------------------- 151 */ 152 #define REG_RQPN_8723D 0x0200 153 #define REG_FIFOPAGE_8723D 0x0204 154 #define REG_TDECTRL_8723D 0x0208 155 #define REG_TXDMA_OFFSET_CHK_8723D 0x020C 156 #define REG_TXDMA_STATUS_8723D 0x0210 157 #define REG_RQPN_NPQ_8723D 0x0214 158 #define REG_AUTO_LLT_8723D 0x0224 159 #define REG_DWBCN1_CTRL_8723D 0x0228 160 161 /* ----------------------------------------------------- 162 * 163 * 0x0280h ~ 0x02FFh RXDMA Configuration 164 * 165 * ----------------------------------------------------- 166 */ 167 #define REG_RXDMA_AGG_PG_TH_8723D 0x0280 168 #define REG_RXPKT_NUM_8723D 0x0284 /* The number of packets in RXPKTBUF. */ 169 #define REG_RXDMA_CONTROL_8723D 0x0286 /* ?????? Control the RX DMA. */ 170 #define REG_RXDMA_STATUS_8723D 0x0288 171 #define REG_RXDMA_PRO_8723D 0x0290 /* ?????? */ 172 #define REG_EARLY_MODE_CONTROL_8723D 0x02BC /* ?????? */ 173 #define REG_RSVD5_8723D 0x02F0 /* ?????? */ 174 175 /* ----------------------------------------------------- 176 * 177 * 0x0300h ~ 0x03FFh PCIe 178 * 179 * ----------------------------------------------------- 180 */ 181 #define REG_PCIE_CTRL_REG_8723D 0x0300 182 #define REG_INT_MIG_8723D 0x0304 /* Interrupt Migration */ 183 #define REG_BCNQ_TXBD_DESA_8723D 0x0308 /* TX Beacon Descriptor Address */ 184 #define REG_MGQ_TXBD_DESA_8723D 0x0310 /* TX Manage Queue Descriptor Address */ 185 #define REG_VOQ_TXBD_DESA_8723D 0x0318 /* TX VO Queue Descriptor Address */ 186 #define REG_VIQ_TXBD_DESA_8723D 0x0320 /* TX VI Queue Descriptor Address */ 187 #define REG_BEQ_TXBD_DESA_8723D 0x0328 /* TX BE Queue Descriptor Address */ 188 #define REG_BKQ_TXBD_DESA_8723D 0x0330 /* TX BK Queue Descriptor Address */ 189 #define REG_RXQ_RXBD_DESA_8723D 0x0338 /* RX Queue Descriptor Address */ 190 #define REG_HI0Q_TXBD_DESA_8723D 0x0340 191 #define REG_HI1Q_TXBD_DESA_8723D 0x0348 192 #define REG_HI2Q_TXBD_DESA_8723D 0x0350 193 #define REG_HI3Q_TXBD_DESA_8723D 0x0358 194 #define REG_HI4Q_TXBD_DESA_8723D 0x0360 195 #define REG_HI5Q_TXBD_DESA_8723D 0x0368 196 #define REG_HI6Q_TXBD_DESA_8723D 0x0370 197 #define REG_HI7Q_TXBD_DESA_8723D 0x0378 198 #define REG_MGQ_TXBD_NUM_8723D 0x0380 199 #define REG_RX_RXBD_NUM_8723D 0x0382 200 #define REG_VOQ_TXBD_NUM_8723D 0x0384 201 #define REG_VIQ_TXBD_NUM_8723D 0x0386 202 #define REG_BEQ_TXBD_NUM_8723D 0x0388 203 #define REG_BKQ_TXBD_NUM_8723D 0x038A 204 #define REG_HI0Q_TXBD_NUM_8723D 0x038C 205 #define REG_HI1Q_TXBD_NUM_8723D 0x038E 206 #define REG_HI2Q_TXBD_NUM_8723D 0x0390 207 #define REG_HI3Q_TXBD_NUM_8723D 0x0392 208 #define REG_HI4Q_TXBD_NUM_8723D 0x0394 209 #define REG_HI5Q_TXBD_NUM_8723D 0x0396 210 #define REG_HI6Q_TXBD_NUM_8723D 0x0398 211 #define REG_HI7Q_TXBD_NUM_8723D 0x039A 212 #define REG_TSFTIMER_HCI_8723D 0x039C 213 214 /* Read Write Point */ 215 #define REG_VOQ_TXBD_IDX_8723D 0x03A0 216 #define REG_VIQ_TXBD_IDX_8723D 0x03A4 217 #define REG_BEQ_TXBD_IDX_8723D 0x03A8 218 #define REG_BKQ_TXBD_IDX_8723D 0x03AC 219 #define REG_MGQ_TXBD_IDX_8723D 0x03B0 220 #define REG_RXQ_TXBD_IDX_8723D 0x03B4 221 #define REG_HI0Q_TXBD_IDX_8723D 0x03B8 222 #define REG_HI1Q_TXBD_IDX_8723D 0x03BC 223 #define REG_HI2Q_TXBD_IDX_8723D 0x03C0 224 #define REG_HI3Q_TXBD_IDX_8723D 0x03C4 225 #define REG_HI4Q_TXBD_IDX_8723D 0x03C8 226 #define REG_HI5Q_TXBD_IDX_8723D 0x03CC 227 #define REG_HI6Q_TXBD_IDX_8723D 0x03D0 228 #define REG_HI7Q_TXBD_IDX_8723D 0x03D4 229 230 #define REG_PCIE_HCPWM_8723DE 0x03D8 /* ?????? */ 231 #define REG_PCIE_HRPWM_8723DE 0x03DC /* PCIe RPWM */ /* ?????? */ 232 #define REG_DBI_WDATA_V1_8723D 0x03E8 233 #define REG_DBI_RDATA_V1_8723D 0x03EC 234 #define REG_DBI_FLAG_V1_8723D 0x03F0 235 #define REG_MDIO_V1_8723D 0x03F4 236 #define REG_PCIE_MIX_CFG_8723D 0x03F8 237 #define REG_HCI_MIX_CFG_8723D 0x03FC 238 239 /* ----------------------------------------------------- 240 * 241 * 0x0400h ~ 0x047Fh Protocol Configuration 242 * 243 * ----------------------------------------------------- 244 */ 245 #define REG_TXPKT_EMPTY_8723D 0x041A 246 #define REG_PTCL_POLL_MGN_8723D 0x041F 247 #define REG_FWHW_TXQ_CTRL_8723D 0x0420 248 #define REG_HWSEQ_CTRL_8723D 0x0423 249 #define REG_BCNQ_BDNY_8723D 0x0424 250 #define REG_MGQ_BDNY_8723D 0x0425 251 #define REG_LIFETIME_EN_8723D 0x0426 252 #define REG_FW_FREE_TAIL_8723D 0x0427 253 #define REG_SPEC_SIFS_8723D 0x0428 254 #define REG_RETRY_LIMIT_8723D 0x042A 255 #define REG_TXBF_CTRL_8723D 0x042C 256 #define REG_DARFRC_8723D 0x0430 257 #define REG_RARFRC_8723D 0x0438 258 #define REG_RRSR_8723D 0x0440 259 #define REG_ARFR0_8723D 0x0444 260 #define REG_ARFR1_8723D 0x044C 261 #define REG_CCK_CHECK_8723D 0x0454 262 #define REG_BCNQ2_BDNY_8723D 0x0455 263 #define REG_AMPDU_MAX_TIME_8723D 0x0456 264 #define REG_BCNQ1_BDNY_8723D 0x0457 265 #define REG_AMPDU_MAX_LENGTH_8723D 0x0458 266 #define REG_WMAC_LBK_BUF_HD_8723D 0x045D 267 #define REG_NDPA_OPT_CTRL_8723D 0x045F 268 #define REG_FAST_EDCA_CTRL_8723D 0x0460 269 #define REG_RD_RESP_PKT_TH_8723D 0x0463 270 #define REG_DATA_SC_8723D 0x0483 271 #define REG_TXRPT_START_OFFSET 0x04AC 272 #define REG_POWER_STAGE1_8723D 0x04B4 273 #define REG_PTCL_SDF_STATUS_8723D 0x04BB 274 #define REG_SW_AMPDU_BURST_MODE_CTRL_8723D 0x04BC 275 #define REG_EVTQ_BNDY_8723D 0x04BF 276 #define REG_PKT_LIFE_TIME_8723D 0x04C0 277 #define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 /* ?????? */ 278 279 #define REG_STBC_SETTING_8723D 0x04C4 280 #define REG_HT_SINGLE_AMPDU_8723D 0x04C7 281 #define REG_PROT_MODE_CTRL_8723D 0x04C8 282 #define REG_MAX_AGGR_NUM_8723D 0x04CA 283 #define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB 284 #define REG_BAR_MODE_CTRL_8723D 0x04CC 285 #define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF 286 #define REG_MACID_SLEEP2_8723D 0x04D0 287 #define REG_PTCL_HWSSN0_8723D 0x04D8 288 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D /* ?????? */ 289 290 /************* 0x1480~0x14A7 is for NAN ***************/ 291 /* Own Master Rank, 8Bytes */ 292 #define REG_NAN_INTERFACE_ADDR_8723D 0x2480 /* 6 bytes */ 293 #define REG_NAN_RANDOM_FACTOR_8723D 0x2486 /* 1 byte */ 294 #define REG_NAN_MASTER_PREF_8723D 0x2487 /* 1 byte */ 295 296 /* 0x5dc[25:24] NAN role */ 297 298 /* Current Anchor Master Record */ 299 #define REG_NAN_CAMR_L_8723D 0x2488 /* 4 bytes */ 300 #define REG_NAN_CAMR_H_8723D 0x248C /* 4 byte */ 301 #define REG_NAN_CAMR_AMBTT_8723D 0x2490 /* 4 bytes */ 302 303 /* Last Anchor Master Record */ 304 #define REG_NAN_LAMR_L_8723D 0x2494 /* 4 bytes */ 305 #define REG_NAN_LAMR_H_8723D 0x2498 /* 4 byte */ 306 #define REG_NAN_LAMR_AMBTT_8723D 0x249C /* 4 bytes */ 307 308 /* TSF Synced:bit 0 309 * Anchor Master: bit 7 310 */ 311 #define REG_NAN_STATUS_8723D 0x24A0 /* BIT0 */ 312 313 /* ----------------------------------------------------- 314 * 315 * 0x0500h ~ 0x05FFh EDCA Configuration 316 * 317 * ----------------------------------------------------- 318 * gogogo 319 */ 320 #define REG_EDCA_VO_PARAM_8723D 0x0500 321 #define REG_EDCA_VI_PARAM_8723D 0x0504 322 #define REG_EDCA_BE_PARAM_8723D 0x0508 323 #define REG_EDCA_BK_PARAM_8723D 0x050C 324 #define REG_BCNTCFG_8723D 0x0510 325 #define REG_PIFS_8723D 0x0512 326 #define REG_RDG_PIFS_8723D 0x0513 327 #define REG_SIFS_CTX_8723D 0x0514 328 #define REG_SIFS_TRX_8723D 0x0516 329 #define REG_AGGR_BREAK_TIME_8723D 0x051A 330 #define REG_SLOT_8723D 0x051B 331 #define REG_TX_PTCL_CTRL_8723D 0x0520 332 #define REG_TXPAUSE_8723D 0x0522 333 #define REG_DIS_TXREQ_CLR_8723D 0x0523 334 #define REG_RD_CTRL_8723D 0x0524 335 /* 336 * Format for offset 540h-542h: 337 * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 338 * [7:4]: Reserved. 339 * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 340 * [23:20]: Reserved 341 * Description: 342 * | 343 * |<--Setup--|--Hold------------>| 344 * --------------|---------------------- 345 * | 346 * TBTT 347 * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 348 * Described by Designer Tim and Bruce, 2011-01-14. 349 * 350 */ 351 #define REG_TBTT_PROHIBIT_8723D 0x0540 352 #define REG_RD_NAV_NXT_8723D 0x0544 353 #define REG_NAV_PROT_LEN_8723D 0x0546 354 #define REG_BCN_CTRL_8723D 0x0550 355 #define REG_EDCA_BCNCTRL1_IOREG_8723D 0x0551 356 #define REG_MBID_NUM_8723D 0x0552 357 #define REG_DUAL_TSF_RST_8723D 0x0553 358 #define REG_BCN_INTERVAL_8723D 0x0554 359 #define REG_DRVERLYINT_8723D 0x0558 360 #define REG_BCNDMATIM_8723D 0x0559 361 #define REG_ATIMWND_8723D 0x055A 362 #define REG_USTIME_TSF_8723D 0x055C 363 #define REG_BCN_MAX_ERR_8723D 0x055D 364 #define REG_RXTSF_OFFSET_CCK_8723D 0x055E 365 #define REG_RXTSF_OFFSET_OFDM_8723D 0x055F 366 #define REG_TSFTR_8723D 0x0560 367 #define REG_CTWND_8723D 0x0572 368 #define REG_SECONDARY_CCA_CTRL_8723D 0x0577 /* ?????? */ 369 #define REG_TSFTR2_8723D 0x0578 370 #define REG_PSTIMER_8723D 0x0580 371 #define REG_TIMER0_8723D 0x0584 372 #define REG_TIMER1_8723D 0x0588 373 #define REG_SCH_MULTI_BCN_8723D 0x05B2 374 #define REG_SCH_CURRENT_BCN_8723D 0x05B3 375 #define REG_ACMHWCTRL_8723D 0x05C0 376 #define REG_SCH_SDFX_EARLY_8723D 0x05CF 377 #define REG_SCH_PORT2_EARLY_8723D 0x05D0 378 #define REG_SCH_TSFT_DIFF_8723D 0x05D2 379 #define REG_EDCA_BCNCTRL2_IOREG_8723D 0x05D4 380 #define REG_EDCA_DRVERLYINT1_IOREG_8723D 0x05D4 381 #define REG_EDCA_BCNSPACE3_IOREG_8723D 0x05D8 382 #define REG_EDCA_BCNSPACE4_IOREG_8723D 0x05DA 383 #define REG_HOP_CNT_8723D 0x05DC 384 #define REG_SCH_M_DW_8723D 0x05DD 385 #define REG_SCH_M_SLOT_8723D 0x05DE 386 #define REG_SCH_EARLY_DWEND_8723D 0x05DF 387 #define REG_SCH_TXCMD_8723D 0x05F8 388 389 /* ----------------------------------------------------- 390 * 391 * 0x0600h ~ 0x07FFh WMAC Configuration 392 * 393 * ----------------------------------------------------- 394 * gogogo 395 */ 396 #define REG_MAC_CR_8723D 0x0600 397 #define REG_TCR_8723D 0x0604 398 #define REG_RCR_8723D 0x0608 399 #define REG_RX_PKT_LIMIT_8723D 0x060C 400 #define REG_RX_DLK_TIME_8723D 0x060D 401 #define REG_RX_DRVINFO_SZ_8723D 0x060F 402 403 #define REG_MACID_8723D 0x0610 404 #define REG_BSSID_8723D 0x0618 405 #define REG_MAR_8723D 0x0620 406 #define REG_MBIDCAMCFG_8723D 0x0628 407 408 #define REG_USTIME_EDCA_8723D 0x0638 409 #define REG_MAC_SPEC_SIFS_8723D 0x063A 410 #define REG_RESP_SIFP_CCK_8723D 0x063C 411 #define REG_RESP_SIFS_OFDM_8723D 0x063E 412 #define REG_ACKTO_8723D 0x0640 413 #define REG_CTS2TO_8723D 0x0641 414 #define REG_EIFS_8723D 0x0642 415 416 #define REG_NAV_UPPER_8723D 0x0652 /* ?????? */ 417 #define REG_TRXPTCL_CTL_8723D 0x0668 418 419 /* security */ 420 #define REG_CAMCMD_8723D 0x0670 421 #define REG_CAMWRITE_8723D 0x0674 422 #define REG_CAMREAD_8723D 0x0678 423 #define REG_CAMDBG_8723D 0x067C 424 #define REG_SECCFG_8723D 0x0680 425 426 /* Power */ 427 #define REG_WOW_CTRL_8723D 0x0690 428 #define REG_PS_RX_INFO_8723D 0x0692 429 #define REG_UAPSD_TID_8723D 0x0693 430 #define REG_WKFMCAM_NUM_8723D 0x0698 431 #define REG_RXFLTMAP0_8723D 0x06A0 432 #define REG_RXFLTMAP1_8723D 0x06A2 433 #define REG_RXFLTMAP2_8723D 0x06A4 434 #define REG_BCN_PSR_RPT_8723D 0x06A8 435 #define REG_BT_COEX_TABLE_8723D 0x06C0 436 #define REG_ASSOCIATED_BFMER0_INFO_8723D 0x06E4 437 #define REG_ASSOCIATED_BFMER1_INFO_8723D 0x06EC 438 #define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4 439 #define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8 440 #define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC 441 442 /* Hardware Port 2 */ 443 #define REG_MACID1_8723D 0x0700 444 #define REG_BSSID1_8723D 0x0708 445 #define REG_ASSOCIATED_BFMEE_SEL_8723D 0x0714 446 #define REG_SND_PTCL_CTRL_8723D 0x0718 447 448 /* ----------------------------------------------------- 449 * 450 * Redifine 8192C register definition for compatibility 451 * 452 * ----------------------------------------------------- 453 */ 454 455 /* TODO: use these definition when using REG_xxx naming rule. 456 * NOTE: DO NOT Remove these definition. Use later. 457 */ 458 #define EFUSE_CTRL_8723D REG_EFUSE_CTRL_8723D /* E-Fuse Control. */ 459 #define EFUSE_TEST_8723D REG_LDO_EFUSE_CTRL_8723D /* E-Fuse Test. */ 460 #define MSR_8723D (REG_CR_8723D + 2) /* Media status register */ 461 #define ISR_8723D REG_HISR0_8723D 462 #define TSFR_8723D REG_TSFTR_8723D /* Timing Sync Function Timer Register. */ 463 464 /* Redifine MACID register, to compatible prior ICs. */ 465 #define IDR0_8723D REG_MACID_8723D /* MAC ID Register, Offset 0x0050-0x0053 */ 466 #define IDR4_8723D (REG_MACID_8723D + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ 467 468 /* 469 * 9. security Control Registers (Offset: ) 470 * 471 */ 472 #define RWCAM_8723D REG_CAMCMD_8723D /* 8190 data Sheet is called CAMcmd */ 473 #define WCAMI_8723D REG_CAMWRITE_8723D /* Software write CAM input content */ 474 #define RCAMO_8723D REG_CAMREAD_8723D /* Software read/write CAM config */ 475 #define CAMDBG_8723D REG_CAMDBG_8723D 476 #define SECR_8723D REG_SECCFG_8723D /* security Configuration Register */ 477 478 /* ---------------------------------------------------------------------------- 479 * 8195 IMR/ISR bits (offset 0xB0, 8bits) 480 * ---------------------------------------------------------------------------- 481 */ 482 #define IMR_DISABLED_8723D 0 483 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 484 #define IMR_TIMER2_8723D BIT(31) /* Timeout interrupt 2 */ 485 #define IMR_TIMER1_8723D BIT(30) /* Timeout interrupt 1 */ 486 #define IMR_PSTIMEOUT_8723D BIT(29) /* Power Save Time Out Interrupt */ 487 #define IMR_GTINT4_8723D BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 488 #define IMR_GTINT3_8723D BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 489 #define IMR_TXBCN0ERR_8723D BIT(26) /* Transmit Beacon0 Error */ 490 #define IMR_TXBCN0OK_8723D BIT(25) /* Transmit Beacon0 OK */ 491 #define IMR_TSF_BIT32_TOGGLE_8723D BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ 492 #define IMR_BCNDMAINT0_8723D BIT(20) /* Beacon DMA Interrupt 0 */ 493 #define IMR_BCNDERR0_8723D BIT(16) /* Beacon Queue DMA OK0 */ 494 #define IMR_HSISR_IND_ON_INT_8723D BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 495 #define IMR_BCNDMAINT_E_8723D BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 496 #define IMR_ATIMEND_8723D BIT(12) /* CTWidnow End or ATIM Window End */ 497 #define IMR_C2HCMD_8723D BIT(10) /* CPU to Host Command INT status, Write 1 clear */ 498 #define IMR_CPWM2_8723D BIT(9) /* CPU power mode exchange INT status, Write 1 clear */ 499 #define IMR_CPWM_8723D BIT(8) /* CPU power mode exchange INT status, Write 1 clear */ 500 #define IMR_HIGHDOK_8723D BIT(7) /* High Queue DMA OK */ 501 #define IMR_MGNTDOK_8723D BIT(6) /* Management Queue DMA OK */ 502 #define IMR_BKDOK_8723D BIT(5) /* AC_BK DMA OK */ 503 #define IMR_BEDOK_8723D BIT(4) /* AC_BE DMA OK */ 504 #define IMR_VIDOK_8723D BIT(3) /* AC_VI DMA OK */ 505 #define IMR_VODOK_8723D BIT(2) /* AC_VO DMA OK */ 506 #define IMR_RDU_8723D BIT(1) /* Rx Descriptor Unavailable */ 507 #define IMR_ROK_8723D BIT(0) /* Receive DMA OK */ 508 509 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 510 #define IMR_BCNDMAINT7_8723D BIT(27) /* Beacon DMA Interrupt 7 */ 511 #define IMR_BCNDMAINT6_8723D BIT(26) /* Beacon DMA Interrupt 6 */ 512 #define IMR_BCNDMAINT5_8723D BIT(25) /* Beacon DMA Interrupt 5 */ 513 #define IMR_BCNDMAINT4_8723D BIT(24) /* Beacon DMA Interrupt 4 */ 514 #define IMR_BCNDMAINT3_8723D BIT(23) /* Beacon DMA Interrupt 3 */ 515 #define IMR_BCNDMAINT2_8723D BIT(22) /* Beacon DMA Interrupt 2 */ 516 #define IMR_BCNDMAINT1_8723D BIT(21) /* Beacon DMA Interrupt 1 */ 517 #define IMR_BCNDOK7_8723D BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ 518 #define IMR_BCNDOK6_8723D BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ 519 #define IMR_BCNDOK5_8723D BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ 520 #define IMR_BCNDOK4_8723D BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ 521 #define IMR_BCNDOK3_8723D BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ 522 #define IMR_BCNDOK2_8723D BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ 523 #define IMR_BCNDOK1_8723D BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ 524 #define IMR_ATIMEND_E_8723D BIT(13) /* ATIM Window End Extension for Win7 */ 525 #define IMR_TXERR_8723D BIT(11) /* Tx Error Flag Interrupt status, write 1 clear. */ 526 #define IMR_RXERR_8723D BIT(10) /* Rx Error Flag INT status, Write 1 clear */ 527 #define IMR_TXFOVW_8723D BIT(9) /* Transmit FIFO Overflow */ 528 #define IMR_RXFOVW_8723D BIT(8) /* Receive FIFO Overflow */ 529 530 #define IMR_MCUERR_8723D BIT(28) /* Beacon DMA Interrupt 7 */ 531 532 /*=================================================================== 533 *===================================================================== 534 *Here the register defines are for 92C. When the define is as same with 92C, 535 *we will use the 92C's define for the consistency 536 *So the following defines for 92C is not entire!!!!!! 537 *===================================================================== 538 *===================================================================== 539 */ 540 /* 541 * Based on Datasheet V33---090401 542 * Register Summary 543 * Current IOREG MAP 544 * 0x0000h ~ 0x00FFh System Configuration (256 Bytes) 545 * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) 546 * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) 547 * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) 548 * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) 549 * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) 550 * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) 551 * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 552 * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) 553 */ 554 /* ---------------------------------------------------------------------------- 555 * 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) 556 * ---------------------------------------------------------------------------- 557 */ 558 #if 0 559 #define StopBecon BIT(6) 560 #define StopHigh BIT(5) 561 #define StopMgt BIT(4) 562 #define StopVO BIT(3) 563 #define StopVI BIT(2) 564 #define StopBE BIT(1) 565 #define StopBK BIT(0) 566 #endif 567 568 569 /* **************************************************************************** 570 * 8192C Regsiter Bit and Content definition 571 * **************************************************************************** 572 * ----------------------------------------------------- 573 * 574 * 0x0000h ~ 0x00FFh System Configuration 575 * 576 * ----------------------------------------------------- 577 */ 578 #if 0 579 /* 2 SYS_ISO_CTRL */ 580 #define ISO_MD2PP BIT(0) 581 #define ISO_UA2USB BIT(1) 582 #define ISO_UD2CORE BIT(2) 583 #define ISO_PA2PCIE BIT(3) 584 #define ISO_PD2CORE BIT(4) 585 #define ISO_IP2MAC BIT(5) 586 #define ISO_DIOP BIT(6) 587 #define ISO_DIOE BIT(7) 588 #define ISO_EB2CORE BIT(8) 589 #define ISO_DIOR BIT(9) 590 #define PWC_EV12V BIT(15) 591 592 593 /* 2 SYS_FUNC_EN */ 594 #define FEN_BBRSTB BIT(0) 595 #define FEN_BB_GLB_RSTn BIT(1) 596 #define FEN_USBA BIT(2) 597 #define FEN_UPLL BIT(3) 598 #define FEN_USBD BIT(4) 599 #define FEN_DIO_PCIE BIT(5) 600 #define FEN_PCIEA BIT(6) 601 #define FEN_PPLL BIT(7) 602 #define FEN_PCIED BIT(8) 603 #define FEN_DIOE BIT(9) 604 #define FEN_CPUEN BIT(10) 605 #define FEN_DCORE BIT(11) 606 #define FEN_ELDR BIT(12) 607 #define FEN_DIO_RF BIT(13) 608 #define FEN_HWPDN BIT(14) 609 #define FEN_MREGEN BIT(15) 610 611 /* 2 APS_FSMCO */ 612 #define PFM_LDALL BIT(0) 613 #define PFM_ALDN BIT(1) 614 #define PFM_LDKP BIT(2) 615 #define PFM_WOWL BIT(3) 616 #define EnPDN BIT(4) 617 #define PDN_PL BIT(5) 618 #define APFM_ONMAC BIT(8) 619 #define APFM_OFF BIT(9) 620 #define APFM_RSM BIT(10) 621 #define AFSM_HSUS BIT(11) 622 #define AFSM_PCIE BIT(12) 623 #define APDM_MAC BIT(13) 624 #define APDM_HOST BIT(14) 625 #define APDM_HPDN BIT(15) 626 #define RDY_MACON BIT(16) 627 #define SUS_HOST BIT(17) 628 #define ROP_ALD BIT(20) 629 #define ROP_PWR BIT(21) 630 #define ROP_SPS BIT(22) 631 #define SOP_MRST BIT(25) 632 #define SOP_FUSE BIT(26) 633 #define SOP_ABG BIT(27) 634 #define SOP_AMB BIT(28) 635 #define SOP_RCK BIT(29) 636 #define SOP_A8M BIT(30) 637 #define XOP_BTCK BIT(31) 638 639 /* 2 SYS_CLKR */ 640 #define ANAD16V_EN BIT(0) 641 #define ANA8M BIT(1) 642 #define MACSLP BIT(4) 643 #define LOADER_CLK_EN BIT(5) 644 645 646 /* 2 9346CR */ 647 648 #define BOOT_FROM_EEPROM BIT(4) 649 #define EEPROM_EN BIT(5) 650 651 652 /* 2 RF_CTRL */ 653 #define RF_EN BIT(0) 654 #define RF_RSTB BIT(1) 655 #define RF_SDMRSTB BIT(2) 656 657 /* 2 LDOV12D_CTRL */ 658 #define LDV12_EN BIT(0) 659 #define LDV12_SDBY BIT(1) 660 #define LPLDO_HSM BIT(2) 661 #define LPLDO_LSM_DIS BIT(3) 662 #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 663 664 665 /* 2 EFUSE_TEST (For RTL8723 partially) */ 666 #define EF_TRPT BIT(7) 667 #define EF_CELL_SEL (BIT(8) | BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 668 #define LDOE25_EN BIT(31) 669 #define EFUSE_SEL(x) (((x) & 0x3) << 8) 670 #define EFUSE_SEL_MASK 0x300 671 #define EFUSE_WIFI_SEL_0 0x0 672 #define EFUSE_BT_SEL_0 0x1 673 #define EFUSE_BT_SEL_1 0x2 674 #define EFUSE_BT_SEL_2 0x3 675 676 677 /* 2 8051FWDL */ 678 /* 2 MCUFWDL */ 679 #define MCUFWDL_EN BIT(0) 680 #define MCUFWDL_RDY BIT(1) 681 #define FWDL_ChkSum_rpt BIT(2) 682 #define MACINI_RDY BIT(3) 683 #define BBINI_RDY BIT(4) 684 #define RFINI_RDY BIT(5) 685 #define WINTINI_RDY BIT(6) 686 #define RAM_DL_SEL BIT(7) 687 #define ROM_DLEN BIT(19) 688 #define CPRST BIT(23) 689 690 691 692 /* 2 REG_SYS_CFG */ 693 #define XCLK_VLD BIT(0) 694 #define ACLK_VLD BIT(1) 695 #define UCLK_VLD BIT(2) 696 #define PCLK_VLD BIT(3) 697 #define PCIRSTB BIT(4) 698 #define V15_VLD BIT(5) 699 #define TRP_B15V_EN BIT(7) 700 #define SIC_IDLE BIT(8) 701 #define BD_MAC2 BIT(9) 702 #define BD_MAC1 BIT(10) 703 #define IC_MACPHY_MODE BIT(11) 704 #define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 705 #define BT_FUNC BIT(16) 706 #define VENDOR_ID BIT(19) 707 #define PAD_HWPD_IDN BIT(22) 708 #define TRP_VAUX_EN BIT(23) /* RTL ID */ 709 #define TRP_BT_EN BIT(24) 710 #define BD_PKG_SEL BIT(25) 711 #define BD_HCI_SEL BIT(26) 712 #define TYPE_ID BIT(27) 713 714 #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ 715 #define CHIP_VER_RTL_SHIFT 12 716 717 #endif 718 /* ----------------------------------------------------- 719 * 720 * 0x0100h ~ 0x01FFh MACTOP General Configuration 721 * 722 * ----------------------------------------------------- 723 */ 724 #if 0 725 726 /* 2 Function Enable Registers */ 727 /* 2 CR 0x0100-0x0103 */ 728 729 #define HCI_TXDMA_EN BIT(0) 730 #define HCI_RXDMA_EN BIT(1) 731 #define TXDMA_EN BIT(2) 732 #define RXDMA_EN BIT(3) 733 #define PROTOCOL_EN BIT(4) 734 #define SCHEDULE_EN BIT(5) 735 #define MACTXEN BIT(6) 736 #define MACRXEN BIT(7) 737 #define ENSWBCN BIT(8) 738 #define ENSEC BIT(9) 739 #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ 740 741 /* Network type */ 742 #define _NETTYPE(x) (((x) & 0x3) << 16) 743 #define MASK_NETTYPE 0x30000 744 #define NT_NO_LINK 0x0 745 #define NT_LINK_AD_HOC 0x1 746 #define NT_LINK_AP 0x2 747 #define NT_AS_AP 0x3 748 749 750 /* 2 PBP - Page Size Register 0x0104 */ 751 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 752 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 753 #define _PSRX_MASK 0xF 754 #define _PSTX_MASK 0xF0 755 #define _PSRX(x) (x) 756 #define _PSTX(x) ((x) << 4) 757 758 #define PBP_64 0x0 759 #define PBP_128 0x1 760 #define PBP_256 0x2 761 #define PBP_512 0x3 762 #define PBP_1024 0x4 763 764 765 /* 2 TX/RXDMA 0x010C */ 766 #define RXDMA_ARBBW_EN BIT(0) 767 #define RXSHFT_EN BIT(1) 768 #define RXDMA_AGG_EN BIT(2) 769 #define QS_VO_QUEUE BIT(8) 770 #define QS_VI_QUEUE BIT(9) 771 #define QS_BE_QUEUE BIT(10) 772 #define QS_BK_QUEUE BIT(11) 773 #define QS_MANAGER_QUEUE BIT(12) 774 #define QS_HIGH_QUEUE BIT(13) 775 776 #define HQSEL_VOQ BIT(0) 777 #define HQSEL_VIQ BIT(1) 778 #define HQSEL_BEQ BIT(2) 779 #define HQSEL_BKQ BIT(3) 780 #define HQSEL_MGTQ BIT(4) 781 #define HQSEL_HIQ BIT(5) 782 783 /* For normal driver, 0x10C */ 784 #define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14) 785 #define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12) 786 #define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10) 787 #define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8) 788 #define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6) 789 #define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4) 790 791 #define QUEUE_LOW 1 792 #define QUEUE_NORMAL 2 793 #define QUEUE_HIGH 3 794 795 796 /* 2 REG_C2HEVT_CLEAR 0x01AF */ 797 #define C2H_EVT_HOST_CLOSE 0x00 /* Set by driver and notify FW that the driver has read the C2H command message */ 798 #define C2H_EVT_FW_CLOSE 0xFF /* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */ 799 800 801 802 /* 2 LLT_INIT 0x01E0 */ 803 #define _LLT_NO_ACTIVE 0x0 804 #define _LLT_WRITE_ACCESS 0x1 805 #define _LLT_READ_ACCESS 0x2 806 807 #define _LLT_INIT_DATA(x) ((x) & 0xFF) 808 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 809 #define _LLT_OP(x) (((x) & 0x3) << 30) 810 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 811 812 #endif 813 /* ----------------------------------------------------- 814 * 815 * 0x0200h ~ 0x027Fh TXDMA Configuration 816 * 817 * ----------------------------------------------------- 818 */ 819 #if 0 820 /* 2 TDECTL 0x0208 */ 821 #define BLK_DESC_NUM_SHIFT 4 822 #define BLK_DESC_NUM_MASK 0xF 823 824 825 /* 2 TXDMA_OFFSET_CHK 0x020C */ 826 #define DROP_DATA_EN BIT(9) 827 #endif 828 /* ----------------------------------------------------- 829 * 830 * 0x0280h ~ 0x028Bh RX DMA Configuration 831 * 832 * ----------------------------------------------------- 833 */ 834 #if 0 835 /* 2 REG_RXDMA_CONTROL, 0x0286h */ 836 837 /* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */ 838 /* this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */ 839 #define RXPKT_RELEASE_POLL BIT(0) 840 /* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */ 841 /* this bit. FW can start releasing packets after RXDMA entering idle mode. */ 842 #define RXDMA_IDLE BIT(1) 843 /* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */ 844 /* completed, and stop DMA packet to host. RXDMA will then report Default: 0; */ 845 #define RW_RELEASE_EN BIT(2) 846 #endif 847 /* ----------------------------------------------------- 848 * 849 * 0x0400h ~ 0x047Fh Protocol Configuration 850 * 851 * ----------------------------------------------------- 852 */ 853 #if 0 854 /* 2 FWHW_TXQ_CTRL 0x0420 */ 855 #define EN_AMPDU_RTY_NEW BIT(7) 856 857 858 /* 2 REG_LIFECTRL_CTRL 0x0426 */ 859 #define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) 860 #define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) 861 #define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) 862 #define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) 863 864 #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ 865 866 867 /* 2 SPEC SIFS 0x0428 */ 868 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 869 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 870 871 /* 2 RL 0x042A */ 872 #define RETRY_LIMIT_SHORT_SHIFT 8 873 #define RETRY_LIMIT_LONG_SHIFT 0 874 875 #define _LRL(x) ((x) & 0x3F) 876 #define _SRL(x) (((x) & 0x3F) << 8) 877 #endif 878 879 /* ----------------------------------------------------- 880 * 881 * 0x0500h ~ 0x05FFh EDCA Configuration 882 * 883 * ----------------------------------------------------- 884 */ 885 #if 0 886 /* 2 EDCA setting 0x050C */ 887 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 888 #define AC_PARAM_ECW_MAX_OFFSET 12 889 #define AC_PARAM_ECW_MIN_OFFSET 8 890 #define AC_PARAM_AIFS_OFFSET 0 891 892 893 /* 2 BCN_CTRL 0x0550 */ 894 #define EN_TXBCN_RPT BIT(2) 895 #define EN_BCN_FUNCTION BIT(3) 896 897 /* 2 TxPause 0x0522 */ 898 #define STOP_BCNQ BIT(6) 899 #endif 900 901 /* 2 ACMHWCTRL 0x05C0 */ 902 #define acm_hw_hw_en_8723d BIT(0) 903 #define acm_hw_voq_en_8723d BIT(1) 904 #define acm_hw_viq_en_8723d BIT(2) 905 #define acm_hw_beq_en_8723d BIT(3) 906 #define acm_hw_voq_status_8723d BIT(5) 907 #define acm_hw_viq_status_8723d BIT(6) 908 #define acm_hw_beq_status_8723d BIT(7) 909 910 /* ----------------------------------------------------- 911 * 912 * 0x0600h ~ 0x07FFh WMAC Configuration 913 * 914 * ----------------------------------------------------- 915 */ 916 #if 0 917 918 /* 2 TCR 0x0604 */ 919 #define DIS_GCLK BIT(1) 920 #define PAD_SEL BIT(2) 921 #define PWR_ST BIT(6) 922 #define PWRBIT_OW_EN BIT(7) 923 #define ACRC BIT(8) 924 #define CFENDFORM BIT(9) 925 #define ICV BIT(10) 926 #endif 927 928 /* ---------------------------------------------------------------------------- 929 * 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) 930 * ---------------------------------------------------------------------------- 931 */ 932 #if 0 933 #define RCR_APPFCS BIT(31) /* WMAC append FCS after pauload */ 934 #define RCR_APP_MIC BIT(30) /* MACRX will retain the MIC at the bottom of the packet. */ 935 #define RCR_APP_ICV BIT(29) /* MACRX will retain the ICV at the bottom of the packet. */ 936 #define RCR_APP_PHYST_RXFF BIT(28) /* HY status is appended before RX packet in RXFF */ 937 #define RCR_APP_BA_SSN BIT(27) /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ 938 #define RCR_RSVD_BIT(26) BIT26 /* Reserved */ 939 #endif 940 #define RCR_TCPOFLD_EN BIT(25) /* Enable TCP checksum offload */ 941 #if 0 942 #define RCR_ENMBID BIT(24) /* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */ 943 #define RCR_LSIGEN BIT(23) /* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */ 944 #define RCR_MFBEN BIT(22) /* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */ 945 #endif 946 947 #endif /* #ifndef __INC_HAL8723DREG_H */ 948