1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_COMPILE_MU
phydm_get_gid(struct dm_struct * dm,u8 * phy_status_inf)34 u8 phydm_get_gid(struct dm_struct *dm, u8 *phy_status_inf)
35 {
36 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
37 struct phy_sts_rpt_jgr2_type1 *rpt_jgr2 = NULL;
38 #endif
39 #ifdef PHYSTS_3RD_TYPE_SUPPORT
40 struct phy_sts_rpt_jgr3_type1 *rpt_jgr3 = NULL;
41 #endif
42 u8 gid = 0;
43
44 if (dm->ic_phy_sts_type == PHYDM_PHYSTS_TYPE_1)
45 return 0;
46
47 if ((*phy_status_inf & 0xf) != 1)
48 return 0;
49
50 switch (dm->ic_phy_sts_type) {
51 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
52 case PHYDM_PHYSTS_TYPE_2:
53 rpt_jgr2 = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
54 gid = rpt_jgr2->gid;
55 break;
56 #endif
57 #ifdef PHYSTS_3RD_TYPE_SUPPORT
58 case PHYDM_PHYSTS_TYPE_3:
59 rpt_jgr3 = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
60 gid = rpt_jgr3->gid;
61 break;
62 #endif
63 default:
64 break;
65 }
66
67 return gid;
68 }
69 #endif
70
phydm_rx_statistic_cal(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo)71 void phydm_rx_statistic_cal(struct dm_struct *dm,
72 struct phydm_phyinfo_struct *phy_info,
73 u8 *phy_status_inf,
74 struct phydm_perpkt_info_struct *pktinfo)
75 {
76 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
77
78 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
79 struct phydm_bf_rate_info_jgr3 *bfrateinfo = &dm->bf_rate_info_jgr3;
80 #endif
81
82 u8 rate = (pktinfo->data_rate & 0x7f);
83 u8 bw_idx = phy_info->band_width;
84 u8 offset = 0;
85 u8 gid = 0;
86 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
87 u8 val = 0;
88 #endif
89 #ifdef PHYDM_COMPILE_MU
90 u8 is_mu_pkt = 0;
91 #endif
92
93 if (rate <= ODM_RATE54M) {
94 dbg_i->num_qry_legacy_pkt[rate]++;
95 } else if (rate <= ODM_RATEMCS31) {
96 dbg_i->ht_pkt_not_zero = true;
97 offset = rate - ODM_RATEMCS0;
98
99 if (offset > (HT_RATE_NUM - 1))
100 offset = HT_RATE_NUM - 1;
101
102 if (dm->support_ic_type &
103 (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
104 if (bw_idx == *dm->band_width) {
105 dbg_i->num_qry_ht_pkt[offset]++;
106
107 } else if (bw_idx == CHANNEL_WIDTH_20) {
108 dbg_i->num_qry_pkt_sc_20m[offset]++;
109 dbg_i->low_bw_20_occur = true;
110 }
111 } else {
112 dbg_i->num_qry_ht_pkt[offset]++;
113 }
114 }
115 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
116 else if (rate <= ODM_RATEVHTSS4MCS9) {
117 offset = rate - ODM_RATEVHTSS1MCS0;
118
119 if (offset > (VHT_RATE_NUM - 1))
120 offset = VHT_RATE_NUM - 1;
121
122 #ifdef PHYDM_COMPILE_MU
123 gid = phydm_get_gid(dm, phy_status_inf);
124
125 if (gid != 0 && gid != 63)
126 is_mu_pkt = true;
127
128 if (is_mu_pkt) {
129 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
130 (defined(PHYSTS_3RD_TYPE_SUPPORT)))
131 dbg_i->num_mu_vht_pkt[offset]++;
132 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
133 bfrateinfo->num_mu_vht_pkt[offset]++;
134 #endif
135 #else
136 dbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/
137 #endif
138 } else
139 #endif
140 {
141 dbg_i->vht_pkt_not_zero = true;
142
143 if (dm->support_ic_type &
144 (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
145 if (bw_idx == *dm->band_width) {
146 dbg_i->num_qry_vht_pkt[offset]++;
147 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
148 bfrateinfo->num_qry_vht_pkt[offset]++;
149 #endif
150
151 } else if (bw_idx == CHANNEL_WIDTH_20) {
152 dbg_i->num_qry_pkt_sc_20m[offset]++;
153 dbg_i->low_bw_20_occur = true;
154 } else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/
155 dbg_i->num_qry_pkt_sc_40m[offset]++;
156 dbg_i->low_bw_40_occur = true;
157 }
158 } else {
159 dbg_i->num_qry_vht_pkt[offset]++;
160 }
161 }
162
163 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
164 (defined(PHYSTS_3RD_TYPE_SUPPORT)))
165 if (pktinfo->ppdu_cnt < 4) {
166 val = rate;
167
168 #ifdef PHYDM_COMPILE_MU
169 if (is_mu_pkt)
170 val |= BIT(7);
171 #endif
172
173 dbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val;
174 dbg_i->gid_num[pktinfo->ppdu_cnt] = gid;
175 }
176 #endif
177 }
178 #endif
179 }
180
phydm_reset_phystatus_avg(struct dm_struct * dm)181 void phydm_reset_phystatus_avg(struct dm_struct *dm)
182 {
183 struct phydm_phystatus_avg *dbg_avg = NULL;
184
185 dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg;
186 odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0,
187 sizeof(struct phydm_phystatus_avg));
188 }
189
phydm_reset_phystatus_statistic(struct dm_struct * dm)190 void phydm_reset_phystatus_statistic(struct dm_struct *dm)
191 {
192 struct phydm_phystatus_statistic *dbg_s = NULL;
193
194 dbg_s = &dm->phy_dbg_info.physts_statistic_info;
195
196 odm_memory_set(dm, &dbg_s->rssi_cck_sum, 0,
197 sizeof(struct phydm_phystatus_statistic));
198 }
199
phydm_reset_phy_info(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info)200 void phydm_reset_phy_info(struct dm_struct *dm,
201 struct phydm_phyinfo_struct *phy_info)
202 {
203 u8 i = 0;
204
205 odm_memory_set(dm, &phy_info->physts_rpt_valid, 0,
206 sizeof(struct phydm_phyinfo_struct));
207
208 phy_info->rx_power = -110;
209 phy_info->recv_signal_power = -110;
210
211 for (i = 0; i < dm->num_rf_path; i++)
212 phy_info->rx_pwr[i] = -110;
213 }
214
phydm_avg_rssi_evm_snr(void * dm_void,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)215 void phydm_avg_rssi_evm_snr(void *dm_void,
216 struct phydm_phyinfo_struct *phy_info,
217 struct phydm_perpkt_info_struct *pktinfo)
218 {
219 struct dm_struct *dm = (struct dm_struct *)dm_void;
220 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
221 struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
222 u8 *rssi = phy_info->rx_mimo_signal_strength;
223 u8 *evm = phy_info->rx_mimo_evm_dbm;
224 s8 *snr = phy_info->rx_snr;
225 u32 size = PHYSTS_PATH_NUM; /*size of path=4*/
226 u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
227 u16 val = 0, intvl = 0;
228 u8 i = 0;
229
230 if (pktinfo->is_packet_beacon) {
231 for (i = 0; i < dm->num_rf_path; i++)
232 dbg_s->rssi_beacon_sum[i] += rssi[i];
233
234 dbg_s->rssi_beacon_cnt++;
235 }
236
237 if (pktinfo->data_rate <= ODM_RATE11M) {
238 /*RSSI*/
239 dbg_s->rssi_cck_sum += rssi[0];
240 #if (defined(PHYSTS_3RD_TYPE_SUPPORT) && defined(PHYDM_COMPILE_ABOVE_2SS))
241 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
242 for (i = 1; i < dm->num_rf_path; i++)
243 dbg_s->rssi_cck_sum_abv_2ss[i - 1] += rssi[i];
244 }
245 #endif
246 dbg_s->rssi_cck_cnt++;
247 } else if (pktinfo->data_rate <= ODM_RATE54M) {
248 for (i = 0; i < dm->num_rf_path; i++) {
249 /*SNR & RSSI*/
250 dbg_s->snr_ofdm_sum[i] += snr[i];
251 dbg_s->rssi_ofdm_sum[i] += rssi[i];
252 }
253 /*@evm*/
254 dbg_s->evm_ofdm_sum += evm[0];
255 dbg_s->rssi_ofdm_cnt++;
256
257 val = (u16)evm[0];
258 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
259 dbg_s->evm_ofdm_hist[intvl]++;
260
261 val = (u16)snr[0];
262 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
263 dbg_s->snr_ofdm_hist[intvl]++;
264
265 } else if (pktinfo->rate_ss == 1) {
266 /*@===[1-SS]==================================================================*/
267 for (i = 0; i < dm->num_rf_path; i++) {
268 /*SNR & RSSI*/
269 dbg_s->snr_1ss_sum[i] += snr[i];
270 dbg_s->rssi_1ss_sum[i] += rssi[i];
271 }
272
273 /*@evm*/
274 dbg_s->evm_1ss_sum += evm[0];
275 /*@EVM Histogram*/
276 val = (u16)evm[0];
277 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
278 dbg_s->evm_1ss_hist[intvl]++;
279
280 /*SNR Histogram*/
281 val = (u16)snr[0];
282 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
283 dbg_s->snr_1ss_hist[intvl]++;
284
285 dbg_s->rssi_1ss_cnt++;
286 } else if (pktinfo->rate_ss == 2) {
287 /*@===[2-SS]==================================================================*/
288 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
289 for (i = 0; i < dm->num_rf_path; i++) {
290 /*SNR & RSSI*/
291 dbg_s->snr_2ss_sum[i] += snr[i];
292 dbg_s->rssi_2ss_sum[i] += rssi[i];
293 }
294
295 for (i = 0; i < pktinfo->rate_ss; i++) {
296 /*@evm*/
297 dbg_s->evm_2ss_sum[i] += evm[i];
298 /*@EVM Histogram*/
299 val = (u16)evm[i];
300 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
301 size_th);
302 dbg_s->evm_2ss_hist[i][intvl]++;
303
304 /*SNR Histogram*/
305 val = (u16)snr[i];
306 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
307 size_th);
308 dbg_s->snr_2ss_hist[i][intvl]++;
309 }
310 dbg_s->rssi_2ss_cnt++;
311 #endif
312 } else if (pktinfo->rate_ss == 3) {
313 /*@===[3-SS]==================================================================*/
314 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
315 for (i = 0; i < dm->num_rf_path; i++) {
316 /*SNR & RSSI*/
317 dbg_s->snr_3ss_sum[i] += snr[i];
318 dbg_s->rssi_3ss_sum[i] += rssi[i];
319 }
320
321 for (i = 0; i < pktinfo->rate_ss; i++) {
322 /*@evm*/
323 dbg_s->evm_3ss_sum[i] += evm[i];
324 /*@EVM Histogram*/
325 val = (u16)evm[i];
326 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
327 size_th);
328 dbg_s->evm_3ss_hist[i][intvl]++;
329
330 /*SNR Histogram*/
331 val = (u16)snr[i];
332 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
333 size_th);
334 dbg_s->snr_3ss_hist[i][intvl]++;
335 }
336 dbg_s->rssi_3ss_cnt++;
337 #endif
338 } else if (pktinfo->rate_ss == 4) {
339 /*@===[4-SS]==================================================================*/
340 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
341 for (i = 0; i < dm->num_rf_path; i++) {
342 /*SNR & RSSI*/
343 dbg_s->snr_4ss_sum[i] += snr[i];
344 dbg_s->rssi_4ss_sum[i] += rssi[i];
345 }
346
347 for (i = 0; i < pktinfo->rate_ss; i++) {
348 /*@evm*/
349 dbg_s->evm_4ss_sum[i] += evm[i];
350
351 /*@EVM Histogram*/
352 val = (u16)evm[i];
353 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
354 size_th);
355 dbg_s->evm_4ss_hist[i][intvl]++;
356
357 /*SNR Histogram*/
358 val = (u16)snr[i];
359 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
360 size_th);
361 dbg_s->snr_4ss_hist[i][intvl]++;
362 }
363 dbg_s->rssi_4ss_cnt++;
364 #endif
365 }
366 }
367
phydm_avg_phystatus_init(void * dm_void)368 void phydm_avg_phystatus_init(void *dm_void)
369 {
370 struct dm_struct *dm = (struct dm_struct *)dm_void;
371 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
372 u16 snr_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
373 29, 32, 35};
374 u16 evm_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
375 29, 32, 35};
376 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
377 u16 cn_hist_th[PHY_HIST_TH_SIZE] = {2, 3, 4, 5, 6, 8, 10,
378 12, 14, 16, 18};
379 #endif
380 u32 size = PHY_HIST_TH_SIZE * 2;
381 u8 i = 0;
382
383 odm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size);
384 odm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size);
385 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
386 dm->pkt_proc_struct.physts_auto_swch_en = false;
387 for (i = 0; i < PHY_HIST_TH_SIZE; i++)
388 dbg_i->cn_hist_th[i] = cn_hist_th[i] << 1;
389 #endif
390 }
391
phydm_get_signal_quality(struct phydm_phyinfo_struct * phy_info,struct dm_struct * dm,struct phy_status_rpt_8192cd * phy_sts)392 u8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info,
393 struct dm_struct *dm,
394 struct phy_status_rpt_8192cd *phy_sts)
395 {
396 u8 sq_rpt;
397 u8 result = 0;
398
399 if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) {
400 result = 100;
401 } else {
402 sq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all;
403
404 if (sq_rpt > 64)
405 result = 0;
406 else if (sq_rpt < 20)
407 result = 100;
408 else
409 result = ((64 - sq_rpt) * 100) / 44;
410 }
411
412 return result;
413 }
414
phydm_pw_2_percent(s8 ant_power)415 u8 phydm_pw_2_percent(s8 ant_power)
416 {
417 if ((ant_power <= -100) || ant_power >= 20)
418 return 0;
419 else if (ant_power >= 0)
420 return 100;
421 else
422 return 100 + ant_power;
423 }
424
425 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
phydm_process_signal_strength(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)426 void phydm_process_signal_strength(struct dm_struct *dm,
427 struct phydm_phyinfo_struct *phy_info,
428 struct phydm_perpkt_info_struct *pktinfo)
429 {
430 boolean is_cck_rate = 0;
431 u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0;
432 u8 ss = 0; /*signal strenth after scale mapping*/
433 u8 pwdb = phy_info->rx_pwdb_all;
434 u8 i;
435
436 is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
437
438 /*use the best two RSSI only*/
439 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
440 tmp_rssi = phy_info->rx_mimo_signal_strength[i];
441
442 /*@Get the best two RSSI*/
443 if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) {
444 second_rssi = best_rssi;
445 best_rssi = tmp_rssi;
446 } else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) {
447 second_rssi = tmp_rssi;
448 }
449 }
450
451 if (best_rssi == 0)
452 return;
453
454 if (pktinfo->rate_ss == 1)
455 avg_rssi = best_rssi;
456 else
457 avg_rssi = (best_rssi + second_rssi) >> 1;
458
459 /* Update signal strength to UI,
460 * and phy_info->rx_pwdb_all is the maximum RSSI of all path
461 */
462 if (dm->support_ic_type & (PHYSTS_3RD_TYPE_IC | PHYSTS_2ND_TYPE_IC))
463 ss = SignalScaleProc(dm->adapter, pwdb, false, false);
464 else
465 ss = SignalScaleProc(dm->adapter, pwdb, true, is_cck_rate);
466
467 phy_info->signal_strength = ss;
468 }
469
phydm_sq_patch_lenovo(struct dm_struct * dm,u8 is_cck_rate,u8 pwdb_all,u8 path,u8 RSSI)470 static u8 phydm_sq_patch_lenovo(
471 struct dm_struct *dm,
472 u8 is_cck_rate,
473 u8 pwdb_all,
474 u8 path,
475 u8 RSSI)
476 {
477 u8 sq = 0;
478
479 if (is_cck_rate) {
480 if (dm->support_ic_type & ODM_RTL8192E) {
481 /*@
482 * <Roger_Notes>
483 * Expected signal strength and bars indication at Lenovo lab. 2013.04.11
484 * 802.11n, 802.11b, 802.11g only at channel 6
485 *
486 * Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm)
487 * 50 5 -49
488 * 55 5 -49
489 * 60 5 -50
490 * 65 5 -51
491 * 70 5 -52
492 * 75 5 -54
493 * 80 5 -55
494 * 85 4 -60
495 * 90 3 -63
496 * 95 3 -65
497 * 100 2 -67
498 * 102 2 -67
499 * 104 1 -70
500 */
501 if (pwdb_all >= 50)
502 sq = 100;
503 else if (pwdb_all >= 35 && pwdb_all < 50)
504 sq = 80;
505 else if (pwdb_all >= 31 && pwdb_all < 35)
506 sq = 60;
507 else if (pwdb_all >= 22 && pwdb_all < 31)
508 sq = 40;
509 else if (pwdb_all >= 18 && pwdb_all < 22)
510 sq = 20;
511 else
512 sq = 10;
513 } else {
514 if (pwdb_all >= 50)
515 sq = 100;
516 else if (pwdb_all >= 35 && pwdb_all < 50)
517 sq = 80;
518 else if (pwdb_all >= 22 && pwdb_all < 35)
519 sq = 60;
520 else if (pwdb_all >= 18 && pwdb_all < 22)
521 sq = 40;
522 else
523 sq = 10;
524 }
525
526 } else {
527 /* OFDM rate */
528
529 if (dm->support_ic_type & ODM_RTL8192E) {
530 if (RSSI >= 45)
531 sq = 100;
532 else if (RSSI >= 22 && RSSI < 45)
533 sq = 80;
534 else if (RSSI >= 18 && RSSI < 22)
535 sq = 40;
536 else
537 sq = 20;
538 } else {
539 if (RSSI >= 45)
540 sq = 100;
541 else if (RSSI >= 22 && RSSI < 45)
542 sq = 80;
543 else if (RSSI >= 18 && RSSI < 22)
544 sq = 40;
545 else
546 sq = 20;
547 }
548 }
549 return sq;
550 }
551
phydm_sq_patch_rt_cid_819x_acer(struct dm_struct * dm,u8 is_cck_rate,u8 pwdb_all,u8 path,u8 RSSI)552 static u8 phydm_sq_patch_rt_cid_819x_acer(
553 struct dm_struct *dm,
554 u8 is_cck_rate,
555 u8 pwdb_all,
556 u8 path,
557 u8 RSSI)
558 {
559 u8 sq = 0;
560
561 if (is_cck_rate) {
562 #if OS_WIN_FROM_WIN8(OS_VERSION)
563 if (pwdb_all >= 50)
564 sq = 100;
565 else if (pwdb_all >= 35 && pwdb_all < 50)
566 sq = 80;
567 else if (pwdb_all >= 30 && pwdb_all < 35)
568 sq = 60;
569 else if (pwdb_all >= 25 && pwdb_all < 30)
570 sq = 40;
571 else if (pwdb_all >= 20 && pwdb_all < 25)
572 sq = 20;
573 else
574 sq = 10;
575 #else
576 if (pwdb_all >= 50)
577 sq = 100;
578 else if (pwdb_all >= 35 && pwdb_all < 50)
579 sq = 80;
580 else if (pwdb_all >= 30 && pwdb_all < 35)
581 sq = 60;
582 else if (pwdb_all >= 25 && pwdb_all < 30)
583 sq = 40;
584 else if (pwdb_all >= 20 && pwdb_all < 25)
585 sq = 20;
586 else
587 sq = 10;
588
589 /* @Abnormal case, do not indicate the value above 20 on Win7 */
590 if (pwdb_all == 0)
591 sq = 20;
592 #endif
593
594 } else {
595 /* OFDM rate */
596 if (dm->support_ic_type & ODM_RTL8192E) {
597 if (RSSI >= 45)
598 sq = 100;
599 else if (RSSI >= 22 && RSSI < 45)
600 sq = 80;
601 else if (RSSI >= 18 && RSSI < 22)
602 sq = 40;
603 else
604 sq = 20;
605 } else {
606 if (RSSI >= 35)
607 sq = 100;
608 else if (RSSI >= 30 && RSSI < 35)
609 sq = 80;
610 else if (RSSI >= 25 && RSSI < 30)
611 sq = 40;
612 else
613 sq = 20;
614 }
615 }
616 return sq;
617 }
618 #endif
619
620 static u8
phydm_evm_2_percent(s8 value)621 phydm_evm_2_percent(s8 value)
622 {
623 /* @-33dB~0dB to 0%~99% */
624 s8 ret_val;
625
626 ret_val = value;
627 ret_val /= 2;
628
629 /*@dbg_print("value=%d\n", value);*/
630 #ifdef ODM_EVM_ENHANCE_ANTDIV
631 if (ret_val >= 0)
632 ret_val = 0;
633
634 if (ret_val <= -40)
635 ret_val = -40;
636
637 ret_val = 0 - ret_val;
638 ret_val *= 3;
639 #else
640 if (ret_val >= 0)
641 ret_val = 0;
642
643 if (ret_val <= -33)
644 ret_val = -33;
645
646 ret_val = 0 - ret_val;
647 ret_val *= 3;
648
649 if (ret_val == 99)
650 ret_val = 100;
651 #endif
652
653 return (u8)ret_val;
654 }
655
phydm_cck_rssi_convert(struct dm_struct * dm,u16 lna_idx,u8 vga_idx)656 s8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
657 {
658 /*@phydm_get_cck_rssi_table_from_reg*/
659 return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1));
660 }
661
phydm_get_cck_rssi_table_from_reg(struct dm_struct * dm)662 void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm)
663 {
664 u8 used_lna_idx_tmp;
665 u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd;
666 u32 val = 0;
667 u8 i;
668
669 /*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/
670 /*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/
671
672 PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n");
673
674 if (!(dm->support_ic_type & ODM_RTL8197F))
675 return;
676
677 reg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF);
678 reg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD);
679
680 PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80);
681 PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc);
682
683 for (i = 0; i <= 3; i++) {
684 used_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7);
685 val = (reg_0xabc >> (8 * i)) & 0xff;
686 dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val;
687 }
688
689 PHYDM_DBG(dm, ODM_COMP_INIT,
690 "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n",
691 dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1],
692 dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3],
693 dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5],
694 dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]);
695 }
696
phydm_get_cck_rssi(void * dm_void,u8 lna_idx,u8 vga_idx)697 s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx)
698 {
699 struct dm_struct *dm = (struct dm_struct *)dm_void;
700 s8 rx_pow = 0;
701
702 switch (dm->support_ic_type) {
703 #if (RTL8197F_SUPPORT)
704 case ODM_RTL8197F:
705 rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx);
706 break;
707 #endif
708
709 #if (RTL8723D_SUPPORT)
710 case ODM_RTL8723D:
711 rx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx);
712 break;
713 #endif
714
715 #if (RTL8710B_SUPPORT)
716 case ODM_RTL8710B:
717 rx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx);
718 break;
719 #endif
720
721 #if (RTL8721D_SUPPORT)
722 case ODM_RTL8721D:
723 rx_pow = phydm_cckrssi_8721d(dm, lna_idx, vga_idx);
724 break;
725 #endif
726
727 #if (RTL8710C_SUPPORT)
728 case ODM_RTL8710C:
729 rx_pow = phydm_cckrssi_8710c(dm, lna_idx, vga_idx);
730 break;
731 #endif
732
733 #if (RTL8192F_SUPPORT)
734 case ODM_RTL8192F:
735 rx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx);
736 break;
737 #endif
738
739 #if (RTL8821C_SUPPORT)
740 case ODM_RTL8821C:
741 rx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx);
742 break;
743 #endif
744
745 #if (RTL8195B_SUPPORT)
746 case ODM_RTL8195B:
747 rx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx);
748 break;
749 #endif
750
751 #if (RTL8188E_SUPPORT)
752 case ODM_RTL8188E:
753 rx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx);
754 break;
755 #endif
756
757 #if (RTL8192E_SUPPORT)
758 case ODM_RTL8192E:
759 rx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx);
760 break;
761 #endif
762
763 #if (RTL8723B_SUPPORT)
764 case ODM_RTL8723B:
765 rx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx);
766 break;
767 #endif
768
769 #if (RTL8703B_SUPPORT)
770 case ODM_RTL8703B:
771 rx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx);
772 break;
773 #endif
774
775 #if (RTL8188F_SUPPORT)
776 case ODM_RTL8188F:
777 rx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx);
778 break;
779 #endif
780
781 #if (RTL8195A_SUPPORT)
782 case ODM_RTL8195A:
783 rx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx);
784 break;
785 #endif
786
787 #if (RTL8812A_SUPPORT)
788 case ODM_RTL8812:
789 rx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx);
790 break;
791 #endif
792
793 #if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
794 case ODM_RTL8821:
795 case ODM_RTL8881A:
796 rx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx);
797 break;
798 #endif
799
800 #if (RTL8814A_SUPPORT)
801 case ODM_RTL8814A:
802 rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx);
803 break;
804 #endif
805
806 default:
807 break;
808 }
809
810 return rx_pow;
811 }
812
813 #if (ODM_IC_11N_SERIES_SUPPORT)
phydm_phy_sts_n_parsing(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo)814 void phydm_phy_sts_n_parsing(struct dm_struct *dm,
815 struct phydm_phyinfo_struct *phy_info,
816 u8 *phy_status_inf,
817 struct phydm_perpkt_info_struct *pktinfo)
818 {
819 u8 i = 0;
820 s8 rx_pwr[4], rx_pwr_all = 0;
821 u8 EVM, pwdb_all = 0, pwdb_all_bt = 0;
822 u8 RSSI, total_rssi = 0;
823 u8 rf_rx_num = 0;
824 u8 lna_idx = 0;
825 u8 vga_idx = 0;
826 u8 cck_agc_rpt;
827 s8 evm_tmp = 0;
828 u8 sq = 0;
829 u8 val_tmp = 0;
830 s8 val_s8 = 0;
831 struct phy_status_rpt_8192cd *phy_sts = NULL;
832
833 phy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf;
834
835 if (pktinfo->is_cck_rate) {
836 cck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a;
837
838 /*@3 bit LNA*/
839 lna_idx = ((cck_agc_rpt & 0xE0) >> 5);
840 vga_idx = (cck_agc_rpt & 0x1F);
841
842 #if (RTL8703B_SUPPORT)
843 if (dm->support_ic_type & (ODM_RTL8703B) &&
844 dm->cck_agc_report_type == 1) {
845 /*@4 bit LNA*/
846 if (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7))
847 val_tmp = 1;
848 else
849 val_tmp = 0;
850 lna_idx = (val_tmp << 3) | lna_idx;
851 }
852 #endif
853
854 rx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
855
856 PHYDM_DBG(dm, DBG_RSSI_MNTR,
857 "ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
858 dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all);
859
860 if (dm->board_type & ODM_BOARD_EXT_LNA)
861 rx_pwr_all -= dm->ext_lna_gain;
862
863 pwdb_all = phydm_pw_2_percent(rx_pwr_all);
864
865 if (pktinfo->is_to_self) {
866 dm->cck_lna_idx = lna_idx;
867 dm->cck_vga_idx = vga_idx;
868 }
869
870 phy_info->rx_pwdb_all = pwdb_all;
871 phy_info->bt_rx_rssi_percentage = pwdb_all;
872 phy_info->recv_signal_power = rx_pwr_all;
873
874 /* @(3) Get Signal Quality (EVM) */
875 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
876 if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)
877 sq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
878 else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
879 sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
880 else
881 #endif
882 sq = phydm_get_signal_quality(phy_info, dm, phy_sts);
883
884 /* @dbg_print("cck sq = %d\n", sq); */
885
886 phy_info->signal_quality = sq;
887 phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq;
888 phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
889
890 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
891 if (i == 0)
892 phy_info->rx_mimo_signal_strength[0] = pwdb_all;
893 else
894 phy_info->rx_mimo_signal_strength[i] = 0;
895 }
896 } else { /* @2 is OFDM rate */
897
898 /* @(1)Get RSSI for HT rate */
899
900 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
901 if (dm->rf_path_rx_enable & BIT(i))
902 rf_rx_num++;
903
904 val_s8 = phy_sts->path_agc[i].gain & 0x3F;
905 rx_pwr[i] = (val_s8 * 2) - 110;
906
907 if (pktinfo->is_to_self)
908 dm->ofdm_agc_idx[i] = val_s8;
909
910 phy_info->rx_pwr[i] = rx_pwr[i];
911 RSSI = phydm_pw_2_percent(rx_pwr[i]);
912 total_rssi += RSSI;
913
914 phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
915
916 /* @Get Rx snr value in DB */
917 val_s8 = (s8)(phy_sts->path_rxsnr[i] / 2);
918 phy_info->rx_snr[i] = val_s8;
919
920 /* Record Signal Strength for next packet */
921
922 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
923 if (i == RF_PATH_A) {
924 if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
925 phy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI);
926 } else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
927 phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI);
928 }
929 #endif
930 }
931
932 /* @(2)PWDB, Average PWDB calculated by hardware (for RA) */
933 val_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1;
934 rx_pwr_all = (val_s8 & 0x7f) - 110;
935
936 pwdb_all = phydm_pw_2_percent(rx_pwr_all);
937 pwdb_all_bt = pwdb_all;
938
939 phy_info->rx_pwdb_all = pwdb_all;
940 phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
941 phy_info->rx_power = rx_pwr_all;
942 phy_info->recv_signal_power = rx_pwr_all;
943
944 /* @(3)EVM of HT rate */
945 for (i = 0; i < pktinfo->rate_ss; i++) {
946 /* @Do not use shift operation like "rx_evmX >>= 1"
947 * because the compilor of free build environment
948 * fill most significant bit to "zero" when doing shifting
949 * operation which may change a negative
950 * value to positive one, then the dbm value
951 * (which is supposed to be negative) is not correct anymore.
952 */
953 if (i >= PHYDM_MAX_RF_PATH_N)
954 break;
955
956 EVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]);
957
958 /*@Fill value in RFD, Get the 1st spatial stream only*/
959 if (i == RF_PATH_A)
960 phy_info->signal_quality = (u8)(EVM & 0xff);
961
962 phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);
963
964 if (phy_sts->stream_rxevm[i] < 0)
965 evm_tmp = 0 - phy_sts->stream_rxevm[i];
966
967 if (evm_tmp == 64)
968 evm_tmp = 0;
969
970 phy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp;
971 }
972 phydm_parsing_cfo(dm, pktinfo,
973 phy_sts->path_cfotail, pktinfo->rate_ss);
974 }
975
976 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
977 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel;
978 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b;
979 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2;
980 #endif
981 }
982 #endif
983
984 #if ODM_IC_11AC_SERIES_SUPPORT
985 static s16
phydm_cfo(s8 value)986 phydm_cfo(s8 value)
987 {
988 s16 ret_val;
989
990 if (value < 0) {
991 ret_val = 0 - value;
992 ret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */
993 ret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/
994 } else {
995 ret_val = value;
996 ret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/
997 }
998 return ret_val;
999 }
1000
1001 static u8
phydm_evm_dbm(s8 value)1002 phydm_evm_dbm(s8 value)
1003 {
1004 s8 ret_val = value;
1005
1006 /* @-33dB~0dB to 33dB ~ 0dB */
1007 if (ret_val == -128)
1008 ret_val = 127;
1009 else if (ret_val < 0)
1010 ret_val = 0 - ret_val;
1011
1012 ret_val = ret_val >> 1;
1013 return (u8)ret_val;
1014 }
1015
phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo,struct phy_status_rpt_8812 * phy_sts)1016 void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info,
1017 struct phydm_perpkt_info_struct *
1018 pktinfo,
1019 struct phy_status_rpt_8812 *
1020 phy_sts)
1021 {
1022 if (pktinfo->data_rate > ODM_RATE54M) {
1023 switch (phy_sts->r_RFMOD) {
1024 case 1:
1025 if (phy_sts->sub_chnl == 0)
1026 phy_info->band_width = 1;
1027 else
1028 phy_info->band_width = 0;
1029 break;
1030
1031 case 2:
1032 if (phy_sts->sub_chnl == 0)
1033 phy_info->band_width = 2;
1034 else if (phy_sts->sub_chnl == 9 ||
1035 phy_sts->sub_chnl == 10)
1036 phy_info->band_width = 1;
1037 else
1038 phy_info->band_width = 0;
1039 break;
1040
1041 default:
1042 case 0:
1043 phy_info->band_width = 0;
1044 break;
1045 }
1046 }
1047 }
1048
phydm_get_sq(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 is_cck_rate)1049 void phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info,
1050 u8 is_cck_rate)
1051 {
1052 u8 sq = 0;
1053 u8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/
1054 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1055 u8 rssi = phy_info->rx_mimo_signal_strength[0];
1056 #endif
1057
1058 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1059 if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
1060 if (is_cck_rate)
1061 sq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0);
1062 else
1063 sq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi);
1064 } else
1065 #endif
1066 {
1067 if (is_cck_rate) {
1068 if (pwdb_all > 40 && !dm->is_in_hct_test) {
1069 sq = 100;
1070 } else {
1071 if (pwdb_all > 64)
1072 sq = 0;
1073 else if (pwdb_all < 20)
1074 sq = 100;
1075 else
1076 sq = ((64 - pwdb_all) * 100) / 44;
1077 }
1078 } else {
1079 sq = phy_info->rx_mimo_signal_quality[0];
1080 }
1081 }
1082
1083 #if 0
1084 /* @dbg_print("cck sq = %d\n", sq); */
1085 #endif
1086 phy_info->signal_quality = sq;
1087 }
1088
phydm_rx_physts_1st_type(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo)1089 void phydm_rx_physts_1st_type(struct dm_struct *dm,
1090 struct phydm_phyinfo_struct *phy_info,
1091 u8 *phy_status_inf,
1092 struct phydm_perpkt_info_struct *pktinfo)
1093 {
1094 u8 i = 0;
1095 s8 rx_pwr_db = 0;
1096 u8 val = 0; /*tmp value*/
1097 s8 val_s8 = 0; /*tmp value*/
1098 u8 rssi = 0; /*pre path RSSI*/
1099 u8 rf_rx_num = 0;
1100 u8 lna_idx = 0, vga_idx = 0;
1101 u8 cck_agc_rpt = 0;
1102 struct phy_status_rpt_8812 *phy_sts = NULL;
1103 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1104 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1105 #endif
1106
1107 phy_sts = (struct phy_status_rpt_8812 *)phy_status_inf;
1108 phydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts);
1109
1110 /* @== [CCK rate] ====================================================*/
1111 if (pktinfo->is_cck_rate) {
1112 cck_agc_rpt = phy_sts->cfosho[0];
1113 lna_idx = (cck_agc_rpt & 0xE0) >> 5;
1114 vga_idx = cck_agc_rpt & 0x1F;
1115
1116 rx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
1117 rssi = phydm_pw_2_percent(rx_pwr_db);
1118
1119 if (dm->support_ic_type == ODM_RTL8812 &&
1120 !dm->is_cck_high_power) {
1121 if (rssi >= 80) {
1122 rssi = ((rssi - 80) << 1) +
1123 ((rssi - 80) >> 1) + 80;
1124 } else if ((rssi <= 78) && (rssi >= 20)) {
1125 rssi += 3;
1126 }
1127 }
1128 dm->cck_lna_idx = lna_idx;
1129 dm->cck_vga_idx = vga_idx;
1130
1131 phy_info->rx_pwdb_all = rssi;
1132 phy_info->rx_mimo_signal_strength[0] = rssi;
1133 } else {
1134 /* @== [OFDM rate] ===================================================*/
1135 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
1136 /*@[RSSI]*/
1137 if (dm->rf_path_rx_enable & BIT(i))
1138 rf_rx_num++;
1139
1140 if (i < RF_PATH_C)
1141 val = phy_sts->gain_trsw[i];
1142 else
1143 val = phy_sts->gain_trsw_cd[i - 2];
1144
1145 phy_info->rx_pwr[i] = (val & 0x7F) - 110;
1146 rssi = phydm_pw_2_percent(phy_info->rx_pwr[i]);
1147 phy_info->rx_mimo_signal_strength[i] = rssi;
1148
1149 /*@[SNR]*/
1150 if (i < RF_PATH_C)
1151 val_s8 = phy_sts->rxsnr[i];
1152 else if (dm->support_ic_type & (ODM_RTL8814A))
1153 val_s8 = (s8)phy_sts->csi_current[i - 2];
1154
1155 phy_info->rx_snr[i] = val_s8 >> 1;
1156
1157 /*@[CFO_short & CFO_tail]*/
1158 if (i < RF_PATH_C) {
1159 val_s8 = phy_sts->cfosho[i];
1160 phy_info->cfo_short[i] = phydm_cfo(val_s8);
1161 val_s8 = phy_sts->cfotail[i];
1162 phy_info->cfo_tail[i] = phydm_cfo(val_s8);
1163 }
1164
1165 if (i < RF_PATH_C && pktinfo->is_to_self)
1166 dm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i];
1167 }
1168
1169 /* @== [PWDB] ========================================================*/
1170
1171 /*@(Avg PWDB calculated by hardware*/
1172 if (!dm->is_mp_chip) /*@8812, 8821*/
1173 val = phy_sts->pwdb_all;
1174 else
1175 val = phy_sts->pwdb_all >> 1; /*old fomula*/
1176
1177 rx_pwr_db = (val & 0x7f) - 110;
1178 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db);
1179
1180 /*@(4)EVM of OFDM rate*/
1181 for (i = 0; i < pktinfo->rate_ss; i++) {
1182 if (!pktinfo->is_cck_rate &&
1183 pktinfo->data_rate <= ODM_RATE54M) {
1184 val_s8 = phy_sts->sigevm;
1185 } else if (i < RF_PATH_C) {
1186 if (phy_sts->rxevm[i] == -128)
1187 phy_sts->rxevm[i] = -25;
1188
1189 val_s8 = phy_sts->rxevm[i];
1190 } else {
1191 if (phy_sts->rxevm_cd[i - 2] == -128)
1192 phy_sts->rxevm_cd[i - 2] = -25;
1193
1194 val_s8 = phy_sts->rxevm_cd[i - 2];
1195 }
1196 /*@[EVM to 0~100%]*/
1197 val = phydm_evm_2_percent(val_s8);
1198 phy_info->rx_mimo_signal_quality[i] = val;
1199 /*@[EVM dBm]*/
1200 phy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8);
1201 }
1202 phydm_parsing_cfo(dm, pktinfo,
1203 phy_sts->cfotail, pktinfo->rate_ss);
1204 }
1205
1206 /* @== [General Info] ================================================*/
1207
1208 phy_info->rx_power = rx_pwr_db;
1209 phy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all;
1210 phy_info->recv_signal_power = phy_info->rx_power;
1211 phydm_get_sq(dm, phy_info, pktinfo->is_cck_rate);
1212
1213 dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;
1214
1215 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1216 fat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur;
1217 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta;
1218 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb;
1219 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc;
1220 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd;
1221 #endif
1222 }
1223
1224 #endif
1225
phydm_reset_rssi_for_dm(struct dm_struct * dm,u8 station_id)1226 void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id)
1227 {
1228 struct cmn_sta_info *sta;
1229
1230 sta = dm->phydm_sta_info[station_id];
1231
1232 if (!is_sta_active(sta))
1233 return;
1234 PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n",
1235 station_id);
1236
1237 sta->rssi_stat.rssi_cck = -1;
1238 sta->rssi_stat.rssi_ofdm = -1;
1239 sta->rssi_stat.rssi = -1;
1240 sta->rssi_stat.ofdm_pkt_cnt = 0;
1241 sta->rssi_stat.cck_pkt_cnt = 0;
1242 sta->rssi_stat.cck_sum_power = 0;
1243 sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
1244 sta->rssi_stat.packet_map = 0;
1245 sta->rssi_stat.valid_bit = 0;
1246 }
1247
1248 #if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
1249
phydm_get_rssi_8814_ofdm(struct dm_struct * dm,u8 * rssi_in)1250 s32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in)
1251 {
1252 s32 rssi_avg;
1253 u8 rx_count = 0;
1254 u64 rssi_linear = 0;
1255
1256 if (dm->rx_ant_status & BB_PATH_A) {
1257 rx_count++;
1258 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]);
1259 }
1260
1261 if (dm->rx_ant_status & BB_PATH_B) {
1262 rx_count++;
1263 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]);
1264 }
1265
1266 if (dm->rx_ant_status & BB_PATH_C) {
1267 rx_count++;
1268 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]);
1269 }
1270
1271 if (dm->rx_ant_status & BB_PATH_D) {
1272 rx_count++;
1273 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]);
1274 }
1275
1276 /* @Rounding and removing fractional bits */
1277 rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
1278
1279 /* @Calculate average RSSI */
1280 switch (rx_count) {
1281 case 2:
1282 rssi_linear = DIVIDED_2(rssi_linear);
1283 break;
1284 case 3:
1285 rssi_linear = DIVIDED_3(rssi_linear);
1286 break;
1287 case 4:
1288 rssi_linear = DIVIDED_4(rssi_linear);
1289 break;
1290 }
1291 rssi_avg = odm_convert_to_db(rssi_linear);
1292
1293 return rssi_avg;
1294 }
1295
phydm_process_rssi_for_dm(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)1296 void phydm_process_rssi_for_dm(struct dm_struct *dm,
1297 struct phydm_phyinfo_struct *phy_info,
1298 struct phydm_perpkt_info_struct *pktinfo)
1299 {
1300 s32 rssi_ave = 0; /*@average among all paths*/
1301 s8 rssi_all = 0; /*@average value of CCK & OFDM*/
1302 s8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0;
1303 u8 i = 0;
1304 u8 rssi_max = 0, rssi_min = 0;
1305 u32 w1 = 0, w2 = 0; /*weighting*/
1306 u8 send_rssi_2_fw = 0;
1307 u8 *rssi_tmp = NULL;
1308 struct cmn_sta_info *sta = NULL;
1309 struct rssi_info *rssi_t = NULL;
1310 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1311 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1312 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1313 #endif
1314 #endif
1315
1316 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
1317 return;
1318
1319 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
1320 odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo);
1321 #endif
1322
1323 sta = dm->phydm_sta_info[pktinfo->station_id];
1324
1325 if (!is_sta_active(sta))
1326 return;
1327
1328 rssi_t = &sta->rssi_stat;
1329
1330 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1331 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1332 if ((dm->support_ability & ODM_BB_ANT_DIV) &&
1333 fat_tab->enable_ctrl_frame_antdiv) {
1334 if (pktinfo->is_packet_match_bssid)
1335 dm->data_frame_num++;
1336
1337 if (fat_tab->use_ctrl_frame_antdiv) {
1338 if (!pktinfo->is_to_self) /*@data frame + CTRL frame*/
1339 return;
1340 } else {
1341 /*@data frame only*/
1342 if (!pktinfo->is_packet_match_bssid)
1343 return;
1344 }
1345 } else
1346 #endif
1347 #endif
1348 {
1349 if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
1350 return;
1351 }
1352
1353 if (pktinfo->is_packet_beacon) {
1354 dm->phy_dbg_info.num_qry_beacon_pkt++;
1355 dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
1356 }
1357
1358 /* @--------------Statistic for antenna/path diversity--------------- */
1359 #ifdef ODM_EVM_ENHANCE_ANTDIV
1360 if (dm->antdiv_evm_en)
1361 phydm_rx_rate_for_antdiv(dm, pktinfo);
1362 #endif
1363
1364 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
1365 if (dm->support_ability & ODM_BB_ANT_DIV)
1366 odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
1367 #endif
1368
1369 #if (defined(CONFIG_PATH_DIVERSITY))
1370 if (dm->support_ability & ODM_BB_PATH_DIV)
1371 phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
1372 #endif
1373 /* @----------------------------------------------------------------- */
1374
1375 rssi_cck_tmp = rssi_t->rssi_cck;
1376 rssi_ofdm_tmp = rssi_t->rssi_ofdm;
1377 rssi_all = rssi_t->rssi;
1378
1379 if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon))
1380 return;
1381
1382 if (!pktinfo->is_cck_rate) {
1383 /* @=== [ofdm RSSI] ======================================================== */
1384 rssi_tmp = phy_info->rx_mimo_signal_strength;
1385
1386 #if (RTL8814A_SUPPORT == 1)
1387 if (dm->support_ic_type & (ODM_RTL8814A)) {
1388 rssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp);
1389 } else
1390 #endif
1391 {
1392 if (rssi_tmp[RF_PATH_B] == 0) {
1393 rssi_ave = rssi_tmp[RF_PATH_A];
1394 } else {
1395 if (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) {
1396 rssi_max = rssi_tmp[RF_PATH_A];
1397 rssi_min = rssi_tmp[RF_PATH_B];
1398 } else {
1399 rssi_max = rssi_tmp[RF_PATH_B];
1400 rssi_min = rssi_tmp[RF_PATH_A];
1401 }
1402 if ((rssi_max - rssi_min) < 3)
1403 rssi_ave = rssi_max;
1404 else if ((rssi_max - rssi_min) < 6)
1405 rssi_ave = rssi_max - 1;
1406 else if ((rssi_max - rssi_min) < 10)
1407 rssi_ave = rssi_max - 2;
1408 else
1409 rssi_ave = rssi_max - 3;
1410 }
1411 }
1412
1413 /* OFDM MA RSSI */
1414 if (rssi_ofdm_tmp <= 0) { /* @initialize */
1415 rssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all;
1416 } else {
1417 rssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp,
1418 (1 << RSSI_MA) - 1,
1419 rssi_ave, 1);
1420 if (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp)
1421 rssi_ofdm_tmp++;
1422 }
1423
1424 PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_ofdm=%d\n", rssi_ofdm_tmp);
1425 } else {
1426 /* @=== [cck RSSI] ========================================================= */
1427 rssi_ave = phy_info->rx_pwdb_all;
1428
1429 if (rssi_t->cck_pkt_cnt <= 63)
1430 rssi_t->cck_pkt_cnt++;
1431
1432 /* @1 Process CCK RSSI */
1433 if (rssi_cck_tmp <= 0) { /* @initialize */
1434 rssi_cck_tmp = (s8)phy_info->rx_pwdb_all;
1435 rssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all;
1436 rssi_t->cck_pkt_cnt = 1; /*reset*/
1437 PHYDM_DBG(dm, DBG_RSSI_MNTR, "[1]CCK_INIT\n");
1438 } else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) {
1439 rssi_t->cck_sum_power = rssi_t->cck_sum_power +
1440 (u16)phy_info->rx_pwdb_all;
1441
1442 rssi_cck_tmp = rssi_t->cck_sum_power /
1443 rssi_t->cck_pkt_cnt;
1444
1445 PHYDM_DBG(dm, DBG_RSSI_MNTR,
1446 "[2]SumPow=%d, cck_pkt=%d\n",
1447 rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt);
1448 } else {
1449 rssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp,
1450 (1 << RSSI_MA) - 1,
1451 phy_info->rx_pwdb_all,
1452 1);
1453 if (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp)
1454 rssi_cck_tmp++;
1455 }
1456 PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_cck=%d\n", rssi_cck_tmp);
1457 }
1458
1459 /* @=== [ofdm + cck weighting RSSI] ========================================= */
1460 if (!pktinfo->is_cck_rate) {
1461 if (rssi_t->ofdm_pkt_cnt < 8 && !(rssi_t->packet_map & BIT(7)))
1462 rssi_t->ofdm_pkt_cnt++; /*OFDM packet cnt in bitmap*/
1463
1464 rssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0);
1465 } else {
1466 if (rssi_t->ofdm_pkt_cnt > 0 && rssi_t->packet_map & BIT(7))
1467 rssi_t->ofdm_pkt_cnt--;
1468
1469 rssi_t->packet_map = rssi_t->packet_map << 1;
1470 }
1471
1472 if (rssi_t->ofdm_pkt_cnt == 8) {
1473 rssi_all = rssi_ofdm_tmp;
1474 } else {
1475 if (rssi_t->valid_bit < 8)
1476 rssi_t->valid_bit++;
1477
1478 if (rssi_t->valid_bit == 8) {
1479 if (rssi_t->ofdm_pkt_cnt > 4)
1480 w1 = 64;
1481 else
1482 w1 = (u32)(rssi_t->ofdm_pkt_cnt << 4);
1483
1484 w2 = 64 - w1;
1485
1486 rssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp +
1487 w2 * (u32)rssi_cck_tmp) >> 6);
1488 } else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 8)*/
1489 w1 = (u32)rssi_t->ofdm_pkt_cnt;
1490 w2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt);
1491 rssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1,
1492 (u32)rssi_cck_tmp, w2);
1493 } else {
1494 rssi_all = 0;
1495 }
1496 }
1497 PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi=%d,w1=%d,w2=%d\n", rssi_all, w1, w2);
1498
1499 if ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) &&
1500 rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) {
1501 send_rssi_2_fw = 1;
1502 rssi_t->is_send_rssi = RA_RSSI_STATE_SEND;
1503 }
1504
1505 rssi_t->rssi_cck = rssi_cck_tmp;
1506 rssi_t->rssi_ofdm = rssi_ofdm_tmp;
1507 rssi_t->rssi = rssi_all;
1508
1509 if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
1510 if (rssi_t->ofdm_pkt_cnt != 0)
1511 rssi_t->rssi = rssi_ofdm_tmp;
1512
1513 PHYDM_DBG(dm, DBG_RSSI_MNTR,
1514 "[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\n",
1515 rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt);
1516 }
1517
1518 #if 0
1519 /* @dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting);*/
1520 /* @dbg_print("rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\n", */
1521 /* rssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */
1522 #endif
1523 }
1524 #endif
1525
1526 #ifdef PHYSTS_3RD_TYPE_SUPPORT
1527 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
phydm_physts_auto_switch_jgr3_reset(void * dm_void)1528 void phydm_physts_auto_switch_jgr3_reset(void *dm_void)
1529 {
1530 struct dm_struct *dm = (struct dm_struct *)dm_void;
1531 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
1532
1533 pkt_proc->phy_ppdu_cnt = 0xff;
1534 pkt_proc->mac_ppdu_cnt = 0xff;
1535 pkt_proc->page_bitmap_record = 0;
1536 }
1537
phydm_physts_auto_switch_jgr3(void * dm_void,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo)1538 boolean phydm_physts_auto_switch_jgr3(void *dm_void, u8 *phy_sts,
1539 struct phydm_perpkt_info_struct *pktinfo)
1540 {
1541 struct dm_struct *dm = (struct dm_struct *)dm_void;
1542 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
1543 boolean is_skip_physts_parsing = false;
1544 u8 phy_sts_byte0 = (*phy_sts & 0xff);
1545 u8 phy_ppdu_cnt_pre = 0, mac_ppdu_cnt_pre = 0;
1546 u8 ppdu_phy_rate_pre = 0, ppdu_macid_pre = 0;
1547 u8 page = phy_sts_byte0 & 0xf;
1548
1549 if (!pkt_proc->physts_auto_swch_en)
1550 return is_skip_physts_parsing;
1551
1552 phy_ppdu_cnt_pre = pkt_proc->phy_ppdu_cnt;
1553 mac_ppdu_cnt_pre = pkt_proc->mac_ppdu_cnt;
1554 ppdu_phy_rate_pre = pkt_proc->ppdu_phy_rate;
1555 ppdu_macid_pre = pkt_proc->ppdu_macid;
1556
1557 pkt_proc->phy_ppdu_cnt = (phy_sts_byte0 & 0x30) >> 4;
1558 pkt_proc->mac_ppdu_cnt = pktinfo->ppdu_cnt;
1559 pkt_proc->ppdu_phy_rate = pktinfo->data_rate;
1560 pkt_proc->ppdu_macid = pktinfo->station_id;
1561
1562 PHYDM_DBG(dm, DBG_PHY_STATUS,
1563 "[rate:0x%x] PPDU mac{pre, curr}= {%d, %d}, phy{pre, curr}= {%d, %d}\n",
1564 pktinfo->data_rate, mac_ppdu_cnt_pre, pkt_proc->mac_ppdu_cnt,
1565 phy_ppdu_cnt_pre, pkt_proc->phy_ppdu_cnt);
1566
1567 if (pktinfo->data_rate < ODM_RATEMCS0) {
1568 pkt_proc->page_bitmap_record = 0;
1569 return is_skip_physts_parsing;
1570 }
1571
1572 if (ppdu_macid_pre == pkt_proc->ppdu_macid &&
1573 ppdu_phy_rate_pre == pkt_proc->ppdu_phy_rate &&
1574 phy_ppdu_cnt_pre == pkt_proc->phy_ppdu_cnt &&
1575 mac_ppdu_cnt_pre == pkt_proc->mac_ppdu_cnt) {
1576 if (pkt_proc->page_bitmap_record & BIT(page)) {
1577 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect page-%d enough\n", page);*/
1578 is_skip_physts_parsing = true;
1579 } else if (pkt_proc->page_bitmap_record ==
1580 pkt_proc->page_bitmap_target) {
1581 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect all enough\n");*/
1582 is_skip_physts_parsing = true;
1583 } else {
1584 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "update page-%d\n", page);*/
1585 pkt_proc->page_bitmap_record |= BIT(page);
1586 }
1587 pkt_proc->is_1st_mpdu = false;
1588 } else {
1589 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "[New Pkt] update page-%d\n", page);*/
1590 pkt_proc->page_bitmap_record = BIT(page);
1591 pkt_proc->is_1st_mpdu = true;
1592 }
1593
1594 PHYDM_DBG(dm, DBG_PHY_STATUS,
1595 "bitmap{record, target}= {0x%x, 0x%x}\n",
1596 pkt_proc->page_bitmap_record,
1597 pkt_proc->page_bitmap_target);
1598
1599 return is_skip_physts_parsing;
1600 }
1601
phydm_physts_auto_switch_jgr3_set(void * dm_void,boolean enable,u8 bitmap_en)1602 void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable,
1603 u8 bitmap_en)
1604 {
1605 struct dm_struct *dm = (struct dm_struct *)dm_void;
1606 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
1607 u16 en_page_num = 1;
1608
1609 if (!(dm->support_ic_type & PHYSTS_AUTO_SWITCH_IC))
1610 return;
1611 #if 0
1612 if (!(dm->support_ic_type & PHYSTS_3RD_TYPE_IC))
1613 return;
1614 #endif
1615 pkt_proc->physts_auto_swch_en = enable;
1616 pkt_proc->page_bitmap_target = bitmap_en;
1617 phydm_physts_auto_switch_jgr3_reset(dm);
1618 en_page_num = phydm_ones_num_in_bitmap((u64)bitmap_en, 8);
1619
1620 PHYDM_DBG(dm, DBG_CMN, "[%s]en=%d, bitmap_en=%d, en_page_num=%d\n",
1621 __func__, enable, bitmap_en, en_page_num);
1622
1623 if (enable) {
1624 /*@per MPDU latch & update phy-staatus*/
1625 odm_set_mac_reg(dm, R_0x60c, BIT(31), 1);
1626 /*@Update Period (OFDM Symbol)*/
1627 odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 3);
1628 /*@switchin bitmap*/
1629 odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, bitmap_en);
1630 /*@mode 3*/
1631 odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 3);
1632 } else {
1633 odm_set_mac_reg(dm, R_0x60c, BIT(31), 0);
1634 odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x1);
1635 odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, 0x2);
1636 odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 0);
1637 }
1638 }
1639
phydm_avg_condi_num(void * dm_void,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)1640 void phydm_avg_condi_num(void *dm_void,
1641 struct phydm_phyinfo_struct *phy_info,
1642 struct phydm_perpkt_info_struct *pktinfo)
1643 {
1644 struct dm_struct *dm = (struct dm_struct *)dm_void;
1645 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
1646 struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
1647 u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
1648 u16 val = 0, intvl = 0;
1649 u8 arry_idx = 0;
1650
1651 if (pktinfo->rate_ss == 1)
1652 return;
1653
1654 arry_idx = pktinfo->rate_ss - 1;
1655
1656 dbg_s->p4_cnt[arry_idx]++;
1657 dbg_s->cn_sum[arry_idx] += dbg_i->condition_num_seg0;
1658
1659 /*CN Histogram*/
1660 val = (u16)dbg_i->condition_num_seg0;
1661 intvl = phydm_find_intrvl(dm, val, dbg_i->cn_hist_th, size_th);
1662 dbg_s->cn_hist[arry_idx][intvl]++;
1663
1664 dbg_i->condi_num = (u32)dbg_i->condition_num_seg0; /*will remove*/
1665 }
1666 #endif
1667
phydm_print_phystat_jgr3(struct dm_struct * dm,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)1668 void phydm_print_phystat_jgr3(struct dm_struct *dm, u8 *phy_sts,
1669 struct phydm_perpkt_info_struct *pktinfo,
1670 struct phydm_phyinfo_struct *phy_info)
1671 {
1672 struct phy_sts_rpt_jgr3_type0 *rpt0 = NULL;
1673 struct phy_sts_rpt_jgr3_type1 *rpt1 = NULL;
1674 struct phy_sts_rpt_jgr3_type2_3 *rpt2 = NULL;
1675 struct phy_sts_rpt_jgr3_type4 *rpt3 = NULL;
1676 struct phy_sts_rpt_jgr3_type5 *rpt4 = NULL;
1677 struct phy_sts_rpt_jgr3_type6 *rpt5 = NULL;
1678
1679 struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
1680 u8 phy_status_page_num = (*phy_sts & 0xf);
1681 u32 *phy_status_tmp = NULL;
1682 u8 i = 0;
1683 /*u32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2;*/
1684
1685 if (!(dm->debug_components & DBG_PHY_STATUS))
1686 return;
1687
1688 rpt0 = (struct phy_sts_rpt_jgr3_type0 *)phy_sts;
1689 rpt1 = (struct phy_sts_rpt_jgr3_type1 *)phy_sts;
1690 rpt2 = (struct phy_sts_rpt_jgr3_type2_3 *)phy_sts;
1691 rpt3 = (struct phy_sts_rpt_jgr3_type4 *)phy_sts;
1692 rpt4 = (struct phy_sts_rpt_jgr3_type5 *)phy_sts;
1693
1694 if (dm->support_ic_type & ODM_RTL8723F) {
1695 rpt5 = (struct phy_sts_rpt_jgr3_type6 *)phy_sts;
1696
1697 if (pktinfo->is_cck_rate)
1698 phy_status_page_num = 0;
1699 }
1700
1701 phy_status_tmp = (u32 *)phy_sts;
1702
1703 if (dbg->show_phy_sts_all_pkt == 0) {
1704 if (!pktinfo->is_packet_match_bssid)
1705 return;
1706 }
1707
1708 dbg->show_phy_sts_cnt++;
1709
1710 if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
1711 if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
1712 return;
1713 }
1714
1715 if (phy_status_page_num == 0)
1716 pr_debug("Phy Status Rpt: CCK\n");
1717 else
1718 pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
1719
1720 pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d, ppdu_cnt=%d\n",
1721 pktinfo->station_id, pktinfo->data_rate,
1722 pktinfo->is_packet_match_bssid, pktinfo->ppdu_cnt);
1723
1724 for (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++)
1725 pr_debug("Offset[%d:%d] = 0x%x\n",
1726 ((4 * i) + 3), (4 * i), phy_status_tmp[i]);
1727
1728 if (phy_status_page_num == 0) { /* @CCK(default) */
1729 if (dm->support_ic_type & ODM_RTL8723F) {
1730 #if (RTL8723F_SUPPORT)
1731 pr_debug("[0] Pop_idx=%d, Pkt_cnt=%d, Channel_msb=%d, AGC_table_path0=%d, TRSW_mux_keep=%d, HW_AntSW_occur_keep_cck=%d, Gnt_BT_keep_cnt=%d,Rssi_msb=%d\n",
1732 rpt5->pop_idx, rpt5->pkt_cnt,
1733 rpt5->channel_msb, rpt5->agc_table_a,
1734 rpt5->trsw, rpt5->hw_antsw_occur_keep_cck,
1735 rpt5->gnt_bt_keep_cck, rpt5->rssi_msb);
1736 pr_debug("[4] Channel=%d, Antidx_CCK_keep=%d, Cck_mp_gain_idx_keep=%d\n",
1737 rpt5->channel, rpt5->antidx_a,
1738 rpt5->mp_gain_idx_a);
1739 pr_debug("[8] Rssi=%d\n",rpt5->rssi);
1740 pr_debug("[12] Avg_cfo=%d\n",rpt5->avg_cfo);
1741 pr_debug("[16] Coarse_cfo=%d, Coarse_cfo_msb=%d, Avg_cfo_msb=%d, Evm_hdr=%d\n",
1742 rpt5->coarse_cfo, rpt5->coarse_cfo_msb,
1743 rpt5->avg_cfo_msb, rpt5->evm_hdr);
1744 pr_debug("[20] Evm_pld=%d\n",rpt5->evm_pld);
1745 #endif
1746 } else {
1747 pr_debug("[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\n",
1748 rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a,
1749 rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b,
1750 rpt0->agc_table_c);
1751 pr_debug("[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\n",
1752 rpt0->path_sel_o, rpt0->gnt_bt_keep_cck,
1753 rpt0->hw_antsw_occur_keep_cck, rpt0->band,
1754 rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc,
1755 rpt0->agc_table_d);
1756 pr_debug("[8] AntIdx={%d, %d, %d, %d}, Length=%d\n",
1757 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
1758 rpt0->antidx_a, rpt0->length);
1759 pr_debug("[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\n",
1760 rpt0->mf_off, rpt0->sqloss, rpt0->lockbit,
1761 rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a,
1762 rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a,
1763 rpt0->signal_quality);
1764 pr_debug("[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\n",
1765 rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b,
1766 rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b);
1767 pr_debug("[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\n",
1768 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
1769 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
1770 pr_debug("[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\n",
1771 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
1772 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
1773 }
1774 } else if (phy_status_page_num == 1) {
1775 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\n",
1776 rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a,
1777 rpt1->channel_pri_msb, rpt1->pkt_cnt);
1778 pr_debug("[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\n",
1779 rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt,
1780 rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc,
1781 rpt1->l_rxsc, rpt1->pwdb_d);
1782 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Channel_sec[msb,lsb]={%d, %d}\n",
1783 rpt1->antidx_d, rpt1->antidx_c,
1784 rpt1->antidx_b, rpt1->antidx_a,
1785 rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c,
1786 rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a,
1787 rpt1->channel_sec_msb, rpt1->channel_sec_lsb);
1788 pr_debug("[12] GID=%d, PAID[msb,lsb]={%d,%d}\n",
1789 rpt1->gid, rpt1->paid_msb, rpt1->paid);
1790 pr_debug("[16] RX_EVM[D:A]={%d, %d, %d, %d}\n",
1791 rpt1->rxevm[3], rpt1->rxevm[2],
1792 rpt1->rxevm[1], rpt1->rxevm[0]);
1793 pr_debug("[20] CFO_tail[D:A]={%d, %d, %d, %d}\n",
1794 rpt1->cfo_tail[3], rpt1->cfo_tail[2],
1795 rpt1->cfo_tail[1], rpt1->cfo_tail[0]);
1796 pr_debug("[24] RX_SNR[D:A]={%d, %d, %d, %d}\n\n",
1797 rpt1->rxsnr[3], rpt1->rxsnr[2],
1798 rpt1->rxsnr[1], rpt1->rxsnr[0]);
1799 } else if (phy_status_page_num == 2 || phy_status_page_num == 3) {
1800 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
1801 rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0],
1802 rpt2->channel_msb, rpt2->pkt_cnt);
1803 pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
1804 rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt,
1805 rpt2->band, rpt2->channel_lsb,
1806 rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]);
1807 pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\n",
1808 rpt2->agc_table_d, rpt2->agc_table_c,
1809 rpt2->agc_table_b, rpt2->agc_table_a,
1810 rpt2->pwed_th, rpt2->shift_l_map);
1811 pr_debug("[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\n",
1812 rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb,
1813 rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb,
1814 rpt2->mp_gain_b_lsb, rpt2->mp_gain_a,
1815 rpt2->cnt_cca2agc_rdy);
1816 pr_debug("[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\n",
1817 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0],
1818 rpt2->aagc_step_d, rpt2->aagc_step_c,
1819 rpt2->aagc_step_b, rpt2->aagc_step_a,
1820 rpt2->is_freq_select_fading, rpt2->mp_gain_d);
1821 pr_debug("[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\n",
1822 rpt2->dagc_gain[1], rpt2->dagc_gain[0],
1823 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]);
1824 pr_debug("[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\n",
1825 rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb,
1826 rpt2->syn_count_lsb, rpt2->counter,
1827 rpt2->dagc_gain[3], rpt2->dagc_gain[2]);
1828 } else if (phy_status_page_num == 4) { /*type 4*/
1829 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
1830 rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0],
1831 rpt3->channel_msb, rpt3->pkt_cnt);
1832 pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
1833 rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt,
1834 rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc,
1835 rpt3->l_rxsc, rpt3->pwdb[3]);
1836 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\n BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\n",
1837 rpt3->antidx_d, rpt3->antidx_c,
1838 rpt3->antidx_b, rpt3->antidx_a,
1839 rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c,
1840 rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a,
1841 rpt3->training_done_d, rpt3->training_done_c,
1842 rpt3->training_done_b, rpt3->training_done_a,
1843 rpt3->bad_tone_cnt_cn_excess_0,
1844 rpt3->bad_tone_cnt_min_eign_0);
1845 pr_debug("[12] avg_cond_num_1=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d,\n bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\n",
1846 ((rpt3->avg_cond_num_1_msb << 1) |
1847 rpt3->avg_cond_num_1_lsb),
1848 rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1,
1849 rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt);
1850 pr_debug("[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\n",
1851 rpt3->rxevm[3], rpt3->rxevm[2],
1852 rpt3->rxevm[1], rpt3->rxevm[0]);
1853 pr_debug("[20] Eigenvalue[D:A]={%d, %d, %d, %d}\n",
1854 rpt3->eigenvalue[3], rpt3->eigenvalue[2],
1855 rpt3->eigenvalue[1], rpt3->eigenvalue[0]);
1856 pr_debug("[24] RX SNR[D:A]={%d, %d, %d, %d}\n",
1857 rpt3->rxsnr[3], rpt3->rxsnr[2],
1858 rpt3->rxsnr[1], rpt3->rxsnr[0]);
1859 } else if (phy_status_page_num == 5) { /*type 5*/
1860 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
1861 rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0],
1862 rpt4->channel_msb, rpt4->pkt_cnt);
1863 pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
1864 rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt,
1865 rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc,
1866 rpt4->l_rxsc, rpt4->pwdb[3]);
1867 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\n",
1868 rpt4->antidx_d, rpt4->antidx_c,
1869 rpt4->antidx_b, rpt4->antidx_a,
1870 rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c,
1871 rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a);
1872 pr_debug("[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\n",
1873 rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg,
1874 rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg,
1875 rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg,
1876 rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg,
1877 rpt4->tx_pkt_cnt);
1878 pr_debug("[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\n",
1879 rpt4->inf_pos_1_b, rpt4->inf_pos_0_b,
1880 rpt4->inf_pos_1_a, rpt4->inf_pos_0_a);
1881 pr_debug("[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\n",
1882 rpt4->inf_pos_1_d, rpt4->inf_pos_0_d,
1883 rpt4->inf_pos_1_c, rpt4->inf_pos_0_c);
1884 }
1885 }
1886
phydm_reset_phy_info_jgr3(struct dm_struct * phydm,struct phydm_phyinfo_struct * phy_info)1887 void phydm_reset_phy_info_jgr3(struct dm_struct *phydm,
1888 struct phydm_phyinfo_struct *phy_info)
1889 {
1890 u8 i;
1891
1892 phy_info->rx_pwdb_all = 0;
1893 phy_info->signal_quality = 0;
1894 phy_info->band_width = 0;
1895 phy_info->rx_count = 0;
1896 phy_info->rx_power = -110;
1897 phy_info->recv_signal_power = -110;
1898 phy_info->bt_rx_rssi_percentage = 0;
1899 phy_info->signal_strength = 0;
1900 phy_info->channel = 0;
1901 phy_info->is_mu_packet = 0;
1902 phy_info->is_beamformed = 0;
1903 phy_info->rxsc = 0;
1904
1905 for (i = 0; i < 4; i++) {
1906 phy_info->rx_mimo_signal_strength[i] = 0;
1907 phy_info->rx_mimo_signal_quality[i] = 0;
1908 phy_info->rx_mimo_evm_dbm[i] = 0;
1909 phy_info->cfo_short[i] = 0;
1910 phy_info->cfo_tail[i] = 0;
1911 phy_info->rx_pwr[i] = -110;
1912 phy_info->rx_snr[i] = 0;
1913 }
1914 }
1915
1916 #if 0
1917 void phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
1918 s8 rx_snr, struct phydm_phyinfo_struct *phy_info)
1919 {
1920 u8 evm_dbm = 0;
1921 u8 evm_percentage = 0;
1922
1923 /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
1924
1925 evm_dbm = (rx_evm == -128) ? 0 : ((u8)(0 - rx_evm) >> 1);
1926 evm_percentage = (evm_dbm >= 34) ? 100 : evm_dbm * 3;
1927
1928 phy_info->rx_pwr[rx_path] = pwr;
1929
1930 /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
1931 phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
1932 phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
1933 phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
1934 phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
1935 phy_info->rx_snr[rx_path] = rx_snr >> 1;
1936 }
1937
1938 void phydm_common_phy_info_jgr3(s8 rx_power, u8 channel, boolean is_beamformed,
1939 boolean is_mu_packet, u8 bandwidth,
1940 u8 signal_quality, u8 rxsc,
1941 struct phydm_phyinfo_struct *phy_info)
1942 {
1943 phy_info->rx_power = rx_power; /* RSSI in dB */
1944 phy_info->recv_signal_power = rx_power; /* RSSI in dB */
1945 phy_info->channel = channel; /* @channel number */
1946 phy_info->is_beamformed = is_beamformed; /* @apply BF */
1947 phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
1948 phy_info->rxsc = rxsc;
1949
1950 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power); /*percentage */
1951 phy_info->signal_quality = signal_quality; /* signal quality */
1952 phy_info->band_width = bandwidth; /* @bandwidth */
1953 }
1954 #endif
1955
phydm_get_physts_0_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)1956 void phydm_get_physts_0_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
1957 struct phydm_perpkt_info_struct *pktinfo,
1958 struct phydm_phyinfo_struct *phy_info)
1959 {
1960 /* type 0 is used for cck packet */
1961 struct phy_sts_rpt_jgr3_type0 *phy_sts = NULL;
1962 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
1963 u8 sq = 0, i, rx_cnt = 0;
1964 s8 rx_power[4], pwdb;
1965 s8 rx_pwr_db_max = -120;
1966
1967 phy_sts = (struct phy_sts_rpt_jgr3_type0 *)phy_status_inf;
1968
1969 #if (RTL8197G_SUPPORT)
1970 if (dm->support_ic_type & ODM_RTL8197G) {
1971 if (dm->rx_ant_status == BB_PATH_B) {
1972 phy_sts->pwdb_b = phy_sts->pwdb_a;
1973 phy_sts->gain_b = phy_sts->gain_a;
1974 phy_sts->pwdb_a = 0;
1975 phy_sts->gain_a = 0;
1976 }
1977 }
1978 #endif
1979
1980 rx_power[0] = phy_sts->pwdb_a;
1981 rx_power[1] = phy_sts->pwdb_b;
1982 rx_power[2] = phy_sts->pwdb_c;
1983 rx_power[3] = phy_sts->pwdb_d;
1984
1985 #if (RTL8822C_SUPPORT || RTL8197G_SUPPORT)
1986 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8197G)) {
1987 struct phydm_physts *physts_table = &dm->dm_physts_table;
1988 if (phy_sts->gain_a < physts_table->cck_gi_l_bnd)
1989 rx_power[0] += ((physts_table->cck_gi_l_bnd -
1990 phy_sts->gain_a) << 1);
1991 else if (phy_sts->gain_a > physts_table->cck_gi_u_bnd)
1992 rx_power[0] -= ((phy_sts->gain_a -
1993 physts_table->cck_gi_u_bnd) << 1);
1994
1995 if (phy_sts->gain_b < physts_table->cck_gi_l_bnd)
1996 rx_power[1] += ((physts_table->cck_gi_l_bnd -
1997 phy_sts->gain_b) << 1);
1998 else if (phy_sts->gain_b > physts_table->cck_gi_u_bnd)
1999 rx_power[1] -= ((phy_sts->gain_b -
2000 physts_table->cck_gi_u_bnd) << 1);
2001 }
2002 #endif
2003
2004 /* @Update per-path information */
2005 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2006 if ((dm->rx_ant_status & BIT(i)) == 0)
2007 continue;
2008
2009 rx_cnt++; /* @check the number of the ant */
2010
2011 if (rx_cnt > dm->num_rf_path)
2012 break;
2013
2014 if (pktinfo->is_to_self)
2015 dm->ofdm_agc_idx[i] = rx_power[i];
2016
2017 /* @Setting the RX power: agc_idx -110 dBm*/
2018 pwdb = rx_power[i] - 110;
2019
2020 phy_info->rx_pwr[i] = pwdb;
2021 phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
2022
2023 /* search maximum pwdb */
2024 if (pwdb > rx_pwr_db_max)
2025 rx_pwr_db_max = pwdb;
2026 }
2027
2028 /* @Calculate Signal Quality*/
2029 if (phy_sts->signal_quality >= 64) {
2030 sq = 0;
2031 } else if (phy_sts->signal_quality <= 20) {
2032 sq = 100;
2033 } else {
2034 /* @mapping to 2~99% */
2035 sq = 64 - phy_sts->signal_quality;
2036 sq = ((sq << 3) + sq) >> 2;
2037 }
2038
2039 /* @Modify CCK PWDB if old AGC */
2040 if (!dm->cck_new_agc) {
2041 u8 lna_idx[4], vga_idx[4];
2042
2043 lna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a);
2044 vga_idx[0] = phy_sts->vga_a;
2045 lna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b);
2046 vga_idx[1] = phy_sts->vga_b;
2047 lna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c);
2048 vga_idx[2] = phy_sts->vga_c;
2049 lna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d);
2050 vga_idx[3] = phy_sts->vga_d;
2051 }
2052
2053 /*@CCK no STBC and LDPC*/
2054 dbg_i->is_ldpc_pkt = false;
2055 dbg_i->is_stbc_pkt = false;
2056
2057 /*cck channel has hw bug, [WLANBB-1429]*/
2058 phy_info->channel = 0;
2059 phy_info->rx_power = rx_pwr_db_max;
2060 phy_info->recv_signal_power = rx_pwr_db_max;
2061 phy_info->is_beamformed = false;
2062 phy_info->is_mu_packet = false;
2063 phy_info->rxsc = phy_sts->l_rxsc;
2064 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
2065 phy_info->signal_quality = sq;
2066 phy_info->band_width = CHANNEL_WIDTH_20;
2067
2068 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2069 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2070 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2071 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2072 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2073 #endif
2074 }
2075
phydm_get_physts_1_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2076 void phydm_get_physts_1_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2077 struct phydm_perpkt_info_struct *pktinfo,
2078 struct phydm_phyinfo_struct *phy_info)
2079 {
2080 struct phy_sts_rpt_jgr3_type1 *phy_sts = NULL;
2081 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2082 s8 evm = 0;
2083 u8 i;
2084 s8 sq = 0;
2085
2086 phy_sts = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
2087
2088 /* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
2089
2090 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2091 if ((dm->rx_ant_status & BIT(i)) == 0)
2092 continue;
2093
2094 evm = phy_sts->rxevm[i];
2095 evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
2096 sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
2097
2098 phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
2099 phy_info->rx_mimo_signal_quality[i] = sq;
2100 phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
2101 /*@CFO(kHz) = CFO_tail*312.5(kHz)/2^7 ~= CFO tail * 5/2 (kHz)*/
2102 phy_info->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
2103 dbg_i->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
2104 }
2105 phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
2106
2107 if (phy_sts->gid != 0 && phy_sts->gid != 63) {
2108 phy_info->is_mu_packet = true;
2109 dbg_i->num_qry_mu_pkt++;
2110 } else {
2111 phy_info->is_mu_packet = false;
2112 }
2113
2114 phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
2115
2116 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2117 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2118 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2119 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2120 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2121 #endif
2122 }
2123
phydm_get_physts_2_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2124 void phydm_get_physts_2_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2125 struct phydm_perpkt_info_struct *pktinfo,
2126 struct phydm_phyinfo_struct *phy_info)
2127 {
2128 /* type 2 & 3 is used for ofdm packet */
2129 struct phy_sts_rpt_jgr3_type2_3 *phy_sts = NULL;
2130 }
2131
phydm_get_physts_4_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2132 void phydm_get_physts_4_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2133 struct phydm_perpkt_info_struct *pktinfo,
2134 struct phydm_phyinfo_struct *phy_info)
2135 {
2136 struct phy_sts_rpt_jgr3_type4 *phy_sts = NULL;
2137 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2138 s8 evm = 0;
2139 u8 i;
2140 s8 sq = 0;
2141
2142 phy_sts = (struct phy_sts_rpt_jgr3_type4 *)phy_status_inf;
2143
2144 /* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
2145
2146 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2147 if ((dm->rx_ant_status & BIT(i)) == 0)
2148 continue;
2149
2150 evm = phy_sts->rxevm[i];
2151 evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
2152 sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
2153
2154 phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
2155 phy_info->rx_mimo_signal_quality[i] = sq;
2156 phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
2157 }
2158 phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
2159 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2160 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2161 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2162 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2163 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2164 #endif
2165 odm_move_memory(dm, dbg_i->eigen_val, phy_sts->eigenvalue, 4);
2166 dbg_i->condition_num_seg0 = phy_sts->avg_cond_num_0;
2167 }
2168
phydm_get_physts_5_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2169 void phydm_get_physts_5_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2170 struct phydm_perpkt_info_struct *pktinfo,
2171 struct phydm_phyinfo_struct *phy_info)
2172 {
2173 struct phy_sts_rpt_jgr3_type5 *phy_sts = NULL;
2174
2175 }
2176 #if (RTL8723F_SUPPORT)
phydm_get_physts_6_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2177 void phydm_get_physts_6_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2178 struct phydm_perpkt_info_struct *pktinfo,
2179 struct phydm_phyinfo_struct *phy_info)
2180 {
2181 /* type 0 is used for cck packet */
2182 struct phy_sts_rpt_jgr3_type6 *phy_sts = NULL;
2183 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2184 u8 sq = 0, i, rx_cnt = 0;
2185 s8 rx_power[4], pwdb;
2186 s8 rx_pwr_db_max = -120;
2187 u8 evm = 0;
2188 phy_sts = (struct phy_sts_rpt_jgr3_type6 *)phy_status_inf;
2189 /* judy_add_8723F_0512 */
2190 /* rssi S(11,3) */
2191 rx_power[0] = (s8)((phy_sts->rssi_msb << 5) + (phy_sts->rssi >> 3));
2192 /* @Update per-path information */
2193 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2194 if ((dm->rx_ant_status & BIT(i)) == 0)
2195 continue;
2196
2197 rx_cnt++; /* @check the number of the ant */
2198
2199 if (rx_cnt > dm->num_rf_path)
2200 break;
2201
2202 if (pktinfo->is_to_self)
2203 dm->ofdm_agc_idx[i] = rx_power[i]+110;
2204
2205 /* @Setting the RX power: agc_idx dBm*/
2206 pwdb = rx_power[i];
2207
2208 phy_info->rx_pwr[i] = pwdb;
2209 phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
2210
2211 /* search maximum pwdb */
2212 if (pwdb > rx_pwr_db_max)
2213 rx_pwr_db_max = pwdb;
2214 }
2215
2216 /* @Calculate EVM U(8,2)*/
2217 evm = phy_sts->evm_pld >> 2;
2218 if (pktinfo->data_rate > ODM_RATE2M)
2219 phy_info->rx_cck_evm = (u8)(evm - 10);/* @5_5M/11M*/
2220 else
2221 phy_info->rx_cck_evm = (u8)(evm - 12);/* @1M/2M*/
2222
2223 sq = (phy_info->rx_cck_evm >= 34) ? 100 : phy_info->rx_cck_evm * 3;
2224 phy_info->signal_quality = sq;
2225 /*@CCK no STBC and LDPC*/
2226 dbg_i->is_ldpc_pkt = false;
2227 dbg_i->is_stbc_pkt = false;
2228
2229 /*cck channel has hw bug, [WLANBB-1429]*/
2230 phy_info->channel = 0;
2231 phy_info->rx_power = rx_pwr_db_max;
2232 phy_info->recv_signal_power = rx_pwr_db_max;
2233 phy_info->is_beamformed = false;
2234 phy_info->is_mu_packet = false;
2235 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
2236 phy_info->band_width = CHANNEL_WIDTH_20;
2237
2238 //phydm_parsing_cfo(dm, pktinfo, phy_sts->avg_cfo, pktinfo->rate_ss);
2239
2240 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2241 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2242 dm->dm_fat_table.antsel_rx_keep_1 = 0;
2243 dm->dm_fat_table.antsel_rx_keep_2 = 0;
2244 dm->dm_fat_table.antsel_rx_keep_3 = 0;
2245 #endif
2246 }
2247 #endif
phydm_get_physts_ofdm_cmn_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2248 void phydm_get_physts_ofdm_cmn_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2249 struct phydm_perpkt_info_struct *pktinfo,
2250 struct phydm_phyinfo_struct *phy_info)
2251 {
2252 struct phy_sts_rpt_jgr3_ofdm_cmn *phy_sts = NULL;
2253 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2254 s8 rx_pwr_db_max = -120;
2255 s8 pwdb = 0;
2256 u8 i, rx_cnt = 0;
2257
2258 phy_sts = (struct phy_sts_rpt_jgr3_ofdm_cmn *)phy_status_inf;
2259
2260 /* Parsing Offset0 & 4*/
2261 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2262 if ((dm->rx_ant_status & BIT(i)) == 0)
2263 continue;
2264
2265 rx_cnt++; /* @check the number of the ant */
2266
2267 pwdb = (s8)phy_sts->pwdb[i] - 110; /*@dB*/
2268
2269 if (pktinfo->is_to_self)
2270 dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
2271
2272 /* search maximum pwdb */
2273 if (pwdb > rx_pwr_db_max)
2274 rx_pwr_db_max = pwdb;
2275
2276 phy_info->rx_pwr[i] = pwdb;
2277 phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
2278 }
2279
2280 phy_info->rx_count = (rx_cnt > 0) ? rx_cnt - 1 : 0; /*from 1~4 to 0~3 */
2281 phy_info->rx_power = rx_pwr_db_max;
2282 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
2283 phy_info->recv_signal_power = rx_pwr_db_max;
2284 phy_info->channel = phy_sts->channel_lsb;
2285 phy_info->is_beamformed = (boolean)phy_sts->beamformed;
2286 phy_info->rxsc = (PHYDM_IS_LEGACY_RATE(pktinfo->data_rate)) ?
2287 phy_sts->l_rxsc : phy_sts->ht_rxsc;
2288 phy_info->band_width = phydm_rxsc_2_bw(dm, phy_info->rxsc);
2289
2290 dbg_i->is_ldpc_pkt = phy_sts->ldpc;
2291 dbg_i->is_stbc_pkt = phy_sts->stbc;
2292 dbg_i->num_qry_bf_pkt += phy_sts->beamformed;
2293 }
2294
phydm_process_dm_rssi_jgr3(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)2295 void phydm_process_dm_rssi_jgr3(struct dm_struct *dm,
2296 struct phydm_phyinfo_struct *phy_info,
2297 struct phydm_perpkt_info_struct *pktinfo)
2298 {
2299 struct cmn_sta_info *sta = NULL;
2300 struct rssi_info *rssi_t = NULL;
2301 u8 rssi_tmp = 0;
2302 u64 rssi_linear = 0;
2303 s16 rssi_db = 0;
2304 u8 i = 0;
2305 u8 rx_count = 0;
2306
2307 #if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
2308 struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
2309 #endif
2310
2311 /*@[Step4]*/
2312 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
2313 return;
2314
2315 sta = dm->phydm_sta_info[pktinfo->station_id];
2316
2317 if (!is_sta_active(sta))
2318 return;
2319
2320 if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
2321 return;
2322
2323 if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
2324 return;
2325
2326 if (pktinfo->is_packet_beacon) {
2327 dm->phy_dbg_info.num_qry_beacon_pkt++;
2328 dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
2329 }
2330
2331 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2332 if (dm->support_ability & ODM_BB_ANT_DIV)
2333 odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
2334 #endif
2335
2336 #ifdef ODM_EVM_ENHANCE_ANTDIV
2337 phydm_rx_rate_for_antdiv(dm, pktinfo);
2338 #endif
2339
2340 #if (defined(CONFIG_PATH_DIVERSITY))
2341 if (dm->support_ability & ODM_BB_PATH_DIV)
2342 phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
2343 #endif
2344
2345 #if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
2346 if (cckrx_t->en_cck_rx_pathdiv)
2347 phydm_process_rssi_for_cck_rx_pathdiv(dm, phy_info, pktinfo);
2348 #endif
2349
2350 rssi_t = &sta->rssi_stat;
2351
2352 for (i = 0; i < dm->num_rf_path; i++) {
2353 rssi_tmp = phy_info->rx_mimo_signal_strength[i];
2354 if (rssi_tmp != 0) {
2355 rx_count++;
2356 rssi_linear += phydm_db_2_linear(rssi_tmp);
2357 }
2358 }
2359 /* @Rounding and removing fractional bits */
2360 rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
2361
2362 switch (rx_count) {
2363 case 2:
2364 rssi_linear = DIVIDED_2(rssi_linear);
2365 break;
2366 case 3:
2367 rssi_linear = DIVIDED_3(rssi_linear);
2368 break;
2369 case 4:
2370 rssi_linear = DIVIDED_4(rssi_linear);
2371 break;
2372 }
2373
2374 rssi_db = (s16)odm_convert_to_db(rssi_linear);
2375
2376 if (rssi_t->rssi_acc == 0) {
2377 rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
2378 rssi_t->rssi = (s8)(rssi_db);
2379 } else {
2380 rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
2381 rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
2382 }
2383
2384 if (pktinfo->is_cck_rate)
2385 rssi_t->rssi_cck = (s8)rssi_db;
2386 else
2387 rssi_t->rssi_ofdm = (s8)rssi_db;
2388 }
2389
phydm_rx_physts_jgr3(void * dm_void,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2390 void phydm_rx_physts_jgr3(void *dm_void, u8 *phy_sts,
2391 struct phydm_perpkt_info_struct *pktinfo,
2392 struct phydm_phyinfo_struct *phy_info)
2393 {
2394 struct dm_struct *dm = (struct dm_struct *)dm_void;
2395 u8 phy_status_type = (*phy_sts & 0xf);
2396 if (dm->support_ic_type & ODM_RTL8723F) {
2397 if (pktinfo->data_rate <= ODM_RATE11M)
2398 phy_status_type = 6;
2399 }
2400 /*@[Step 2]*/
2401 /*phydm_reset_phy_info_jgr3(dm, phy_info);*/ /* @Memory reset */
2402
2403 /* Phy status parsing */
2404 switch (phy_status_type) {
2405 case 0: /*@CCK*/
2406 phydm_get_physts_0_jgr3(dm, phy_sts, pktinfo, phy_info);
2407 break;
2408 case 1:
2409 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2410 phydm_get_physts_1_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2411 break;
2412 case 2:
2413 case 3:
2414 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2415 phydm_get_physts_2_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2416 break;
2417 case 4:
2418 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2419 phydm_get_physts_4_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2420 break;
2421 case 5:
2422 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2423 phydm_get_physts_5_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2424 break;
2425 #if (RTL8723F_SUPPORT)
2426 case 6:
2427 phydm_get_physts_6_jgr3(dm, phy_sts, pktinfo, phy_info);
2428 break;
2429 #endif
2430 default:
2431 break;
2432 }
2433
2434 #if 0
2435 PHYDM_DBG(dm, DBG_PHY_STATUS, "RSSI: {%d, %d}\n",
2436 phy_info->rx_mimo_signal_strength[0],
2437 phy_info->rx_mimo_signal_strength[1]);
2438 PHYDM_DBG(dm, DBG_PHY_STATUS, "rxdb: {%d, %d}\n",
2439 phy_info->rx_pwr[0], phy_info->rx_pwr[1]);
2440 PHYDM_DBG(dm, DBG_PHY_STATUS, "EVM: {%d, %d}\n",
2441 phy_info->rx_mimo_evm_dbm[0], phy_info->rx_mimo_evm_dbm[1]);
2442 PHYDM_DBG(dm, DBG_PHY_STATUS, "SQ: {%d, %d}\n",
2443 phy_info->rx_mimo_signal_quality[0],
2444 phy_info->rx_mimo_signal_quality[1]);
2445 PHYDM_DBG(dm, DBG_PHY_STATUS, "SNR: {%d, %d}\n",
2446 phy_info->rx_snr[0], phy_info->rx_snr[1]);
2447 PHYDM_DBG(dm, DBG_PHY_STATUS, "CFO: {%d, %d}\n",
2448 phy_info->cfo_tail[0], phy_info->cfo_tail[1]);
2449 PHYDM_DBG(dm, DBG_PHY_STATUS,
2450 "rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
2451 phy_info->rx_pwdb_all, phy_info->rx_power,
2452 phy_info->recv_signal_power);
2453 PHYDM_DBG(dm, DBG_PHY_STATUS, "signal_quality = %d\n",
2454 phy_info->signal_quality);
2455 PHYDM_DBG(dm, DBG_PHY_STATUS,
2456 "is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
2457 phy_info->is_beamformed, phy_info->is_mu_packet,
2458 phy_info->rx_count);
2459 PHYDM_DBG(dm, DBG_PHY_STATUS,
2460 "channel = %d, rxsc = %d, band_width = %d\n",
2461 phy_info->channel, phy_info->rxsc, phy_info->band_width);
2462 #endif
2463
2464 /*@[Step 1]*/
2465 phydm_print_phystat_jgr3(dm, phy_sts, pktinfo, phy_info);
2466 }
2467
2468 #endif
2469
2470 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
2471 /* @For 8822B only!! need to move to FW finally */
2472 /*@==============================================*/
2473
2474 boolean
phydm_query_is_mu_api(struct dm_struct * phydm,u8 ppdu_idx,u8 * p_data_rate,u8 * p_gid)2475 phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
2476 u8 *p_gid)
2477 {
2478 u8 data_rate = 0, gid = 0;
2479 boolean is_mu = false;
2480
2481 data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
2482 gid = phydm->phy_dbg_info.gid_num[ppdu_idx];
2483
2484 if (data_rate & BIT(7)) {
2485 is_mu = true;
2486 data_rate = data_rate & ~(BIT(7));
2487 } else {
2488 is_mu = false;
2489 }
2490
2491 *p_data_rate = data_rate;
2492 *p_gid = gid;
2493
2494 return is_mu;
2495 }
2496
phydm_print_phy_sts_jgr2(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2497 void phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf,
2498 struct phydm_perpkt_info_struct *pktinfo,
2499 struct phydm_phyinfo_struct *phy_info)
2500 {
2501 struct phy_sts_rpt_jgr2_type0 *rpt0 = NULL;
2502 struct phy_sts_rpt_jgr2_type1 *rpt = NULL;
2503 struct phy_sts_rpt_jgr2_type2 *rpt2 = NULL;
2504 struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
2505 u8 phy_status_page_num = (*phy_status_inf & 0xf);
2506 u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0};
2507 u8 i;
2508 u32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2;
2509
2510 rpt0 = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
2511 rpt = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
2512 rpt2 = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
2513
2514 odm_move_memory(dm, phy_status, phy_status_inf, size);
2515
2516 if (!(dm->debug_components & DBG_PHY_STATUS))
2517 return;
2518
2519 if (dbg->show_phy_sts_all_pkt == 0) {
2520 if (!pktinfo->is_packet_match_bssid)
2521 return;
2522 }
2523
2524 dbg->show_phy_sts_cnt++;
2525 #if 0
2526 dbg_print("cnt=%d, max=%d\n",
2527 dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt);
2528 #endif
2529
2530 if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
2531 if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
2532 return;
2533 }
2534
2535 pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
2536 pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n",
2537 pktinfo->station_id, pktinfo->data_rate,
2538 pktinfo->is_packet_match_bssid);
2539
2540 for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++)
2541 pr_debug("Offset[%d:%d] = 0x%x\n",
2542 ((4 * i) + 3), (4 * i), phy_status[i]);
2543
2544 if (phy_status_page_num == 0) {
2545 pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n",
2546 rpt0->trsw, rpt0->gain, rpt0->pwdb);
2547 pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n",
2548 rpt0->band, rpt0->channel,
2549 rpt0->agc_table, rpt0->rxsc);
2550 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
2551 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
2552 rpt0->antidx_a, rpt0->length);
2553 pr_debug("[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\n",
2554 rpt0->lna_h, rpt0->bb_power, rpt0->lna_l,
2555 rpt0->vga, rpt0->signal_quality);
2556
2557 } else if (phy_status_page_num == 1) {
2558 pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
2559 rpt->pwdb[3], rpt->pwdb[2],
2560 rpt->pwdb[1], rpt->pwdb[0]);
2561 pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n",
2562 rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt,
2563 rpt->hw_antsw_occu, rpt->band, rpt->channel,
2564 rpt->ht_rxsc, rpt->l_rxsc);
2565 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
2566 rpt->antidx_d, rpt->antidx_c, rpt->antidx_b,
2567 rpt->antidx_a, rpt->lsig_length);
2568 pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n",
2569 rpt->rf_mode, rpt->nb_intf_flag,
2570 (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid,
2571 (rpt->paid + (rpt->paid_msb << 8)));
2572 pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n",
2573 rpt->rxevm[3], rpt->rxevm[2],
2574 rpt->rxevm[1], rpt->rxevm[0]);
2575 pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n",
2576 rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1],
2577 rpt->cfo_tail[0]);
2578 pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n",
2579 rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1],
2580 rpt->rxsnr[0]);
2581
2582 } else if (phy_status_page_num == 2) {
2583 pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
2584 rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1],
2585 rpt2->pwdb[0]);
2586 pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\n",
2587 rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt,
2588 rpt2->hw_antsw_occu, rpt2->band, rpt2->channel,
2589 rpt2->ht_rxsc, rpt2->l_rxsc);
2590 pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n",
2591 rpt2->agc_table_d, rpt2->agc_table_c,
2592 rpt2->agc_table_b, rpt2->agc_table_a,
2593 rpt2->cnt_pw2cca, rpt2->shift_l_map);
2594 pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n",
2595 rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c,
2596 rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a,
2597 rpt2->gain_a, rpt2->cnt_cca2agc_rdy);
2598 pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n",
2599 rpt2->aagc_step_d, rpt2->aagc_step_c,
2600 rpt2->aagc_step_b, rpt2->aagc_step_a,
2601 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2],
2602 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]);
2603 pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n",
2604 rpt2->dagc_gain[3],
2605 rpt2->dagc_gain[2], rpt2->dagc_gain[1],
2606 rpt2->dagc_gain[0]);
2607 pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n",
2608 rpt2->syn_count, rpt2->counter);
2609 }
2610 }
2611
phydm_set_per_path_phy_info(u8 rx_path,s8 pwr,s8 rx_evm,s8 cfo_tail,s8 rx_snr,u8 ant_idx,struct phydm_phyinfo_struct * phy_info)2612 void phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
2613 s8 rx_snr, u8 ant_idx,
2614 struct phydm_phyinfo_struct *phy_info)
2615 {
2616 u8 evm_dbm = 0;
2617 u8 evm_percentage = 0;
2618
2619 /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
2620
2621 if (rx_evm < 0) {
2622 /* @Calculate EVM in dBm */
2623 evm_dbm = ((u8)(0 - rx_evm) >> 1);
2624
2625 if (evm_dbm == 64)
2626 evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/
2627
2628 if (evm_dbm != 0) {
2629 /* @Convert EVM to 0%~100% percentage */
2630 if (evm_dbm >= 34)
2631 evm_percentage = 100;
2632 else
2633 evm_percentage = (evm_dbm << 1) + (evm_dbm);
2634 }
2635 }
2636
2637 phy_info->rx_pwr[rx_path] = pwr;
2638
2639 /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
2640 phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
2641 phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
2642 phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
2643 phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
2644 phy_info->rx_snr[rx_path] = rx_snr >> 1;
2645 phy_info->ant_idx[rx_path] = ant_idx;
2646
2647 #if 0
2648 if (!pktinfo->is_packet_match_bssid)
2649 return;
2650
2651 dbg_print("path (%d)--------\n", rx_path);
2652 dbg_print("rx_pwr = %d, Signal strength = %d\n",
2653 phy_info->rx_pwr[rx_path],
2654 phy_info->rx_mimo_signal_strength[rx_path]);
2655 dbg_print("evm_dbm = %d, Signal quality = %d\n",
2656 phy_info->rx_mimo_evm_dbm[rx_path],
2657 phy_info->rx_mimo_signal_quality[rx_path]);
2658 dbg_print("CFO = %d, SNR = %d\n",
2659 phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]);
2660
2661 #endif
2662 }
2663
phydm_set_common_phy_info(s8 rx_power,u8 channel,boolean is_beamformed,boolean is_mu_packet,u8 bandwidth,u8 signal_quality,u8 rxsc,struct phydm_phyinfo_struct * phy_info)2664 void phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed,
2665 boolean is_mu_packet, u8 bandwidth,
2666 u8 signal_quality, u8 rxsc,
2667 struct phydm_phyinfo_struct *phy_info)
2668 {
2669 phy_info->rx_power = rx_power; /* RSSI in dB */
2670 phy_info->recv_signal_power = rx_power; /* RSSI in dB */
2671 phy_info->channel = channel; /* @channel number */
2672 phy_info->is_beamformed = is_beamformed; /* @apply BF */
2673 phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
2674 phy_info->rxsc = rxsc;
2675
2676 /* RSSI in percentage */
2677 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power);
2678 phy_info->signal_quality = signal_quality; /* signal quality */
2679 phy_info->band_width = bandwidth; /* @bandwidth */
2680
2681 #if 0
2682 if (!pktinfo->is_packet_match_bssid)
2683 return;
2684
2685 dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
2686 phy_info->rx_pwdb_all, phy_info->rx_power,
2687 phy_info->recv_signal_power);
2688 dbg_print("signal_quality = %d\n", phy_info->signal_quality);
2689 dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
2690 phy_info->is_beamformed, phy_info->is_mu_packet,
2691 phy_info->rx_count + 1);
2692 dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel,
2693 rxsc, bandwidth);
2694
2695 #endif
2696 }
2697
phydm_get_phy_sts_type0(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2698 void phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf,
2699 struct phydm_perpkt_info_struct *pktinfo,
2700 struct phydm_phyinfo_struct *phy_info)
2701 {
2702 /* type 0 is used for cck packet */
2703 struct phy_sts_rpt_jgr2_type0 *phy_sts = NULL;
2704 u8 sq = 0;
2705 s8 rx_pow = 0;
2706 u8 lna_idx = 0, vga_idx = 0;
2707 u8 ant_idx;
2708
2709 phy_sts = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
2710 rx_pow = phy_sts->pwdb - 110;
2711
2712 /* Fill in per-path antenna index */
2713 ant_idx = phy_sts->antidx_a;
2714
2715 if (dm->support_ic_type & ODM_RTL8723D) {
2716 #if (RTL8723D_SUPPORT)
2717 rx_pow = phy_sts->pwdb - 97;
2718 #endif
2719 }
2720 #if (RTL8821C_SUPPORT)
2721 else if (dm->support_ic_type & ODM_RTL8821C) {
2722 if (phy_sts->pwdb >= -57)
2723 rx_pow = phy_sts->pwdb - 100;
2724 else
2725 rx_pow = phy_sts->pwdb - 102;
2726 }
2727 #endif
2728
2729 if (pktinfo->is_to_self) {
2730 dm->ofdm_agc_idx[0] = phy_sts->pwdb;
2731 dm->ofdm_agc_idx[1] = 0;
2732 dm->ofdm_agc_idx[2] = 0;
2733 dm->ofdm_agc_idx[3] = 0;
2734 }
2735
2736 /* @Calculate Signal Quality*/
2737 if (phy_sts->signal_quality >= 64) {
2738 sq = 0;
2739 } else if (phy_sts->signal_quality <= 20) {
2740 sq = 100;
2741 } else {
2742 /* @mapping to 2~99% */
2743 sq = 64 - phy_sts->signal_quality;
2744 sq = ((sq << 3) + sq) >> 2;
2745 }
2746
2747 /* @Get RSSI for old CCK AGC */
2748 if (!dm->cck_new_agc) {
2749 vga_idx = phy_sts->vga;
2750
2751 if (dm->support_ic_type & ODM_RTL8197F) {
2752 /*@3bit LNA*/
2753 lna_idx = phy_sts->lna_l;
2754 } else {
2755 /*@4bit LNA*/
2756 lna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l;
2757 }
2758 rx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
2759 }
2760
2761 /* @Confirm CCK RSSI */
2762 #if (RTL8197F_SUPPORT)
2763 if (dm->support_ic_type & ODM_RTL8197F) {
2764 u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */
2765 u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */
2766
2767 if (phy_sts->bb_power < bb_pwr_th_l ||
2768 phy_sts->bb_power > bb_pwr_th_h)
2769 rx_pow = 0; /* @Error RSSI for CCK ; set 100*/
2770 }
2771 #endif
2772
2773 /*@CCK no STBC and LDPC*/
2774 dm->phy_dbg_info.is_ldpc_pkt = false;
2775 dm->phy_dbg_info.is_stbc_pkt = false;
2776
2777 /* Update Common information */
2778 phydm_set_common_phy_info(rx_pow, phy_sts->channel, false,
2779 false, CHANNEL_WIDTH_20, sq,
2780 phy_sts->rxsc, phy_info);
2781 /* Update CCK pwdb */
2782 phydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, ant_idx,
2783 phy_info);
2784
2785 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2786 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2787 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2788 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2789 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2790 #endif
2791 }
2792
phydm_get_phy_sts_type1(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2793 void phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf,
2794 struct phydm_perpkt_info_struct *pktinfo,
2795 struct phydm_phyinfo_struct *phy_info)
2796 {
2797 /* type 1 is used for ofdm packet */
2798 struct phy_sts_rpt_jgr2_type1 *phy_sts = NULL;
2799 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2800 s8 rx_pwr_db = -120;
2801 s8 rx_pwr = 0;
2802 u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
2803 boolean is_mu;
2804 u8 ant_idx[4];
2805
2806 phy_sts = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
2807
2808 /* Fill in per-path antenna index */
2809 ant_idx[0] = phy_sts->antidx_a;
2810 ant_idx[1] = phy_sts->antidx_b;
2811 ant_idx[2] = phy_sts->antidx_c;
2812 ant_idx[3] = phy_sts->antidx_d;
2813
2814 /* Update per-path information */
2815 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
2816 if (!(dm->rx_ant_status & BIT(i)))
2817 continue;
2818 rx_count++;
2819
2820 if (rx_count > dm->num_rf_path)
2821 break;
2822
2823 /* Update per-path information
2824 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
2825 */
2826 /* @EVM report is reported by stream, not path */
2827 rx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/
2828
2829 if (pktinfo->is_to_self)
2830 dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
2831
2832 phydm_set_per_path_phy_info(i, rx_pwr,
2833 phy_sts->rxevm[rx_count - 1],
2834 phy_sts->cfo_tail[i],
2835 phy_sts->rxsnr[i],
2836 ant_idx[i], phy_info);
2837 /* search maximum pwdb */
2838 if (rx_pwr > rx_pwr_db)
2839 rx_pwr_db = rx_pwr;
2840 }
2841
2842 /* @mapping RX counter from 1~4 to 0~3 */
2843 if (rx_count > 0)
2844 phy_info->rx_count = rx_count - 1;
2845
2846 /* @Check if MU packet or not */
2847 if (phy_sts->gid != 0 && phy_sts->gid != 63) {
2848 is_mu = true;
2849 dbg_i->num_qry_mu_pkt++;
2850 } else {
2851 is_mu = false;
2852 }
2853
2854 /* @count BF packet */
2855 dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;
2856
2857 /*STBC or LDPC pkt*/
2858 dbg_i->is_ldpc_pkt = phy_sts->ldpc;
2859 dbg_i->is_stbc_pkt = phy_sts->stbc;
2860
2861 /* @Check sub-channel */
2862 if (pktinfo->data_rate > ODM_RATE11M &&
2863 pktinfo->data_rate < ODM_RATEMCS0)
2864 rxsc = phy_sts->l_rxsc;
2865 else
2866 rxsc = phy_sts->ht_rxsc;
2867
2868 /* @Check RX bandwidth */
2869 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2870 if (rxsc >= 1 && rxsc <= 8)
2871 bw = CHANNEL_WIDTH_20;
2872 else if ((rxsc >= 9) && (rxsc <= 12))
2873 bw = CHANNEL_WIDTH_40;
2874 else if (rxsc >= 13)
2875 bw = CHANNEL_WIDTH_80;
2876 else
2877 bw = phy_sts->rf_mode;
2878
2879 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
2880 if (phy_sts->rf_mode == 0)
2881 bw = CHANNEL_WIDTH_20;
2882 else if ((rxsc == 1) || (rxsc == 2))
2883 bw = CHANNEL_WIDTH_20;
2884 else
2885 bw = CHANNEL_WIDTH_40;
2886 }
2887
2888 /* Update packet information */
2889 phydm_set_common_phy_info(rx_pwr_db, phy_sts->channel,
2890 (boolean)phy_sts->beamformed, is_mu, bw,
2891 phy_info->rx_mimo_signal_quality[0],
2892 rxsc, phy_info);
2893
2894 phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
2895 #ifdef PHYDM_LNA_SAT_CHK_TYPE2
2896 phydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr);
2897 #endif
2898
2899 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2900 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2901 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2902 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2903 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2904 #endif
2905 }
2906
phydm_get_phy_sts_type2(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2907 void phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf,
2908 struct phydm_perpkt_info_struct *pktinfo,
2909 struct phydm_phyinfo_struct *phy_info)
2910 {
2911 struct phy_sts_rpt_jgr2_type2 *phy_sts = NULL;
2912 s8 rx_pwr_db_max = -120;
2913 s8 rx_pwr = 0;
2914 u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
2915
2916 phy_sts = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
2917
2918 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
2919 if (!(dm->rx_ant_status & BIT(i)))
2920 continue;
2921 rx_count++;
2922
2923 if (rx_count > dm->num_rf_path)
2924 break;
2925
2926 /* Update per-path information*/
2927 /* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */
2928 #if (RTL8197F_SUPPORT)
2929 if ((dm->support_ic_type & ODM_RTL8197F) &&
2930 phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/
2931
2932 if (i == RF_PATH_A) {
2933 rx_pwr = (phy_sts->gain_a) << 1;
2934 rx_pwr = rx_pwr - 110;
2935 } else if (i == RF_PATH_B) {
2936 rx_pwr = (phy_sts->gain_b) << 1;
2937 rx_pwr = rx_pwr - 110;
2938 } else {
2939 rx_pwr = 0;
2940 }
2941 } else
2942 #endif
2943 rx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/
2944
2945 phydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, 0, phy_info);
2946
2947 if (rx_pwr > rx_pwr_db_max) /* search max pwdb */
2948 rx_pwr_db_max = rx_pwr;
2949 }
2950
2951 /* @mapping RX counter from 1~4 to 0~3 */
2952 if (rx_count > 0)
2953 phy_info->rx_count = rx_count - 1;
2954
2955 /* @Check RX sub-channel */
2956 if (pktinfo->data_rate > ODM_RATE11M &&
2957 pktinfo->data_rate < ODM_RATEMCS0)
2958 rxsc = phy_sts->l_rxsc;
2959 else
2960 rxsc = phy_sts->ht_rxsc;
2961
2962 /*STBC or LDPC pkt*/
2963 dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
2964 dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
2965
2966 /* @Check RX bandwidth */
2967 /* @BW information of sc=0 is useless,
2968 *because there is no information of RF mode
2969 */
2970 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2971 if (rxsc >= 1 && rxsc <= 8)
2972 bw = CHANNEL_WIDTH_20;
2973 else if ((rxsc >= 9) && (rxsc <= 12))
2974 bw = CHANNEL_WIDTH_40;
2975 else if (rxsc >= 13)
2976 bw = CHANNEL_WIDTH_80;
2977
2978 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
2979 if (rxsc == 3)
2980 bw = CHANNEL_WIDTH_40;
2981 else if ((rxsc == 1) || (rxsc == 2))
2982 bw = CHANNEL_WIDTH_20;
2983 }
2984
2985 /* Update packet information */
2986 phydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel,
2987 (boolean)phy_sts->beamformed,
2988 false, bw, 0, rxsc, phy_info);
2989 }
2990
phydm_process_rssi_for_dm_2nd_type(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)2991 void phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm,
2992 struct phydm_phyinfo_struct *phy_info,
2993 struct phydm_perpkt_info_struct *pktinfo
2994 )
2995 {
2996 struct cmn_sta_info *sta = NULL;
2997 struct rssi_info *rssi_t = NULL;
2998 u8 rssi_tmp = 0;
2999 u64 rssi_linear = 0;
3000 s16 rssi_db = 0;
3001 u8 i = 0;
3002
3003 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
3004 return;
3005
3006 sta = dm->phydm_sta_info[pktinfo->station_id];
3007
3008 if (!is_sta_active(sta))
3009 return;
3010
3011 if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
3012 return;
3013
3014 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3015 if (dm->support_ability & ODM_BB_ANT_DIV)
3016 odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
3017 #endif
3018
3019 #if (defined(CONFIG_PATH_DIVERSITY))
3020 if (dm->support_ability & ODM_BB_PATH_DIV)
3021 phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
3022 #endif
3023
3024 #ifdef CONFIG_ADAPTIVE_SOML
3025 phydm_rx_qam_for_soml(dm, pktinfo);
3026 phydm_rx_rate_for_soml(dm, pktinfo);
3027 #endif
3028
3029 if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
3030 return;
3031
3032 if (pktinfo->is_packet_beacon) {
3033 dm->phy_dbg_info.num_qry_beacon_pkt++;
3034 dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
3035 }
3036
3037 rssi_t = &sta->rssi_stat;
3038
3039 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
3040 rssi_tmp = phy_info->rx_mimo_signal_strength[i];
3041 if (rssi_tmp != 0)
3042 rssi_linear += phydm_db_2_linear(rssi_tmp);
3043 }
3044 /* @Rounding and removing fractional bits */
3045 rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
3046
3047 switch (phy_info->rx_count + 1) {
3048 case 2:
3049 rssi_linear = DIVIDED_2(rssi_linear);
3050 break;
3051 case 3:
3052 rssi_linear = DIVIDED_3(rssi_linear);
3053 break;
3054 case 4:
3055 rssi_linear = DIVIDED_4(rssi_linear);
3056 break;
3057 }
3058
3059 rssi_db = (s16)odm_convert_to_db(rssi_linear);
3060
3061 if (rssi_t->rssi_acc == 0) {
3062 rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
3063 rssi_t->rssi = (s8)(rssi_db);
3064 } else {
3065 rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
3066 rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
3067 }
3068
3069 if (pktinfo->is_cck_rate)
3070 rssi_t->rssi_cck = (s8)rssi_db;
3071 else
3072 rssi_t->rssi_ofdm = (s8)rssi_db;
3073 }
3074
phydm_rx_physts_2nd_type(void * dm_void,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)3075 void phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts,
3076 struct phydm_perpkt_info_struct *pktinfo,
3077 struct phydm_phyinfo_struct *phy_info)
3078 {
3079 struct dm_struct *dm = (struct dm_struct *)dm_void;
3080 u8 page = (*phy_sts & 0xf);
3081
3082 /* Phy status parsing */
3083 switch (page) {
3084 case 0: /*@CCK*/
3085 phydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info);
3086 break;
3087 case 1:
3088 phydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info);
3089 break;
3090 case 2:
3091 phydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info);
3092 break;
3093 default:
3094 break;
3095 }
3096
3097 #if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
3098 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B))
3099 phydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info);
3100 #endif
3101 }
3102
3103 /*@==============================================*/
3104 #endif
3105
odm_phy_status_query(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo)3106 boolean odm_phy_status_query(struct dm_struct *dm,
3107 struct phydm_phyinfo_struct *phy_info,
3108 u8 *phy_sts,
3109 struct phydm_perpkt_info_struct *pktinfo)
3110 {
3111 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3112 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
3113 boolean auto_swch_en = dm->pkt_proc_struct.physts_auto_swch_en;
3114 #endif
3115 u8 rate = pktinfo->data_rate;
3116 u8 page = (*phy_sts & 0xf);
3117
3118 pktinfo->is_cck_rate = PHYDM_IS_CCK_RATE(rate);
3119 pktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate);
3120 dm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/
3121
3122 if (pktinfo->is_cck_rate)
3123 dm->phy_dbg_info.num_qry_phy_status_cck++;
3124 else
3125 dm->phy_dbg_info.num_qry_phy_status_ofdm++;
3126
3127 /*Reset phy_info*/
3128 phydm_reset_phy_info(dm, phy_info);
3129
3130 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
3131 #ifdef PHYSTS_3RD_TYPE_SUPPORT
3132 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3133 if (phydm_physts_auto_switch_jgr3(dm, phy_sts, pktinfo)) {
3134 PHYDM_DBG(dm, DBG_PHY_STATUS, "SKIP parsing\n");
3135 phy_info->physts_rpt_valid = false;
3136 return false;
3137 }
3138 #endif
3139 phydm_rx_physts_jgr3(dm, phy_sts, pktinfo, phy_info);
3140 phydm_process_dm_rssi_jgr3(dm, phy_info, pktinfo);
3141 #endif
3142 } else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
3143 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
3144 phydm_rx_physts_2nd_type(dm, phy_sts, pktinfo, phy_info);
3145 phydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo);
3146 #endif
3147 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
3148 #if ODM_IC_11AC_SERIES_SUPPORT
3149 phydm_rx_physts_1st_type(dm, phy_info, phy_sts, pktinfo);
3150 phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
3151 #endif
3152 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
3153 #if ODM_IC_11N_SERIES_SUPPORT
3154 phydm_phy_sts_n_parsing(dm, phy_info, phy_sts, pktinfo);
3155 phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
3156 #endif
3157 }
3158 phy_info->signal_strength = phy_info->rx_pwdb_all;
3159 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3160 phydm_process_signal_strength(dm, phy_info, pktinfo);
3161 #endif
3162
3163 /*For basic debug message*/
3164 if (pktinfo->is_packet_match_bssid || *dm->mp_mode) {
3165 dm->curr_station_id = pktinfo->station_id;
3166 dm->rx_rate = rate;
3167 dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A];
3168 dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B];
3169 dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C];
3170 dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D];
3171
3172 if (rate >= ODM_RATE6M && rate <= ODM_RATE54M)
3173 dm->rxsc_l = (s8)phy_info->rxsc;
3174 else if (phy_info->band_width == CHANNEL_WIDTH_20)
3175 dm->rxsc_20 = (s8)phy_info->rxsc;
3176 else if (phy_info->band_width == CHANNEL_WIDTH_40)
3177 dm->rxsc_40 = (s8)phy_info->rxsc;
3178 else if (phy_info->band_width == CHANNEL_WIDTH_80)
3179 dm->rxsc_80 = (s8)phy_info->rxsc;
3180
3181 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3182 if (auto_swch_en && page == 4 && pktinfo->rate_ss > 1)
3183 phydm_avg_condi_num(dm, phy_info, pktinfo);
3184
3185 if (!auto_swch_en ||
3186 (pkt_proc->is_1st_mpdu || PHYDM_IS_LEGACY_RATE(rate)))
3187 #endif
3188 {
3189 phydm_avg_rssi_evm_snr(dm, phy_info, pktinfo);
3190 phydm_rx_statistic_cal(dm, phy_info, phy_sts, pktinfo);
3191 }
3192 }
3193
3194 phy_info->physts_rpt_valid = true;
3195 return true;
3196 }
3197
phydm_rx_phy_status_init(void * dm_void)3198 void phydm_rx_phy_status_init(void *dm_void)
3199 {
3200 struct dm_struct *dm = (struct dm_struct *)dm_void;
3201 struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
3202
3203 dbg->show_phy_sts_all_pkt = 0;
3204 dbg->show_phy_sts_max_cnt = 1;
3205 dbg->show_phy_sts_cnt = 0;
3206
3207 phydm_avg_phystatus_init(dm);
3208
3209 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3210 dm->pkt_proc_struct.physts_auto_swch_en = false;
3211 #endif
3212 }
3213
phydm_physts_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3214 void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used,
3215 char *output, u32 *_out_len)
3216 {
3217 struct dm_struct *dm = (struct dm_struct *)dm_void;
3218 char help[] = "-h";
3219 boolean enable;
3220 u32 var[10] = {0};
3221 u32 used = *_used;
3222 u32 out_len = *_out_len;
3223 u8 i = 0;
3224
3225 for (i = 0; i < 3; i++) {
3226 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
3227 }
3228
3229 if ((strcmp(input[1], help) == 0)) {
3230 PDM_SNPF(out_len, used, output + used, out_len - used,
3231 "Page Auto Switching: swh {en} {bitmap(hex)}\n");
3232 } else if ((strcmp(input[1], "swh") == 0)) {
3233 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3234 PHYDM_SSCANF(input[3], DCMD_HEX, &var[2]);
3235 enable = (boolean)var[1];
3236 phydm_physts_auto_switch_jgr3_set(dm, enable, (u8)var[2]);
3237
3238 PDM_SNPF(out_len, used, output + used, out_len - used,
3239 "Page Auto Switching: en=%d, bitmap=0x%x\n",
3240 enable, var[2]);
3241 #endif
3242 }
3243 *_used = used;
3244 *_out_len = out_len;
3245 }
3246