1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@
27 * ============================================================
28 * include files
29 * ============================================================
30 */
31
32 #include "mp_precomp.h"
33 #include "phydm_precomp.h"
34
35 #if defined(CONFIG_PHYDM_DFS_MASTER)
36
phydm_dfs_is_meteorology_channel(void * dm_void)37 boolean phydm_dfs_is_meteorology_channel(void *dm_void)
38 {
39 struct dm_struct *dm = (struct dm_struct *)dm_void;
40
41 u8 ch = *dm->channel;
42 u8 bw = *dm->band_width;
43
44 return ((bw == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) ||
45 (bw == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) ||
46 (bw == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128));
47 }
48
phydm_dfs_segment_distinguish(void * dm_void,enum rf_syn syn_path)49 void phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path)
50 {
51 struct dm_struct *dm = (struct dm_struct *)dm_void;
52
53 if (!(dm->support_ic_type & (ODM_RTL8814B)))
54 return;
55 if (syn_path == RF_SYN1)
56 dm->seg1_dfs_flag = 1;
57 else
58 dm->seg1_dfs_flag = 0;
59 }
60
phydm_dfs_segment_flag_reset(void * dm_void)61 void phydm_dfs_segment_flag_reset(void *dm_void)
62 {
63 struct dm_struct *dm = (struct dm_struct *)dm_void;
64
65 if (!(dm->support_ic_type & (ODM_RTL8814B)))
66 return;
67 if (dm->seg1_dfs_flag)
68 dm->seg1_dfs_flag = 0;
69 }
70
phydm_radar_detect_reset(void * dm_void)71 void phydm_radar_detect_reset(void *dm_void)
72 {
73 struct dm_struct *dm = (struct dm_struct *)dm_void;
74
75 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
76 ODM_RTL8197G | ODM_RTL8723F)) {
77 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
78 odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
79 #if (RTL8721D_SUPPORT)
80 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
81 odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
82 odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
83 #endif
84 } else if (dm->support_ic_type & (ODM_RTL8814B)) {
85 if (dm->seg1_dfs_flag == 1) {
86 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
87 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
88 return;
89 }
90 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
91 odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
92 } else {
93 odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
94 odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
95 }
96 }
97
phydm_radar_detect_disable(void * dm_void)98 void phydm_radar_detect_disable(void *dm_void)
99 {
100 struct dm_struct *dm = (struct dm_struct *)dm_void;
101
102 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
103 ODM_RTL8197G | ODM_RTL8723F))
104 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
105 else if (dm->support_ic_type & (ODM_RTL8814B)) {
106 if (dm->seg1_dfs_flag == 1) {
107 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
108 dm->seg1_dfs_flag = 0;
109 return;
110 }
111 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
112 }
113 #if (RTL8721D_SUPPORT)
114 else if (dm->support_ic_type & (ODM_RTL8721D))
115 odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
116 #endif
117 else
118 odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
119
120 PHYDM_DBG(dm, DBG_DFS, "\n");
121 }
122
phydm_radar_detect_with_dbg_parm(void * dm_void)123 static void phydm_radar_detect_with_dbg_parm(void *dm_void)
124 {
125 struct dm_struct *dm = (struct dm_struct *)dm_void;
126
127 if (dm->support_ic_type & ODM_RTL8721D) {
128 odm_set_bb_reg(dm, R_0xf54, MASKDWORD,
129 dm->radar_detect_reg_f54);
130 odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
131 dm->radar_detect_reg_f58);
132 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD,
133 dm->radar_detect_reg_f5c);
134 odm_set_bb_reg(dm, R_0xf70, MASKDWORD,
135 dm->radar_detect_reg_f70);
136 odm_set_bb_reg(dm, R_0xf74, MASKDWORD,
137 dm->radar_detect_reg_f74);
138 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
139 odm_set_bb_reg(dm, R_0xa40, MASKDWORD,
140 dm->radar_detect_reg_a40);
141 odm_set_bb_reg(dm, R_0xa44, MASKDWORD,
142 dm->radar_detect_reg_a44);
143 odm_set_bb_reg(dm, R_0xa48, MASKDWORD,
144 dm->radar_detect_reg_a48);
145 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD,
146 dm->radar_detect_reg_a4c);
147 odm_set_bb_reg(dm, R_0xa50, MASKDWORD,
148 dm->radar_detect_reg_a50);
149 odm_set_bb_reg(dm, R_0xa54, MASKDWORD,
150 dm->radar_detect_reg_a54);
151 } else {
152 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
153 dm->radar_detect_reg_918);
154 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
155 dm->radar_detect_reg_91c);
156 odm_set_bb_reg(dm, R_0x920, MASKDWORD,
157 dm->radar_detect_reg_920);
158 odm_set_bb_reg(dm, R_0x924, MASKDWORD,
159 dm->radar_detect_reg_924);
160 }
161 }
162
163 /* @Init radar detection parameters, called after ch, bw is set */
164
phydm_radar_detect_enable(void * dm_void)165 void phydm_radar_detect_enable(void *dm_void)
166 {
167 struct dm_struct *dm = (struct dm_struct *)dm_void;
168 struct _DFS_STATISTICS *dfs = &dm->dfs;
169 u8 region_domain = dm->dfs_region_domain;
170 u8 c_channel = *dm->channel;
171 u8 band_width = *dm->band_width;
172 u8 enable = 0, i;
173 u8 short_pw_upperbound = 0;
174
175 PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain);
176 if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
177 PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n");
178 goto exit;
179 }
180
181 if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
182 odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
183 odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
184
185 if (dm->radar_detect_dbg_parm_en) {
186 phydm_radar_detect_with_dbg_parm(dm);
187 enable = 1;
188 goto exit;
189 }
190
191 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
192 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf);
193 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
194 odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20);
195 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204);
196
197 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
198 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
199 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
200
201 if (c_channel >= 52 && c_channel <= 64) {
202 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
203 0x1c16ecdf);
204 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
205 0x0f141a20);
206 } else {
207 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
208 0x1c16acdf);
209 if (band_width == CHANNEL_WIDTH_20)
210 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
211 0x64721a20);
212 else
213 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
214 0x68721a20);
215 }
216
217 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
218 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
219 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
220 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231);
221 if (band_width == CHANNEL_WIDTH_20)
222 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
223 0x64741a20);
224 else
225 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
226 0x68741a20);
227
228 } else {
229 /* not supported */
230 PHYDM_DBG(dm, DBG_DFS,
231 "Unsupported dfs_region_domain:%d\n",
232 region_domain);
233 goto exit;
234 }
235
236 } else if (dm->support_ic_type &
237 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
238
239 odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
240 odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
241
242 /* @8822B only, when BW = 20M, DFIR output is 40Mhz,
243 * but DFS input is 80MMHz, so it need to upgrade to 80MHz
244 */
245 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
246 if (band_width == CHANNEL_WIDTH_20)
247 odm_set_bb_reg(dm, R_0x1984, BIT(26), 1);
248 else
249 odm_set_bb_reg(dm, R_0x1984, BIT(26), 0);
250 }
251
252 if (dm->radar_detect_dbg_parm_en) {
253 phydm_radar_detect_with_dbg_parm(dm);
254 enable = 1;
255 goto exit;
256 }
257
258 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
259 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
260 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
261 odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fc01a1f);
262 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204);
263
264 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
265 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
266 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
267
268 if (c_channel >= 52 && c_channel <= 64) {
269 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
270 0x1c16ecdf);
271 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
272 0x0f141a1f);
273 } else {
274 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
275 0x1c166cdf);
276 if (band_width == CHANNEL_WIDTH_20)
277 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
278 0x64721a1f);
279 else
280 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
281 0x68721a1f);
282 }
283
284 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
285 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf);
286 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400);
287 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231);
288 if (band_width == CHANNEL_WIDTH_20)
289 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
290 0x64901a1f);
291 else
292 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
293 0x62901a1f);
294
295 } else {
296 /* not supported */
297 PHYDM_DBG(dm, DBG_DFS,
298 "Unsupported dfs_region_domain:%d\n",
299 region_domain);
300 goto exit;
301 }
302 /*RXHP low corner will extend the pulse width,
303 *so we need to increase the upper bound.
304 */
305 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
306 if (odm_get_bb_reg(dm, 0x8d8,
307 BIT28 | BIT27 | BIT26) == 0) {
308 short_pw_upperbound =
309 (u8)odm_get_bb_reg(dm, 0x91c,
310 BIT23 | BIT22 |
311 BIT21 | BIT20);
312 if ((short_pw_upperbound + 4) > 15)
313 odm_set_bb_reg(dm, 0x91c,
314 BIT23 | BIT22 |
315 BIT21 | BIT20, 15);
316 else
317 odm_set_bb_reg(dm, 0x91c,
318 BIT23 | BIT22 |
319 BIT21 | BIT20,
320 short_pw_upperbound + 4);
321 }
322 /*@if peak index -1~+1, use original NB method*/
323 odm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13);
324 odm_set_bb_reg(dm, 0x924, 0x70000, 0);
325 }
326
327 if (dm->support_ic_type & (ODM_RTL8881A))
328 odm_set_bb_reg(dm, 0xb00, 0xc0000000, 3);
329
330 /*@for 8814 new dfs mechanism setting*/
331 if (dm->support_ic_type &
332 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
333 /*Turn off dfs scaling factor*/
334 odm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00);
335 /*NonDC peak_th = 2times DC peak_th*/
336 odm_set_bb_reg(dm, 0x19e4, 0x30000, 1);
337 /*power for debug and auto test flow latch after ST*/
338 odm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3);
339
340 /*@low pulse width radar pattern will cause wrong drop*/
341 /*@disable peak index should the same
342 *during the same short pulse (new mechan)
343 */
344 odm_set_bb_reg(dm, 0x9f4, 0x80000000, 0);
345
346 /*@disable peak index should the same
347 *during the same short pulse (old mechan)
348 */
349 odm_set_bb_reg(dm, 0x924, 0x20000000, 0);
350
351 /*@if peak index diff >=2, then drop the result*/
352 odm_set_bb_reg(dm, 0x19e4, 0xe000, 2);
353 if (region_domain == 2) {
354 if ((c_channel >= 52) && (c_channel <= 64)) {
355 /*pulse width hist th setting*/
356 /*th1=2*04us*/
357 odm_set_bb_reg(dm, 0x19e4,
358 0xff000000, 2);
359 /*th2 = 3*0.4us, th3 = 4*0.4us
360 *th4 = 7*0.4, th5 = 34*0.4
361 */
362 odm_set_bb_reg(dm, 0x19e8,
363 MASKDWORD, 0x22070403);
364
365 /*PRI hist th setting*/
366 /*th1=42*32us*/
367 odm_set_bb_reg(dm, 0x19b8,
368 0x00007f80, 42);
369 /*th2=47*32us, th3=115*32us,
370 *th4=123*32us, th5=130*32us
371 */
372 odm_set_bb_reg(dm, 0x19ec,
373 MASKDWORD, 0x827b732f);
374 } else {
375 /*pulse width hist th setting*/
376 /*th1=2*04us*/
377 odm_set_bb_reg(dm, 0x19e4,
378 0xff000000, 1);
379 /*th2 = 13*0.4us, th3 = 26*0.4us
380 *th4 = 75*0.4us, th5 = 255*0.4us
381 */
382 odm_set_bb_reg(dm, 0x19e8,
383 MASKDWORD, 0xff4b1a0d);
384 /*PRI hist th setting*/
385 /*th1=4*32us*/
386
387 odm_set_bb_reg(dm, 0x19b8,
388 0x00007f80, 4);
389 /*th2=8*32us, th3=16*32us,
390 *th4=32*32us, th5=128*32=4096us
391 */
392 odm_set_bb_reg(dm, 0x19ec,
393 MASKDWORD, 0x80201008);
394 }
395 }
396 /*@ETSI*/
397 else if (region_domain == 3) {
398 /*pulse width hist th setting*/
399 /*th1=2*04us*/
400 odm_set_bb_reg(dm, 0x19e4, 0xff000000, 1);
401 odm_set_bb_reg(dm, 0x19e8,
402 MASKDWORD, 0x68260d06);
403 /*PRI hist th setting*/
404 /*th1=7*32us*/
405 odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7);
406 /*th2=40*32us, th3=80*32us,
407 *th4=110*32us, th5=157*32=5024
408 */
409 odm_set_bb_reg(dm, 0x19ec,
410 MASKDWORD, 0xc06e2010);
411 }
412 /*@FCC*/
413 else if (region_domain == 1) {
414 /*pulse width hist th setting*/
415 /*th1=2*04us*/
416 odm_set_bb_reg(dm, 0x19e4, 0xff000000, 2);
417 /*th2 = 13*0.4us, th3 = 26*0.4us,
418 *th4 = 75*0.4us, th5 = 255*0.4us
419 */
420 odm_set_bb_reg(dm, 0x19e8,
421 MASKDWORD, 0xff4b1a0d);
422
423 /*PRI hist th setting*/
424 /*th1=4*32us*/
425 odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4);
426 /*th2=8*32us, th3=21*32us,
427 *th4=32*32us, th5=96*32=3072
428 */
429 if (band_width == CHANNEL_WIDTH_20)
430 odm_set_bb_reg(dm, 0x19ec,
431 MASKDWORD, 0x60282010);
432 else
433 odm_set_bb_reg(dm, 0x19ec,
434 MASKDWORD, 0x60282420);
435 } else {
436 }
437 }
438 } else if (dm->support_ic_type &
439 ODM_IC_JGR3_SERIES) {
440 if (dm->radar_detect_dbg_parm_en) {
441 phydm_radar_detect_with_dbg_parm(dm);
442 enable = 1;
443 goto exit;
444 }
445 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
446 odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
447 if (dm->support_ic_type & (ODM_RTL8814B)) {
448 if (dm->seg1_dfs_flag == 1)
449 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
450 }
451 odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
452 odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
453 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
454 odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
455 odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
456 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
457 odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
458 if (dm->support_ic_type & (ODM_RTL8814B)) {
459 if (dm->seg1_dfs_flag == 1)
460 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
461 }
462 odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
463 odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
464 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
465 odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
466 odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
467 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
468 odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
469 if (dm->support_ic_type & (ODM_RTL8814B)) {
470 if (dm->seg1_dfs_flag == 1)
471 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
472 }
473 odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
474 odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
475 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
476 odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
477 odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
478 } else {
479 /* not supported */
480 PHYDM_DBG(dm, DBG_DFS,
481 "Unsupported dfs_region_domain:%d\n",
482 region_domain);
483 goto exit;
484 }
485 #if (RTL8721D_SUPPORT)
486 } else if (dm->support_ic_type & ODM_RTL8721D) {
487 odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
488 /*CCA MASK*/
489 odm_set_bb_reg(dm, R_0xc38, 0x07c00000, 0x06);
490 /*CCA Threshold*/
491 odm_set_bb_reg(dm, R_0xc3c, 0x00000007, 0x0);
492
493 if (dm->radar_detect_dbg_parm_en) {
494 phydm_radar_detect_with_dbg_parm(dm);
495 enable = 1;
496 goto exit;
497 }
498
499 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
500 odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
501 odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x354cd7dd);
502 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
503 odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fab98);
504 odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc45029f);
505
506 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
507 odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
508 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
509 odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
510 odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc450e9d);
511
512 if (c_channel >= 52 && c_channel <= 64) {
513 odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
514 0x354cd7fd);
515 } else {
516 odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
517 0x354cd7bd);
518 }
519 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
520 odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
521 odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x3558d7bd);
522 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab35);
523 odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
524 odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc444e9d);
525 } else {
526 /* not supported */
527 PHYDM_DBG(dm, DBG_DFS,
528 "Unsupported dfs_region_domain:%d\n",
529 region_domain);
530 goto exit;
531 }
532
533 /*if peak index -1~+1, use original NB method*/
534 odm_set_bb_reg(dm, R_0xf70, 0x00070000, 0x7);
535 odm_set_bb_reg(dm, R_0xf74, 0x000c0000, 0);
536
537 /*Turn off dfs scaling factor*/
538 odm_set_bb_reg(dm, R_0xf70, 0x00080000, 0x0);
539 /*NonDC peak_th = 2times DC peak_th*/
540 odm_set_bb_reg(dm, R_0xf58, 0x00007800, 1);
541
542 /*low pulse width radar pattern will cause wrong drop*/
543 /*disable peak index should the same*/
544 /*during the same short pulse (new mechan)*/
545 odm_set_bb_reg(dm, R_0xf70, 0x00100000, 0x0);
546 /*if peak index diff >=2, then drop the result*/
547 odm_set_bb_reg(dm, R_0xf70, 0x30000000, 0x2);
548 #endif
549 } else {
550 /*not supported IC type*/
551 PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n",
552 dm->support_ic_type);
553 goto exit;
554 }
555
556 enable = 1;
557
558 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
559 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
560 dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xa50, 0x000000f0);
561 dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xa48, 0x00c00000);
562 dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa50,
563 0x00f00000);
564 dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa4c,
565 0xf0000000);
566 dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00030000);
567 dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xa40,
568 0x30000000);
569 dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, R_0xa44,
570 0x00000007);
571 #if (RTL8721D_SUPPORT)
572 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
573 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xf54,
574 0x0000001f) << 2);
575 dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
576 dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xf70, 0x03c00000);
577 dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xf5c, 0x00000030);
578 dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf70,
579 0x00007800);
580 dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf74,
581 0x0000000f);
582 dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xf58, 0x18000000);
583 dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xf58,
584 0x00030000);
585 dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm,
586 R_0xf58, 0x00007c00);
587 #endif
588 } else {
589 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
590 dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00);
591 dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000);
592 dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
593 0x000f0000);
594 dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
595 0x00f00000);
596 dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300);
597 dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180);
598 dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000);
599 }
600
601 phydm_dfs_parameter_init(dm);
602
603 exit:
604 if (enable) {
605 phydm_radar_detect_reset(dm);
606 PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel,
607 band_width);
608 } else
609 phydm_radar_detect_disable(dm);
610 }
611
phydm_dfs_parameter_init(void * dm_void)612 void phydm_dfs_parameter_init(void *dm_void)
613 {
614 struct dm_struct *dm = (struct dm_struct *)dm_void;
615 struct _DFS_STATISTICS *dfs = &dm->dfs;
616
617 u8 i;
618 for (i = 0; i < 5; i++) {
619 dfs->pulse_flag_hist[i] = 0;
620 dfs->pulse_type_hist[i] = 0;
621 dfs->radar_det_mask_hist[i] = 0;
622 dfs->fa_inc_hist[i] = 0;
623 }
624
625 /*@for dfs mode*/
626 dfs->force_TP_mode = 0;
627 dfs->sw_trigger_mode = 0;
628 dfs->det_print = 0;
629 dfs->det_print2 = 0;
630 dfs->print_hist_rpt = 0;
631 if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
632 dfs->hist_cond_on = 1;
633 else
634 dfs->hist_cond_on = 0;
635
636 /*@for dynamic dfs*/
637 dfs->pwdb_th = 8;
638 dfs->fa_mask_th = 30 * (dfs->dfs_polling_time) / 100;
639 dfs->st_l2h_min = 0x20;
640 dfs->st_l2h_max = 0x4e;
641 dfs->pwdb_scalar_factor = 12;
642
643 /*@for dfs histogram*/
644 dfs->pri_hist_th = 5;
645 dfs->pri_sum_g1_th = 9;
646 dfs->pri_sum_g5_th = 5;
647 dfs->pri_sum_g1_fcc_th = 4; /*@FCC Type6*/
648 dfs->pri_sum_g3_fcc_th = 6;
649 dfs->pri_sum_safe_th = 50;
650 dfs->pri_sum_safe_fcc_th = 110; /*@30 for AP*/
651 dfs->pri_sum_type4_th = 16;
652 dfs->pri_sum_type6_th = 12;
653 dfs->pri_sum_g5_under_g1_th = 4;
654 dfs->pri_pw_diff_th = 4;
655 dfs->pri_pw_diff_fcc_th = 8;
656 dfs->pri_pw_diff_fcc_idle_th = 2;
657 dfs->pri_pw_diff_w53_th = 10;
658 dfs->pw_std_th = 7; /*@FCC Type4*/
659 dfs->pw_std_idle_th = 10;
660 dfs->pri_std_th = 6; /*@FCC Type3,4,6*/
661 dfs->pri_std_idle_th = 10;
662 dfs->pri_type1_upp_fcc_th = 110;
663 dfs->pri_type1_low_fcc_th = 50;
664 dfs->pri_type1_cen_fcc_th = 70;
665 dfs->pw_g0_th = 8;
666 dfs->pw_long_lower_th = 6; /*@7->6*/
667 dfs->pri_long_upper_th = 30;
668 dfs->pw_long_lower_20m_th = 7; /*@7 for AP*/
669 dfs->pw_long_sum_upper_th = 60;
670 dfs->type4_pw_max_cnt = 7;
671 dfs->type4_safe_pri_sum_th = 5;
672 }
673
phydm_dfs_dynamic_setting(void * dm_void)674 void phydm_dfs_dynamic_setting(
675 void *dm_void)
676 {
677 struct dm_struct *dm = (struct dm_struct *)dm_void;
678 struct _DFS_STATISTICS *dfs = &dm->dfs;
679
680 u8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0;
681 u8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0;
682 u8 three_peak_th2_cur = 0;
683 u8 peak_window_cur = 0;
684 u8 region_domain = dm->dfs_region_domain;
685 u8 c_channel = *dm->channel;
686
687 if (dm->rx_tp + dm->tx_tp <= 2) {
688 dfs->idle_mode = 1;
689 if (dfs->force_TP_mode)
690 dfs->idle_mode = 0;
691 } else {
692 dfs->idle_mode = 0;
693 }
694
695 if (dfs->idle_mode == 1) { /*@idle (no traffic)*/
696 peak_th_cur = 3;
697 short_pulse_cnt_th_cur = 6;
698 long_pulse_cnt_th_cur = 9;
699 peak_window_cur = 2;
700 three_peak_opt_cur = 0;
701 three_peak_th2_cur = 2;
702 if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
703 if (c_channel >= 52 && c_channel <= 64) {
704 short_pulse_cnt_th_cur = 14;
705 long_pulse_cnt_th_cur = 15;
706 three_peak_th2_cur = 0;
707 } else {
708 short_pulse_cnt_th_cur = 6;
709 three_peak_th2_cur = 0;
710 long_pulse_cnt_th_cur = 10;
711 }
712 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
713 three_peak_th2_cur = 0;
714 } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
715 long_pulse_cnt_th_cur = 15;
716 if (phydm_dfs_is_meteorology_channel(dm)) {
717 /*need to add check cac end condition*/
718 peak_th_cur = 2;
719 three_peak_opt_cur = 0;
720 three_peak_th2_cur = 0;
721 short_pulse_cnt_th_cur = 7;
722 } else {
723 three_peak_opt_cur = 0;
724 three_peak_th2_cur = 0;
725 short_pulse_cnt_th_cur = 7;
726 }
727 } else /*@default: FCC*/
728 three_peak_th2_cur = 0;
729
730 } else { /*@in service (with TP)*/
731 peak_th_cur = 2;
732 short_pulse_cnt_th_cur = 6;
733 long_pulse_cnt_th_cur = 7;
734 peak_window_cur = 2;
735 three_peak_opt_cur = 0;
736 three_peak_th2_cur = 2;
737 if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
738 if (c_channel >= 52 && c_channel <= 64) {
739 long_pulse_cnt_th_cur = 15;
740 /*@for high duty cycle*/
741 short_pulse_cnt_th_cur = 5;
742 three_peak_th2_cur = 0;
743 } else {
744 three_peak_opt_cur = 0;
745 three_peak_th2_cur = 0;
746 long_pulse_cnt_th_cur = 8;
747 }
748 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
749 long_pulse_cnt_th_cur = 5; /*for 80M FCC*/
750 short_pulse_cnt_th_cur = 5; /*for 80M FCC*/
751 } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
752 long_pulse_cnt_th_cur = 15;
753 short_pulse_cnt_th_cur = 5;
754 three_peak_opt_cur = 0;
755 }
756 }
757
758 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
759 if (dfs->peak_th != peak_th_cur)
760 odm_set_bb_reg(dm, R_0xa48, 0x00c00000, peak_th_cur);
761 if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
762 odm_set_bb_reg(dm, R_0xa50, 0x00f00000,
763 short_pulse_cnt_th_cur);
764 if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
765 odm_set_bb_reg(dm, R_0xa4c, 0xf0000000,
766 long_pulse_cnt_th_cur);
767 if (dfs->peak_window != peak_window_cur)
768 odm_set_bb_reg(dm, R_0xa40, 0x00030000,
769 peak_window_cur);
770 if (dfs->three_peak_opt != three_peak_opt_cur)
771 odm_set_bb_reg(dm, R_0xa40, 0x30000000,
772 three_peak_opt_cur);
773 if (dfs->three_peak_th2 != three_peak_th2_cur)
774 odm_set_bb_reg(dm, R_0xa44, 0x00000007,
775 three_peak_th2_cur);
776 #if (RTL8721D_SUPPORT)
777 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
778 if (dfs->peak_th != peak_th_cur)
779 odm_set_bb_reg(dm, R_0xf5c, 0x00000030, peak_th_cur);
780 if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
781 odm_set_bb_reg(dm, R_0xf70, 0x00007800,
782 short_pulse_cnt_th_cur);
783 if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
784 odm_set_bb_reg(dm, R_0xf74, 0x0000000f,
785 long_pulse_cnt_th_cur);
786 if (dfs->peak_window != peak_window_cur)
787 odm_set_bb_reg(dm, R_0xf58, 0x18000000,
788 peak_window_cur);
789 if (dfs->three_peak_opt != three_peak_opt_cur)
790 odm_set_bb_reg(dm, R_0xf58, 0x00030000,
791 three_peak_opt_cur);
792 if (dfs->three_peak_th2 != three_peak_th2_cur)
793 odm_set_bb_reg(dm, R_0xf58, 0x00007c00,
794 three_peak_th2_cur);
795 #endif
796 } else {
797 if (dfs->peak_th != peak_th_cur)
798 odm_set_bb_reg(dm, R_0x918, 0x00030000, peak_th_cur);
799 if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
800 odm_set_bb_reg(dm, R_0x920, 0x000f0000,
801 short_pulse_cnt_th_cur);
802 if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
803 odm_set_bb_reg(dm, R_0x920, 0x00f00000,
804 long_pulse_cnt_th_cur);
805 if (dfs->peak_window != peak_window_cur)
806 odm_set_bb_reg(dm, R_0x920, 0x00000300,
807 peak_window_cur);
808 if (dfs->three_peak_opt != three_peak_opt_cur)
809 odm_set_bb_reg(dm, R_0x924, 0x00000180,
810 three_peak_opt_cur);
811 if (dfs->three_peak_th2 != three_peak_th2_cur)
812 odm_set_bb_reg(dm, R_0x924, 0x00007000,
813 three_peak_th2_cur);
814 }
815
816 dfs->peak_th = peak_th_cur;
817 dfs->short_pulse_cnt_th = short_pulse_cnt_th_cur;
818 dfs->long_pulse_cnt_th = long_pulse_cnt_th_cur;
819 dfs->peak_window = peak_window_cur;
820 dfs->three_peak_opt = three_peak_opt_cur;
821 dfs->three_peak_th2 = three_peak_th2_cur;
822 }
823
824 boolean
phydm_radar_detect_dm_check(void * dm_void)825 phydm_radar_detect_dm_check(
826 void *dm_void)
827 {
828 struct dm_struct *dm = (struct dm_struct *)dm_void;
829 struct _DFS_STATISTICS *dfs = &dm->dfs;
830 u8 region_domain = dm->dfs_region_domain, index = 0;
831
832 u16 i = 0, j = 0, fa_count_cur = 0, fa_count_inc = 0;
833 u16 total_fa_in_hist = 0, total_pulse_count_inc = 0;
834 u16 short_pulse_cnt_inc = 0, short_pulse_cnt_cur = 0;
835 u16 long_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
836 u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;
837 u32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0;
838 u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
839 u32 regdf4_value = 0, regf70_value = 0, regf74_value = 0;
840 #if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
841 u32 rega40_value = 0, rega44_value = 0, rega48_value = 0;
842 u32 rega4c_value = 0, rega50_value = 0, rega54_value = 0;
843 #endif
844 #if (RTL8721D_SUPPORT)
845 u32 reg908_value = 0, regdf4_value = 0;
846 u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
847 u32 regf70_value = 0, regf74_value = 0;
848 #endif
849 boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0;
850 boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0;
851 boolean radar_detected = 0;
852 u8 st_l2h_new = 0, fa_mask_th = 0, k = 0, sum = 0;
853 u8 c_channel = *dm->channel;
854
855 /*@Get FA count during past 100ms, R_0xf48 for AC series*/
856 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
857 fa_count_cur = (u16)odm_get_bb_reg(dm, R_0x2d00, MASKLWORD);
858 #if (RTL8721D_SUPPORT)
859 else if (dm->support_ic_type & (ODM_RTL8721D)) {
860 fa_count_cur = (u16)odm_get_bb_reg(dm,
861 ODM_REG_OFDM_FA_TYPE2_11N,
862 MASKHWORD);
863 fa_count_cur += (u16)odm_get_bb_reg(dm,
864 ODM_REG_OFDM_FA_TYPE3_11N,
865 MASKLWORD);
866 fa_count_cur += (u16)odm_get_bb_reg(dm,
867 ODM_REG_OFDM_FA_TYPE3_11N,
868 MASKHWORD);
869 fa_count_cur += (u16)odm_get_bb_reg(dm,
870 ODM_REG_OFDM_FA_TYPE4_11N,
871 MASKLWORD);
872 fa_count_cur += (u16)odm_get_bb_reg(dm,
873 ODM_REG_OFDM_FA_TYPE1_11N,
874 MASKLWORD);
875 fa_count_cur += (u16)odm_get_bb_reg(dm,
876 ODM_REG_OFDM_FA_TYPE1_11N,
877 MASKHWORD);
878 }
879 #endif
880 else
881 fa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff);
882
883 if (dfs->fa_count_pre == 0)
884 fa_count_inc = 0;
885 else if (fa_count_cur >= dfs->fa_count_pre)
886 fa_count_inc = fa_count_cur - dfs->fa_count_pre;
887 else
888 fa_count_inc = fa_count_cur;
889 dfs->fa_count_pre = fa_count_cur;
890
891 dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc;
892
893 for (i = 0; i < 5; i++)
894 total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];
895
896 if (dfs->mask_idx >= 2)
897 index = dfs->mask_idx - 2;
898 else
899 index = 5 + dfs->mask_idx - 2;
900
901 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
902 ODM_RTL8197G| ODM_RTL8723F)) {
903 radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff);
904 short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
905 >> 11);
906 long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
907 >> 22);
908 #if (RTL8721D_SUPPORT)
909 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
910 reg908_value = (u32)odm_get_bb_reg(dm, R_0x908, MASKDWORD);
911 odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x254);
912 regdf4_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);
913 short_pulse_cnt_cur = (u16)((regdf4_value & 0x000ff000) >> 12);
914 long_pulse_cnt_cur = (u16)((regdf4_value & 0x0fc00000) >> 22);
915
916 tri_short_pulse = (regdf4_value & BIT(20)) ? 1 : 0;
917 tri_long_pulse = (regdf4_value & BIT(28)) ? 1 : 0;
918 if (tri_short_pulse || tri_long_pulse) {
919 odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
920 odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
921 }
922 #endif
923 } else if (dm->support_ic_type & (ODM_RTL8814B)) {
924 if (dm->seg1_dfs_flag == 1)
925 radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e20,
926 0xffffffff);
927 else
928 radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00,
929 0xffffffff);
930 short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
931 >> 11);
932 long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
933 >> 22);
934 } else {
935 regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff);
936 short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);
937 long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);
938 }
939
940 /*@Get short pulse count, need carefully handle the counter overflow*/
941 if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) {
942 short_pulse_cnt_inc = short_pulse_cnt_cur -
943 dfs->short_pulse_cnt_pre;
944 } else {
945 short_pulse_cnt_inc = short_pulse_cnt_cur;
946 }
947 dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;
948
949 /*@Get long pulse count, need carefully handle the counter overflow*/
950 if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) {
951 long_pulse_cnt_inc = long_pulse_cnt_cur -
952 dfs->long_pulse_cnt_pre;
953 } else {
954 long_pulse_cnt_inc = long_pulse_cnt_cur;
955 }
956 dfs->long_pulse_cnt_pre = long_pulse_cnt_cur;
957
958 total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
959
960 if (dfs->det_print) {
961 PHYDM_DBG(dm, DBG_DFS,
962 "===============================================\n");
963 PHYDM_DBG(dm, DBG_DFS, "FA_count_inc[%d]\n", fa_count_inc);
964 if (dm->support_ic_type & (ODM_RTL8721D)) {
965 PHYDM_DBG(dm, DBG_DFS,
966 "Init_Gain[%x] st_l2h_cur[%x] 0xdf4[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
967 dfs->igi_cur, dfs->st_l2h_cur, regdf4_value,
968 short_pulse_cnt_inc, long_pulse_cnt_inc);
969 regf54_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
970 regf58_value = odm_get_bb_reg(dm, R_0xf58, MASKDWORD);
971 regf5c_value = odm_get_bb_reg(dm, R_0xf5c, MASKDWORD);
972 regf70_value = odm_get_bb_reg(dm, R_0xf70, MASKDWORD);
973 regf74_value = odm_get_bb_reg(dm, R_0xf74, MASKDWORD);
974 PHYDM_DBG(dm, DBG_DFS,
975 "0xf54[%08x] 0xf58[%08x] 0xf5c[%08x] 0xf70[%08x] 0xf74[%08x]\n",
976 regf54_value, regf58_value, regf5c_value,
977 regf70_value, regf74_value);
978 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
979 PHYDM_DBG(dm, DBG_DFS,
980 "Init_Gain[%x] st_l2h_cur[%x] 0x2dbc[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
981 dfs->igi_cur, dfs->st_l2h_cur,
982 radar_rpt_reg_value, short_pulse_cnt_inc,
983 long_pulse_cnt_inc);
984 #if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
985 rega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD);
986 rega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD);
987 rega48_value = odm_get_bb_reg(dm, R_0xa48, MASKDWORD);
988 rega4c_value = odm_get_bb_reg(dm, R_0xa4c, MASKDWORD);
989 rega50_value = odm_get_bb_reg(dm, R_0xa50, MASKDWORD);
990 rega54_value = odm_get_bb_reg(dm, R_0xa54, MASKDWORD);
991 PHYDM_DBG(dm, DBG_DFS,
992 "0xa40[%08x] 0xa44[%08x] 0xa48[%08x] 0xa4c[%08x] 0xa50[%08x] 0xa54[%08x]\n",
993 rega40_value, rega44_value, rega48_value,
994 rega4c_value, rega50_value, rega54_value);
995 #endif
996 } else {
997 PHYDM_DBG(dm, DBG_DFS,
998 "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
999 dfs->igi_cur, dfs->st_l2h_cur, regf98_value,
1000 short_pulse_cnt_inc, long_pulse_cnt_inc);
1001 reg918_value = odm_get_bb_reg(dm, R_0x918,
1002 0xffffffff);
1003 reg91c_value = odm_get_bb_reg(dm, R_0x91c,
1004 0xffffffff);
1005 reg920_value = odm_get_bb_reg(dm, R_0x920,
1006 0xffffffff);
1007 reg924_value = odm_get_bb_reg(dm, R_0x924,
1008 0xffffffff);
1009 PHYDM_DBG(dm, DBG_DFS,
1010 "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n",
1011 reg918_value, reg91c_value,
1012 reg920_value, reg924_value);
1013 }
1014 PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n",
1015 (dm->rx_tp + dm->tx_tp));
1016
1017 PHYDM_DBG(dm, DBG_DFS,
1018 "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\n",
1019 region_domain, dfs->dbg_mode,
1020 dfs->idle_mode, dfs->print_hist_rpt,
1021 dfs->hist_cond_on);
1022 }
1023 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1024 tri_short_pulse = (radar_rpt_reg_value & BIT(20)) ? 1 : 0;
1025 tri_long_pulse = (radar_rpt_reg_value & BIT(28)) ? 1 : 0;
1026 } else {
1027 tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0;
1028 tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0;
1029 }
1030
1031 if (tri_short_pulse) {
1032 phydm_radar_detect_reset(dm);
1033 }
1034 if (tri_long_pulse) {
1035 phydm_radar_detect_reset(dm);
1036 if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
1037 if (c_channel >= 52 && c_channel <= 64) {
1038 tri_long_pulse = 0;
1039 }
1040 }
1041 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
1042 tri_long_pulse = 0;
1043 }
1044 }
1045
1046 st_l2h_new = dfs->st_l2h_cur;
1047 dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse;
1048 dfs->pulse_type_hist[dfs->mask_idx] = (tri_long_pulse) ? 1 : 0;
1049
1050 /* PSD(not ready) */
1051
1052 fault_flag_det = 0;
1053 fault_flag_psd = 0;
1054 fa_flag = 0;
1055 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
1056 fa_mask_th = dfs->fa_mask_th + 20;
1057 } else {
1058 fa_mask_th = dfs->fa_mask_th;
1059 }
1060 if (total_fa_in_hist >= fa_mask_th || dfs->igi_cur >= 0x30) {
1061 /* st_l2h_new = dfs->st_l2h_max; */
1062 dfs->radar_det_mask_hist[index] = 1;
1063 if (dfs->pulse_flag_hist[index] == 1) {
1064 dfs->pulse_flag_hist[index] = 0;
1065 if (dfs->det_print2) {
1066 PHYDM_DBG(dm, DBG_DFS,
1067 "Radar is masked : FA mask\n");
1068 }
1069 }
1070 fa_flag = 1;
1071 } else {
1072 dfs->radar_det_mask_hist[index] = 0;
1073 }
1074
1075 if (dfs->det_print) {
1076 PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx);
1077 PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: ");
1078 for (i = 0; i < 5; i++)
1079 PHYDM_DBG(dm, DBG_DFS, "%d ",
1080 dfs->radar_det_mask_hist[i]);
1081 PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: ");
1082 for (i = 0; i < 5; i++)
1083 PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]);
1084 PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: ");
1085 for (i = 0; i < 5; i++)
1086 PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]);
1087 PHYDM_DBG(dm, DBG_DFS,
1088 "\nfa_mask_th: %d, total_fa_in_hist: %d ",
1089 fa_mask_th, total_fa_in_hist);
1090 }
1091
1092 sum = 0;
1093 for (k = 0; k < 5; k++) {
1094 if (dfs->radar_det_mask_hist[k] == 1)
1095 sum++;
1096 }
1097
1098 if (dfs->mask_hist_checked <= 5)
1099 dfs->mask_hist_checked++;
1100
1101 if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) {
1102 if (sum <= 2) {
1103 if (dfs->hist_cond_on) {
1104 /*return the value from hist_radar_detected*/
1105 radar_detected = phydm_dfs_hist_log(dm, index);
1106 } else {
1107 if (dfs->pulse_type_hist[index] == 0)
1108 dfs->radar_type = 0;
1109 else if (dfs->pulse_type_hist[index] == 1)
1110 dfs->radar_type = 1;
1111 radar_detected = 1;
1112 PHYDM_DBG(dm, DBG_DFS,
1113 "Detected type %d radar signal!\n",
1114 dfs->radar_type);
1115 }
1116 } else {
1117 fault_flag_det = 1;
1118 if (dfs->det_print2) {
1119 PHYDM_DBG(dm, DBG_DFS,
1120 "Radar is masked : mask_hist large than thd\n");
1121 }
1122 }
1123 }
1124
1125 dfs->mask_idx++;
1126 if (dfs->mask_idx == 5)
1127 dfs->mask_idx = 0;
1128
1129 if (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) {
1130 if (dfs->igi_cur < 0x30) {
1131 st_l2h_new = dfs->st_l2h_min;
1132 }
1133 }
1134
1135 if (st_l2h_new != dfs->st_l2h_cur) {
1136 if (st_l2h_new < dfs->st_l2h_min) {
1137 dfs->st_l2h_cur = dfs->st_l2h_min;
1138 } else if (st_l2h_new > dfs->st_l2h_max)
1139 dfs->st_l2h_cur = dfs->st_l2h_max;
1140 else
1141 dfs->st_l2h_cur = st_l2h_new;
1142 /*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/
1143
1144 dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
1145 / 2 + dfs->pwdb_scalar_factor;
1146
1147 /*@limit the pwdb value to absolute lower bound 8*/
1148 dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
1149
1150 /*@limit the pwdb value to absolute upper bound 0x1f*/
1151 dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
1152
1153 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
1154 odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
1155 dfs->pwdb_th_cur);
1156 #if (RTL8721D_SUPPORT)
1157 else if (dm->support_ic_type & ODM_RTL8721D) {
1158 odm_set_bb_reg(dm, R_0xf54, 0x0000001f,
1159 ((dfs->st_l2h_cur & 0x0000007c) >> 2));
1160 odm_set_bb_reg(dm, R_0xf58, 0xc0000000,
1161 (dfs->st_l2h_cur & 0x00000003));
1162 odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
1163 dfs->pwdb_th_cur);
1164 }
1165 #endif
1166 else
1167 odm_set_bb_reg(dm, R_0x918, 0x00001f00,
1168 dfs->pwdb_th_cur);
1169 }
1170
1171 if (dfs->det_print) {
1172 PHYDM_DBG(dm, DBG_DFS,
1173 "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",
1174 fault_flag_det, fault_flag_psd, radar_detected);
1175 }
1176 #if (RTL8721D_SUPPORT)
1177 if (dm->support_ic_type & (ODM_RTL8721D))
1178 odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908_value);
1179 #endif
1180
1181 return radar_detected;
1182 }
1183
1184 #if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
phydm_dfs_histogram_radar_distinguish(void * dm_void)1185 void phydm_dfs_histogram_radar_distinguish(
1186 void *dm_void)
1187 {
1188 struct dm_struct *dm = (struct dm_struct *)dm_void;
1189 struct _DFS_STATISTICS *dfs = &dm->dfs;
1190 u8 region_domain = dm->dfs_region_domain;
1191 u8 c_channel = *dm->channel;
1192 u8 band_width = *dm->band_width;
1193
1194 u8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0;
1195 u8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0;
1196 u8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0;
1197 u8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0;
1198 u8 pri_th = 0, i = 0;
1199 u8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0;
1200 u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0;
1201 u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0;
1202 u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0;
1203 u8 j = 0;
1204 u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0};
1205 u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0};
1206 u8 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;
1207 u8 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;
1208 u16 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;
1209 u8 max_pri_cnt = 0, max_pw_cnt = 0;
1210 #if (RTL8721D_SUPPORT)
1211 if (dm->support_ic_type & (ODM_RTL8721D))
1212 return;
1213 #endif
1214
1215 /*read pulse width hist report*/
1216 odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1);
1217 dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
1218 dfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
1219
1220 g_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24);
1221 g_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16);
1222 g_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8);
1223 g_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff;
1224 g_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24);
1225 g_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16);
1226
1227 /*read pulse repetition interval hist report*/
1228 odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3);
1229 dfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
1230 dfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
1231 odm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/
1232 odm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/
1233
1234 g_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24);
1235 g_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16);
1236 g_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8);
1237 g_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff;
1238 g_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24);
1239 g_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16);
1240
1241 dfs->pri_cond1 = 0;
1242 dfs->pri_cond2 = 0;
1243 dfs->pri_cond3 = 0;
1244 dfs->pri_cond4 = 0;
1245 dfs->pri_cond5 = 0;
1246 dfs->pw_cond1 = 0;
1247 dfs->pw_cond2 = 0;
1248 dfs->pw_cond3 = 0;
1249 dfs->pri_type3_4_cond1 = 0; /*@for ETSI*/
1250 dfs->pri_type3_4_cond2 = 0; /*@for ETSI*/
1251 dfs->pw_long_cond1 = 0; /*@for long radar*/
1252 dfs->pw_long_cond2 = 0; /*@for long radar*/
1253 dfs->pri_long_cond1 = 0; /*@for long radar*/
1254 dfs->pw_flag = 0;
1255 dfs->pri_flag = 0;
1256 dfs->pri_type3_4_flag = 0; /*@for ETSI*/
1257 dfs->long_radar_flag = 0;
1258 dfs->pw_std = 0; /*The std(var) of reasonable num of pw group*/
1259 dfs->pri_std = 0; /*The std(var) of reasonable num of pri group*/
1260
1261 for (i = 0; i < 6; i++) {
1262 dfs->pw_hold_sum[i] = 0;
1263 dfs->pri_hold_sum[i] = 0;
1264 }
1265
1266 if (dfs->idle_mode == 1)
1267 pri_th = dfs->pri_hist_th;
1268 else
1269 pri_th = dfs->pri_hist_th - 1;
1270
1271 for (i = 0; i < 6; i++) {
1272 dfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i];
1273 dfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i];
1274 /*@collect whole histogram report may take some time
1275 *so we add the counter of 2 time slots in FCC and ETSI
1276 */
1277 dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
1278 dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +
1279 dfs->pw_hold[(dfs->hist_idx + 2) % 3][i];
1280 dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
1281 dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +
1282 dfs->pri_hold[(dfs->hist_idx + 2) % 3][i];
1283 }
1284 /*@For long radar type*/
1285 for (j = 1; j < 4; j++) {
1286 dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] +
1287 dfs->pw_hold[(dfs->hist_long_idx + j) % 4][i];
1288 dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] +
1289 dfs->pri_hold[(dfs->hist_long_idx + j) % 4][i];
1290 }
1291
1292 dfs->hist_idx++;
1293 if (dfs->hist_idx == 3)
1294 dfs->hist_idx = 0;
1295 dfs->hist_long_idx++;
1296 if (dfs->hist_long_idx == 4)
1297 dfs->hist_long_idx = 0;
1298
1299 max_pri_cnt = 0;
1300 max_pri_idx = 0;
1301 max_pw_cnt = 0;
1302 max_pw_idx = 0;
1303 max_pri_cnt_th = dfs->pri_sum_g1_th;
1304 max_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th;
1305 max_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th;
1306 safe_pri_pw_diff_th = dfs->pri_pw_diff_th;
1307 safe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th;
1308 safe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th;
1309 safe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th;
1310
1311 /*@g1 to g4 is the reseasonable range of pri and pw*/
1312 for (i = 1; i <= 4; i++) {
1313 if (dfs->pri_hold_sum[i] > max_pri_cnt) {
1314 max_pri_cnt = dfs->pri_hold_sum[i];
1315 max_pri_idx = i;
1316 }
1317 if (dfs->pw_hold_sum[i] > max_pw_cnt) {
1318 max_pw_cnt = dfs->pw_hold_sum[i];
1319 max_pw_idx = i;
1320 }
1321 if (dfs->pri_hold_sum[i] >= pri_th)
1322 dfs->pri_cond1 = 1;
1323 }
1324
1325 pri_sum_g0g5 = dfs->pri_hold_sum[0];
1326 if (pri_sum_g0g5 == 0)
1327 pri_sum_g0g5 = 1;
1328 pri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2]
1329 + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4];
1330
1331 /*pw will reduce because of dc, so we do not treat g0 as illegal group*/
1332 pw_sum_g0g5 = dfs->pw_hold_sum[5];
1333 if (pw_sum_g0g5 == 0)
1334 pw_sum_g0g5 = 1;
1335 pw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] +
1336 dfs->pw_hold_sum[3] + dfs->pw_hold_sum[4];
1337
1338 /*@Calculate the variation from g1 to g4*/
1339 for (i = 1; i < 5; i++) {
1340 /*Sum of square*/
1341 pw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 +
1342 (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) *
1343 (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4));
1344 pri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 +
1345 (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) *
1346 (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4));
1347 }
1348 /*The value may less than the normal variance,
1349 *since the variable type is int (not float)
1350 */
1351 dfs->pw_std = (u8)(pw_sum_ss_g1g2g3g4 / 4);
1352 dfs->pri_std = (u8)(pri_sum_ss_g1g2g3g4 / 4);
1353
1354 if (region_domain == 1) {
1355 dfs->pri_type3_4_flag = 1; /*@ETSI flag*/
1356
1357 /*(OTA) Cancel long PRI case*/
1358 dfs->pri_cond2 = 1;
1359
1360 /*reasonable group shouldn't large*/
1361 if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 &&
1362 pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
1363 dfs->pri_cond3 = 1;
1364
1365 /*@Cancel the condition that the abs between pri and pw*/
1366 if (dfs->pri_std >= dfs->pri_std_th)
1367 dfs->pri_cond4 = 1;
1368 else if (max_pri_idx == 1 &&
1369 max_pri_cnt >= max_pri_cnt_fcc_g1_th)
1370 dfs->pri_cond4 = 1;
1371
1372 /*(OTA) Cancel the condition (type 3,4 distinction)*/
1373 dfs->pri_cond5 = 1;
1374
1375 if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
1376 dfs->pri_cond4 && dfs->pri_cond5)
1377 dfs->pri_flag = 1;
1378
1379 /* PW judgment conditions for short radar type */
1380 /*ratio of reasonable and illegal group && g5 should be zero*/
1381 if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
1382 (dfs->pw_hold_sum[5] <= 1))
1383 dfs->pw_cond1 = 1;
1384 /*unreasonable group*/
1385 if (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0)
1386 dfs->pw_cond2 = 1;
1387 /*pw's std (short radar) should be large(=7)*/
1388 if (dfs->pw_std >= dfs->pw_std_th)
1389 dfs->pw_cond3 = 1;
1390 if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
1391 dfs->pw_flag = 1;
1392
1393 /* @Judgment conditions of long radar type */
1394 if (band_width == CHANNEL_WIDTH_20) {
1395 if (dfs->pw_long_hold_sum[4] >=
1396 dfs->pw_long_lower_20m_th)
1397 dfs->pw_long_cond1 = 1;
1398 } else{
1399 if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
1400 dfs->pw_long_cond1 = 1;
1401 }
1402 /* @Disable the condition that dfs->pw_long_hold_sum[1] */
1403 if (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] +
1404 dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th &&
1405 dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] &&
1406 dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4])
1407 dfs->pw_long_cond2 = 1;
1408 /*@g4 should be large for long radar*/
1409 if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
1410 dfs->pri_long_cond1 = 1;
1411 if (dfs->pw_long_cond1 && dfs->pw_long_cond2 &&
1412 dfs->pri_long_cond1)
1413 dfs->long_radar_flag = 1;
1414 } else if (region_domain == 2) {
1415 dfs->pri_type3_4_flag = 1; /*@ETSI flag*/
1416
1417 /*PRI judgment conditions for short radar type*/
1418 if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
1419 dfs->pri_cond2 = 1;
1420
1421 /*reasonable group shouldn't too large*/
1422 if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
1423 dfs->pri_cond3 = 1;
1424
1425 /*Cancel the abs diff between pri and pw for idle mode (thr=2)*/
1426 dfs->pri_cond4 = 1;
1427
1428 if (dfs->idle_mode == 1) {
1429 if (dfs->pri_std >= dfs->pri_std_idle_th) {
1430 if (max_pw_idx == 3 &&
1431 pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){
1432 /*To distinguish between type 4 radar and false detection*/
1433 dfs->pri_cond5 = 1;
1434 } else if (max_pw_idx == 1 &&
1435 pri_sum_g1g2g3g4 >=
1436 dfs->pri_sum_type6_th) {
1437 /*To distinguish between type 6 radar and false detection*/
1438 dfs->pri_cond5 = 1;
1439 } else {
1440 /*pri variation of short radar should be large (idle mode)*/
1441 dfs->pri_cond5 = 1;
1442 }
1443 }
1444 } else {
1445 /*pri variation of short radar should be large (TP mode)*/
1446 if (dfs->pri_std >= dfs->pri_std_th)
1447 dfs->pri_cond5 = 1;
1448 }
1449
1450 if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
1451 dfs->pri_cond4 && dfs->pri_cond5)
1452 dfs->pri_flag = 1;
1453
1454 /* PW judgment conditions for short radar type */
1455 if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
1456 (dfs->pw_hold_sum[5] <= 1))
1457 /*ratio of reasonable and illegal group && g5 should be zero*/
1458 dfs->pw_cond1 = 1;
1459
1460 if ((c_channel >= 52) && (c_channel <= 64))
1461 dfs->pw_cond2 = 1;
1462 /*unreasonable group shouldn't too large*/
1463 else if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th)
1464 dfs->pw_cond2 = 1;
1465
1466 if (dfs->idle_mode == 1) {
1467 /*pw variation of short radar should be large (idle mode)*/
1468 if (dfs->pw_std >= dfs->pw_std_idle_th)
1469 dfs->pw_cond3 = 1;
1470 } else {
1471 /*pw variation of short radar should be large (TP mode)*/
1472 if (dfs->pw_std >= dfs->pw_std_th)
1473 dfs->pw_cond3 = 1;
1474 }
1475 if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
1476 dfs->pw_flag = 1;
1477
1478 /* @Judgment conditions of long radar type */
1479 if (band_width == CHANNEL_WIDTH_20) {
1480 if (dfs->pw_long_hold_sum[4] >=
1481 dfs->pw_long_lower_20m_th)
1482 dfs->pw_long_cond1 = 1;
1483 } else{
1484 if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
1485 dfs->pw_long_cond1 = 1;
1486 }
1487 if (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] +
1488 dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4]
1489 <= dfs->pw_long_sum_upper_th)
1490 dfs->pw_long_cond2 = 1;
1491 /*@g4 should be large for long radar*/
1492 if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
1493 dfs->pri_long_cond1 = 1;
1494 if (dfs->pw_long_cond1 &&
1495 dfs->pw_long_cond2 && dfs->pri_long_cond1)
1496 dfs->long_radar_flag = 1;
1497 } else if (region_domain == 3) {
1498 /*ratio of reasonable group and illegal group */
1499 if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
1500 dfs->pri_cond2 = 1;
1501
1502 if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th)
1503 dfs->pri_cond3 = 1;
1504
1505 /*@Cancel the condition that the abs between pri and pw*/
1506 dfs->pri_cond4 = 1;
1507
1508 if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th)
1509 dfs->pri_cond5 = 1;
1510
1511 if (band_width == CHANNEL_WIDTH_40) {
1512 if (max_pw_idx == 4) {
1513 if (max_pw_cnt >= dfs->type4_pw_max_cnt &&
1514 pri_sum_g1g2g3g4 >=
1515 dfs->type4_safe_pri_sum_th) {
1516 dfs->pri_cond1 = 1;
1517 dfs->pri_cond4 = 1;
1518 dfs->pri_type3_4_cond1 = 1;
1519 }
1520 }
1521 }
1522
1523 if (dfs->pri_cond1 && dfs->pri_cond2 &&
1524 dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5)
1525 dfs->pri_flag = 1;
1526
1527 if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2))
1528 dfs->pw_flag = 1;
1529
1530 /*@max num pri group is g1 means radar type3 or type4*/
1531 if (max_pri_idx == 1) {
1532 if (max_pri_cnt >= max_pri_cnt_th)
1533 dfs->pri_type3_4_cond1 = 1;
1534 if (dfs->pri_hold_sum[4] <=
1535 dfs->pri_sum_g5_under_g1_th &&
1536 dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th)
1537 dfs->pri_type3_4_cond2 = 1;
1538 } else {
1539 dfs->pri_type3_4_cond1 = 1;
1540 dfs->pri_type3_4_cond2 = 1;
1541 }
1542 if (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2)
1543 dfs->pri_type3_4_flag = 1;
1544 } else {
1545 }
1546
1547 if (dfs->print_hist_rpt) {
1548 dfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000);
1549 dfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff);
1550 dfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00);
1551 dfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000);
1552 dfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000);
1553
1554 dfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80);
1555 dfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff);
1556 dfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00);
1557 dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000);
1558 dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000);
1559
1560 PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n",
1561 dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3,
1562 dfs_pw_thd4, dfs_pw_thd5);
1563 PHYDM_DBG(dm, DBG_DFS, "-----pulse width hist-----\n");
1564 PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pw=%x %x\n",
1565 dfs_hist1_pw, dfs_hist2_pw);
1566 PHYDM_DBG(dm, DBG_DFS, "g_pw_hist = %x %x %x %x %x %x\n",
1567 g_pw[0], g_pw[1], g_pw[2], g_pw[3],
1568 g_pw[4], g_pw[5]);
1569 PHYDM_DBG(dm, DBG_DFS, "dfs_pri_thd=%d %d %d %d %d\n",
1570 dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3,
1571 dfs_pri_thd4, dfs_pri_thd5);
1572 PHYDM_DBG(dm, DBG_DFS, "-----pulse interval hist-----\n");
1573 PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pri=%x %x\n",
1574 dfs_hist1_pri, dfs_hist2_pri);
1575 PHYDM_DBG(dm, DBG_DFS,
1576 "g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\n",
1577 g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4],
1578 g_pri[5], dfs->pw_flag, dfs->pri_flag);
1579 if (region_domain == 1 || region_domain == 3) {
1580 PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
1581 (dfs->hist_idx + 2) % 3);
1582 } else {
1583 PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
1584 (dfs->hist_idx + 3) % 4);
1585 }
1586 PHYDM_DBG(dm, DBG_DFS, "hist_long_idx= %d\n",
1587 (dfs->hist_long_idx + 299) % 300);
1588 PHYDM_DBG(dm, DBG_DFS,
1589 "pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\n",
1590 pw_sum_g0g5, pw_sum_g1g2g3g4);
1591 PHYDM_DBG(dm, DBG_DFS,
1592 "pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\n",
1593 pri_sum_g0g5, pri_sum_g1g2g3g4);
1594 PHYDM_DBG(dm, DBG_DFS, "pw_hold_sum = %d %d %d %d %d %d\n",
1595 dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
1596 dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
1597 dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
1598 PHYDM_DBG(dm, DBG_DFS, "pri_hold_sum = %d %d %d %d %d %d\n",
1599 dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
1600 dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
1601 dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
1602 PHYDM_DBG(dm, DBG_DFS, "pw_long_hold_sum = %d %d %d %d %d %d\n",
1603 dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1],
1604 dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3],
1605 dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]);
1606 PHYDM_DBG(dm, DBG_DFS,
1607 "pri_long_hold_sum = %d %d %d %d %d %d\n",
1608 dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1],
1609 dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3],
1610 dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]);
1611 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode);
1612 PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std);
1613 PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std);
1614 PHYDM_DBG(dm, DBG_DFS, "\n");
1615 PHYDM_DBG(dm, DBG_DFS,
1616 "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n",
1617 dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3,
1618 dfs->pri_cond4, dfs->pri_cond5);
1619 PHYDM_DBG(dm, DBG_DFS,
1620 "bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\n",
1621 band_width, pri_th, max_pri_cnt_th,
1622 safe_pri_pw_diff_th);
1623 }
1624 }
1625 #endif
phydm_dfs_hist_log(void * dm_void,u8 index)1626 boolean phydm_dfs_hist_log(void *dm_void, u8 index)
1627 {
1628 struct dm_struct *dm = (struct dm_struct *)dm_void;
1629 struct _DFS_STATISTICS *dfs = &dm->dfs;
1630 u8 i = 0, j = 0;
1631 boolean hist_radar_detected = 0;
1632
1633 if (dfs->pulse_type_hist[index] == 0) {
1634 dfs->radar_type = 0;
1635 if (dfs->pw_flag && dfs->pri_flag &&
1636 dfs->pri_type3_4_flag) {
1637 hist_radar_detected = 1;
1638 PHYDM_DBG(dm, DBG_DFS,
1639 "Detected type %d radar signal!\n",
1640 dfs->radar_type);
1641 if (dfs->det_print2) {
1642 PHYDM_DBG(dm, DBG_DFS,
1643 "hist_idx= %d\n",
1644 (dfs->hist_idx + 3) % 4);
1645 for (j = 0; j < 4; j++) {
1646 for (i = 0; i < 6; i++) {
1647 PHYDM_DBG(dm, DBG_DFS,
1648 "pri_hold = %d ",
1649 dfs->pri_hold[j][i]);
1650 }
1651 PHYDM_DBG(dm, DBG_DFS, "\n");
1652 }
1653 PHYDM_DBG(dm, DBG_DFS, "\n");
1654 for (j = 0; j < 4; j++) {
1655 for (i = 0; i < 6; i++) {
1656 PHYDM_DBG(dm, DBG_DFS, "pw_hold = %d ",
1657 dfs->pw_hold[j][i]);
1658 }
1659 PHYDM_DBG(dm, DBG_DFS, "\n");
1660 }
1661 PHYDM_DBG(dm, DBG_DFS, "\n");
1662 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
1663 dfs->idle_mode);
1664 PHYDM_DBG(dm, DBG_DFS,
1665 "pw_hold_sum = %d %d %d %d %d %d\n",
1666 dfs->pw_hold_sum[0],
1667 dfs->pw_hold_sum[1],
1668 dfs->pw_hold_sum[2],
1669 dfs->pw_hold_sum[3],
1670 dfs->pw_hold_sum[4],
1671 dfs->pw_hold_sum[5]);
1672 PHYDM_DBG(dm, DBG_DFS,
1673 "pri_hold_sum = %d %d %d %d %d %d\n",
1674 dfs->pri_hold_sum[0],
1675 dfs->pri_hold_sum[1],
1676 dfs->pri_hold_sum[2],
1677 dfs->pri_hold_sum[3],
1678 dfs->pri_hold_sum[4],
1679 dfs->pri_hold_sum[5]);
1680 }
1681 } else {
1682 if (dfs->det_print2) {
1683 if (dfs->pulse_flag_hist[index] &&
1684 dfs->pri_flag == 0) {
1685 PHYDM_DBG(dm, DBG_DFS, "pri_variation = %d\n",
1686 dfs->pri_std);
1687 PHYDM_DBG(dm, DBG_DFS,
1688 "PRI criterion is not satisfied!\n");
1689 if (dfs->pri_cond1 == 0)
1690 PHYDM_DBG(dm, DBG_DFS,
1691 "pri_cond1 is not satisfied!\n");
1692 if (dfs->pri_cond2 == 0)
1693 PHYDM_DBG(dm, DBG_DFS,
1694 "pri_cond2 is not satisfied!\n");
1695 if (dfs->pri_cond3 == 0)
1696 PHYDM_DBG(dm, DBG_DFS,
1697 "pri_cond3 is not satisfied!\n");
1698 if (dfs->pri_cond4 == 0)
1699 PHYDM_DBG(dm, DBG_DFS,
1700 "pri_cond4 is not satisfied!\n");
1701 if (dfs->pri_cond5 == 0)
1702 PHYDM_DBG(dm, DBG_DFS,
1703 "pri_cond5 is not satisfied!\n");
1704 }
1705 if (dfs->pulse_flag_hist[index] &&
1706 dfs->pw_flag == 0) {
1707 PHYDM_DBG(dm, DBG_DFS, "pw_variation = %d\n",
1708 dfs->pw_std);
1709 PHYDM_DBG(dm, DBG_DFS,
1710 "PW criterion is not satisfied!\n");
1711 if (dfs->pw_cond1 == 0)
1712 PHYDM_DBG(dm, DBG_DFS,
1713 "pw_cond1 is not satisfied!\n");
1714 if (dfs->pw_cond2 == 0)
1715 PHYDM_DBG(dm, DBG_DFS,
1716 "pw_cond2 is not satisfied!\n");
1717 if (dfs->pw_cond3 == 0)
1718 PHYDM_DBG(dm, DBG_DFS,
1719 "pw_cond3 is not satisfied!\n");
1720 }
1721 if (dfs->pulse_flag_hist[index] &&
1722 (dfs->pri_type3_4_flag == 0)) {
1723 PHYDM_DBG(dm, DBG_DFS,
1724 "pri_type3_4 criterion is not satisfied!\n");
1725 if (dfs->pri_type3_4_cond1 == 0)
1726 PHYDM_DBG(dm, DBG_DFS,
1727 "pri_type3_4_cond1 is not satisfied!\n");
1728 if (dfs->pri_type3_4_cond2 == 0)
1729 PHYDM_DBG(dm, DBG_DFS,
1730 "pri_type3_4_cond2 is not satisfied!\n");
1731 }
1732 PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
1733 (dfs->hist_idx + 3) % 4);
1734 for (j = 0; j < 4; j++) {
1735 for (i = 0; i < 6; i++) {
1736 PHYDM_DBG(dm, DBG_DFS,
1737 "pri_hold = %d ",
1738 dfs->pri_hold[j][i]);
1739 }
1740 PHYDM_DBG(dm, DBG_DFS, "\n");
1741 }
1742 PHYDM_DBG(dm, DBG_DFS, "\n");
1743 for (j = 0; j < 4; j++) {
1744 for (i = 0; i < 6; i++)
1745 PHYDM_DBG(dm, DBG_DFS,
1746 "pw_hold = %d ",
1747 dfs->pw_hold[j][i]);
1748 PHYDM_DBG(dm, DBG_DFS, "\n");
1749 }
1750 PHYDM_DBG(dm, DBG_DFS, "\n");
1751 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
1752 dfs->idle_mode);
1753 PHYDM_DBG(dm, DBG_DFS,
1754 "pw_hold_sum = %d %d %d %d %d %d\n",
1755 dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
1756 dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
1757 dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
1758 PHYDM_DBG(dm, DBG_DFS,
1759 "pri_hold_sum = %d %d %d %d %d %d\n",
1760 dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
1761 dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
1762 dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
1763 }
1764 }
1765 } else {
1766 dfs->radar_type = 1;
1767 if (dfs->det_print2) {
1768 PHYDM_DBG(dm, DBG_DFS, "\n");
1769 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
1770 dfs->idle_mode);
1771 }
1772 /* @Long radar should satisfy three conditions */
1773 if (dfs->long_radar_flag == 1) {
1774 hist_radar_detected = 1;
1775 PHYDM_DBG(dm, DBG_DFS,
1776 "Detected type %d radar signal!\n",
1777 dfs->radar_type);
1778 } else {
1779 if (dfs->det_print2) {
1780 if (dfs->pw_long_cond1 == 0)
1781 PHYDM_DBG(dm, DBG_DFS,
1782 "--pw_long_cond1 is not satisfied!--\n");
1783 if (dfs->pw_long_cond2 == 0)
1784 PHYDM_DBG(dm, DBG_DFS,
1785 "--pw_long_cond2 is not satisfied!--\n");
1786 if (dfs->pri_long_cond1 == 0)
1787 PHYDM_DBG(dm, DBG_DFS,
1788 "--pri_long_cond1 is not satisfied!--\n");
1789 }
1790 }
1791 }
1792 return hist_radar_detected;
1793 }
1794
phydm_radar_detect(void * dm_void)1795 boolean phydm_radar_detect(void *dm_void)
1796 {
1797 struct dm_struct *dm = (struct dm_struct *)dm_void;
1798 struct _DFS_STATISTICS *dfs = &dm->dfs;
1799 boolean radar_detected = false;
1800
1801 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1802 dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0x1d70, 0x0000007f);
1803 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
1804 #if (RTL8721D_SUPPORT)
1805 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
1806 dfs->st_l2h_cur = (u8)(odm_get_bb_reg(dm, R_0xf54,
1807 0x0000001f) << 2);
1808 dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
1809 #endif
1810 } else {
1811 dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f);
1812 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
1813 }
1814
1815 /* @dynamic pwdb calibration */
1816 if (dfs->igi_pre != dfs->igi_cur) {
1817 dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
1818 / 2 + dfs->pwdb_scalar_factor;
1819
1820 /* @limit the pwdb value to absolute lower bound 0xa */
1821 dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
1822 /* @limit the pwdb value to absolute upper bound 0x1f */
1823 dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
1824
1825 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
1826 odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
1827 dfs->pwdb_th_cur);
1828 #if (RTL8721D_SUPPORT)
1829 else if (dm->support_ic_type & (ODM_RTL8721D))
1830 odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
1831 dfs->pwdb_th_cur);
1832 #endif
1833 else
1834 odm_set_bb_reg(dm, R_0x918, 0x00001f00,
1835 dfs->pwdb_th_cur);
1836 }
1837 dfs->igi_pre = dfs->igi_cur;
1838
1839 phydm_dfs_dynamic_setting(dm);
1840 #if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
1841 if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
1842 phydm_dfs_histogram_radar_distinguish(dm);
1843 #endif
1844 radar_detected = phydm_radar_detect_dm_check(dm);
1845
1846 if (radar_detected) {
1847 PHYDM_DBG(dm, DBG_DFS,
1848 "Radar detect: %d\n", radar_detected);
1849 phydm_radar_detect_reset(dm);
1850 if (dfs->dbg_mode == 1) {
1851 PHYDM_DBG(dm, DBG_DFS,
1852 "Radar is detected in DFS dbg mode.\n");
1853 radar_detected = 0;
1854 }
1855 }
1856
1857 if (dfs->sw_trigger_mode) {
1858 radar_detected = 1;
1859 PHYDM_DBG(dm, DBG_DFS,
1860 "Radar is detected in DFS SW trigger mode.\n");
1861 }
1862
1863 return radar_detected;
1864 }
1865
phydm_dfs_hist_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1866 void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
1867 char *output, u32 *_out_len)
1868 {
1869 struct dm_struct *dm = (struct dm_struct *)dm_void;
1870 struct _DFS_STATISTICS *dfs = &dm->dfs;
1871 char help[] = "-h";
1872 u32 argv[5] = {0};
1873 u32 used = *_used;
1874 u32 out_len = *_out_len;
1875 u8 i;
1876
1877 if ((strcmp(input[1], help) == 0)) {
1878 PDM_SNPF(out_len, used, output + used, out_len - used,
1879 "{0} pri_hist_th = %d\n", dfs->pri_hist_th);
1880 PDM_SNPF(out_len, used, output + used, out_len - used,
1881 "{1} pri_sum_g1_th = %d\n", dfs->pri_sum_g1_th);
1882 PDM_SNPF(out_len, used, output + used, out_len - used,
1883 "{2} pri_sum_g5_th = %d\n", dfs->pri_sum_g5_th);
1884 PDM_SNPF(out_len, used, output + used, out_len - used,
1885 "{3} pri_sum_g1_fcc_th = %d\n",
1886 dfs->pri_sum_g1_fcc_th);
1887 PDM_SNPF(out_len, used, output + used, out_len - used,
1888 "{4} pri_sum_g3_fcc_th = %d\n",
1889 dfs->pri_sum_g3_fcc_th);
1890 PDM_SNPF(out_len, used, output + used, out_len - used,
1891 "{5} pri_sum_safe_fcc_th = %d\n",
1892 dfs->pri_sum_safe_fcc_th);
1893 PDM_SNPF(out_len, used, output + used, out_len - used,
1894 "{6} pri_sum_type4_th = %d\n", dfs->pri_sum_type4_th);
1895 PDM_SNPF(out_len, used, output + used, out_len - used,
1896 "{7} pri_sum_type6_th = %d\n", dfs->pri_sum_type6_th);
1897 PDM_SNPF(out_len, used, output + used, out_len - used,
1898 "{8} pri_sum_safe_th = %d\n", dfs->pri_sum_safe_th);
1899 PDM_SNPF(out_len, used, output + used, out_len - used,
1900 "{9} pri_sum_g5_under_g1_th = %d\n",
1901 dfs->pri_sum_g5_under_g1_th);
1902 PDM_SNPF(out_len, used, output + used, out_len - used,
1903 "{10} pri_pw_diff_th = %d\n", dfs->pri_pw_diff_th);
1904 PDM_SNPF(out_len, used, output + used, out_len - used,
1905 "{11} pri_pw_diff_fcc_th = %d\n",
1906 dfs->pri_pw_diff_fcc_th);
1907 PDM_SNPF(out_len, used, output + used, out_len - used,
1908 "{12} pri_pw_diff_fcc_idle_th = %d\n",
1909 dfs->pri_pw_diff_fcc_idle_th);
1910 PDM_SNPF(out_len, used, output + used, out_len - used,
1911 "{13} pri_pw_diff_w53_th = %d\n",
1912 dfs->pri_pw_diff_w53_th);
1913 PDM_SNPF(out_len, used, output + used, out_len - used,
1914 "{14} pri_type1_low_fcc_th = %d\n",
1915 dfs->pri_type1_low_fcc_th);
1916 PDM_SNPF(out_len, used, output + used, out_len - used,
1917 "{15} pri_type1_upp_fcc_th = %d\n",
1918 dfs->pri_type1_upp_fcc_th);
1919 PDM_SNPF(out_len, used, output + used, out_len - used,
1920 "{16} pri_type1_cen_fcc_th = %d\n",
1921 dfs->pri_type1_cen_fcc_th);
1922 PDM_SNPF(out_len, used, output + used, out_len - used,
1923 "{17} pw_g0_th = %d\n", dfs->pw_g0_th);
1924 PDM_SNPF(out_len, used, output + used, out_len - used,
1925 "{18} pw_long_lower_20m_th = %d\n",
1926 dfs->pw_long_lower_20m_th);
1927 PDM_SNPF(out_len, used, output + used, out_len - used,
1928 "{19} pw_long_lower_th = %d\n",
1929 dfs->pw_long_lower_th);
1930 PDM_SNPF(out_len, used, output + used, out_len - used,
1931 "{20} pri_long_upper_th = %d\n",
1932 dfs->pri_long_upper_th);
1933 PDM_SNPF(out_len, used, output + used, out_len - used,
1934 "{21} pw_long_sum_upper_th = %d\n",
1935 dfs->pw_long_sum_upper_th);
1936 PDM_SNPF(out_len, used, output + used, out_len - used,
1937 "{22} pw_std_th = %d\n", dfs->pw_std_th);
1938 PDM_SNPF(out_len, used, output + used, out_len - used,
1939 "{23} pw_std_idle_th = %d\n", dfs->pw_std_idle_th);
1940 PDM_SNPF(out_len, used, output + used, out_len - used,
1941 "{24} pri_std_th = %d\n", dfs->pri_std_th);
1942 PDM_SNPF(out_len, used, output + used, out_len - used,
1943 "{25} pri_std_idle_th = %d\n", dfs->pri_std_idle_th);
1944 PDM_SNPF(out_len, used, output + used, out_len - used,
1945 "{26} type4_pw_max_cnt = %d\n", dfs->type4_pw_max_cnt);
1946 PDM_SNPF(out_len, used, output + used, out_len - used,
1947 "{27} type4_safe_pri_sum_th = %d\n",
1948 dfs->type4_safe_pri_sum_th);
1949 } else {
1950 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &argv[0]);
1951
1952 for (i = 1; i < 5; i++) {
1953 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
1954 &argv[i]);
1955 }
1956 if (argv[0] == 0) {
1957 dfs->pri_hist_th = (u8)argv[1];
1958 PDM_SNPF(out_len, used, output + used, out_len - used,
1959 "pri_hist_th = %d\n",
1960 dfs->pri_hist_th);
1961 } else if (argv[0] == 1) {
1962 dfs->pri_sum_g1_th = (u8)argv[1];
1963 PDM_SNPF(out_len, used, output + used, out_len - used,
1964 "pri_sum_g1_th = %d\n",
1965 dfs->pri_sum_g1_th);
1966 } else if (argv[0] == 2) {
1967 dfs->pri_sum_g5_th = (u8)argv[1];
1968 PDM_SNPF(out_len, used, output + used, out_len - used,
1969 "pri_sum_g5_th = %d\n",
1970 dfs->pri_sum_g5_th);
1971 } else if (argv[0] == 3) {
1972 dfs->pri_sum_g1_fcc_th = (u8)argv[1];
1973 PDM_SNPF(out_len, used, output + used, out_len - used,
1974 "pri_sum_g1_fcc_th = %d\n",
1975 dfs->pri_sum_g1_fcc_th);
1976 } else if (argv[0] == 4) {
1977 dfs->pri_sum_g3_fcc_th = (u8)argv[1];
1978 PDM_SNPF(out_len, used, output + used, out_len - used,
1979 "pri_sum_g3_fcc_th = %d\n",
1980 dfs->pri_sum_g3_fcc_th);
1981 } else if (argv[0] == 5) {
1982 dfs->pri_sum_safe_fcc_th = (u8)argv[1];
1983 PDM_SNPF(out_len, used, output + used, out_len - used,
1984 "pri_sum_safe_fcc_th = %d\n",
1985 dfs->pri_sum_safe_fcc_th);
1986 } else if (argv[0] == 6) {
1987 dfs->pri_sum_type4_th = (u8)argv[1];
1988 PDM_SNPF(out_len, used, output + used, out_len - used,
1989 "pri_sum_type4_th = %d\n",
1990 dfs->pri_sum_type4_th);
1991 } else if (argv[0] == 7) {
1992 dfs->pri_sum_type6_th = (u8)argv[1];
1993 PDM_SNPF(out_len, used, output + used, out_len - used,
1994 "pri_sum_type6_th = %d\n",
1995 dfs->pri_sum_type6_th);
1996 } else if (argv[0] == 8) {
1997 dfs->pri_sum_safe_th = (u8)argv[1];
1998 PDM_SNPF(out_len, used, output + used, out_len - used,
1999 "pri_sum_safe_th = %d\n",
2000 dfs->pri_sum_safe_th);
2001 } else if (argv[0] == 9) {
2002 dfs->pri_sum_g5_under_g1_th = (u8)argv[1];
2003 PDM_SNPF(out_len, used, output + used, out_len - used,
2004 "pri_sum_g5_under_g1_th = %d\n",
2005 dfs->pri_sum_g5_under_g1_th);
2006 } else if (argv[0] == 10) {
2007 dfs->pri_pw_diff_th = (u8)argv[1];
2008 PDM_SNPF(out_len, used, output + used, out_len - used,
2009 "pri_pw_diff_th = %d\n",
2010 dfs->pri_pw_diff_th);
2011 } else if (argv[0] == 11) {
2012 dfs->pri_pw_diff_fcc_th = (u8)argv[1];
2013 PDM_SNPF(out_len, used, output + used, out_len - used,
2014 "pri_pw_diff_fcc_th = %d\n",
2015 dfs->pri_pw_diff_fcc_th);
2016 } else if (argv[0] == 12) {
2017 dfs->pri_pw_diff_fcc_idle_th = (u8)argv[1];
2018 PDM_SNPF(out_len, used, output + used, out_len - used,
2019 "pri_pw_diff_fcc_idle_th = %d\n",
2020 dfs->pri_pw_diff_fcc_idle_th);
2021 } else if (argv[0] == 13) {
2022 dfs->pri_pw_diff_w53_th = (u8)argv[1];
2023 PDM_SNPF(out_len, used, output + used, out_len - used,
2024 "pri_pw_diff_w53_th = %d\n",
2025 dfs->pri_pw_diff_w53_th);
2026 } else if (argv[0] == 14) {
2027 dfs->pri_type1_low_fcc_th = (u8)argv[1];
2028 PDM_SNPF(out_len, used, output + used, out_len - used,
2029 "pri_type1_low_fcc_th = %d\n",
2030 dfs->pri_type1_low_fcc_th);
2031 } else if (argv[0] == 15) {
2032 dfs->pri_type1_upp_fcc_th = (u8)argv[1];
2033 PDM_SNPF(out_len, used, output + used, out_len - used,
2034 "pri_type1_upp_fcc_th = %d\n",
2035 dfs->pri_type1_upp_fcc_th);
2036 } else if (argv[0] == 16) {
2037 dfs->pri_type1_cen_fcc_th = (u8)argv[1];
2038 PDM_SNPF(out_len, used, output + used, out_len - used,
2039 "pri_type1_cen_fcc_th = %d\n",
2040 dfs->pri_type1_cen_fcc_th);
2041 } else if (argv[0] == 17) {
2042 dfs->pw_g0_th = (u8)argv[1];
2043 PDM_SNPF(out_len, used, output + used, out_len - used,
2044 "pw_g0_th = %d\n",
2045 dfs->pw_g0_th);
2046 } else if (argv[0] == 18) {
2047 dfs->pw_long_lower_20m_th = (u8)argv[1];
2048 PDM_SNPF(out_len, used, output + used, out_len - used,
2049 "pw_long_lower_20m_th = %d\n",
2050 dfs->pw_long_lower_20m_th);
2051 } else if (argv[0] == 19) {
2052 dfs->pw_long_lower_th = (u8)argv[1];
2053 PDM_SNPF(out_len, used, output + used, out_len - used,
2054 "pw_long_lower_th = %d\n",
2055 dfs->pw_long_lower_th);
2056 } else if (argv[0] == 20) {
2057 dfs->pri_long_upper_th = (u8)argv[1];
2058 PDM_SNPF(out_len, used, output + used, out_len - used,
2059 "pri_long_upper_th = %d\n",
2060 dfs->pri_long_upper_th);
2061 } else if (argv[0] == 21) {
2062 dfs->pw_long_sum_upper_th = (u8)argv[1];
2063 PDM_SNPF(out_len, used, output + used, out_len - used,
2064 "pw_long_sum_upper_th = %d\n",
2065 dfs->pw_long_sum_upper_th);
2066 } else if (argv[0] == 22) {
2067 dfs->pw_std_th = (u8)argv[1];
2068 PDM_SNPF(out_len, used, output + used, out_len - used,
2069 "pw_std_th = %d\n",
2070 dfs->pw_std_th);
2071 } else if (argv[0] == 23) {
2072 dfs->pw_std_idle_th = (u8)argv[1];
2073 PDM_SNPF(out_len, used, output + used, out_len - used,
2074 "pw_std_idle_th = %d\n",
2075 dfs->pw_std_idle_th);
2076 } else if (argv[0] == 24) {
2077 dfs->pri_std_th = (u8)argv[1];
2078 PDM_SNPF(out_len, used, output + used, out_len - used,
2079 "pri_std_th = %d\n",
2080 dfs->pri_std_th);
2081 } else if (argv[0] == 25) {
2082 dfs->pri_std_idle_th = (u8)argv[1];
2083 PDM_SNPF(out_len, used, output + used, out_len - used,
2084 "pri_std_idle_th = %d\n",
2085 dfs->pri_std_idle_th);
2086 } else if (argv[0] == 26) {
2087 dfs->type4_pw_max_cnt = (u8)argv[1];
2088 PDM_SNPF(out_len, used, output + used, out_len - used,
2089 "type4_pw_max_cnt = %d\n",
2090 dfs->type4_pw_max_cnt);
2091 } else if (argv[0] == 27) {
2092 dfs->type4_safe_pri_sum_th = (u8)argv[1];
2093 PDM_SNPF(out_len, used, output + used, out_len - used,
2094 "type4_safe_pri_sum_th = %d\n",
2095 dfs->type4_safe_pri_sum_th);
2096 }
2097 }
2098 *_used = used;
2099 *_out_len = out_len;
2100 }
2101
phydm_dfs_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2102 void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
2103 char *output, u32 *_out_len)
2104 {
2105 struct dm_struct *dm = (struct dm_struct *)dm_void;
2106 struct _DFS_STATISTICS *dfs = &dm->dfs;
2107 u32 used = *_used;
2108 u32 out_len = *_out_len;
2109 u32 argv[10] = {0};
2110 u8 i, input_idx = 0;
2111
2112 for (i = 0; i < 7; i++) {
2113 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);
2114 input_idx++;
2115 }
2116
2117 if (input_idx == 0)
2118 return;
2119
2120 dfs->dbg_mode = (boolean)argv[0];
2121 dfs->sw_trigger_mode = (boolean)argv[1];
2122 dfs->force_TP_mode = (boolean)argv[2];
2123 dfs->det_print = (boolean)argv[3];
2124 dfs->det_print2 = (boolean)argv[4];
2125 dfs->print_hist_rpt = (boolean)argv[5];
2126 dfs->hist_cond_on = (boolean)argv[6];
2127
2128 PDM_SNPF(out_len, used, output + used, out_len - used,
2129 "dbg_mode: %d, sw_trigger_mode: %d, force_TP_mode: %d, det_print: %d,det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\n",
2130 dfs->dbg_mode, dfs->sw_trigger_mode, dfs->force_TP_mode,
2131 dfs->det_print, dfs->det_print2, dfs->print_hist_rpt,
2132 dfs->hist_cond_on);
2133 }
2134
phydm_dfs_polling_time(void * dm_void)2135 u8 phydm_dfs_polling_time(void *dm_void)
2136 {
2137 struct dm_struct *dm = (struct dm_struct *)dm_void;
2138 struct _DFS_STATISTICS *dfs = &dm->dfs;
2139
2140 if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
2141 dfs->dfs_polling_time = 40;
2142 else
2143 dfs->dfs_polling_time = 100;
2144
2145 return dfs->dfs_polling_time;
2146 }
2147
2148 #endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
2149
2150 boolean
phydm_is_dfs_band(void * dm_void)2151 phydm_is_dfs_band(void *dm_void)
2152 {
2153 struct dm_struct *dm = (struct dm_struct *)dm_void;
2154
2155 if (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
2156 ((*dm->channel >= 100) && (*dm->channel <= 144)))
2157 return true;
2158 else
2159 return false;
2160 }
2161
2162 boolean
phydm_dfs_master_enabled(void * dm_void)2163 phydm_dfs_master_enabled(void *dm_void)
2164 {
2165 #ifdef CONFIG_PHYDM_DFS_MASTER
2166 struct dm_struct *dm = (struct dm_struct *)dm_void;
2167 boolean ret_val = false;
2168
2169 if (dm->dfs_master_enabled) /*pointer protection*/
2170 ret_val = *dm->dfs_master_enabled ? true : false;
2171
2172 return ret_val;
2173 #else
2174 return false;
2175 #endif
2176 }
2177
2178 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
2179 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_dfs_ap_reset_radar_detect_counter_and_flag(void * dm_void)2180 void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void)
2181 {
2182 struct dm_struct *dm = (struct dm_struct *)dm_void;
2183
2184 /* @Clear Radar Counter and Radar flag */
2185 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
2186 odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
2187
2188 /* RT_TRACE(COMP_DFS, DBG_LOUD, ("[DFS], After reset radar counter, 0xcf8 = 0x%x, 0xcf4 = 0x%x\n", */
2189 /* PHY_QueryBBReg(Adapter, 0xcf8, bMaskDWord), */
2190 /* PHY_QueryBBReg(Adapter, 0xcf4, bMaskDWord))); */
2191 }
2192 #endif
2193 #endif
2194