1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMADAPTIVITY_H__ 27 #define __PHYDMADAPTIVITY_H__ 28 29 #define ADAPTIVITY_VERSION "9.7.07" /*@20190321 changed by Kevin, 30 *add 8721D threshold l2h init 31 */ 32 #define ADC_BACKOFF 12 33 #define EDCCA_TH_L2H_LB 48 34 #define TH_L2H_DIFF_IGI 8 35 #define EDCCA_HL_DIFF_NORMAL 8 36 #define IGI_2_DBM(igi) (igi - 110) 37 /*@ [PHYDM-337][Old IC] EDCCA TH = IGI + REG setting*/ 38 #define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\ 39 ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812) 40 41 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) 42 #define ADAPT_DC_BACKOFF 2 43 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) 44 #define ADAPT_DC_BACKOFF 4 45 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) 46 #define ADAPT_DC_BACKOFF 0 47 #endif 48 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 49 enum phydm_regulation_type { 50 REGULATION_FCC = 0, 51 REGULATION_MKK = 1, 52 REGULATION_ETSI = 2, 53 REGULATION_WW = 3, 54 MAX_REGULATION_NUM = 4 55 }; 56 #endif 57 58 enum phydm_edcca_mode { 59 PHYDM_EDCCA_NORMAL_MODE = 0, 60 PHYDM_EDCCA_ADAPT_MODE = 1 61 }; 62 63 enum phydm_adapinfo { 64 PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, 65 PHYDM_ADAPINFO_TH_L2H_INI, 66 PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, 67 PHYDM_ADAPINFO_AP_NUM_TH, 68 PHYDM_ADAPINFO_DOMAIN_CODE_2G, 69 PHYDM_ADAPINFO_DOMAIN_CODE_5G, 70 PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND 71 }; 72 73 enum phydm_mac_edcca_type { 74 PHYDM_IGNORE_EDCCA = 0, 75 PHYDM_DONT_IGNORE_EDCCA = 1 76 }; 77 78 enum phydm_adaptivity_debug_mode { 79 PHYDM_ADAPT_MSG = 0, 80 PHYDM_ADAPT_DEBUG = 1, 81 PHYDM_ADAPT_RESUME = 2, 82 }; 83 84 struct phydm_adaptivity_struct { 85 boolean mode_cvrt_en; 86 s8 th_l2h_ini_backup; 87 s8 th_edcca_hl_diff_backup; 88 s8 igi_base; 89 s8 h2l_lb; 90 s8 l2h_lb; 91 u8 ap_num_th; 92 u8 l2h_dyn_min; 93 u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/ 94 u8 debug_mode; 95 u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/ 96 u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/ 97 boolean igi_lmt_en; 98 u8 adapt_igi_up; 99 u32 rvrt_val[2]; /*@all rvrt_val for pause API must set to u32*/ 100 s8 th_l2h; 101 s8 th_h2l; 102 u8 regulation_2g; 103 u8 regulation_5g; 104 u8 switch_th_l2h_ini_in_band; 105 }; 106 107 #ifdef PHYDM_SUPPORT_ADAPTIVITY 108 void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used, 109 char *output, u32 *_out_len); 110 111 void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len); 112 #endif 113 114 void phydm_set_edcca_threshold_api(void *dm_void); 115 116 void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info, 117 u32 value); 118 119 void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info, 120 u32 value); 121 122 void phydm_adaptivity_init(void *dm_void); 123 124 void phydm_adaptivity(void *dm_void); 125 126 #endif 127