1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
34 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
35 RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
36 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
37 RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
38 RTL8197G_SUPPORT == 1)
39
_iqk_check_if_reload(void * dm_void)40 void _iqk_check_if_reload(void *dm_void)
41 {
42 struct dm_struct *dm = (struct dm_struct *)dm_void;
43 struct dm_iqk_info *iqk_info = &dm->IQK_info;
44
45 iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
46 }
47
_iqk_page_switch(void * dm_void)48 void _iqk_page_switch(void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51
52 if (dm->support_ic_type == ODM_RTL8821C)
53 odm_write_4byte(dm, 0x1b00, 0xf8000008);
54 else
55 odm_write_4byte(dm, 0x1b00, 0xf800000a);
56 }
57
halrf_psd_log2base(u32 val)58 u32 halrf_psd_log2base(u32 val)
59 {
60 u8 j;
61 u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
62 u32 result, val_fractiond_b = 0;
63 u32 table_fraction[21] = {
64 0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
65 100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
66
67 if (val == 0)
68 return 0;
69
70 tmp = val;
71
72 while (1) {
73 if (tmp == 1)
74 break;
75
76 tmp = (tmp >> 1);
77 shiftcount++;
78 }
79
80 val_integerd_b = shiftcount + 1;
81
82 tmp2 = 1;
83 for (j = 1; j <= val_integerd_b; j++)
84 tmp2 = tmp2 * 2;
85
86 tmp = (val * 100) / tmp2;
87 tindex = tmp / 5;
88
89 if (tindex > 20)
90 tindex = 20;
91
92 val_fractiond_b = table_fraction[tindex];
93
94 result = val_integerd_b * 100 - val_fractiond_b;
95
96 return result;
97 }
98 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
99 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
halrf_iqk_xym_enable(struct dm_struct * dm,u8 xym_enable)100 void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)
101 {
102 struct dm_iqk_info *iqk_info = &dm->IQK_info;
103
104 if (xym_enable == 0)
105 iqk_info->xym_read = false;
106 else
107 iqk_info->xym_read = true;
108
109 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ",
110 (iqk_info->xym_read ? "true" : "false"));
111 }
112
113 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_read(void * dm_void,u8 path,u8 xym_type)114 void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)
115 {
116 struct dm_struct *dm = (struct dm_struct *)dm_void;
117 struct dm_iqk_info *iqk_info = &dm->IQK_info;
118 u8 i, start, num;
119 u32 tmp1, tmp2;
120
121 if (!iqk_info->xym_read)
122 return;
123
124 if (*dm->band_width == 0) {
125 start = 3;
126 num = 4;
127 } else if (*dm->band_width == 1) {
128 start = 2;
129 num = 6;
130 } else {
131 start = 0;
132 num = 10;
133 }
134
135 odm_write_4byte(dm, 0x1b00, 0xf8000008);
136 tmp1 = odm_read_4byte(dm, 0x1b1c);
137 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
138
139 odm_write_4byte(dm, 0x1b00, 0xf800000a);
140 tmp2 = odm_read_4byte(dm, 0x1b1c);
141 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
142
143 for (path = 0; path < 2; path++) {
144 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
145 switch (xym_type) {
146 case 0:
147 for (i = 0; i < num; i++) {
148 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
149 odm_write_4byte(dm, 0x1b14, 0x0);
150 iqk_info->rx_xym[path][i] =
151 odm_read_4byte(dm, 0x1b38);
152 }
153 break;
154 case 1:
155 for (i = 0; i < num; i++) {
156 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
157 odm_write_4byte(dm, 0x1b14, 0x0);
158 iqk_info->tx_xym[path][i] =
159 odm_read_4byte(dm, 0x1b38);
160 }
161 break;
162 case 2:
163 for (i = 0; i < 6; i++) {
164 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
165 odm_write_4byte(dm, 0x1b14, 0x0);
166 iqk_info->gs1_xym[path][i] =
167 odm_read_4byte(dm, 0x1b38);
168 }
169 break;
170 case 3:
171 for (i = 0; i < 6; i++) {
172 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
173 odm_write_4byte(dm, 0x1b14, 0x0);
174 iqk_info->gs2_xym[path][i] =
175 odm_read_4byte(dm, 0x1b38);
176 }
177 break;
178 case 4:
179 for (i = 0; i < 6; i++) {
180 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
181 odm_write_4byte(dm, 0x1b14, 0x0);
182 iqk_info->rxk1_xym[path][i] =
183 odm_read_4byte(dm, 0x1b38);
184 }
185 break;
186 }
187 odm_write_4byte(dm, 0x1b38, 0x20000000);
188 odm_write_4byte(dm, 0x1b00, 0xf8000008);
189 odm_write_4byte(dm, 0x1b1c, tmp1);
190 odm_write_4byte(dm, 0x1b00, 0xf800000a);
191 odm_write_4byte(dm, 0x1b1c, tmp2);
192 _iqk_page_switch(dm);
193 }
194 }
195
196 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_show(struct dm_struct * dm,u8 xym_type)197 void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)
198 {
199 u8 num, path, path_num, i;
200 struct dm_iqk_info *iqk_info = &dm->IQK_info;
201
202 if (dm->rf_type == RF_1T1R)
203 path_num = 0x1;
204 else if (dm->rf_type == RF_2T2R)
205 path_num = 0x2;
206 else
207 path_num = 0x4;
208
209 if (*dm->band_width == CHANNEL_WIDTH_20)
210 num = 4;
211 else if (*dm->band_width == CHANNEL_WIDTH_40)
212 num = 6;
213 else
214 num = 10;
215
216 for (path = 0; path < path_num; path++) {
217 switch (xym_type) {
218 case 0:
219 for (i = 0; i < num; i++)
220 RF_DBG(dm, DBG_RF_IQK,
221 "[IQK]%-20s %-2d: 0x%x\n",
222 (path == 0) ? "PATH A RX-XYM " :
223 "PATH B RX-XYM", i,
224 iqk_info->rx_xym[path][i]);
225 break;
226 case 1:
227 for (i = 0; i < num; i++)
228 RF_DBG(dm, DBG_RF_IQK,
229 "[IQK]%-20s %-2d: 0x%x\n",
230 (path == 0) ? "PATH A TX-XYM " :
231 "PATH B TX-XYM", i,
232 iqk_info->tx_xym[path][i]);
233 break;
234 case 2:
235 for (i = 0; i < 6; i++)
236 RF_DBG(dm, DBG_RF_IQK,
237 "[IQK]%-20s %-2d: 0x%x\n",
238 (path == 0) ? "PATH A GS1-XYM " :
239 "PATH B GS1-XYM", i,
240 iqk_info->gs1_xym[path][i]);
241 break;
242 case 3:
243 for (i = 0; i < 6; i++)
244 RF_DBG(dm, DBG_RF_IQK,
245 "[IQK]%-20s %-2d: 0x%x\n",
246 (path == 0) ? "PATH A GS2-XYM " :
247 "PATH B GS2-XYM", i,
248 iqk_info->gs2_xym[path][i]);
249 break;
250 case 4:
251 for (i = 0; i < 6; i++)
252 RF_DBG(dm, DBG_RF_IQK,
253 "[IQK]%-20s %-2d: 0x%x\n",
254 (path == 0) ? "PATH A RXK1-XYM " :
255 "PATH B RXK1-XYM", i,
256 iqk_info->rxk1_xym[path][i]);
257 break;
258 }
259 }
260 }
261
halrf_iqk_xym_dump(void * dm_void)262 void halrf_iqk_xym_dump(void *dm_void)
263 {
264 u32 tmp1, tmp2;
265 struct dm_struct *dm = (struct dm_struct *)dm_void;
266
267 odm_write_4byte(dm, 0x1b00, 0xf8000008);
268 tmp1 = odm_read_4byte(dm, 0x1b1c);
269 odm_write_4byte(dm, 0x1b00, 0xf800000a);
270 tmp2 = odm_read_4byte(dm, 0x1b1c);
271 #if 0
272 /*halrf_iqk_xym_read(dm, xym_type);*/
273 #endif
274 odm_write_4byte(dm, 0x1b00, 0xf8000008);
275 odm_write_4byte(dm, 0x1b1c, tmp1);
276 odm_write_4byte(dm, 0x1b00, 0xf800000a);
277 odm_write_4byte(dm, 0x1b1c, tmp2);
278 _iqk_page_switch(dm);
279 }
280 #endif
halrf_iqk_info_dump(void * dm_void,u32 * _used,char * output,u32 * _out_len)281 void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
282 {
283 struct dm_struct *dm = (struct dm_struct *)dm_void;
284 u32 used = *_used;
285 u32 out_len = *_out_len;
286 u8 rf_path, j, reload_iqk = 0;
287 u32 tmp;
288 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
289 boolean iqk_result[2][NUM][2];
290 struct dm_iqk_info *iqk_info = &dm->IQK_info;
291
292 if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))
293 return;
294
295 /* IQK INFO */
296 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
297 "% IQK Info %");
298 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
299 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
300 "Driver-IQK");
301
302 reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
303 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
304 "reload", (reload_iqk) ? "True" : "False");
305
306 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
307 "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
308 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
309 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
310 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
311 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
312 "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
313 #endif
314
315 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n",
316 "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
317
318 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n",
319 "channel", *dm->channel);
320
321 if (*dm->band_width == CHANNEL_WIDTH_20)
322 PDM_SNPF(out_len, used, output + used, out_len - used,
323 "%-20s: %s\n", "bandwidth", "BW_20");
324 else if (*dm->band_width == CHANNEL_WIDTH_40)
325 PDM_SNPF(out_len, used, output + used, out_len - used,
326 "%-20s: %s\n", "bandwidth", "BW_40");
327 else if (*dm->band_width == CHANNEL_WIDTH_80)
328 PDM_SNPF(out_len, used, output + used, out_len - used,
329 "%-20s: %s\n", "bandwidth", "BW_80");
330 else if (*dm->band_width == CHANNEL_WIDTH_160)
331 PDM_SNPF(out_len, used, output + used, out_len - used,
332 "%-20s: %s\n", "bandwidth", "BW_160");
333 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
334 PDM_SNPF(out_len, used, output + used, out_len - used,
335 "%-20s: %s\n", "bandwidth", "BW_80_80");
336 else
337 PDM_SNPF(out_len, used, output + used, out_len - used,
338 "%-20s: %s\n", "bandwidth", "BW_UNKNOWN");
339
340 PDM_SNPF(out_len, used, output + used, out_len - used,
341 "%-20s: %llu %s\n", "progressing_time",
342 dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
343
344 tmp = odm_read_4byte(dm, 0x1bf0);
345 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
346 for (j = 0; j < 2; j++)
347 iqk_result[0][rf_path][j] = (boolean)
348 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
349
350 PDM_SNPF(out_len, used, output + used, out_len - used,
351 "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
352 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
353 "PATH_A-Tx result",
354 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
355 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
356 "PATH_A-Rx result",
357 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
358 #if (RTL8822B_SUPPORT == 1)
359 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
360 "PATH_B-Tx result",
361 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
362 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
363 "PATH_B-Rx result",
364 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
365 #endif
366 *_used = used;
367 *_out_len = out_len;
368 }
369
halrf_get_fw_version(void * dm_void)370 void halrf_get_fw_version(void *dm_void)
371 {
372 struct dm_struct *dm = (struct dm_struct *)dm_void;
373 struct _hal_rf_ *rf = &dm->rf_table;
374
375 rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;
376 }
377
halrf_iqk_dbg(void * dm_void)378 void halrf_iqk_dbg(void *dm_void)
379 {
380 struct dm_struct *dm = (struct dm_struct *)dm_void;
381 u8 rf_path, j;
382 u32 tmp;
383 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
384 boolean iqk_result[2][NUM][2];
385 struct dm_iqk_info *iqk_info = &dm->IQK_info;
386 struct _hal_rf_ *rf = &dm->rf_table;
387
388 /* IQK INFO */
389 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
390
391 RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
392 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
393 "Driver-IQK");
394
395 if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
396 halrf_get_fw_version(dm);
397 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver);
398 } else {
399 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER);
400 }
401
402 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload",
403 (iqk_info->is_reload) ? "True" : "False");
404
405 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
406 dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
407
408 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel);
409
410 if (*dm->band_width == CHANNEL_WIDTH_20)
411 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20");
412 else if (*dm->band_width == CHANNEL_WIDTH_40)
413 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40");
414 else if (*dm->band_width == CHANNEL_WIDTH_80)
415 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80");
416 else if (*dm->band_width == CHANNEL_WIDTH_160)
417 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160");
418 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
419 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80_80");
420 else
421 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth",
422 "BW_UNKNOWN");
423 #if 0
424 /*
425 * RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n",
426 * "progressing_time",
427 * dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
428 */
429 #endif
430 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden",
431 (iqk_info->rfk_forbidden) ? "True" : "False");
432 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
433 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
434 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
435 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
436 (iqk_info->segment_iqk) ? "True" : "False");
437 #endif
438
439 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
440 dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
441
442 tmp = odm_read_4byte(dm, 0x1bf0);
443 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
444 for (j = 0; j < 2; j++)
445 iqk_result[0][rf_path][j] = (boolean)
446 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
447
448 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
449 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8",
450 odm_read_4byte(dm, 0x1be8));
451 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result",
452 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
453 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result",
454 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
455 #if (RTL8822B_SUPPORT == 1)
456 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result",
457 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
458 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result",
459 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
460 #endif
461 }
462
halrf_lck_dbg(struct dm_struct * dm)463 void halrf_lck_dbg(struct dm_struct *dm)
464 {
465 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======");
466 #if 0
467 /*RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
468 * (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));
469 */
470 #endif
471 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
472 dm->rf_calibrate_info.lck_progressing_time, "(ms)");
473 }
phydm_get_iqk_cfir(void * dm_void,u8 idx,u8 path,boolean debug)474 void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)
475 {
476 struct dm_struct *dm = (struct dm_struct *)dm_void;
477
478 switch (dm->support_ic_type) {
479 #if (RTL8822B_SUPPORT == 1)
480 case ODM_RTL8822B:
481 phy_get_iqk_cfir_8822b(dm, idx, path, debug);
482 break;
483 #endif
484 #if (RTL8822C_SUPPORT == 1)
485 case ODM_RTL8822C:
486 phy_get_iqk_cfir_8822c(dm, idx, path, debug);
487 break;
488 #endif
489 #if (RTL8814B_SUPPORT == 1)
490 case ODM_RTL8814B:
491 phy_get_iqk_cfir_8814b(dm, idx, path, debug);
492 break;
493 #endif
494 default:
495 break;
496 }
497 }
498
499
halrf_iqk_dbg_cfir_backup(void * dm_void)500 void halrf_iqk_dbg_cfir_backup(void *dm_void)
501 {
502 struct dm_struct *dm = (struct dm_struct *)dm_void;
503 struct dm_iqk_info *iqk_info = &dm->IQK_info;
504 u8 path, idx, i;
505
506 switch (dm->support_ic_type) {
507 #if (RTL8822B_SUPPORT == 1)
508 case ODM_RTL8822B:
509 phy_iqk_dbg_cfir_backup_8822b(dm);
510 break;
511 #endif
512 #if (RTL8822C_SUPPORT == 1)
513 case ODM_RTL8822C:
514 phy_iqk_dbg_cfir_backup_8822c(dm);
515 break;
516 #endif
517 #if (RTL8814B_SUPPORT == 1)
518 case ODM_RTL8814B:
519 phy_iqk_dbg_cfir_backup_8814b(dm);
520 break;
521 #endif
522 default:
523 break;
524 }
525
526 }
527
halrf_iqk_dbg_cfir_backup_update(void * dm_void)528 void halrf_iqk_dbg_cfir_backup_update(void *dm_void)
529 {
530 struct dm_struct *dm = (struct dm_struct *)dm_void;
531 struct dm_iqk_info *iqk = &dm->IQK_info;
532 u8 i, path, idx;
533 u32 bmask13_12 = BIT(13) | BIT(12);
534 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
535 u32 data;
536
537 switch (dm->support_ic_type) {
538 #if (RTL8822B_SUPPORT == 1)
539 case ODM_RTL8822B:
540 phy_iqk_dbg_cfir_backup_update_8822b(dm);
541 break;
542 #endif
543 #if (RTL8822C_SUPPORT == 1)
544 case ODM_RTL8822C:
545 phy_iqk_dbg_cfir_backup_update_8822c(dm);
546 break;
547 #endif
548 default:
549 break;
550 }
551 }
552
halrf_iqk_dbg_cfir_reload(void * dm_void)553 void halrf_iqk_dbg_cfir_reload(void *dm_void)
554 {
555 struct dm_struct *dm = (struct dm_struct *)dm_void;
556 struct dm_iqk_info *iqk = &dm->IQK_info;
557 u8 i, path, idx;
558 u32 bmask13_12 = BIT(13) | BIT(12);
559 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
560 u32 data;
561
562 switch (dm->support_ic_type) {
563 #if (RTL8822B_SUPPORT == 1)
564 case ODM_RTL8822B:
565 phy_iqk_dbg_cfir_reload_8822b(dm);
566 break;
567 #endif
568 #if (RTL8822C_SUPPORT == 1)
569 case ODM_RTL8822C:
570 phy_iqk_dbg_cfir_reload_8822c(dm);
571 break;
572 #endif
573 default:
574 break;
575 }
576 }
577
halrf_iqk_dbg_cfir_write(void * dm_void,u8 type,u32 path,u32 idx,u32 i,u32 data)578 void halrf_iqk_dbg_cfir_write(void *dm_void, u8 type, u32 path, u32 idx,
579 u32 i, u32 data)
580 {
581 struct dm_struct *dm = (struct dm_struct *)dm_void;
582 struct dm_iqk_info *iqk_info = &dm->IQK_info;
583
584 switch (dm->support_ic_type) {
585 #if (RTL8822B_SUPPORT == 1)
586 case ODM_RTL8822B:
587 phy_iqk_dbg_cfir_write_8822b(dm, type, path, idx, i, data);
588 break;
589 #endif
590 #if (RTL8822C_SUPPORT == 1)
591 case ODM_RTL8822C:
592 phy_iqk_dbg_cfir_write_8822c(dm, type, path, idx, i, data);
593 break;
594 #endif
595 default:
596 break;
597 }
598 }
599
halrf_iqk_dbg_cfir_backup_show(void * dm_void)600 void halrf_iqk_dbg_cfir_backup_show(void *dm_void)
601 {
602 struct dm_struct *dm = (struct dm_struct *)dm_void;
603 struct dm_iqk_info *iqk_info = &dm->IQK_info;
604 u8 path, idx, i;
605
606 switch (dm->support_ic_type) {
607 #if (RTL8822B_SUPPORT == 1)
608 case ODM_RTL8822B:
609 phy_iqk_dbg_cfir_backup_8822b(dm);
610 break;
611 #endif
612 #if (RTL8822C_SUPPORT == 1)
613 case ODM_RTL8822C:
614 phy_iqk_dbg_cfir_backup_8822c(dm);
615 break;
616 #endif
617 default:
618 break;
619 }
620 }
621
halrf_do_imr_test(void * dm_void,u8 flag_imr_test)622 void halrf_do_imr_test(void *dm_void, u8 flag_imr_test)
623 {
624 struct dm_struct *dm = (struct dm_struct *)dm_void;
625
626 if (flag_imr_test != 0x0)
627 switch (dm->support_ic_type) {
628 #if (RTL8822B_SUPPORT == 1)
629 case ODM_RTL8822B:
630 do_imr_test_8822b(dm);
631 break;
632 #endif
633 #if (RTL8821C_SUPPORT == 1)
634 case ODM_RTL8821C:
635 do_imr_test_8821c(dm);
636 break;
637 #endif
638 default:
639 break;
640 }
641 }
642
643 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
halrf_iqk_debug(void * dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)644 void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
645 char *output, u32 *_out_len)
646 {
647 struct dm_struct *dm = (struct dm_struct *)dm_void;
648
649 #if 0
650 /*dm_value[0]=0x0: backup from SRAM & show*/
651 /*dm_value[0]=0x1: write backup CFIR to SRAM*/
652 /*dm_value[0]=0x2: reload default CFIR to SRAM*/
653 /*dm_value[0]=0x3: show backup*/
654 /*dm_value[0]=0x10: write backup CFIR real part*/
655 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
656 /*dm_value[0]=0x11: write backup CFIR imag*/
657 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
658 /*dm_value[0]=0x20 :xym_read enable*/
659 /*--> dm_value[1]:0:disable, 1:enable*/
660 /*if dm_value[0]=0x20 = enable, */
661 /*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
662 #endif
663 if (dm_value[0] == 0x0)
664 halrf_iqk_dbg_cfir_backup(dm);
665 else if (dm_value[0] == 0x1)
666 halrf_iqk_dbg_cfir_backup_update(dm);
667 else if (dm_value[0] == 0x2)
668 halrf_iqk_dbg_cfir_reload(dm);
669 else if (dm_value[0] == 0x3)
670 halrf_iqk_dbg_cfir_backup_show(dm);
671 else if (dm_value[0] == 0x10)
672 halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],
673 dm_value[3], dm_value[4]);
674 else if (dm_value[0] == 0x11)
675 halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],
676 dm_value[3], dm_value[4]);
677 else if (dm_value[0] == 0x20)
678 halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
679 else if (dm_value[0] == 0x21)
680 halrf_iqk_xym_show(dm, (u8)dm_value[1]);
681 else if (dm_value[0] == 0x30)
682 halrf_do_imr_test(dm, (u8)dm_value[1]);
683 }
684 #endif
685
halrf_iqk_hwtx_check(void * dm_void,boolean is_check)686 void halrf_iqk_hwtx_check(void *dm_void, boolean is_check)
687 {
688 #if 0
689 struct dm_struct *dm = (struct dm_struct *)dm_void;
690 struct dm_iqk_info *iqk_info = &dm->IQK_info;
691 u32 tmp_b04;
692
693 if (is_check) {
694 iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));
695 } else {
696 if (iqk_info->is_hwtx) {
697 tmp_b04 = odm_read_4byte(dm, 0xb04);
698 odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);
699 odm_write_4byte(dm, 0xb04, tmp_b04);
700 }
701 }
702 #endif
703 }
704 #endif
705
halrf_match_iqk_version(void * dm_void)706 u8 halrf_match_iqk_version(void *dm_void)
707 {
708 struct dm_struct *dm = (struct dm_struct *)dm_void;
709
710 u32 iqk_version = 0;
711 char temp[10] = {0};
712
713 odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));
714 PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
715
716 if (dm->support_ic_type == ODM_RTL8822B) {
717 if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))
718 return 1;
719 else if ((iqk_version <= 0x23) &&
720 (odm_get_hw_img_version(dm) <= 71))
721 return 1;
722 else
723 return 0;
724 }
725
726 if (dm->support_ic_type == ODM_RTL8821C) {
727 if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))
728 return 1;
729 else
730 return 0;
731 }
732
733 return 1;
734 }
735
halrf_rf_lna_setting(void * dm_void,enum halrf_lna_set type)736 void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)
737 {
738 struct dm_struct *dm = (struct dm_struct *)dm_void;
739
740 switch (dm->support_ic_type) {
741 #if (RTL8188E_SUPPORT == 1)
742 case ODM_RTL8188E:
743 halrf_rf_lna_setting_8188e(dm, type);
744 break;
745 #endif
746 #if (RTL8192E_SUPPORT == 1)
747 case ODM_RTL8192E:
748 halrf_rf_lna_setting_8192e(dm, type);
749 break;
750 #endif
751 #if (RTL8192F_SUPPORT == 1)
752 case ODM_RTL8192F:
753 halrf_rf_lna_setting_8192f(dm, type);
754 break;
755 #endif
756
757 #if (RTL8723B_SUPPORT == 1)
758 case ODM_RTL8723B:
759 halrf_rf_lna_setting_8723b(dm, type);
760 break;
761 #endif
762 #if (RTL8812A_SUPPORT == 1)
763 case ODM_RTL8812:
764 halrf_rf_lna_setting_8812a(dm, type);
765 break;
766 #endif
767 #if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
768 case ODM_RTL8881A:
769 case ODM_RTL8821:
770 halrf_rf_lna_setting_8821a(dm, type);
771 break;
772 #endif
773 #if (RTL8822B_SUPPORT == 1)
774 case ODM_RTL8822B:
775 halrf_rf_lna_setting_8822b(dm_void, type);
776 break;
777 #endif
778 #if (RTL8822C_SUPPORT == 1)
779 case ODM_RTL8822C:
780 halrf_rf_lna_setting_8822c(dm_void, type);
781 break;
782 #endif
783 #if (RTL8812F_SUPPORT == 1)
784 case ODM_RTL8812F:
785 halrf_rf_lna_setting_8812f(dm_void, type);
786 break;
787 #endif
788 #if (RTL8821C_SUPPORT == 1)
789 case ODM_RTL8821C:
790 halrf_rf_lna_setting_8821c(dm_void, type);
791 break;
792 #endif
793 #if (RTL8710C_SUPPORT == 1)
794 case ODM_RTL8710C:
795 halrf_rf_lna_setting_8710c(dm_void, type);
796 break;
797 #endif
798 #if (RTL8721D_SUPPORT == 1)
799 case ODM_RTL8721D:
800 halrf_rf_lna_setting_8721d(dm, type);
801 break;
802 #endif
803 #if (RTL8814B_SUPPORT == 1)
804 case ODM_RTL8814B:
805 break;
806 #endif
807 default:
808 break;
809 }
810 }
811
halrf_support_ability_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)812 void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
813 char *output, u32 *_out_len)
814 {
815 struct dm_struct *dm = (struct dm_struct *)dm_void;
816 struct _hal_rf_ *rf = &dm->rf_table;
817 u32 dm_value[10] = {0};
818 u32 used = *_used;
819 u32 out_len = *_out_len;
820 u8 i;
821
822 for (i = 0; i < 5; i++)
823 if (input[i + 1])
824 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
825
826 if (dm_value[0] == 100) {
827 PDM_SNPF(out_len, used, output + used, out_len - used,
828 "\n[RF Supportability]\n");
829 PDM_SNPF(out_len, used, output + used, out_len - used,
830 "00. (( %s ))Power Tracking\n",
831 ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?
832 ("V") : (".")));
833 PDM_SNPF(out_len, used, output + used, out_len - used,
834 "01. (( %s ))IQK\n",
835 ((rf->rf_supportability & HAL_RF_IQK) ? ("V") :
836 (".")));
837 PDM_SNPF(out_len, used, output + used, out_len - used,
838 "02. (( %s ))LCK\n",
839 ((rf->rf_supportability & HAL_RF_LCK) ? ("V") :
840 (".")));
841 PDM_SNPF(out_len, used, output + used, out_len - used,
842 "03. (( %s ))DPK\n",
843 ((rf->rf_supportability & HAL_RF_DPK) ? ("V") :
844 (".")));
845 PDM_SNPF(out_len, used, output + used, out_len - used,
846 "04. (( %s ))HAL_RF_TXGAPK\n",
847 ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") :
848 (".")));
849 PDM_SNPF(out_len, used, output + used, out_len - used,
850 "05. (( %s ))HAL_RF_DACK\n",
851 ((rf->rf_supportability & HAL_RF_DACK) ? ("V") :
852 (".")));
853 PDM_SNPF(out_len, used, output + used, out_len - used,
854 "06. (( %s ))DPK_TRACK\n",
855 ((rf->rf_supportability & HAL_RF_DPK_TRACK) ? ("V") :
856 (".")));
857 #ifdef CONFIG_2G_BAND_SHIFT
858 PDM_SNPF(out_len, used, output + used, out_len - used,
859 "07. (( %s ))HAL_2GBAND_SHIFT\n",
860 ((rf->rf_supportability & HAL_2GBAND_SHIFT) ? ("V") :
861 (".")));
862 #endif
863 PDM_SNPF(out_len, used, output + used, out_len - used,
864 "08. (( %s ))HAL_RF_RXDCK\n",
865 ((rf->rf_supportability & HAL_RF_RXDCK) ? ("V") :
866 (".")));
867
868 } else {
869 if (dm_value[1] == 1) /* enable */
870 rf->rf_supportability |= BIT(dm_value[0]);
871 else if (dm_value[1] == 2) /* disable */
872 rf->rf_supportability &= ~(BIT(dm_value[0]));
873 else
874 PDM_SNPF(out_len, used, output + used, out_len - used,
875 "[Warning!!!] 1:enable, 2:disable\n");
876 }
877 PDM_SNPF(out_len, used, output + used, out_len - used,
878 "\nCurr-RF_supportability = 0x%x\n\n", rf->rf_supportability);
879
880 *_used = used;
881 *_out_len = out_len;
882 }
883
884 #ifdef CONFIG_2G_BAND_SHIFT
halrf_support_band_shift_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)885 void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
886 char *output, u32 *_out_len)
887 {
888 struct dm_struct *dm = (struct dm_struct *)dm_void;
889 struct _hal_rf_ *rf = &dm->rf_table;
890 //u32 band_value[2] = {00};
891 u32 dm_value[10] = {0};
892 u32 used = *_used;
893 u32 out_len = *_out_len;
894 u8 i;
895
896 #if (RTL8192F_SUPPORT == 1)
897 for (i = 0; i < 7; i++)
898 if (input[i + 1])
899 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
900
901 if (!(rf->rf_supportability & HAL_2GBAND_SHIFT)) {
902 PDM_SNPF(out_len, used, output + used, out_len - used,
903 "\nCurr-RF_supportability[07. (( . ))HAL_2GBAND_SHIFT]\nNo RF Band Shift,default: 2.4G!\n");
904 } else {
905 if (dm_value[0] == 01) {
906 rf->rf_shift_band = HAL_RF_2P3;
907 halrf_lck_trigger(dm);
908 PDM_SNPF(out_len, used, output + used, out_len - used,
909 "\n[rf_shift_band] = %d\nRF Band Shift to 2.3G!\n",
910 rf->rf_shift_band);
911 } else if (dm_value[0] == 02) {
912 rf->rf_shift_band = HAL_RF_2P5;
913 halrf_lck_trigger(dm);
914 PDM_SNPF(out_len, used, output + used, out_len - used,
915 "\n[rf_shift_band] = %d\nRF Band Shift to 2.5G!\n",
916 rf->rf_shift_band);
917 } else {
918 rf->rf_shift_band = HAL_RF_2P4;
919 halrf_lck_trigger(dm);
920 PDM_SNPF(out_len, used, output + used, out_len - used,
921 "\n[rf_shift_band] = %d\nNo RF Band Shift,default: 2.4G!\n",
922 rf->rf_shift_band);
923 }
924 }
925 *_used = used;
926 *_out_len = out_len;
927 #endif
928 }
929 #endif
930
halrf_cmn_info_init(void * dm_void,enum halrf_cmninfo_init cmn_info,u32 value)931 void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
932 u32 value)
933 {
934 struct dm_struct *dm = (struct dm_struct *)dm_void;
935 struct _hal_rf_ *rf = &dm->rf_table;
936
937 switch (cmn_info) {
938 case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
939 rf->eeprom_thermal = (u8)value;
940 break;
941 case HALRF_CMNINFO_PWT_TYPE:
942 rf->pwt_type = (u8)value;
943 break;
944 case HALRF_CMNINFO_MP_POWER_TRACKING_TYPE:
945 rf->mp_pwt_type = (u8)value;
946 break;
947 default:
948 break;
949 }
950 }
951
halrf_cmn_info_hook(void * dm_void,enum halrf_cmninfo_hook cmn_info,void * value)952 void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
953 void *value)
954 {
955 struct dm_struct *dm = (struct dm_struct *)dm_void;
956 struct _hal_rf_ *rf = &dm->rf_table;
957
958 switch (cmn_info) {
959 case HALRF_CMNINFO_CON_TX:
960 rf->is_con_tx = (boolean *)value;
961 break;
962 case HALRF_CMNINFO_SINGLE_TONE:
963 rf->is_single_tone = (boolean *)value;
964 break;
965 case HALRF_CMNINFO_CARRIER_SUPPRESSION:
966 rf->is_carrier_suppresion = (boolean *)value;
967 break;
968 case HALRF_CMNINFO_MP_RATE_INDEX:
969 rf->mp_rate_index = (u8 *)value;
970 break;
971 case HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY:
972 rf->manual_rf_supportability = (u32 *)value;
973 break;
974 default:
975 /*do nothing*/
976 break;
977 }
978 }
979
halrf_cmn_info_set(void * dm_void,u32 cmn_info,u64 value)980 void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)
981 {
982 /* This init variable may be changed in run time. */
983 struct dm_struct *dm = (struct dm_struct *)dm_void;
984 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
985 struct _hal_rf_ *rf = &dm->rf_table;
986
987 switch (cmn_info) {
988 case HALRF_CMNINFO_ABILITY:
989 rf->rf_supportability = (u32)value;
990 break;
991
992 case HALRF_CMNINFO_DPK_EN:
993 rf->dpk_en = (u8)value;
994 break;
995 case HALRF_CMNINFO_RFK_FORBIDDEN:
996 dm->IQK_info.rfk_forbidden = (boolean)value;
997 break;
998 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
999 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1000 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
1001 case HALRF_CMNINFO_IQK_SEGMENT:
1002 dm->IQK_info.segment_iqk = (boolean)value;
1003 break;
1004 #endif
1005 case HALRF_CMNINFO_RATE_INDEX:
1006 rf->p_rate_index = (u32)value;
1007 break;
1008 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
1009 case HALRF_CMNINFO_MP_PSD_POINT:
1010 rf->halrf_psd_data.point = (u32)value;
1011 break;
1012 case HALRF_CMNINFO_MP_PSD_START_POINT:
1013 rf->halrf_psd_data.start_point = (u32)value;
1014 break;
1015 case HALRF_CMNINFO_MP_PSD_STOP_POINT:
1016 rf->halrf_psd_data.stop_point = (u32)value;
1017 break;
1018 case HALRF_CMNINFO_MP_PSD_AVERAGE:
1019 rf->halrf_psd_data.average = (u32)value;
1020 break;
1021 #endif
1022 case HALRF_CMNINFO_POWER_TRACK_CONTROL:
1023 cali_info->txpowertrack_control = (u8)value;
1024 break;
1025 default:
1026 /* do nothing */
1027 break;
1028 }
1029 }
1030
halrf_cmn_info_get(void * dm_void,u32 cmn_info)1031 u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)
1032 {
1033 /* This init variable may be changed in run time. */
1034 struct dm_struct *dm = (struct dm_struct *)dm_void;
1035 struct _hal_rf_ *rf = &dm->rf_table;
1036 u64 return_value = 0;
1037
1038 switch (cmn_info) {
1039 case HALRF_CMNINFO_ABILITY:
1040 return_value = (u32)rf->rf_supportability;
1041 break;
1042 case HALRF_CMNINFO_RFK_FORBIDDEN:
1043 return_value = dm->IQK_info.rfk_forbidden;
1044 break;
1045 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
1046 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1047 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
1048 case HALRF_CMNINFO_IQK_SEGMENT:
1049 return_value = dm->IQK_info.segment_iqk;
1050 break;
1051 case HALRF_CMNINFO_IQK_TIMES:
1052 return_value = dm->IQK_info.iqk_times;
1053 break;
1054 #endif
1055 default:
1056 /* do nothing */
1057 break;
1058 }
1059
1060 return return_value;
1061 }
1062
halrf_supportability_init_mp(void * dm_void)1063 void halrf_supportability_init_mp(void *dm_void)
1064 {
1065 struct dm_struct *dm = (struct dm_struct *)dm_void;
1066 struct _hal_rf_ *rf = &dm->rf_table;
1067
1068 switch (dm->support_ic_type) {
1069 case ODM_RTL8814B:
1070 #if (RTL8814B_SUPPORT == 1)
1071 rf->rf_supportability =
1072 /*HAL_RF_TX_PWR_TRACK |*/
1073 HAL_RF_IQK |
1074 HAL_RF_LCK |
1075 HAL_RF_DPK |
1076 HAL_RF_DACK |
1077 /*HAL_RF_TXGAPK |*/
1078 HAL_RF_DPK_TRACK |
1079 0;
1080 #endif
1081 break;
1082 #if (RTL8822B_SUPPORT == 1)
1083 case ODM_RTL8822B:
1084 rf->rf_supportability =
1085 /*HAL_RF_TX_PWR_TRACK |*/
1086 HAL_RF_IQK |
1087 HAL_RF_LCK |
1088 /*@HAL_RF_DPK |*/
1089 0;
1090 break;
1091 #endif
1092 #if (RTL8822C_SUPPORT == 1)
1093 case ODM_RTL8822C:
1094 rf->rf_supportability =
1095 /*HAL_RF_TX_PWR_TRACK |*/
1096 HAL_RF_IQK |
1097 HAL_RF_LCK |
1098 HAL_RF_DPK |
1099 HAL_RF_DACK |
1100 HAL_RF_DPK_TRACK |
1101 HAL_RF_RXDCK |
1102 HAL_RF_TXGAPK |
1103 0;
1104 break;
1105 #endif
1106 #if (RTL8821C_SUPPORT == 1)
1107 case ODM_RTL8821C:
1108 rf->rf_supportability =
1109 /*HAL_RF_TX_PWR_TRACK |*/
1110 HAL_RF_IQK |
1111 HAL_RF_LCK |
1112 /*@HAL_RF_DPK |*/
1113 /*@HAL_RF_TXGAPK |*/
1114 0;
1115 break;
1116 #endif
1117 #if (RTL8195B_SUPPORT == 1)
1118 case ODM_RTL8195B:
1119 rf->rf_supportability =
1120 /*HAL_RF_TX_PWR_TRACK |*/
1121 HAL_RF_IQK |
1122 HAL_RF_LCK |
1123 HAL_RF_DPK |
1124 /*HAL_RF_TXGAPK |*/
1125 HAL_RF_DPK_TRACK |
1126 0;
1127 break;
1128 #endif
1129 #if (RTL8812F_SUPPORT == 1)
1130 case ODM_RTL8812F:
1131 rf->rf_supportability =
1132 /*HAL_RF_TX_PWR_TRACK |*/
1133 HAL_RF_IQK |
1134 HAL_RF_LCK |
1135 HAL_RF_DPK |
1136 HAL_RF_DACK |
1137 HAL_RF_DPK_TRACK |
1138 0;
1139 break;
1140 #endif
1141
1142 #if (RTL8198F_SUPPORT == 1)
1143 case ODM_RTL8198F:
1144 rf->rf_supportability =
1145 /*HAL_RF_TX_PWR_TRACK |*/
1146 HAL_RF_IQK |
1147 HAL_RF_LCK |
1148 HAL_RF_DPK |
1149 /*@HAL_RF_TXGAPK |*/
1150 0;
1151 break;
1152 #endif
1153
1154 #if (RTL8192F_SUPPORT == 1)
1155 case ODM_RTL8192F:
1156 rf->rf_supportability =
1157 /*HAL_RF_TX_PWR_TRACK |*/
1158 HAL_RF_IQK |
1159 HAL_RF_LCK |
1160 HAL_RF_DPK |
1161 /*@HAL_RF_TXGAPK |*/
1162 #ifdef CONFIG_2G_BAND_SHIFT
1163 /*@HAL_2GBAND_SHIFT |*/
1164 #endif
1165 0;
1166 break;
1167 #endif
1168
1169 #if (RTL8197F_SUPPORT == 1)
1170 case ODM_RTL8197F:
1171 rf->rf_supportability =
1172 /*HAL_RF_TX_PWR_TRACK |*/
1173 HAL_RF_IQK |
1174 HAL_RF_LCK |
1175 HAL_RF_DPK |
1176 /*@HAL_RF_TXGAPK |*/
1177 0;
1178 break;
1179 #endif
1180 #if (RTL8197G_SUPPORT == 1)
1181 case ODM_RTL8197G:
1182 rf->rf_supportability =
1183 /*HAL_RF_TX_PWR_TRACK |*/
1184 HAL_RF_IQK |
1185 /*HAL_RF_LCK |*/
1186 HAL_RF_DPK |
1187 /*@HAL_RF_TXGAPK |*/
1188 HAL_RF_DPK_TRACK |
1189 0;
1190 break;
1191 #endif
1192 #if (RTL8721D_SUPPORT == 1)
1193 case ODM_RTL8721D:
1194 rf->rf_supportability =
1195 HAL_RF_TX_PWR_TRACK |
1196 HAL_RF_IQK |
1197 HAL_RF_LCK |
1198 HAL_RF_DPK |
1199 HAL_RF_DPK_TRACK |
1200 /*@HAL_RF_TXGAPK |*/
1201 0;
1202 break;
1203 #endif
1204 #if (RTL8723F_SUPPORT == 1)
1205 case ODM_RTL8723F:
1206 rf->rf_supportability =
1207 HAL_RF_TX_PWR_TRACK |
1208 HAL_RF_IQK |
1209 HAL_RF_LCK |
1210 HAL_RF_DPK |
1211 HAL_RF_TXGAPK |
1212 HAL_RF_DPK_TRACK |
1213 0;
1214 break;
1215 #endif
1216
1217 default:
1218 rf->rf_supportability =
1219 /*HAL_RF_TX_PWR_TRACK |*/
1220 HAL_RF_IQK |
1221 HAL_RF_LCK |
1222 /*@HAL_RF_DPK |*/
1223 /*@HAL_RF_TXGAPK |*/
1224 0;
1225 break;
1226 }
1227
1228 RF_DBG(dm, DBG_RF_INIT,
1229 "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n",
1230 dm->support_ic_type, rf->rf_supportability);
1231 }
1232
halrf_supportability_init(void * dm_void)1233 void halrf_supportability_init(void *dm_void)
1234 {
1235 struct dm_struct *dm = (struct dm_struct *)dm_void;
1236 struct _hal_rf_ *rf = &dm->rf_table;
1237
1238 switch (dm->support_ic_type) {
1239 case ODM_RTL8814B:
1240 #if (RTL8814B_SUPPORT == 1)
1241 rf->rf_supportability =
1242 HAL_RF_TX_PWR_TRACK |
1243 HAL_RF_IQK |
1244 HAL_RF_LCK |
1245 HAL_RF_DPK |
1246 HAL_RF_DACK |
1247 HAL_RF_DPK_TRACK |
1248 0;
1249 #endif
1250 break;
1251 #if (RTL8822B_SUPPORT == 1)
1252 case ODM_RTL8822B:
1253 rf->rf_supportability =
1254 HAL_RF_TX_PWR_TRACK |
1255 HAL_RF_IQK |
1256 HAL_RF_LCK |
1257 /*@HAL_RF_DPK |*/
1258 0;
1259 break;
1260 #endif
1261 #if (RTL8822C_SUPPORT == 1)
1262 case ODM_RTL8822C:
1263 rf->rf_supportability =
1264 HAL_RF_TX_PWR_TRACK |
1265 HAL_RF_IQK |
1266 HAL_RF_LCK |
1267 HAL_RF_DPK |
1268 HAL_RF_DACK |
1269 HAL_RF_DPK_TRACK |
1270 HAL_RF_RXDCK |
1271 HAL_RF_TXGAPK |
1272 0;
1273 break;
1274 #endif
1275 #if (RTL8821C_SUPPORT == 1)
1276 case ODM_RTL8821C:
1277 rf->rf_supportability =
1278 HAL_RF_TX_PWR_TRACK |
1279 HAL_RF_IQK |
1280 HAL_RF_LCK |
1281 /*@HAL_RF_DPK |*/
1282 /*@HAL_RF_TXGAPK |*/
1283 0;
1284 break;
1285 #endif
1286 #if (RTL8195B_SUPPORT == 1)
1287 case ODM_RTL8195B:
1288 rf->rf_supportability =
1289 HAL_RF_TX_PWR_TRACK |
1290 HAL_RF_IQK |
1291 HAL_RF_LCK |
1292 HAL_RF_DPK |
1293 /*HAL_RF_TXGAPK |*/
1294 HAL_RF_DPK_TRACK |
1295 0;
1296 break;
1297 #endif
1298 #if (RTL8812F_SUPPORT == 1)
1299 case ODM_RTL8812F:
1300 rf->rf_supportability =
1301 HAL_RF_TX_PWR_TRACK |
1302 HAL_RF_IQK |
1303 HAL_RF_LCK |
1304 HAL_RF_DPK |
1305 HAL_RF_DACK |
1306 HAL_RF_DPK_TRACK |
1307 0;
1308 break;
1309 #endif
1310
1311 #if (RTL8198F_SUPPORT == 1)
1312 case ODM_RTL8198F:
1313 rf->rf_supportability =
1314 HAL_RF_TX_PWR_TRACK |
1315 HAL_RF_IQK |
1316 HAL_RF_LCK |
1317 HAL_RF_DPK |
1318 /*@HAL_RF_TXGAPK |*/
1319 0;
1320 break;
1321 #endif
1322
1323 #if (RTL8192F_SUPPORT == 1)
1324 case ODM_RTL8192F:
1325 rf->rf_supportability =
1326 HAL_RF_TX_PWR_TRACK |
1327 HAL_RF_IQK |
1328 HAL_RF_LCK |
1329 HAL_RF_DPK |
1330 /*@HAL_RF_TXGAPK |*/
1331 #ifdef CONFIG_2G_BAND_SHIFT
1332 /*@HAL_2GBAND_SHIFT |*/
1333 #endif
1334 0;
1335 break;
1336 #endif
1337
1338 #if (RTL8197F_SUPPORT == 1)
1339 case ODM_RTL8197F:
1340 rf->rf_supportability =
1341 HAL_RF_TX_PWR_TRACK |
1342 HAL_RF_IQK |
1343 HAL_RF_LCK |
1344 HAL_RF_DPK |
1345 /*@HAL_RF_TXGAPK |*/
1346 0;
1347 break;
1348 #endif
1349 #if (RTL8197G_SUPPORT == 1)
1350 case ODM_RTL8197G:
1351 rf->rf_supportability =
1352 HAL_RF_TX_PWR_TRACK |
1353 HAL_RF_IQK |
1354 /*HAL_RF_LCK |*/
1355 HAL_RF_DPK |
1356 /*@HAL_RF_TXGAPK |*/
1357 HAL_RF_DPK_TRACK |
1358 #ifdef CONFIG_2G_BAND_SHIFT
1359 HAL_2GBAND_SHIFT |
1360 #endif
1361 0;
1362 break;
1363 #endif
1364 #if (RTL8721D_SUPPORT == 1)
1365 case ODM_RTL8721D:
1366 rf->rf_supportability =
1367 HAL_RF_TX_PWR_TRACK |
1368 HAL_RF_IQK |
1369 HAL_RF_LCK |
1370 HAL_RF_DPK |
1371 HAL_RF_DPK_TRACK |
1372 /*@HAL_RF_TXGAPK |*/
1373 0;
1374 break;
1375 #endif
1376 #if (RTL8723F_SUPPORT == 1)
1377 case ODM_RTL8723F:
1378 rf->rf_supportability =
1379 HAL_RF_TX_PWR_TRACK |
1380 HAL_RF_IQK |
1381 HAL_RF_LCK |
1382 HAL_RF_DPK |
1383 HAL_RF_TXGAPK |
1384 HAL_RF_DPK_TRACK |
1385 0;
1386 break;
1387 #endif
1388
1389 default:
1390 rf->rf_supportability =
1391 HAL_RF_TX_PWR_TRACK |
1392 HAL_RF_IQK |
1393 HAL_RF_LCK |
1394 /*@HAL_RF_DPK |*/
1395 0;
1396 break;
1397 }
1398
1399 RF_DBG(dm, DBG_RF_INIT,
1400 "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n",
1401 dm->support_ic_type, rf->rf_supportability);
1402 }
1403
halrf_watchdog(void * dm_void)1404 void halrf_watchdog(void *dm_void)
1405 {
1406 struct dm_struct *dm = (struct dm_struct *)dm_void;
1407 struct _hal_rf_ *rf = &dm->rf_table;
1408 #if 0
1409 /*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/
1410 #endif
1411
1412 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
1413 rf->is_tssi_in_progress)
1414 return;
1415 #if !(RTL8723F_SUPPORT == 1)
1416 phydm_rf_watchdog(dm);
1417 #endif
1418 halrf_dpk_track(dm);
1419 #if (RTL8723F_SUPPORT == 1)
1420 halrf_xtal_thermal_track(dm);
1421 #endif
1422
1423 }
1424
1425 #if 0
1426 void
1427 halrf_iqk_init(
1428 void *dm_void
1429 )
1430 {
1431 struct dm_struct *dm = (struct dm_struct *)dm_void;
1432 struct _hal_rf_ *rf = &dm->rf_table;
1433
1434 switch (dm->support_ic_type) {
1435 #if (RTL8814B_SUPPORT == 1)
1436 case ODM_RTL8814B:
1437 break;
1438 #endif
1439 #if (RTL8822B_SUPPORT == 1)
1440 case ODM_RTL8822B:
1441 _iq_calibrate_8822b_init(dm);
1442 break;
1443 #endif
1444 #if (RTL8822C_SUPPORT == 1)
1445 case ODM_RTL8822C:
1446 _iq_calibrate_8822c_init(dm);
1447 break;
1448 #endif
1449 #if (RTL8821C_SUPPORT == 1)
1450 case ODM_RTL8821C:
1451 break;
1452 #endif
1453
1454 default:
1455 break;
1456 }
1457 }
1458 #endif
1459
halrf_rfk_power_save(void * dm_void,boolean is_power_save)1460 void halrf_rfk_power_save(void *dm_void, boolean is_power_save)
1461 {
1462 struct dm_struct *dm = (struct dm_struct *)dm_void;
1463 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1464
1465 switch (dm->support_ic_type) {
1466 #if (RTL8822C_SUPPORT == 1)
1467 case ODM_RTL8822C:
1468 halrf_rfk_power_save_8822c(dm, is_power_save);
1469 break;
1470 #endif
1471
1472 #if (RTL8723F_SUPPORT == 1)
1473 case ODM_RTL8723F:
1474 halrf_rfk_power_save_8723f(dm, is_power_save);
1475 break;
1476 #endif
1477
1478 default:
1479 break;
1480 }
1481 }
1482
1483
1484
halrf_reload_iqk(void * dm_void,boolean reset)1485 void halrf_reload_iqk(void *dm_void, boolean reset)
1486 {
1487 struct dm_struct *dm = (struct dm_struct *)dm_void;
1488 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1489 u8 i, ch;
1490 u32 tmp;
1491 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
1492
1493 halrf_rfk_power_save(dm, false);
1494 switch (dm->support_ic_type) {
1495 #if (RTL8822C_SUPPORT == 1)
1496 case ODM_RTL8822C:
1497 iqk_reload_iqk_8822c(dm, reset);
1498 break;
1499 #endif
1500 #if (RTL8195B_SUPPORT == 1)
1501 case ODM_RTL8195B:
1502 iqk_reload_iqk_8195b(dm, reset);
1503 break;
1504 #endif
1505
1506 default:
1507 break;
1508 }
1509 halrf_rfk_power_save(dm, true);
1510 }
1511
halrf_rfk_handshake(void * dm_void,boolean is_before_k)1512 void halrf_rfk_handshake(void *dm_void, boolean is_before_k)
1513 {
1514 struct dm_struct *dm = (struct dm_struct *)dm_void;
1515
1516 if (!dm->mp_mode)
1517 return;
1518
1519 if (*dm->mp_mode)
1520 return;
1521
1522 switch (dm->support_ic_type) {
1523 #if (RTL8822C_SUPPORT == 1)
1524 case ODM_RTL8822C:
1525 halrf_rfk_handshake_8822c(dm, is_before_k);
1526 break;
1527 #endif
1528 #if (RTL8710C_SUPPORT == 1)
1529 case ODM_RTL8710C:
1530 halrf_rfk_handshake_8710c(dm, is_before_k);
1531 break;
1532 #endif
1533 #if (RTL8723F_SUPPORT == 1)
1534 case ODM_RTL8723F:
1535 halrf_rfk_handshake_8723f(dm, is_before_k);
1536 break;
1537 #endif
1538 default:
1539 break;
1540 }
1541 }
1542
halrf_bbreset(void * dm_void)1543 void halrf_bbreset(void *dm_void)
1544 {
1545 struct dm_struct *dm = (struct dm_struct *)dm_void;
1546
1547
1548 switch (dm->support_ic_type) {
1549 #if (RTL8814B_SUPPORT == 1)
1550 case ODM_RTL8814B:
1551 phydm_bb_reset_8814b(dm);
1552 break;
1553 #endif
1554 default:
1555 break;
1556 }
1557 }
1558
halrf_rf_k_connect_trigger(void * dm_void,boolean is_recovery,enum halrf_k_segment_time seg_time)1559 void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
1560 enum halrf_k_segment_time seg_time)
1561 {
1562 struct dm_struct *dm = (struct dm_struct *)dm_void;
1563 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1564 struct _hal_rf_ *rf = &dm->rf_table;
1565
1566 if (!dm->mp_mode)
1567 return;
1568
1569 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1570 rf->is_carrier_suppresion) {
1571 if (*dm->mp_mode &
1572 (*rf->is_con_tx || *rf->is_single_tone ||
1573 *rf->is_carrier_suppresion))
1574 return;
1575 }
1576
1577 /*[TX GAP K]*/
1578 halrf_txgapk_trigger(dm);
1579
1580 /*[LOK, IQK]*/
1581 halrf_segment_iqk_trigger(dm, true, seg_time);
1582
1583 /*[TSSI Trk]*/
1584 halrf_tssi_trigger(dm);
1585 /*[DPK]*/
1586 #if 1
1587 if(dpk_info->is_dpk_by_channel == true)
1588 halrf_dpk_trigger(dm);
1589 else
1590 halrf_dpk_reload(dm);
1591 #endif
1592 //ADDA restore to MP_UI setting;
1593 config_halrf_path_adda_setting_trigger(dm);
1594
1595 #if (RTL8723F_SUPPORT == 1)
1596 halrf_spur_compensation_8723f(dm);
1597 #endif
1598 halrf_bbreset(dm);
1599 }
1600
config_halrf_path_adda_setting_trigger(void * dm_void)1601 void config_halrf_path_adda_setting_trigger(void *dm_void)
1602 {
1603 struct dm_struct *dm = (struct dm_struct *)dm_void;
1604
1605 #if (RTL8814B_SUPPORT == 1)
1606 if (dm->support_ic_type & ODM_RTL8814B)
1607 config_phydm_path_adda_setting_8814b(dm);
1608 #endif
1609
1610 }
1611
halrf_dack_restore(void * dm_void)1612 void halrf_dack_restore(void *dm_void)
1613 {
1614 struct dm_struct *dm = (struct dm_struct *)dm_void;
1615 struct _hal_rf_ *rf = &dm->rf_table;
1616
1617 if (!(rf->rf_supportability & HAL_RF_DACK))
1618 return;
1619 switch (dm->support_ic_type) {
1620 #if (RTL8822C_SUPPORT == 1)
1621 case ODM_RTL8822C:
1622 halrf_dack_restore_8822c(dm);
1623 break;
1624 #endif
1625 default:
1626 break;
1627 }
1628 }
halrf_dack_trigger(void * dm_void,boolean force)1629 void halrf_dack_trigger(void *dm_void, boolean force)
1630 {
1631 struct dm_struct *dm = (struct dm_struct *)dm_void;
1632 struct _hal_rf_ *rf = &dm->rf_table;
1633
1634 u64 start_time;
1635
1636 if (!(rf->rf_supportability & HAL_RF_DACK))
1637 return;
1638
1639 start_time = odm_get_current_time(dm);
1640
1641 switch (dm->support_ic_type) {
1642 #if (RTL8822C_SUPPORT == 1)
1643 case ODM_RTL8822C:
1644 halrf_dac_cal_8822c(dm, force);
1645 break;
1646 #endif
1647 #if (RTL8812F_SUPPORT == 1)
1648 case ODM_RTL8812F:
1649 halrf_dac_cal_8812f(dm);
1650 break;
1651 #endif
1652 #if (RTL8814B_SUPPORT == 1)
1653 case ODM_RTL8814B:
1654 halrf_dac_cal_8814b(dm);
1655 break;
1656 #endif
1657 default:
1658 break;
1659 }
1660 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
1661 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK progressing_time = %lld ms\n",
1662 rf->dpk_progressing_time);
1663 }
1664
1665
halrf_dack_dbg(void * dm_void)1666 void halrf_dack_dbg(void *dm_void)
1667 {
1668 struct dm_struct *dm = (struct dm_struct *)dm_void;
1669 struct _hal_rf_ *rf = &dm->rf_table;
1670
1671 u64 start_time;
1672
1673 if (!(rf->rf_supportability & HAL_RF_DACK))
1674 return;
1675
1676 switch (dm->support_ic_type) {
1677 #if (RTL8822C_SUPPORT == 1)
1678 case ODM_RTL8822C:
1679 halrf_dack_dbg_8822c(dm);
1680 break;
1681 #endif
1682 default:
1683 break;
1684 }
1685 }
1686
1687
halrf_segment_iqk_trigger(void * dm_void,boolean clear,boolean segment_iqk)1688 void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
1689 boolean segment_iqk)
1690 {
1691 struct dm_struct *dm = (struct dm_struct *)dm_void;
1692 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1693 struct _hal_rf_ *rf = &dm->rf_table;
1694 u64 start_time;
1695
1696 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1697 if (odm_check_power_status(dm) == false)
1698 return;
1699 #endif
1700
1701 if (!dm->mp_mode)
1702 return;
1703
1704 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1705 rf->is_carrier_suppresion) {
1706 if (*dm->mp_mode &
1707 (*rf->is_con_tx || *rf->is_single_tone ||
1708 *rf->is_carrier_suppresion))
1709 return;
1710 }
1711
1712 if (!(rf->rf_supportability & HAL_RF_IQK))
1713 return;
1714
1715 #if DISABLE_BB_RF
1716 return;
1717 #endif
1718 if (iqk_info->rfk_forbidden)
1719 return;
1720
1721 rf->rfk_type = RF01_IQK;
1722 halrf_rfk_handshake(dm, true);
1723
1724 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1725 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1726 dm->rf_calibrate_info.is_iqk_in_progress = true;
1727 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1728 start_time = odm_get_current_time(dm);
1729 dm->IQK_info.segment_iqk = segment_iqk;
1730
1731 halrf_rfk_power_save(dm, false);
1732 switch (dm->support_ic_type) {
1733 #if (RTL8822B_SUPPORT == 1)
1734 case ODM_RTL8822B:
1735 phy_iq_calibrate_8822b(dm, clear, segment_iqk);
1736 break;
1737 #endif
1738 #if (RTL8822C_SUPPORT == 1)
1739 case ODM_RTL8822C:
1740 phy_iq_calibrate_8822c(dm, clear, segment_iqk);
1741 break;
1742 #endif
1743 #if (RTL8821C_SUPPORT == 1)
1744 case ODM_RTL8821C:
1745 phy_iq_calibrate_8821c(dm, clear, segment_iqk);
1746 break;
1747 #endif
1748 #if (RTL8814B_SUPPORT == 1)
1749 case ODM_RTL8814B:
1750 phy_iq_calibrate_8814b(dm, clear, segment_iqk);
1751 break;
1752 #endif
1753 #if (RTL8195B_SUPPORT == 1)
1754 case ODM_RTL8195B:
1755 phy_iq_calibrate_8195b(dm, clear, segment_iqk);
1756 break;
1757 #endif
1758 #if (RTL8710C_SUPPORT == 1)
1759 case ODM_RTL8710C:
1760 phy_iq_calibrate_8710c(dm, clear, segment_iqk);
1761 break;
1762 #endif
1763 #if (RTL8198F_SUPPORT == 1)
1764 case ODM_RTL8198F:
1765 phy_iq_calibrate_8198f(dm, clear, segment_iqk);
1766 break;
1767 #endif
1768 #if (RTL8812F_SUPPORT == 1)
1769 case ODM_RTL8812F:
1770 phy_iq_calibrate_8812f(dm, clear, segment_iqk);
1771 break;
1772 #endif
1773 #if (RTL8197G_SUPPORT == 1)
1774 case ODM_RTL8197G:
1775 phy_iq_calibrate_8197g(dm, clear, segment_iqk);
1776 break;
1777 #endif
1778 #if (RTL8188E_SUPPORT == 1)
1779 case ODM_RTL8188E:
1780 phy_iq_calibrate_8188e(dm, false);
1781 break;
1782 #endif
1783 #if (RTL8188F_SUPPORT == 1)
1784 case ODM_RTL8188F:
1785 phy_iq_calibrate_8188f(dm, false);
1786 break;
1787 #endif
1788 #if (RTL8192E_SUPPORT == 1)
1789 case ODM_RTL8192E:
1790 phy_iq_calibrate_8192e(dm, false);
1791 break;
1792 #endif
1793 #if (RTL8197F_SUPPORT == 1)
1794 case ODM_RTL8197F:
1795 phy_iq_calibrate_8197f(dm, false);
1796 break;
1797 #endif
1798 #if (RTL8192F_SUPPORT == 1)
1799 case ODM_RTL8192F:
1800 phy_iq_calibrate_8192f(dm, false);
1801 break;
1802 #endif
1803 #if (RTL8703B_SUPPORT == 1)
1804 case ODM_RTL8703B:
1805 phy_iq_calibrate_8703b(dm, false);
1806 break;
1807 #endif
1808 #if (RTL8710B_SUPPORT == 1)
1809 case ODM_RTL8710B:
1810 phy_iq_calibrate_8710b(dm, false);
1811 break;
1812 #endif
1813 #if (RTL8723B_SUPPORT == 1)
1814 case ODM_RTL8723B:
1815 phy_iq_calibrate_8723b(dm, false);
1816 break;
1817 #endif
1818 #if (RTL8723D_SUPPORT == 1)
1819 case ODM_RTL8723D:
1820 phy_iq_calibrate_8723d(dm, false);
1821 break;
1822 #endif
1823 #if (RTL8721D_SUPPORT == 1)
1824 case ODM_RTL8721D:
1825 phy_iq_calibrate_8721d(dm, false);
1826 break;
1827 #endif
1828 #if (RTL8812A_SUPPORT == 1)
1829 case ODM_RTL8812:
1830 phy_iq_calibrate_8812a(dm, false);
1831 break;
1832 #endif
1833 #if (RTL8821A_SUPPORT == 1)
1834 case ODM_RTL8821:
1835 phy_iq_calibrate_8821a(dm, false);
1836 break;
1837 #endif
1838 #if (RTL8814A_SUPPORT == 1)
1839 case ODM_RTL8814A:
1840 phy_iq_calibrate_8814a(dm, false);
1841 break;
1842 #endif
1843 #if (RTL8723F_SUPPORT == 1)
1844 case ODM_RTL8723F:
1845 phy_iq_calibrate_8723f(dm, false);
1846 break;
1847 #endif
1848
1849 default:
1850 break;
1851 }
1852
1853 halrf_rfk_power_save(dm, true);
1854 dm->rf_calibrate_info.iqk_progressing_time =
1855 odm_get_progressing_time(dm, start_time);
1856 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
1857 dm->rf_calibrate_info.iqk_progressing_time);
1858
1859 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1860 dm->rf_calibrate_info.is_iqk_in_progress = false;
1861 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1862
1863 halrf_rfk_handshake(dm, false);
1864 } else {
1865 RF_DBG(dm, DBG_RF_IQK,
1866 "== Return the IQK CMD, because RFKs in Progress ==\n");
1867 }
1868 }
1869
1870
halrf_iqk_trigger(void * dm_void,boolean is_recovery)1871 void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
1872 {
1873 struct dm_struct *dm = (struct dm_struct *)dm_void;
1874 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1875 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1876 struct _hal_rf_ *rf = &dm->rf_table;
1877 u64 start_time;
1878
1879 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1880 if (odm_check_power_status(dm) == false)
1881 return;
1882 #endif
1883
1884 if (!dm->mp_mode)
1885 return;
1886
1887 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1888 rf->is_carrier_suppresion) {
1889 if (*dm->mp_mode &
1890 (*rf->is_con_tx || *rf->is_single_tone ||
1891 *rf->is_carrier_suppresion))
1892 return;
1893 }
1894
1895 if (!(rf->rf_supportability & HAL_RF_IQK))
1896 return;
1897
1898 #if DISABLE_BB_RF
1899 return;
1900 #endif
1901
1902 if (iqk_info->rfk_forbidden)
1903 return;
1904
1905 rf->rfk_type = RF01_IQK;
1906 halrf_rfk_handshake(dm, true);
1907
1908 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1909 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1910 dm->rf_calibrate_info.is_iqk_in_progress = true;
1911 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1912 start_time = odm_get_current_time(dm);
1913 halrf_rfk_power_save(dm, false);
1914 switch (dm->support_ic_type) {
1915 #if (RTL8188E_SUPPORT == 1)
1916 case ODM_RTL8188E:
1917 phy_iq_calibrate_8188e(dm, is_recovery);
1918 break;
1919 #endif
1920 #if (RTL8188F_SUPPORT == 1)
1921 case ODM_RTL8188F:
1922 phy_iq_calibrate_8188f(dm, is_recovery);
1923 break;
1924 #endif
1925 #if (RTL8192E_SUPPORT == 1)
1926 case ODM_RTL8192E:
1927 phy_iq_calibrate_8192e(dm, is_recovery);
1928 break;
1929 #endif
1930 #if (RTL8197F_SUPPORT == 1)
1931 case ODM_RTL8197F:
1932 phy_iq_calibrate_8197f(dm, is_recovery);
1933 break;
1934 #endif
1935 #if (RTL8192F_SUPPORT == 1)
1936 case ODM_RTL8192F:
1937 phy_iq_calibrate_8192f(dm, is_recovery);
1938 break;
1939 #endif
1940 #if (RTL8703B_SUPPORT == 1)
1941 case ODM_RTL8703B:
1942 phy_iq_calibrate_8703b(dm, is_recovery);
1943 break;
1944 #endif
1945 #if (RTL8710B_SUPPORT == 1)
1946 case ODM_RTL8710B:
1947 phy_iq_calibrate_8710b(dm, is_recovery);
1948 break;
1949 #endif
1950 #if (RTL8723B_SUPPORT == 1)
1951 case ODM_RTL8723B:
1952 phy_iq_calibrate_8723b(dm, is_recovery);
1953 break;
1954 #endif
1955 #if (RTL8723D_SUPPORT == 1)
1956 case ODM_RTL8723D:
1957 phy_iq_calibrate_8723d(dm, is_recovery);
1958 break;
1959 #endif
1960 #if (RTL8721D_SUPPORT == 1)
1961 case ODM_RTL8721D:
1962 phy_iq_calibrate_8721d(dm, is_recovery);
1963 break;
1964 #endif
1965 #if (RTL8812A_SUPPORT == 1)
1966 case ODM_RTL8812:
1967 phy_iq_calibrate_8812a(dm, is_recovery);
1968 break;
1969 #endif
1970 #if (RTL8821A_SUPPORT == 1)
1971 case ODM_RTL8821:
1972 phy_iq_calibrate_8821a(dm, is_recovery);
1973 break;
1974 #endif
1975 #if (RTL8814A_SUPPORT == 1)
1976 case ODM_RTL8814A:
1977 phy_iq_calibrate_8814a(dm, is_recovery);
1978 break;
1979 #endif
1980 #if (RTL8822B_SUPPORT == 1)
1981 case ODM_RTL8822B:
1982 phy_iq_calibrate_8822b(dm, false, false);
1983 break;
1984 #endif
1985 #if (RTL8822C_SUPPORT == 1)
1986 case ODM_RTL8822C:
1987 phy_iq_calibrate_8822c(dm, false, false);
1988 break;
1989 #endif
1990 #if (RTL8821C_SUPPORT == 1)
1991 case ODM_RTL8821C:
1992 phy_iq_calibrate_8821c(dm, false, false);
1993 break;
1994 #endif
1995 #if (RTL8814B_SUPPORT == 1)
1996 case ODM_RTL8814B:
1997 phy_iq_calibrate_8814b(dm, false, false);
1998 break;
1999 #endif
2000 #if (RTL8195B_SUPPORT == 1)
2001 case ODM_RTL8195B:
2002 phy_iq_calibrate_8195b(dm, false, false);
2003 break;
2004 #endif
2005 #if (RTL8710C_SUPPORT == 1)
2006 case ODM_RTL8710C:
2007 phy_iq_calibrate_8710c(dm, false, false);
2008 break;
2009 #endif
2010 #if (RTL8198F_SUPPORT == 1)
2011 case ODM_RTL8198F:
2012 phy_iq_calibrate_8198f(dm, false, false);
2013 break;
2014 #endif
2015 #if (RTL8812F_SUPPORT == 1)
2016 case ODM_RTL8812F:
2017 phy_iq_calibrate_8812f(dm, false, false);
2018 break;
2019 #endif
2020 #if (RTL8197G_SUPPORT == 1)
2021 case ODM_RTL8197G:
2022 phy_iq_calibrate_8197g(dm, false, false);
2023 break;
2024 #endif
2025 #if (RTL8723F_SUPPORT == 1)
2026 case ODM_RTL8723F:
2027 phy_iq_calibrate_8723f(dm, is_recovery);
2028 break;
2029 #endif
2030
2031 default:
2032 break;
2033 }
2034
2035 halrf_rfk_power_save(dm, true);
2036 rf->iqk_progressing_time = odm_get_progressing_time(dm, start_time);
2037 RF_DBG(dm, DBG_RF_LCK, "[IQK]Trigger IQK progressing_time = %lld ms\n",
2038 rf->iqk_progressing_time);
2039 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2040 dm->rf_calibrate_info.is_iqk_in_progress = false;
2041 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2042
2043 halrf_rfk_handshake(dm, false);
2044 } else {
2045 RF_DBG(dm, DBG_RF_IQK,
2046 "== Return the IQK CMD, because RFKs in Progress ==\n");
2047 }
2048 }
2049
halrf_lck_trigger(void * dm_void)2050 void halrf_lck_trigger(void *dm_void)
2051 {
2052 struct dm_struct *dm = (struct dm_struct *)dm_void;
2053 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2054 struct _hal_rf_ *rf = &dm->rf_table;
2055 u64 start_time;
2056
2057 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2058 if (odm_check_power_status(dm) == false)
2059 return;
2060 #endif
2061
2062 if (!dm->mp_mode)
2063 return;
2064
2065 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2066 rf->is_carrier_suppresion) {
2067 if (*dm->mp_mode &
2068 (*rf->is_con_tx || *rf->is_single_tone ||
2069 *rf->is_carrier_suppresion))
2070 return;
2071 }
2072
2073 if (!(rf->rf_supportability & HAL_RF_LCK))
2074 return;
2075
2076 #if DISABLE_BB_RF
2077 return;
2078 #endif
2079 if (iqk_info->rfk_forbidden)
2080 return;
2081 while (*dm->is_scan_in_process) {
2082 RF_DBG(dm, DBG_RF_LCK, "[LCK]scan is in process, bypass LCK\n");
2083 return;
2084 }
2085
2086 if (!dm->rf_calibrate_info.is_lck_in_progress) {
2087 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2088 dm->rf_calibrate_info.is_lck_in_progress = true;
2089 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2090 start_time = odm_get_current_time(dm);
2091 switch (dm->support_ic_type) {
2092 #if (RTL8188E_SUPPORT == 1)
2093 case ODM_RTL8188E:
2094 phy_lc_calibrate_8188e(dm);
2095 break;
2096 #endif
2097 #if (RTL8188F_SUPPORT == 1)
2098 case ODM_RTL8188F:
2099 phy_lc_calibrate_8188f(dm);
2100 break;
2101 #endif
2102 #if (RTL8192E_SUPPORT == 1)
2103 case ODM_RTL8192E:
2104 phy_lc_calibrate_8192e(dm);
2105 break;
2106 #endif
2107 #if (RTL8197F_SUPPORT == 1)
2108 case ODM_RTL8197F:
2109 phy_lc_calibrate_8197f(dm);
2110 break;
2111 #endif
2112 #if (RTL8192F_SUPPORT == 1)
2113 case ODM_RTL8192F:
2114 phy_lc_calibrate_8192f(dm);
2115 break;
2116 #endif
2117 #if (RTL8703B_SUPPORT == 1)
2118 case ODM_RTL8703B:
2119 phy_lc_calibrate_8703b(dm);
2120 break;
2121 #endif
2122 #if (RTL8710B_SUPPORT == 1)
2123 case ODM_RTL8710B:
2124 phy_lc_calibrate_8710b(dm);
2125 break;
2126 #endif
2127 #if (RTL8721D_SUPPORT == 1)
2128 case ODM_RTL8721D:
2129 phy_lc_calibrate_8721d(dm);
2130 break;
2131 #endif
2132 #if (RTL8723B_SUPPORT == 1)
2133 case ODM_RTL8723B:
2134 phy_lc_calibrate_8723b(dm);
2135 break;
2136 #endif
2137 #if (RTL8723D_SUPPORT == 1)
2138 case ODM_RTL8723D:
2139 phy_lc_calibrate_8723d(dm);
2140 break;
2141 #endif
2142 #if (RTL8812A_SUPPORT == 1)
2143 case ODM_RTL8812:
2144 phy_lc_calibrate_8812a(dm);
2145 break;
2146 #endif
2147 #if (RTL8821A_SUPPORT == 1)
2148 case ODM_RTL8821:
2149 phy_lc_calibrate_8821a(dm);
2150 break;
2151 #endif
2152 #if (RTL8814A_SUPPORT == 1)
2153 case ODM_RTL8814A:
2154 phy_lc_calibrate_8814a(dm);
2155 break;
2156 #endif
2157 #if (RTL8822B_SUPPORT == 1)
2158 case ODM_RTL8822B:
2159 phy_lc_calibrate_8822b(dm);
2160 break;
2161 #endif
2162 #if (RTL8822C_SUPPORT == 1)
2163 case ODM_RTL8822C:
2164 phy_lc_calibrate_8822c(dm);
2165 break;
2166 #endif
2167 #if (RTL8812F_SUPPORT == 1)
2168 case ODM_RTL8812F:
2169 phy_lc_calibrate_8812f(dm);
2170 break;
2171 #endif
2172 #if (RTL8821C_SUPPORT == 1)
2173 case ODM_RTL8821C:
2174 phy_lc_calibrate_8821c(dm);
2175 break;
2176 #endif
2177 #if (RTL8814B_SUPPORT == 1)
2178 case ODM_RTL8814B:
2179 phy_lc_calibrate_8814b(dm);
2180 break;
2181 #endif
2182 #if (RTL8197G_SUPPORT == 1)
2183 case ODM_RTL8197G:
2184 phy_lc_calibrate_8197g(dm);
2185 break;
2186 #endif
2187 #if (RTL8198F_SUPPORT == 1)
2188 case ODM_RTL8198F:
2189 phy_lc_calibrate_8198f(dm);
2190 break;
2191 #endif
2192 #if (RTL8710C_SUPPORT == 1)
2193 case ODM_RTL8710C:
2194 phy_lc_calibrate_8710c(dm);
2195 break;
2196 #endif
2197 #if (RTL8723F_SUPPORT == 1)
2198 case ODM_RTL8723F:
2199 phy_lc_calibrate_8723f(dm);
2200 break;
2201 #endif
2202
2203 default:
2204 break;
2205 }
2206 dm->rf_calibrate_info.lck_progressing_time =
2207 odm_get_progressing_time(dm, start_time);
2208 RF_DBG(dm, DBG_RF_LCK, "[LCK]LCK progressing_time = %lld ms\n",
2209 dm->rf_calibrate_info.lck_progressing_time);
2210 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
2211 halrf_lck_dbg(dm);
2212 #endif
2213 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2214 dm->rf_calibrate_info.is_lck_in_progress = false;
2215 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2216 } else {
2217 RF_DBG(dm, DBG_RF_LCK,
2218 "[LCK]= Return the LCK CMD, because RFK is in Progress =\n");
2219 }
2220 }
2221
halrf_aac_check(struct dm_struct * dm)2222 void halrf_aac_check(struct dm_struct *dm)
2223 {
2224 switch (dm->support_ic_type) {
2225 #if (RTL8821C_SUPPORT == 1)
2226 case ODM_RTL8821C:
2227 #if 0
2228 aac_check_8821c(dm);
2229 #endif
2230 break;
2231 #endif
2232 #if (RTL8822B_SUPPORT == 1)
2233 case ODM_RTL8822B:
2234 #if 1
2235 aac_check_8822b(dm);
2236 #endif
2237 break;
2238 #endif
2239 default:
2240 break;
2241 }
2242 }
2243
halrf_rxdck(void * dm_void)2244 void halrf_rxdck(void *dm_void)
2245 {
2246 struct dm_struct *dm = (struct dm_struct *)dm_void;
2247 struct _hal_rf_ *rf = &dm->rf_table;
2248
2249 if (!(rf->rf_supportability & HAL_RF_RXDCK))
2250 return;
2251
2252 switch (dm->support_ic_type) {
2253 case ODM_RTL8822C:
2254 #if (RTL8822C_SUPPORT == 1)
2255 halrf_rxdck_8822c(dm);
2256 break;
2257 #endif
2258 default:
2259 break;
2260 }
2261 }
2262
halrf_x2k_check(struct dm_struct * dm)2263 void halrf_x2k_check(struct dm_struct *dm)
2264 {
2265
2266 switch (dm->support_ic_type) {
2267 case ODM_RTL8821C:
2268 #if (RTL8821C_SUPPORT == 1)
2269 #endif
2270 break;
2271 case ODM_RTL8822C:
2272 #if (RTL8822C_SUPPORT == 1)
2273 phy_x2_check_8822c(dm);
2274 break;
2275 #endif
2276 case ODM_RTL8812F:
2277 #if (RTL8812F_SUPPORT == 1)
2278 phy_x2_check_8812f(dm);
2279 break;
2280 #endif
2281 case ODM_RTL8723F:
2282 #if (RTL8723F_SUPPORT == 1)
2283 phy_x2_check_8723f(dm);
2284 break;
2285 #endif
2286
2287 default:
2288 break;
2289 }
2290 }
2291
halrf_set_rfsupportability(void * dm_void)2292 void halrf_set_rfsupportability(void *dm_void)
2293 {
2294 struct dm_struct *dm = (struct dm_struct *)dm_void;
2295 struct _hal_rf_ *rf = &dm->rf_table;
2296
2297 if (!dm->mp_mode)
2298 return;
2299
2300 if (rf->manual_rf_supportability &&
2301 *rf->manual_rf_supportability != 0xffffffff) {
2302 rf->rf_supportability = *rf->manual_rf_supportability;
2303 } else if (*dm->mp_mode) {
2304 halrf_supportability_init_mp(dm);
2305 } else {
2306 halrf_supportability_init(dm);
2307 }
2308 }
2309
halrf_rfe_definition(struct dm_struct * dm)2310 void halrf_rfe_definition(struct dm_struct *dm)
2311 {
2312 struct _hal_rf_ *rf = &dm->rf_table;
2313
2314 switch (dm->support_ic_type) {
2315 case ODM_RTL8822C:
2316 #if (RTL8822C_SUPPORT == 1)
2317 if (dm->rfe_type == 21 || dm->rfe_type == 22) {
2318 rf->ext_pa_5g = 1;
2319 rf->ext_lna_5g = 1;
2320 }
2321 break;
2322 #endif
2323 default:
2324 break;
2325 }
2326 }
2327
halrf_init(void * dm_void)2328 void halrf_init(void *dm_void)
2329 {
2330 struct dm_struct *dm = (struct dm_struct *)dm_void;
2331 struct _hal_rf_ *rf = &dm->rf_table;
2332
2333 RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n");
2334 rf->aac_checked = false;
2335 halrf_init_debug_setting(dm);
2336 halrf_set_rfsupportability(dm);
2337 halrf_rfe_definition(dm);
2338 #if 1
2339 /*Init all RF funciton*/
2340 halrf_aac_check(dm);
2341 halrf_dack_trigger(dm, false);
2342 halrf_x2k_check(dm);
2343 #endif
2344
2345 /*power trim, thrmal trim, pa bias*/
2346 phydm_config_new_kfree(dm);
2347
2348 /*TSSI Init*/
2349 halrf_tssi_dck(dm, true);
2350 halrf_tssi_get_efuse(dm);
2351 halrf_tssi_set_de(dm);
2352 #if (RTL8723F_SUPPORT == 1)
2353 halrf_do_tssi(dm);
2354 halrf_rx_port_ctl_8723f(dm);
2355 #endif
2356
2357 /*TX Gap K*/
2358 halrf_txgapk_write_gain_table(dm);
2359 }
2360
halrf_dpk_trigger(void * dm_void)2361 void halrf_dpk_trigger(void *dm_void)
2362 {
2363 struct dm_struct *dm = (struct dm_struct *)dm_void;
2364 struct _hal_rf_ *rf = &dm->rf_table;
2365 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2366 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2367
2368 u64 start_time;
2369
2370 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2371 if (odm_check_power_status(dm) == false)
2372 return;
2373 #endif
2374
2375 if (!dm->mp_mode)
2376 return;
2377
2378 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2379 rf->is_carrier_suppresion) {
2380 if (*dm->mp_mode &
2381 (*rf->is_con_tx || *rf->is_single_tone ||
2382 *rf->is_carrier_suppresion))
2383 return;
2384 }
2385
2386 if (!(rf->rf_supportability & HAL_RF_DPK))
2387 return;
2388
2389 #if DISABLE_BB_RF
2390 return;
2391 #endif
2392
2393 if (iqk_info->rfk_forbidden)
2394 return;
2395
2396 rf->rfk_type = RF03_DPK;
2397 halrf_rfk_handshake(dm, true);
2398
2399 if (!rf->is_dpk_in_progress) {
2400 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2401 rf->is_dpk_in_progress = true;
2402 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2403 start_time = odm_get_current_time(dm);
2404 halrf_rfk_power_save(dm, false);
2405 switch (dm->support_ic_type) {
2406 #if (RTL8822C_SUPPORT == 1)
2407 case ODM_RTL8822C:
2408 do_dpk_8822c(dm);
2409 break;
2410 #endif
2411
2412 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2413 #if (RTL8197F_SUPPORT == 1)
2414 case ODM_RTL8197F:
2415 do_dpk_8197f(dm);
2416 break;
2417 #endif
2418 #if (RTL8192F_SUPPORT == 1)
2419 case ODM_RTL8192F:
2420 do_dpk_8192f(dm);
2421 break;
2422 #endif
2423
2424 #if (RTL8198F_SUPPORT == 1)
2425 case ODM_RTL8198F:
2426 do_dpk_8198f(dm);
2427 break;
2428 #endif
2429 #if (RTL8812F_SUPPORT == 1)
2430 case ODM_RTL8812F:
2431 do_dpk_8812f(dm);
2432 break;
2433 #endif
2434 #if (RTL8197G_SUPPORT == 1)
2435 case ODM_RTL8197G:
2436 do_dpk_8197g(dm);
2437 break;
2438 #endif
2439
2440 #endif
2441
2442 #if (RTL8814B_SUPPORT == 1)
2443 case ODM_RTL8814B:
2444 do_dpk_8814b(dm);
2445 break;
2446 #endif
2447 #if (RTL8723F_SUPPORT == 1)
2448 case ODM_RTL8723F:
2449 do_dpk_8723f(dm);
2450 break;
2451 #endif
2452
2453 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2454 #if (RTL8195B_SUPPORT == 1)
2455 case ODM_RTL8195B:
2456 do_dpk_8195b(dm);
2457 break;
2458 #endif
2459 #if (RTL8721D_SUPPORT == 1)
2460 case ODM_RTL8721D:
2461 do_dpk_8721d(dm);
2462 break;
2463 #endif
2464 #endif
2465 default:
2466 break;
2467 }
2468 halrf_rfk_power_save(dm, true);
2469 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
2470 RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n",
2471 rf->dpk_progressing_time);
2472
2473 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2474 rf->is_dpk_in_progress = false;
2475 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2476
2477 halrf_rfk_handshake(dm, false);
2478 } else {
2479 RF_DBG(dm, DBG_RF_DPK,
2480 "== Return the DPK CMD, because RFKs in Progress ==\n");
2481 }
2482 }
2483
halrf_set_dpkbychannel(void * dm_void,boolean dpk_by_ch)2484 void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch)
2485 {
2486 struct dm_struct *dm = (struct dm_struct *)dm_void;
2487 struct _hal_rf_ *rf = &dm->rf_table;
2488 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2489 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2490
2491
2492 switch (dm->support_ic_type) {
2493 #if (RTL8814B_SUPPORT == 1)
2494 case ODM_RTL8814B:
2495 dpk_set_dpkbychannel_8814b(dm, dpk_by_ch);
2496 break;
2497 #endif
2498
2499 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2500 #if (RTL8195B_SUPPORT == 1)
2501 case ODM_RTL8195B:
2502 dpk_set_dpkbychannel_8195b(dm,dpk_by_ch);
2503 break;
2504 #endif
2505 #endif
2506 default:
2507 if (dpk_by_ch)
2508 dpk_info->is_dpk_by_channel = 1;
2509 else
2510 dpk_info->is_dpk_by_channel = 0;
2511 break;
2512 }
2513
2514 }
2515
halrf_set_dpkenable(void * dm_void,boolean is_dpk_enable)2516 void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable)
2517 {
2518 struct dm_struct *dm = (struct dm_struct *)dm_void;
2519 struct _hal_rf_ *rf = &dm->rf_table;
2520 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2521 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2522
2523
2524 switch (dm->support_ic_type) {
2525 #if (RTL8814B_SUPPORT == 1)
2526 case ODM_RTL8814B:
2527 dpk_set_is_dpk_enable_8814b(dm, is_dpk_enable);
2528 break;
2529 #endif
2530
2531 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2532 #if (RTL8195B_SUPPORT == 1)
2533 case ODM_RTL8195B:
2534 dpk_set_is_dpk_enable_8195b(dm, is_dpk_enable);
2535 break;
2536 #endif
2537
2538 #if (RTL8721D_SUPPORT == 1)
2539 case ODM_RTL8721D:
2540 dpk_set_is_dpk_enable_8721d(dm, is_dpk_enable);
2541 break;
2542 #endif
2543
2544 #endif
2545 default:
2546 break;
2547 }
2548
2549 }
halrf_get_dpkbychannel(void * dm_void)2550 boolean halrf_get_dpkbychannel(void *dm_void)
2551 {
2552 struct dm_struct *dm = (struct dm_struct *)dm_void;
2553 struct _hal_rf_ *rf = &dm->rf_table;
2554 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2555 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2556 boolean is_dpk_by_channel = true;
2557
2558 switch (dm->support_ic_type) {
2559 #if (RTL8814B_SUPPORT == 1)
2560 case ODM_RTL8814B:
2561 is_dpk_by_channel = dpk_get_dpkbychannel_8814b(dm);
2562 break;
2563 #endif
2564
2565 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2566 #if (RTL8195B_SUPPORT == 1)
2567 case ODM_RTL8195B:
2568 is_dpk_by_channel = dpk_get_dpkbychannel_8195b(dm);
2569 break;
2570 #endif
2571 #endif
2572
2573 default:
2574 break;
2575 }
2576 return is_dpk_by_channel;
2577
2578 }
2579
2580
halrf_get_dpkenable(void * dm_void)2581 boolean halrf_get_dpkenable(void *dm_void)
2582 {
2583 struct dm_struct *dm = (struct dm_struct *)dm_void;
2584 struct _hal_rf_ *rf = &dm->rf_table;
2585 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2586 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2587 boolean is_dpk_enable = true;
2588
2589
2590 switch (dm->support_ic_type) {
2591 #if (RTL8814B_SUPPORT == 1)
2592 case ODM_RTL8814B:
2593 is_dpk_enable = dpk_get_is_dpk_enable_8814b(dm);
2594 break;
2595 #endif
2596
2597 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2598 #if (RTL8195B_SUPPORT == 1)
2599 case ODM_RTL8195B:
2600 is_dpk_enable = dpk_get_is_dpk_enable_8195b(dm);
2601 break;
2602 #endif
2603 #endif
2604 default:
2605 break;
2606 }
2607 return is_dpk_enable;
2608
2609 }
2610
halrf_dpk_result_check(void * dm_void)2611 u8 halrf_dpk_result_check(void *dm_void)
2612 {
2613 struct dm_struct *dm = (struct dm_struct *)dm_void;
2614 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2615
2616 u8 result = 0;
2617
2618 switch (dm->support_ic_type) {
2619 #if (RTL8822C_SUPPORT == 1)
2620 case ODM_RTL8822C:
2621 if (dpk_info->dpk_path_ok == 0x3)
2622 result = 1;
2623 else
2624 result = 0;
2625 break;
2626 #endif
2627
2628 #if (RTL8195B_SUPPORT == 1)
2629 case ODM_RTL8195B:
2630 if (dpk_info->dpk_path_ok == 0x1)
2631 result = 1;
2632 else
2633 result = 0;
2634 break;
2635 #endif
2636
2637 #if (RTL8721D_SUPPORT == 1)
2638 case ODM_RTL8721D:
2639 if (dpk_info->dpk_path_ok == 0x1)
2640 result = 1;
2641 else
2642 result = 0;
2643 break;
2644 #endif
2645
2646 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2647
2648 #if (RTL8197F_SUPPORT == 1)
2649 case ODM_RTL8197F:
2650 if (dpk_info->dpk_path_ok == 0x3)
2651 result = 1;
2652 else
2653 result = 0;
2654 break;
2655 #endif
2656
2657 #if (RTL8192F_SUPPORT == 1)
2658 case ODM_RTL8192F:
2659 if (dpk_info->dpk_path_ok == 0x3)
2660 result = 1;
2661 else
2662 result = 0;
2663 break;
2664 #endif
2665
2666 #if (RTL8198F_SUPPORT == 1)
2667 case ODM_RTL8198F:
2668 if (dpk_info->dpk_path_ok == 0xf)
2669 result = 1;
2670 else
2671 result = 0;
2672 break;
2673 #endif
2674
2675 #if (RTL8814B_SUPPORT == 1)
2676 case ODM_RTL8814B:
2677 if (dpk_info->dpk_path_ok == 0xf)
2678 result = 1;
2679 else
2680 result = 0;
2681 break;
2682 #endif
2683
2684 #if (RTL8812F_SUPPORT == 1)
2685 case ODM_RTL8812F:
2686 if (dpk_info->dpk_path_ok == 0x3)
2687 result = 1;
2688 else
2689 result = 0;
2690 break;
2691 #endif
2692
2693 #if (RTL8197G_SUPPORT == 1)
2694 case ODM_RTL8197G:
2695 if (dpk_info->dpk_path_ok == 0x3)
2696 result = 1;
2697 else
2698 result = 0;
2699 break;
2700 #endif
2701
2702 #endif
2703 default:
2704 break;
2705 }
2706 return result;
2707 }
2708
halrf_dpk_sram_read(void * dm_void)2709 void halrf_dpk_sram_read(void *dm_void)
2710 {
2711 struct dm_struct *dm = (struct dm_struct *)dm_void;
2712
2713 u8 path, group;
2714
2715 switch (dm->support_ic_type) {
2716 #if (RTL8822C_SUPPORT == 1)
2717 case ODM_RTL8822C:
2718 dpk_coef_read_8822c(dm);
2719 break;
2720 #endif
2721
2722 #if (RTL8195B_SUPPORT == 1)
2723 case ODM_RTL8195B:
2724 dpk_sram_read_8195b(dm);
2725 break;
2726 #endif
2727
2728 #if (RTL8721D_SUPPORT == 1)
2729 case ODM_RTL8721D:
2730 dpk_sram_read_8721d(dm);
2731 break;
2732 #endif
2733
2734 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2735
2736 #if (RTL8197F_SUPPORT == 1)
2737 case ODM_RTL8197F:
2738 dpk_sram_read_8197f(dm);
2739 break;
2740 #endif
2741
2742 #if (RTL8192F_SUPPORT == 1)
2743 case ODM_RTL8192F:
2744 dpk_sram_read_8192f(dm);
2745 break;
2746 #endif
2747
2748 #if (RTL8198F_SUPPORT == 1)
2749 case ODM_RTL8198F:
2750 dpk_sram_read_8198f(dm);
2751 break;
2752 #endif
2753
2754 #if (RTL8814B_SUPPORT == 1)
2755 case ODM_RTL8814B:
2756 dpk_sram_read_8814b(dm);
2757 break;
2758 #endif
2759
2760 #if (RTL8812F_SUPPORT == 1)
2761 case ODM_RTL8812F:
2762 dpk_coef_read_8812f(dm);
2763 break;
2764 #endif
2765
2766 #if (RTL8197G_SUPPORT == 1)
2767 case ODM_RTL8197G:
2768 dpk_sram_read_8197g(dm);
2769 break;
2770 #endif
2771
2772 #endif
2773 default:
2774 break;
2775 }
2776 }
2777
halrf_dpk_enable_disable(void * dm_void)2778 void halrf_dpk_enable_disable(void *dm_void)
2779 {
2780 struct dm_struct *dm = (struct dm_struct *)dm_void;
2781 struct _hal_rf_ *rf = &dm->rf_table;
2782
2783 if (!(rf->rf_supportability & HAL_RF_DPK))
2784 return;
2785
2786 if (!rf->is_dpk_in_progress) {
2787 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2788 rf->is_dpk_in_progress = true;
2789 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2790
2791 switch (dm->support_ic_type) {
2792 #if (RTL8822C_SUPPORT == 1)
2793 case ODM_RTL8822C:
2794 dpk_enable_disable_8822c(dm);
2795 break;
2796 #endif
2797 #if (RTL8195B_SUPPORT == 1)
2798 case ODM_RTL8195B:
2799 dpk_enable_disable_8195b(dm);
2800 break;
2801 #endif
2802 #if (RTL8721D_SUPPORT == 1)
2803 case ODM_RTL8721D:
2804 phy_dpk_enable_disable_8721d(dm);
2805 break;
2806 #endif
2807
2808 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2809
2810 #if (RTL8197F_SUPPORT == 1)
2811 case ODM_RTL8197F:
2812 phy_dpk_enable_disable_8197f(dm);
2813 break;
2814 #endif
2815 #if (RTL8192F_SUPPORT == 1)
2816 case ODM_RTL8192F:
2817 phy_dpk_enable_disable_8192f(dm);
2818 break;
2819 #endif
2820
2821 #if (RTL8198F_SUPPORT == 1)
2822 case ODM_RTL8198F:
2823 dpk_enable_disable_8198f(dm);
2824 break;
2825 #endif
2826
2827 #if (RTL8814B_SUPPORT == 1)
2828 case ODM_RTL8814B:
2829 dpk_enable_disable_8814b(dm);
2830 break;
2831 #endif
2832
2833 #if (RTL8812F_SUPPORT == 1)
2834 case ODM_RTL8812F:
2835 dpk_enable_disable_8812f(dm);
2836 break;
2837 #endif
2838
2839 #if (RTL8197G_SUPPORT == 1)
2840 case ODM_RTL8197G:
2841 dpk_enable_disable_8197g(dm);
2842 break;
2843 #endif
2844
2845 #if (RTL8723F_SUPPORT == 1)
2846 case ODM_RTL8723F:
2847 dpk_enable_disable_8723f(dm);
2848 break;
2849 #endif
2850
2851 #endif
2852 default:
2853 break;
2854 }
2855
2856 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2857 rf->is_dpk_in_progress = false;
2858 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2859 } else {
2860 RF_DBG(dm, DBG_RF_DPK,
2861 "== Return the DPK CMD, because RFKs in Progress ==\n");
2862 }
2863 }
2864
halrf_dpk_track(void * dm_void)2865 void halrf_dpk_track(void *dm_void)
2866 {
2867 struct dm_struct *dm = (struct dm_struct *)dm_void;
2868 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2869 struct _hal_rf_ *rf = &dm->rf_table;
2870
2871 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
2872 dm->is_psd_in_process || (dpk_info->dpk_path_ok == 0) ||
2873 !(rf->rf_supportability & HAL_RF_DPK_TRACK) || rf->is_tssi_in_progress
2874 || rf->is_txgapk_in_progress)
2875 return;
2876
2877 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2878 if (*dm->is_fcs_mode_enable)
2879 return;
2880 #endif
2881
2882 switch (dm->support_ic_type) {
2883 #if (RTL8814B_SUPPORT == 1)
2884 case ODM_RTL8814B:
2885 dpk_track_8814b(dm);
2886 break;
2887 #endif
2888
2889 #if (RTL8822C_SUPPORT == 1)
2890 case ODM_RTL8822C:
2891 dpk_track_8822c(dm);
2892 break;
2893 #endif
2894
2895 #if (RTL8195B_SUPPORT == 1)
2896 case ODM_RTL8195B:
2897 dpk_track_8195b(dm);
2898 break;
2899 #endif
2900
2901 #if (RTL8721D_SUPPORT == 1)
2902 case ODM_RTL8721D:
2903 phy_dpk_track_8721d(dm);
2904 break;
2905 #endif
2906
2907 #if (RTL8723F_SUPPORT == 1)
2908 case ODM_RTL8723F:
2909 dpk_track_8723f(dm);
2910 break;
2911 #endif
2912
2913 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2914
2915 #if (RTL8197F_SUPPORT == 1)
2916 case ODM_RTL8197F:
2917 phy_dpk_track_8197f(dm);
2918 break;
2919 #endif
2920
2921 #if (RTL8192F_SUPPORT == 1)
2922 case ODM_RTL8192F:
2923 phy_dpk_track_8192f(dm);
2924 break;
2925 #endif
2926
2927 #if (RTL8198F_SUPPORT == 1)
2928 case ODM_RTL8198F:
2929 dpk_track_8198f(dm);
2930 break;
2931 #endif
2932
2933 #if (RTL8812F_SUPPORT == 1)
2934 case ODM_RTL8812F:
2935 dpk_track_8812f(dm);
2936 break;
2937 #endif
2938
2939 #if (RTL8197G_SUPPORT == 1)
2940 case ODM_RTL8197G:
2941 dpk_track_8197g(dm);
2942 break;
2943 #endif
2944
2945 #endif
2946 default:
2947 break;
2948 }
2949 }
2950
halrf_set_dpk_track(void * dm_void,u8 enable)2951 void halrf_set_dpk_track(void *dm_void, u8 enable)
2952 {
2953 struct dm_struct *dm = (struct dm_struct *)dm_void;
2954 struct _hal_rf_ *rf = &(dm->rf_table);
2955
2956 if (enable)
2957 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK_TRACK;
2958 else
2959 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
2960 }
2961
halrf_dpk_reload(void * dm_void)2962 void halrf_dpk_reload(void *dm_void)
2963 {
2964 struct dm_struct *dm = (struct dm_struct *)dm_void;
2965 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2966
2967 switch (dm->support_ic_type) {
2968 #if (RTL8195B_SUPPORT == 1)
2969 case ODM_RTL8195B:
2970 if (dpk_info->dpk_path_ok > 0)
2971 dpk_reload_8195b(dm);
2972 break;
2973 #endif
2974 #if (RTL8721D_SUPPORT == 1)
2975 case ODM_RTL8721D:
2976 if (dpk_info->dpk_path_ok > 0)
2977 dpk_reload_8721d(dm);
2978 break;
2979 #endif
2980
2981 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2982
2983 #if (RTL8197F_SUPPORT == 1)
2984 case ODM_RTL8197F:
2985 if (dpk_info->dpk_path_ok > 0)
2986 dpk_reload_8197f(dm);
2987 break;
2988 #endif
2989
2990 #if (RTL8192F_SUPPORT == 1)
2991 case ODM_RTL8192F:
2992 if (dpk_info->dpk_path_ok > 0)
2993 dpk_reload_8192f(dm);
2994
2995 break;
2996 #endif
2997
2998 #if (RTL8198F_SUPPORT == 1)
2999 case ODM_RTL8198F:
3000 if (dpk_info->dpk_path_ok > 0)
3001 dpk_reload_8198f(dm);
3002 break;
3003 #endif
3004
3005 #if (RTL8814B_SUPPORT == 1)
3006 case ODM_RTL8814B:
3007 if (dpk_info->dpk_path_ok > 0)
3008 dpk_reload_8814b(dm);
3009 break;
3010 #endif
3011
3012 #endif
3013 default:
3014 break;
3015 }
3016 }
3017
halrf_dpk_switch(void * dm_void,u8 enable)3018 void halrf_dpk_switch(void *dm_void, u8 enable)
3019 {
3020 struct dm_struct *dm = (struct dm_struct *)dm_void;
3021 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3022 struct _hal_rf_ *rf = &dm->rf_table;
3023
3024 if (enable) {
3025 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK;
3026 dpk_info->is_dpk_enable = true;
3027 halrf_dpk_enable_disable(dm);
3028 halrf_dpk_trigger(dm);
3029 halrf_set_dpk_track(dm, 1);
3030 } else {
3031 halrf_set_dpk_track(dm, 0);
3032 dpk_info->is_dpk_enable = false;
3033 halrf_dpk_enable_disable(dm);
3034 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK;
3035 }
3036 }
3037
_halrf_dpk_info_by_chip(void * dm_void,u32 * _used,char * output,u32 * _out_len)3038 void _halrf_dpk_info_by_chip(void *dm_void, u32 *_used, char *output, u32 *_out_len)
3039 {
3040 struct dm_struct *dm = (struct dm_struct *)dm_void;
3041
3042 u32 used = *_used;
3043 u32 out_len = *_out_len;
3044
3045 switch (dm->support_ic_type) {
3046 #if (RTL8822C_SUPPORT == 1)
3047 case ODM_RTL8822C:
3048 dpk_info_by_8822c(dm, &used, output, &out_len);
3049 break;
3050 #endif
3051
3052 #if (RTL8812F_SUPPORT == 1)
3053 case ODM_RTL8812F:
3054 dpk_info_by_8812f(dm, &used, output, &out_len);
3055 break;
3056 #endif
3057
3058 #if (RTL8197G_SUPPORT == 1)
3059 case ODM_RTL8197G:
3060 dpk_info_by_8197g(dm, &used, output, &out_len);
3061 break;
3062 #endif
3063
3064 default:
3065 break;
3066 }
3067
3068 *_used = used;
3069 *_out_len = out_len;
3070 }
3071
_halrf_display_dpk_info(void * dm_void,u32 * _used,char * output,u32 * _out_len)3072 void _halrf_display_dpk_info(void *dm_void, u32 *_used, char *output, u32 *_out_len)
3073 {
3074 struct dm_struct *dm = (struct dm_struct *)dm_void;
3075 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3076 struct _hal_rf_ *rf = &(dm->rf_table);
3077
3078 u32 used = *_used;
3079 u32 out_len = *_out_len;
3080 char *ic_name = NULL;
3081 u8 path;
3082
3083 switch (dm->support_ic_type) {
3084
3085 #if (RTL8822C_SUPPORT)
3086 case ODM_RTL8822C:
3087 ic_name = "8822C";
3088 break;
3089 #endif
3090
3091 #if (RTL8814B_SUPPORT)
3092 case ODM_RTL8814B:
3093 ic_name = "8814B";
3094 break;
3095 #endif
3096
3097 #if (RTL8812F_SUPPORT)
3098 case ODM_RTL8812F:
3099 ic_name = "8812F";
3100 break;
3101 #endif
3102
3103 #if (RTL8198F_SUPPORT)
3104 case ODM_RTL8198F:
3105 ic_name = "8198F";
3106 break;
3107 #endif
3108
3109 #if (RTL8197F_SUPPORT)
3110 case ODM_RTL8197F:
3111 ic_name = "8197F";
3112 break;
3113 #endif
3114
3115 #if (RTL8192F_SUPPORT)
3116 case ODM_RTL8192F:
3117 ic_name = "8192F";
3118 break;
3119 #endif
3120
3121 #if (RTL8197G_SUPPORT)
3122 case ODM_RTL8197G:
3123 ic_name = "8197G";
3124 break;
3125 #endif
3126
3127 #if (RTL8710B_SUPPORT)
3128 case ODM_RTL8721D:
3129 ic_name = "8721D";
3130 break;
3131 #endif
3132
3133 #if (RTL8195B_SUPPORT)
3134 case ODM_RTL8195B:
3135 ic_name = "8195B";
3136 break;
3137 #endif
3138 }
3139
3140 PDM_SNPF(out_len, used, output + used, out_len - used,
3141 "\n===============[ DPK info %s ]===============\n", ic_name);
3142
3143 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s %s\n",
3144 "DPK type", (dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD) ? "FW" : "Driver",
3145 (dpk_info->is_dpk_by_channel) ? "(By channel)" : "(By group)");
3146
3147 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d (%d)\n",
3148 "FW Ver (Sub Ver)", dm->fw_version, dm->fw_sub_version);
3149
3150 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3151 "DPK Ver", HALRF_DPK_VER);
3152
3153 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3154 "RFK init ver", HALRF_RFK_INIT_VER);
3155
3156 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d (RFE type:%d)\n",
3157 "Ext_PA 2G / 5G", dm->ext_pa, dm->ext_pa_5g, dm->rfe_type);
3158
3159 if ((dpk_info->dpk_ch == 0) && (dpk_info->thermal_dpk[0] == 0)) {
3160 PDM_SNPF(out_len, used, output + used, out_len - used, "\n %-25s\n",
3161 "No DPK had been done before!!!");
3162 return;
3163 }
3164
3165 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
3166 "DPK Cal / OK / Reload", dpk_info->dpk_cal_cnt, dpk_info->dpk_ok_cnt,
3167 dpk_info->dpk_reload_cnt);
3168
3169 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3170 "RFK H2C timeout", (rf->is_rfk_h2c_timeout) ? "Yes" : "No");
3171
3172 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3173 "DPD Reload", (dpk_info->dpk_status & BIT(0)) ? "Yes" : "No");
3174
3175 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3176 "DPD status", dpk_info->is_dpk_enable ? "Enable" : "Disable");
3177
3178 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3179 "DPD track status", (rf->rf_supportability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable");
3180
3181 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %d / %s\n",
3182 "TSSI / Band / CH / BW", dpk_info->is_tssi_mode == 1 ? "On" : "Off",
3183 dpk_info->dpk_band == 0 ? "2G" : "5G", dpk_info->dpk_ch,
3184 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
3185
3186 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %s / %s\n",
3187 "DPK result (path)", dpk_info->dpk_path_ok & BIT(0) ? "OK" : "Fail",
3188 (dm->support_ic_type & ODM_IC_2SS) ? ((dpk_info->dpk_path_ok & BIT(1)) >> 1 ? "OK" : "Fail") : "NA",
3189 (dm->support_ic_type & ODM_IC_3SS) ? ((dpk_info->dpk_path_ok & BIT(2)) >> 2 ? "OK" : "Fail") : "NA",
3190 (dm->support_ic_type & ODM_IC_4SS) ? ((dpk_info->dpk_path_ok & BIT(3)) >> 3 ? "OK" : "Fail") : "NA");
3191 #if 0
3192 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d / %d\n",
3193 "DPK thermal (path)", dpk_info->thermal_dpk[0], dpk_info->thermal_dpk[1],
3194 dpk_info->thermal_dpk[2], dpk_info->thermal_dpk[3]);
3195 #endif
3196 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = ",
3197 "DPK thermal (path)");
3198 for (path = 0; path < KPATH; path++) {
3199 PDM_SNPF(out_len, used, output + used, out_len - used,
3200 path == (KPATH - 1) ? "%d\n" : "%d / ",
3201 dpk_info->thermal_dpk[path]);
3202 }
3203
3204 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3205 "DPK bkup GNT control", dpk_info->gnt_control);
3206
3207 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3208 "DPK bkup GNT value", dpk_info->gnt_value);
3209
3210 _halrf_dpk_info_by_chip(dm, &used, output, &out_len);
3211
3212 *_used = used;
3213 *_out_len = out_len;
3214 }
3215
halrf_dpk_debug_cmd(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3216 void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
3217 char *output, u32 *_out_len)
3218 {
3219 struct dm_struct *dm = (struct dm_struct *)dm_void;
3220 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3221 struct _hal_rf_ *rf = &(dm->rf_table);
3222
3223 char *cmd[5] = {"-h", "on", "off", "info", "switch"};
3224 u32 used = *_used;
3225 u32 out_len = *_out_len;
3226 u8 i;
3227
3228 if ((strcmp(input[2], cmd[4]) != 0)) {
3229 if (!(rf->rf_supportability & HAL_RF_DPK)) {
3230 PDM_SNPF(out_len, used, output + used, out_len - used,
3231 "DPK is Unsupported!!!\n");
3232 return;
3233 }
3234 }
3235
3236 if ((strcmp(input[2], cmd[0]) == 0)) {
3237 for (i = 1; i < 4; i++) {
3238 PDM_SNPF(out_len, used, output + used, out_len - used,
3239 " %s\n", cmd[i]);
3240 }
3241 } else if ((strcmp(input[2], cmd[1]) == 0)) {
3242 PDM_SNPF(out_len, used, output + used, out_len - used,
3243 "DPK is Enabled!!\n");
3244 dpk_info->is_dpk_enable = true;
3245 halrf_dpk_enable_disable(dm);
3246 } else if ((strcmp(input[2], cmd[2]) == 0)){
3247 PDM_SNPF(out_len, used, output + used, out_len - used,
3248 "DPK is Disabled!!\n");
3249 dpk_info->is_dpk_enable = false;
3250 halrf_dpk_enable_disable(dm);
3251 } else if ((strcmp(input[2], cmd[3]) == 0))
3252 _halrf_display_dpk_info(dm, &used, output, &out_len);
3253 else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[1]) == 0)) {
3254 PDM_SNPF(out_len, used, output + used, out_len - used,
3255 "DPK Switch on!!\n");
3256 halrf_dpk_switch(dm, 1);
3257 } else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[2]) == 0)) {
3258 PDM_SNPF(out_len, used, output + used, out_len - used,
3259 "DPK Switch off!!\n");
3260 halrf_dpk_switch(dm, 0);
3261 } else {
3262 PDM_SNPF(out_len, used, output + used, out_len - used,
3263 "DPK Trigger start!!\n");
3264 halrf_dpk_trigger(dm);
3265 PDM_SNPF(out_len, used, output + used, out_len - used,
3266 "DPK Trigger finish!!\n");
3267 }
3268 }
3269
halrf_dpk_c2h_report_transfer(void * dm_void,boolean is_ok,u8 * buf,u8 buf_size)3270 void halrf_dpk_c2h_report_transfer(void *dm_void, boolean is_ok, u8 *buf, u8 buf_size)
3271 {
3272 struct dm_struct *dm = (struct dm_struct *)dm_void;
3273 struct _hal_rf_ *rf = &dm->rf_table;
3274 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3275
3276 if (!(rf->rf_supportability & HAL_RF_DPK))
3277 return;
3278
3279 switch (dm->support_ic_type) {
3280 #if (RTL8822C_SUPPORT == 1)
3281 case ODM_RTL8822C:
3282 dpk_c2h_report_transfer_8822c(dm, is_ok, buf, buf_size);
3283 break;
3284 #endif
3285 default:
3286 break;
3287 }
3288 }
3289
halrf_dpk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3290 void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3291 {
3292 struct dm_struct *dm = (struct dm_struct *)dm_void;
3293 struct _hal_rf_ *rf = &dm->rf_table;
3294 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3295
3296 if (!(rf->rf_supportability & HAL_RF_DPK) || rf->is_dpk_in_progress)
3297 return;
3298
3299 switch (dm->support_ic_type) {
3300 #if (RTL8822C_SUPPORT == 1)
3301 case ODM_RTL8822C:
3302 dpk_info_rsvd_page_8822c(dm, buf, buf_size);
3303 break;
3304 #endif
3305 default:
3306 break;
3307 }
3308 }
3309
halrf_iqk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3310 void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3311 {
3312 struct dm_struct *dm = (struct dm_struct *)dm_void;
3313 struct _hal_rf_ *rf = &dm->rf_table;
3314
3315 if (!(rf->rf_supportability & HAL_RF_IQK))
3316 return;
3317
3318 if (dm->rf_calibrate_info.is_iqk_in_progress)
3319 return;
3320
3321 switch (dm->support_ic_type) {
3322 #if (RTL8822C_SUPPORT == 1)
3323 case ODM_RTL8822C:
3324 iqk_info_rsvd_page_8822c(dm, buf, buf_size);
3325 break;
3326 #endif
3327 #if (RTL8195B_SUPPORT == 1)
3328 case ODM_RTL8195B:
3329 iqk_info_rsvd_page_8195b(dm, buf, buf_size);
3330 break;
3331 #endif
3332
3333 default:
3334 break;
3335 }
3336 }
3337
3338 enum hal_status
halrf_config_rfk_with_header_file(void * dm_void,u32 config_type)3339 halrf_config_rfk_with_header_file(void *dm_void, u32 config_type)
3340 {
3341 struct dm_struct *dm = (struct dm_struct *)dm_void;
3342 enum hal_status result = HAL_STATUS_SUCCESS;
3343 #if 0
3344 #if (RTL8822B_SUPPORT == 1)
3345 if (dm->support_ic_type == ODM_RTL8822B) {
3346 if (config_type == CONFIG_BB_RF_CAL_INIT)
3347 odm_read_and_config_mp_8822b_cal_init(dm);
3348 }
3349 #endif
3350 #endif
3351 #if (RTL8197G_SUPPORT == 1)
3352 if (dm->support_ic_type == ODM_RTL8197G) {
3353 if (config_type == CONFIG_BB_RF_CAL_INIT)
3354 odm_read_and_config_mp_8197g_cal_init(dm);
3355 }
3356 #endif
3357 #if (RTL8198F_SUPPORT == 1)
3358 if (dm->support_ic_type == ODM_RTL8198F) {
3359 if (config_type == CONFIG_BB_RF_CAL_INIT)
3360 odm_read_and_config_mp_8198f_cal_init(dm);
3361 }
3362 #endif
3363 #if (RTL8812F_SUPPORT == 1)
3364 if (dm->support_ic_type == ODM_RTL8812F) {
3365 if (config_type == CONFIG_BB_RF_CAL_INIT)
3366 odm_read_and_config_mp_8812f_cal_init(dm);
3367 }
3368 #endif
3369 #if (RTL8822C_SUPPORT == 1)
3370 if (dm->support_ic_type == ODM_RTL8822C) {
3371 if (config_type == CONFIG_BB_RF_CAL_INIT)
3372 odm_read_and_config_mp_8822c_cal_init(dm);
3373 }
3374 #endif
3375 #if (RTL8814B_SUPPORT == 1)
3376 if (dm->support_ic_type == ODM_RTL8814B) {
3377 if (config_type == CONFIG_BB_RF_CAL_INIT)
3378 odm_read_and_config_mp_8814b_cal_init(dm);
3379 }
3380 #endif
3381 #if (RTL8195B_SUPPORT == 1)
3382 if (dm->support_ic_type == ODM_RTL8195B) {
3383 if (config_type == CONFIG_BB_RF_CAL_INIT)
3384 odm_read_and_config_mp_8195b_cal_init(dm);
3385 }
3386 #endif
3387 #if (RTL8721D_SUPPORT == 1)
3388 if (dm->support_ic_type == ODM_RTL8721D) {
3389 if (config_type == CONFIG_BB_RF_CAL_INIT)
3390 odm_read_and_config_mp_8721d_cal_init(dm);
3391 }
3392 #endif
3393 #if (RTL8723F_SUPPORT == 1)
3394 if (dm->support_ic_type == ODM_RTL8723F) {
3395 if (config_type == CONFIG_BB_RF_CAL_INIT)
3396 odm_read_and_config_mp_8723f_cal_init(dm);
3397 }
3398 #endif
3399
3400 #if 1
3401 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
3402 result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, (enum rf_path)0, 0);
3403 RF_DBG(dm, DBG_RF_IQK,"phy param offload end!result = %d", result);
3404 }
3405 #endif
3406 return result;
3407 }
3408
halrf_txgapk_trigger(void * dm_void)3409 void halrf_txgapk_trigger(void *dm_void)
3410 {
3411 struct dm_struct *dm = (struct dm_struct *)dm_void;
3412 struct _hal_rf_ *rf = &dm->rf_table;
3413 u64 start_time = 0x0;
3414
3415 if (!(rf->rf_supportability & HAL_RF_TXGAPK))
3416 return;
3417
3418 rf->rfk_type = RF04_TXGAPK;
3419 halrf_rfk_handshake(dm, true);
3420
3421 start_time = odm_get_current_time(dm);
3422 rf->is_txgapk_in_progress = true;
3423 halrf_rfk_power_save(dm, false);
3424
3425 switch (dm->support_ic_type) {
3426 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
3427 #if (RTL8195B_SUPPORT == 1)
3428 case ODM_RTL8195B:
3429 /*phy_txgap_calibrate_8195b(dm, false);*/
3430 break;
3431 #endif
3432 #if (RTL8721D_SUPPORT == 1)
3433 case ODM_RTL8721D:
3434 /*phy_txgap_calibrate_8721d(dm, false);*/
3435 break;
3436 #endif
3437
3438 #endif
3439
3440 #if (RTL8814B_SUPPORT == 1)
3441 case ODM_RTL8814B:
3442 /*phy_txgap_calibrate_8814b(dm, false);*/
3443 break;
3444 #endif
3445
3446 #if (RTL8822C_SUPPORT == 1)
3447 case ODM_RTL8822C:
3448 halrf_txgapk_8822c(dm);
3449 break;
3450 #endif
3451
3452 #if (RTL8723F_SUPPORT == 1)
3453 case ODM_RTL8723F:
3454 halrf_txgapk_8723f(dm);
3455 break;
3456 #endif
3457
3458 default:
3459 break;
3460 }
3461 halrf_rfk_power_save(dm, true);
3462 rf->is_txgapk_in_progress = false;
3463
3464 halrf_rfk_handshake(dm, false);
3465
3466 rf->dpk_progressing_time =
3467 odm_get_progressing_time(dm_void, start_time);
3468 RF_DBG(dm, DBG_RF_TXGAPK, "[TGGC]TXGAPK progressing_time = %lld ms\n",
3469 rf->dpk_progressing_time);
3470 }
3471
halrf_tssi_get_efuse(void * dm_void)3472 void halrf_tssi_get_efuse(void *dm_void)
3473 {
3474 struct dm_struct *dm = (struct dm_struct *)dm_void;
3475
3476 #if (RTL8822C_SUPPORT == 1)
3477 if (dm->support_ic_type & ODM_RTL8822C) {
3478 halrf_tssi_get_efuse_8822c(dm);
3479 halrf_get_efuse_thermal_pwrtype_8822c(dm);
3480 }
3481 #endif
3482
3483 #if (RTL8812F_SUPPORT == 1)
3484 if (dm->support_ic_type & ODM_RTL8812F) {
3485 halrf_tssi_get_efuse_8812f(dm);
3486 }
3487 #endif
3488
3489 #if (RTL8814B_SUPPORT == 1)
3490 if (dm->support_ic_type & ODM_RTL8814B) {
3491 halrf_tssi_get_efuse_8814b(dm);
3492 halrf_get_efuse_thermal_pwrtype_8814b(dm);
3493 }
3494 #endif
3495
3496 #if (RTL8197G_SUPPORT == 1)
3497 if (dm->support_ic_type & ODM_RTL8197G) {
3498 halrf_tssi_get_efuse_8197g(dm);
3499 }
3500 #endif
3501
3502 #if (RTL8723F_SUPPORT == 1)
3503 if (dm->support_ic_type & ODM_RTL8723F) {
3504 halrf_tssi_get_efuse_8723f(dm);
3505 }
3506 #endif
3507
3508 }
3509
halrf_do_rxbb_dck(void * dm_void)3510 void halrf_do_rxbb_dck(void *dm_void)
3511 {
3512 struct dm_struct *dm = (struct dm_struct *)dm_void;
3513
3514
3515 #if (RTL8814B_SUPPORT == 1)
3516 if (dm->support_ic_type == ODM_RTL8814B)
3517 halrf_do_rxbb_dck_8814b(dm);
3518 #endif
3519
3520 }
3521
halrf_do_tssi(void * dm_void)3522 void halrf_do_tssi(void *dm_void)
3523 {
3524 struct dm_struct *dm = (struct dm_struct *)dm_void;
3525
3526 #if (RTL8822C_SUPPORT == 1)
3527 if (dm->support_ic_type == ODM_RTL8822C)
3528 halrf_do_tssi_8822c(dm);
3529 #endif
3530
3531 #if (RTL8812F_SUPPORT == 1)
3532 if (dm->support_ic_type == ODM_RTL8812F)
3533 halrf_do_tssi_8812f(dm);
3534 #endif
3535
3536 #if (RTL8197G_SUPPORT == 1)
3537 if (dm->support_ic_type == ODM_RTL8197G)
3538 halrf_do_tssi_8197g(dm);
3539 #endif
3540
3541 #if (RTL8723F_SUPPORT == 1)
3542 if (dm->support_ic_type == ODM_RTL8723F) {
3543 halrf_rfk_power_save(dm, false);
3544 halrf_do_tssi_8723f(dm);
3545 halrf_rfk_power_save(dm, true);
3546 }
3547 #endif
3548
3549 }
3550
halrf_set_tssi_enable(void * dm_void,boolean enable)3551 void halrf_set_tssi_enable(void *dm_void, boolean enable)
3552 {
3553 struct dm_struct *dm = (struct dm_struct *)dm_void;
3554 struct _hal_rf_ *rf = &(dm->rf_table);
3555
3556 if (enable == 1) {
3557 rf->power_track_type = 4;
3558 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
3559 } else {
3560 rf->power_track_type = 0;
3561 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
3562 }
3563 }
3564
3565
halrf_do_thermal(void * dm_void)3566 void halrf_do_thermal(void *dm_void)
3567 {
3568 struct dm_struct *dm = (struct dm_struct *)dm_void;
3569
3570 #if (RTL8822C_SUPPORT == 1)
3571 if (dm->support_ic_type & ODM_RTL8822C)
3572 halrf_do_thermal_8822c(dm);
3573 #endif
3574 }
3575
3576
3577
halrf_set_tssi_value(void * dm_void,u32 tssi_value)3578 u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value)
3579 {
3580 struct dm_struct *dm = (struct dm_struct *)dm_void;
3581
3582 #if (RTL8822C_SUPPORT == 1)
3583 if (dm->support_ic_type & ODM_RTL8822C)
3584 return halrf_set_tssi_value_8822c(dm, tssi_value);
3585 #endif
3586
3587 #if (RTL8814B_SUPPORT == 1)
3588 if (dm->support_ic_type & ODM_RTL8814B)
3589 return halrf_set_tssi_value_8814b(dm, tssi_value);
3590 #endif
3591 #if (RTL8723F_SUPPORT == 1)
3592 if (dm->support_ic_type & ODM_RTL8723F)
3593 return halrf_tssi_set_de_8723f(dm, tssi_value);
3594 #endif
3595
3596 return 0;
3597 }
3598
halrf_set_tssi_power(void * dm_void,s8 power)3599 void halrf_set_tssi_power(void *dm_void, s8 power)
3600 {
3601 struct dm_struct *dm = (struct dm_struct *)dm_void;
3602
3603 #if (RTL8822C_SUPPORT == 1)
3604 /*halrf_set_tssi_poewr_8822c(dm, power);*/
3605 #endif
3606 }
3607
halrf_tssi_set_de_for_tx_verify(void * dm_void,u32 tssi_de,u8 path)3608 void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path)
3609 {
3610 struct dm_struct *dm = (struct dm_struct *)dm_void;
3611
3612 #if (RTL8822C_SUPPORT == 1)
3613 if (dm->support_ic_type & ODM_RTL8822C)
3614 halrf_tssi_set_de_for_tx_verify_8822c(dm, tssi_de, path);
3615 #endif
3616
3617 #if (RTL8814B_SUPPORT == 1)
3618 if (dm->support_ic_type & ODM_RTL8814B)
3619 halrf_tssi_set_de_for_tx_verify_8814b(dm, tssi_de, path);
3620 #endif
3621
3622 #if (RTL8812F_SUPPORT == 1)
3623 if (dm->support_ic_type & ODM_RTL8812F)
3624 halrf_tssi_set_de_for_tx_verify_8812f(dm, tssi_de, path);
3625 #endif
3626
3627 #if (RTL8197G_SUPPORT == 1)
3628 if (dm->support_ic_type & ODM_RTL8197G)
3629 halrf_tssi_set_de_for_tx_verify_8197g(dm, tssi_de, path);
3630 #endif
3631
3632 #if (RTL8723F_SUPPORT == 1)
3633 if (dm->support_ic_type & ODM_RTL8723F)
3634 halrf_tssi_set_de_for_tx_verify_8723f(dm, tssi_de, path);
3635 #endif
3636 }
3637
halrf_query_tssi_value(void * dm_void)3638 u32 halrf_query_tssi_value(void *dm_void)
3639 {
3640 struct dm_struct *dm = (struct dm_struct *)dm_void;
3641
3642 #if (RTL8822C_SUPPORT == 1)
3643 if (dm->support_ic_type & ODM_RTL8822C)
3644 return halrf_query_tssi_value_8822c(dm);
3645 #endif
3646
3647 #if (RTL8814B_SUPPORT == 1)
3648 if (dm->support_ic_type & ODM_RTL8814B)
3649 return halrf_query_tssi_value_8814b(dm);
3650 #endif
3651 return 0;
3652 }
3653
halrf_tssi_cck(void * dm_void)3654 void halrf_tssi_cck(void *dm_void)
3655 {
3656 struct dm_struct *dm = (struct dm_struct *)dm_void;
3657
3658 #if (RTL8822C_SUPPORT == 1)
3659 /*halrf_tssi_cck_8822c(dm);*/
3660 if (dm->support_ic_type & ODM_RTL8822C)
3661 halrf_thermal_cck_8822c(dm);
3662 #endif
3663
3664 }
3665
halrf_thermal_cck(void * dm_void)3666 void halrf_thermal_cck(void *dm_void)
3667 {
3668 struct dm_struct *dm = (struct dm_struct *)dm_void;
3669
3670 #if (RTL8822C_SUPPORT == 1)
3671 if (dm->support_ic_type & ODM_RTL8822C)
3672 halrf_thermal_cck_8822c(dm);
3673 #endif
3674
3675 }
3676
halrf_tssi_set_de(void * dm_void)3677 void halrf_tssi_set_de(void *dm_void)
3678 {
3679 struct dm_struct *dm = (struct dm_struct *)dm_void;
3680
3681 #if (RTL8814B_SUPPORT == 1)
3682 if (dm->support_ic_type & ODM_RTL8814B)
3683 halrf_tssi_set_de_8814b(dm);
3684 #endif
3685 }
3686
halrf_tssi_dck(void * dm_void,u8 direct_do)3687 void halrf_tssi_dck(void *dm_void, u8 direct_do)
3688 {
3689 struct dm_struct *dm = (struct dm_struct *)dm_void;
3690
3691 halrf_rfk_handshake(dm, true);
3692
3693 #if (RTL8814B_SUPPORT == 1)
3694 if (dm->support_ic_type & ODM_RTL8814B) {
3695 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3696 if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
3697 return;
3698 #else
3699 if (dm->rfe_type == 1 || dm->rfe_type == 6)
3700 return;
3701 #endif
3702 halrf_tssi_dck_8814b(dm, direct_do);
3703 }
3704 #endif
3705
3706 #if (RTL8822C_SUPPORT == 1)
3707 if (dm->support_ic_type & ODM_RTL8822C)
3708 halrf_tssi_dck_8822c(dm);
3709 #endif
3710
3711 #if (RTL8812F_SUPPORT == 1)
3712 if (dm->support_ic_type & ODM_RTL8812F)
3713 halrf_tssi_dck_8812f(dm);
3714 #endif
3715
3716 #if (RTL8197G_SUPPORT == 1)
3717 if (dm->support_ic_type == ODM_RTL8197G)
3718 halrf_tssi_dck_8197g(dm);
3719 #endif
3720
3721 halrf_rfk_handshake(dm, false);
3722
3723 }
3724
halrf_calculate_tssi_codeword(void * dm_void)3725 void halrf_calculate_tssi_codeword(void *dm_void)
3726 {
3727 struct dm_struct *dm = (struct dm_struct *)dm_void;
3728
3729 #if (RTL8814B_SUPPORT == 1)
3730 if (dm->support_ic_type & ODM_RTL8814B)
3731 halrf_calculate_tssi_codeword_8814b(dm, RF_PATH_A);
3732 #endif
3733
3734 #if (RTL8822C_SUPPORT == 1)
3735 if (dm->support_ic_type & ODM_RTL8822C)
3736 halrf_calculate_tssi_codeword_8822c(dm);
3737 #endif
3738 }
3739
halrf_set_tssi_codeword(void * dm_void)3740 void halrf_set_tssi_codeword(void *dm_void)
3741 {
3742 struct dm_struct *dm = (struct dm_struct *)dm_void;
3743 struct _hal_rf_ *rf = &dm->rf_table;
3744 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
3745 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
3746 #endif
3747
3748 #if (RTL8814B_SUPPORT == 1)
3749 if (dm->support_ic_type & ODM_RTL8814B)
3750 halrf_set_tssi_codeword_8814b(dm, tssi->tssi_codeword);
3751 #endif
3752
3753 #if (RTL8822C_SUPPORT == 1)
3754 if (dm->support_ic_type & ODM_RTL8822C)
3755 halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);
3756 #endif
3757
3758 }
3759
halrf_get_tssi_codeword_for_txindex(void * dm_void)3760 u8 halrf_get_tssi_codeword_for_txindex(void *dm_void)
3761 {
3762 struct dm_struct *dm = (struct dm_struct *)dm_void;
3763
3764 #if (RTL8814B_SUPPORT == 1)
3765 if (dm->support_ic_type & ODM_RTL8814B) {
3766 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3767 return 80;
3768 #else
3769 return 60;
3770 #endif
3771 }
3772 #endif
3773
3774 #if (RTL8822C_SUPPORT == 1)
3775 if (dm->support_ic_type & ODM_RTL8822C)
3776 return 64;
3777 #endif
3778
3779 #if (RTL8812F_SUPPORT == 1)
3780 if (dm->support_ic_type & ODM_RTL8812F)
3781 return 100;
3782 #endif
3783
3784 #if (RTL8197G_SUPPORT == 1)
3785 if (dm->support_ic_type & ODM_RTL8197G)
3786 return 100;
3787 #endif
3788
3789 return 60;
3790 }
3791
halrf_tssi_clean_de(void * dm_void)3792 void halrf_tssi_clean_de(
3793 void *dm_void)
3794 {
3795 struct dm_struct *dm = (struct dm_struct *)dm_void;
3796
3797 #if (RTL8812F_SUPPORT == 1)
3798 if (dm->support_ic_type & ODM_RTL8812F)
3799 halrf_tssi_clean_de_8812f(dm);
3800 #endif
3801
3802 #if (RTL8814B_SUPPORT == 1)
3803 if (dm->support_ic_type & ODM_RTL8814B)
3804 halrf_tssi_clean_de_8814b(dm);
3805 #endif
3806
3807 #if (RTL8197G_SUPPORT == 1)
3808 if (dm->support_ic_type & ODM_RTL8197G)
3809 halrf_tssi_clean_de_8197g(dm);
3810 #endif
3811
3812 }
3813
halrf_tssi_trigger_de(void * dm_void,u8 path)3814 u32 halrf_tssi_trigger_de(void *dm_void, u8 path)
3815 {
3816 struct dm_struct *dm = (struct dm_struct *)dm_void;
3817
3818 #if (RTL8812F_SUPPORT == 1)
3819 if (dm->support_ic_type & ODM_RTL8812F)
3820 return halrf_tssi_trigger_de_8812f(dm, path);
3821 #endif
3822
3823 #if (RTL8814B_SUPPORT == 1)
3824 if (dm->support_ic_type & ODM_RTL8814B)
3825 return halrf_tssi_trigger_de_8814b(dm, path);
3826 #endif
3827
3828 #if (RTL8197G_SUPPORT == 1)
3829 if (dm->support_ic_type & ODM_RTL8197G)
3830 return halrf_tssi_trigger_de_8197g(dm, path);
3831 #endif
3832 return 0;
3833 }
3834
halrf_tssi_get_de(void * dm_void,u8 path)3835 u32 halrf_tssi_get_de(void *dm_void, u8 path)
3836 {
3837 struct dm_struct *dm = (struct dm_struct *)dm_void;
3838
3839 #if (RTL8822C_SUPPORT == 1)
3840 if (dm->support_ic_type & ODM_RTL8822C)
3841 return halrf_tssi_get_de_8822c(dm, path);
3842 #endif
3843
3844 #if (RTL8812F_SUPPORT == 1)
3845 if (dm->support_ic_type & ODM_RTL8812F)
3846 return halrf_tssi_get_de_8812f(dm, path);
3847 #endif
3848
3849 #if (RTL8814B_SUPPORT == 1)
3850 if (dm->support_ic_type & ODM_RTL8814B)
3851 return halrf_tssi_get_de_8814b(dm, path);
3852 #endif
3853
3854 #if (RTL8197G_SUPPORT == 1)
3855 if (dm->support_ic_type & ODM_RTL8197G)
3856 return halrf_tssi_get_de_8197g(dm, path);
3857 #endif
3858
3859 return 0;
3860 }
3861
halrf_get_online_tssi_de(void * dm_void,u8 path,s32 pout)3862 u32 halrf_get_online_tssi_de(void *dm_void, u8 path, s32 pout)
3863 {
3864 struct dm_struct *dm = (struct dm_struct *)dm_void;
3865
3866 #if (RTL8723F_SUPPORT == 1)
3867 if (dm->support_ic_type & ODM_RTL8723F)
3868 return halrf_get_online_tssi_de_8723f(dm, path, pout);
3869 #endif
3870 return 0;
3871 }
3872
halrf_tssi_trigger(void * dm_void)3873 void halrf_tssi_trigger(void *dm_void)
3874 {
3875 struct dm_struct *dm = (struct dm_struct *)dm_void;
3876 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
3877 struct _hal_rf_ *rf = &(dm->rf_table);
3878
3879 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3880 if (*dm->mp_mode == 1) {
3881 if (cali_info->txpowertrack_control == 0 ||
3882 cali_info->txpowertrack_control == 1) {
3883 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3884 "[TSSI]======>%s MP Mode UI chose thermal tracking. return !!!\n", __func__);
3885 return;
3886 }
3887 } else {
3888 if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
3889 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3890 "[TSSI]======>%s Normal Mode efues is thermal tracking. return !!!\n", __func__);
3891 return;
3892 }
3893 }
3894 #endif
3895
3896 halrf_calculate_tssi_codeword(dm);
3897 halrf_set_tssi_codeword(dm);
3898 halrf_tssi_dck(dm, false);
3899 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3900 halrf_tssi_get_efuse(dm);
3901 #endif
3902 halrf_tssi_set_de(dm);
3903 halrf_do_tssi(dm);
3904 }
3905
halrf_txgapk_write_gain_table(void * dm_void)3906 void halrf_txgapk_write_gain_table(void *dm_void)
3907 {
3908 struct dm_struct *dm = (struct dm_struct *)dm_void;
3909
3910 #if (RTL8822C_SUPPORT == 1)
3911 if (dm->support_ic_type & ODM_RTL8822C)
3912 halrf_txgapk_save_all_tx_gain_table_8822c(dm);
3913 #endif
3914 }
3915
halrf_txgapk_reload_tx_gain(void * dm_void)3916 void halrf_txgapk_reload_tx_gain(void *dm_void)
3917 {
3918 struct dm_struct *dm = (struct dm_struct *)dm_void;
3919
3920 #if (RTL8822C_SUPPORT == 1)
3921 if (dm->support_ic_type & ODM_RTL8822C)
3922 halrf_txgapk_reload_tx_gain_8822c(dm);
3923 #endif
3924 }
3925
halrf_txgap_enable_disable(void * dm_void,u8 enable)3926 void halrf_txgap_enable_disable(void *dm_void, u8 enable)
3927 {
3928 struct dm_struct *dm = (struct dm_struct *)dm_void;
3929 struct _hal_rf_ *rf = &(dm->rf_table);
3930
3931 if (enable) {
3932 rf->rf_supportability = rf->rf_supportability | HAL_RF_TXGAPK;
3933 halrf_txgapk_trigger(dm);
3934 } else {
3935 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TXGAPK;
3936 halrf_txgapk_reload_tx_gain(dm);
3937 }
3938 }
3939
3940 #if (RTL8723F_SUPPORT == 1)
halrf_xtal_thermal_track(void * dm_void)3941 void halrf_xtal_thermal_track(void *dm_void)
3942 {
3943 struct dm_struct *dm = (struct dm_struct *)dm_void;
3944 struct _hal_rf_ *rf = &dm->rf_table;
3945 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
3946 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
3947 s8 *delta_swing_table_xtal_up = NULL;
3948 u8 xtal_offset_eanble = 0, i =0;
3949 s8 thermal_value = 0, thermal_detla = 0;
3950 u8 thermal_base = 0;
3951 s8 xtal_table_up[DELTA_SWINGIDX_SIZE] = {0};
3952 s8 xtal_table_down[DELTA_SWINGIDX_SIZE] = {0};
3953 u32 reg_val = 0, crystal_cap = 0;
3954
3955 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3956 "[RF][xtal] ======>%s\n", __func__);
3957
3958 if ( dm->support_ic_type == ODM_RTL8723F) {
3959 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
3960 dm->is_psd_in_process || rf->is_tssi_in_progress ||
3961 !(rf->rf_supportability & HAL_RF_DPK_TRACK) ||
3962 rf->is_txgapk_in_progress)
3963 return;
3964
3965 if(tssi->thermal[0] == 0xff) {
3966 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal 0xFF, return!\n");
3967 return;
3968 } else {
3969 thermal_base = tssi->thermal[0];
3970 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal_base = 0x%x\n", thermal_base);
3971 }
3972
3973 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal_base = 0x%x\n", thermal_base);
3974
3975 thermal_value = (s8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x42, 0x7E); /* 0x42: RF Reg[6:1]*/
3976
3977 thermal_detla = (s8)(thermal_value - thermal_base);
3978
3979 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] cali_info->xtal_offset = 0x%x\n", cali_info->xtal_offset);
3980
3981 cali_info->xtal_offset_last = cali_info->xtal_offset;
3982 /*
3983 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3984 "[RF][Xtal] cali_info->delta_swing_table_xtal_p = %d\n", cali_info->delta_swing_table_xtal_p[2]);
3985 */
3986 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3987 "[RF][Xtal] thermal_value = 0x%x, thermal_detla = 0x%x, xtal_offset_last = 0x%x\n",
3988 thermal_value, thermal_detla, cali_info->xtal_offset_last);
3989 odm_move_memory(dm, xtal_table_up, cali_info->delta_swing_table_xtal_p, sizeof(xtal_table_up));//(void *)
3990 odm_move_memory(dm, xtal_table_down, cali_info->delta_swing_table_xtal_n, sizeof(xtal_table_down));
3991 /*
3992 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3993 "[RF][Xtal] xtal_table_up[1] = %d\n", xtal_table_up[1]);*/
3994 if(thermal_detla < 0) {
3995
3996 if (thermal_detla < -29)
3997 i = 29;
3998 else
3999 i = (u8)(-1 * thermal_detla);
4000 cali_info->xtal_offset = xtal_table_down[i];
4001 } else {
4002
4003 if (thermal_detla >= 30)
4004 i = 29;
4005 else
4006 i = thermal_detla;
4007
4008 cali_info->xtal_offset = xtal_table_up[i];
4009 }
4010
4011 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4012 "[RF][Xtal] xtal_offset = %d\n", cali_info->xtal_offset);
4013 if (cali_info->xtal_offset_last == cali_info->xtal_offset)
4014 xtal_offset_eanble = 0;
4015 else
4016 xtal_offset_eanble = 1;
4017 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4018 "[RF][Xtal] xtal_offset_eanble = %d\n", xtal_offset_eanble);
4019 if (xtal_offset_eanble != 0) {
4020 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
4021 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4022 "[RF][Xtal] R_0x103c[16:10] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x0001FC00));
4023
4024 crystal_cap = dm->dm_cfo_track.crystal_cap_default & 0x7F;
4025 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4026 "[RF][Xtal] DEFAULT crystal_cap = 0x%x\n", crystal_cap);
4027 reg_val = crystal_cap + cali_info->xtal_offset;
4028 //reg_val = (u32)(odm_get_mac_reg(dm, R_0x103c, 0x0001FC00) + cali_info->xtal_offset);
4029 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4030 "[RF][Xtal] reg_val = 0x%x\n", reg_val);
4031 /* write 0x103c[23:17] = 0x103c[16:10] = crystal_cap */
4032 crystal_cap = reg_val | (reg_val << 7);
4033 odm_set_mac_reg(dm, R_0x103c, 0x00FFFC00, crystal_cap);
4034 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4035 "[RF][Xtal] R_0x103c[16:10] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x0001FC00));
4036 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4037 "[RF][Xtal] R_0x103c[23:17] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x00FE0000));
4038 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
4039 }
4040 //odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, 0x30000, 0x3);
4041 //delay
4042 }
4043 /*RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4044 "[RF][xtal] <======%s\n", __func__);*/
4045 }
4046 #endif
4047
_halrf_dump_subpage(void * dm_void,u32 * _used,char * output,u32 * _out_len,u8 page)4048 void _halrf_dump_subpage(void *dm_void, u32 *_used, char *output, u32 *_out_len, u8 page)
4049 {
4050 struct dm_struct *dm = (struct dm_struct *)dm_void;
4051
4052 u32 used = *_used;
4053 u32 out_len = *_out_len;
4054 u32 addr;
4055
4056 PDM_SNPF(out_len, used, output + used, out_len - used,
4057 "\n===============[ Subpage_%d start]===============\n", page);
4058
4059 RF_DBG(dm, DBG_RF_RFK, " ===============[ Subpage_%d start]===============\n", page);
4060
4061 odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), page);
4062
4063 for (addr = 0x1b00; addr < 0x1c00; addr += 0x10) {
4064 PDM_SNPF(out_len, used, output + used, out_len - used,
4065 " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
4066 odm_get_bb_reg(dm, addr, MASKDWORD),
4067 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
4068 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
4069 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
4070 RF_DBG(dm, DBG_RF_RFK, " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
4071 odm_get_bb_reg(dm, addr, MASKDWORD),
4072 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
4073 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
4074 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
4075 }
4076
4077 *_used = used;
4078 *_out_len = out_len;
4079 }
4080
halrf_dump_rfk_reg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)4081 void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
4082 char *output, u32 *_out_len)
4083 {
4084 struct dm_struct *dm = (struct dm_struct *)dm_void;
4085 struct _hal_rf_ *rf = &dm->rf_table;
4086
4087 char help[] = "-h";
4088 u32 var1[10] = {0};
4089 u32 used = *_used;
4090 u32 out_len = *_out_len;
4091 u32 reg_1b00, supportability;
4092 u8 page;
4093
4094 if (!(dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES))) {
4095 PDM_SNPF(out_len, used, output + used, out_len - used,
4096 "CMD is Unsupported due to IC type!!!\n");
4097 RF_DBG(dm, DBG_RF_RFK, "[RFK] CMD is Unsupported due to IC type!!!\n");
4098 return;
4099 } else if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
4100 dm->is_psd_in_process || rf->is_tssi_in_progress || rf->is_txgapk_in_progress) {
4101 PDM_SNPF(out_len, used, output + used, out_len - used,
4102 "Bypass CMD due to RFK is doing!!!\n");
4103 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to RFK is doing!!!\n");
4104 return;
4105 }
4106
4107 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4108 if (*dm->is_fcs_mode_enable) {
4109 PDM_SNPF(out_len, used, output + used, out_len - used,
4110 "Bypass CMD due to FCS mode!!!\n");
4111 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to FCS mode!!!\n");
4112 return;
4113 }
4114 #endif
4115 supportability = rf->rf_supportability;
4116
4117 /*to avoid DPK track interruption*/
4118 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
4119
4120 reg_1b00 = odm_get_bb_reg(dm, R_0x1b00, MASKDWORD);
4121
4122 if (input[2])
4123 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[0]);
4124
4125 if ((strcmp(input[2], help) == 0))
4126 PDM_SNPF(out_len, used, output + used, out_len - used,
4127 "dump subpage {0:Page0, 1:Page1, 2:Page2, 3:Page3, 4:all}\n");
4128 else if (var1[0] > 4)
4129 PDM_SNPF(out_len, used, output + used, out_len - used,
4130 "Wrong subpage number!!\n");
4131 else if (var1[0] == 4) {
4132 for (page = 0; page < 4; page++)
4133 _halrf_dump_subpage(dm, &used, output, &out_len, page);
4134 } else
4135 _halrf_dump_subpage(dm, &used, output, &out_len, (u8)var1[0]);
4136
4137 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, reg_1b00);
4138
4139 rf->rf_supportability = supportability;
4140
4141 *_used = used;
4142 *_out_len = out_len;
4143 }
4144
4145 /*Golbal function*/
halrf_reload_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)4146 void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
4147 {
4148 struct dm_struct *dm = (struct dm_struct *)dm_void;
4149 u32 i;
4150
4151 for (i = 0; i < num; i++)
4152 odm_write_4byte(dm, bp_reg[i], bp[i]);
4153 }
4154
halrf_reload_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)4155 void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
4156 u8 ss)
4157 {
4158 struct dm_struct *dm = (struct dm_struct *)dm_void;
4159 u32 i, path;
4160
4161 for (i = 0; i < num; i++) {
4162 for (path = 0; path < ss; path++)
4163 odm_set_rf_reg(dm, (enum rf_path)path, bp_reg[i],
4164 MASK20BITS, bp[i][path]);
4165 }
4166 }
4167
halrf_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)4168 void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
4169 {
4170 struct dm_struct *dm = (struct dm_struct *)dm_void;
4171 u32 i;
4172
4173 for (i = 0; i < num; i++)
4174 bp[i] = odm_read_4byte(dm, bp_reg[i]);
4175 }
4176
halrf_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)4177 void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss)
4178 {
4179 struct dm_struct *dm = (struct dm_struct *)dm_void;
4180 u32 i, path;
4181
4182 for (i = 0; i < num; i++) {
4183 for (path = 0; path < ss; path++) {
4184 bp[i][path] =
4185 odm_get_rf_reg(dm, (enum rf_path)path,
4186 bp_reg[i], MASK20BITS);
4187 }
4188 }
4189 }
4190
halrf_swap(void * dm_void,u32 * v1,u32 * v2)4191 void halrf_swap(void *dm_void, u32 *v1, u32 *v2)
4192 {
4193 struct dm_struct *dm = (struct dm_struct *)dm_void;
4194 u32 temp;
4195
4196 temp = *v1;
4197 *v1 = *v2;
4198 *v2 = temp;
4199 }
4200
halrf_bubble(void * dm_void,u32 * v1,u32 * v2)4201 void halrf_bubble(void *dm_void, u32 *v1, u32 *v2)
4202 {
4203 struct dm_struct *dm = (struct dm_struct *)dm_void;
4204 u32 temp;
4205
4206 if (*v1 >= 0x200 && *v2 >= 0x200) {
4207 if (*v1 > *v2)
4208 halrf_swap(dm, v1, v2);
4209 } else if (*v1 < 0x200 && *v2 < 0x200) {
4210 if (*v1 > *v2)
4211 halrf_swap(dm, v1, v2);
4212 } else if (*v1 < 0x200 && *v2 >= 0x200) {
4213 halrf_swap(dm, v1, v2);
4214 }
4215 }
4216
halrf_b_sort(void * dm_void,u32 * iv,u32 * qv)4217 void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv)
4218 {
4219 struct dm_struct *dm = (struct dm_struct *)dm_void;
4220 u32 temp;
4221 u32 i, j;
4222
4223 RF_DBG(dm, DBG_RF_DACK, "[DACK]bubble!!!!!!!!!!!!");
4224 for (i = 0; i < SN - 1; i++) {
4225 for (j = 0; j < (SN - 1 - i) ; j++) {
4226 halrf_bubble(dm, &iv[j], &iv[j + 1]);
4227 halrf_bubble(dm, &qv[j], &qv[j + 1]);
4228 }
4229 }
4230 }
4231
halrf_minmax_compare(void * dm_void,u32 value,u32 * min,u32 * max)4232 void halrf_minmax_compare(void *dm_void, u32 value, u32 *min,
4233 u32 *max)
4234 {
4235 struct dm_struct *dm = (struct dm_struct *)dm_void;
4236
4237 if (value >= 0x200) {
4238 if (*min >= 0x200) {
4239 if (*min > value)
4240 *min = value;
4241 } else {
4242 *min = value;
4243 }
4244 if (*max >= 0x200) {
4245 if (*max < value)
4246 *max = value;
4247 }
4248 } else {
4249 if (*min < 0x200) {
4250 if (*min > value)
4251 *min = value;
4252 }
4253
4254 if (*max >= 0x200) {
4255 *max = value;
4256 } else {
4257 if (*max < value)
4258 *max = value;
4259 }
4260 }
4261 }
4262
halrf_delta(void * dm_void,u32 v1,u32 v2)4263 u32 halrf_delta(void *dm_void, u32 v1, u32 v2)
4264 {
4265 struct dm_struct *dm = (struct dm_struct *)dm_void;
4266
4267 if (v1 >= 0x200 && v2 >= 0x200) {
4268 if (v1 > v2)
4269 return v1 - v2;
4270 else
4271 return v2 - v1;
4272 } else if (v1 >= 0x200 && v2 < 0x200) {
4273 return v2 + (0x400 - v1);
4274 } else if (v1 < 0x200 && v2 >= 0x200) {
4275 return v1 + (0x400 - v2);
4276 }
4277
4278 if (v1 > v2)
4279 return v1 - v2;
4280 else
4281 return v2 - v1;
4282 }
4283
halrf_compare(void * dm_void,u32 value)4284 boolean halrf_compare(void *dm_void, u32 value)
4285 {
4286 struct dm_struct *dm = (struct dm_struct *)dm_void;
4287
4288 boolean fail = false;
4289
4290 if (value >= 0x200 && (0x400 - value) > 0x64)
4291 fail = true;
4292 else if (value < 0x200 && value > 0x64)
4293 fail = true;
4294
4295 if (fail)
4296 RF_DBG(dm, DBG_RF_DACK, "[DACK]overflow!!!!!!!!!!!!!!!");
4297 return fail;
4298 }
4299
halrf_mode(void * dm_void,u32 * i_value,u32 * q_value)4300 void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value)
4301 {
4302 struct dm_struct *dm = (struct dm_struct *)dm_void;
4303 u32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;
4304 u32 p, m, t;
4305 u32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;
4306 u32 i_delta, q_delta;
4307 u8 i, j, ii = 0, qi = 0;
4308 boolean fail = false;
4309
4310 ODM_delay_ms(10);
4311 for (i = 0; i < SN; i++) {
4312 im[i] = 0;
4313 qm[i] = 0;
4314 }
4315 i = 0;
4316 c = 0;
4317 while (i < SN && c < 1000) {
4318 c++;
4319 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4320 iv[i] = (temp & 0x3ff000) >> 12;
4321 qv[i] = temp & 0x3ff;
4322
4323 fail = false;
4324 if (halrf_compare(dm, iv[i]))
4325 fail = true;
4326 if (halrf_compare(dm, qv[i]))
4327 fail = true;
4328 if (!fail)
4329 i++;
4330 }
4331 c = 0;
4332 do {
4333 c++;
4334 i_min = iv[0];
4335 i_max = iv[0];
4336 q_min = qv[0];
4337 q_max = qv[0];
4338 for (i = 0; i < SN; i++) {
4339 halrf_minmax_compare(dm, iv[i], &i_min, &i_max);
4340 halrf_minmax_compare(dm, qv[i], &q_min, &q_max);
4341 }
4342 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_min=0x%x, i_max=0x%x",
4343 i_min, i_max);
4344 RF_DBG(dm, DBG_RF_DACK, "[DACK]q_min=0x%x, q_max=0x%x",
4345 q_min, q_max);
4346 if (i_max < 0x200 && i_min < 0x200)
4347 i_delta = i_max - i_min;
4348 else if (i_max >= 0x200 && i_min >= 0x200)
4349 i_delta = i_max - i_min;
4350 else
4351 i_delta = i_max + (0x400 - i_min);
4352
4353 if (q_max < 0x200 && q_min < 0x200)
4354 q_delta = q_max - q_min;
4355 else if (q_max >= 0x200 && q_min >= 0x200)
4356 q_delta = q_max - q_min;
4357 else
4358 q_delta = q_max + (0x400 - q_min);
4359 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_delta=0x%x, q_delta=0x%x",
4360 i_delta, q_delta);
4361 halrf_b_sort(dm, iv, qv);
4362 if (i_delta > 5 || q_delta > 5) {
4363 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4364 iv[0] = (temp & 0x3ff000) >> 12;
4365 qv[0] = temp & 0x3ff;
4366 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4367 iv[SN - 1] = (temp & 0x3ff000) >> 12;
4368 qv[SN - 1] = temp & 0x3ff;
4369 } else {
4370 break;
4371 }
4372 } while (c < 100);
4373 #if 1
4374 #if 0
4375 for (i = 0; i < SN; i++)
4376 RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
4377 for (i = 0; i < SN; i++)
4378 RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
4379 #endif
4380 /*i*/
4381 m = 0;
4382 p = 0;
4383 for (i = 10; i < SN - 10; i++) {
4384 if (iv[i] > 0x200)
4385 m = (0x400 - iv[i]) + m;
4386 else
4387 p = iv[i] + p;
4388 }
4389
4390 if (p > m) {
4391 t = p - m;
4392 t = t / (SN - 20);
4393 } else {
4394 t = m - p;
4395 t = t / (SN - 20);
4396 if (t != 0x0)
4397 t = 0x400 - t;
4398 }
4399 *i_value = t;
4400 /*q*/
4401 m = 0;
4402 p = 0;
4403 for (i = 10; i < SN - 10; i++) {
4404 if (qv[i] > 0x200)
4405 m = (0x400 - qv[i]) + m;
4406 else
4407 p = qv[i] + p;
4408 }
4409 if (p > m) {
4410 t = p - m;
4411 t = t / (SN - 20);
4412 } else {
4413 t = m - p;
4414 t = t / (SN - 20);
4415 if (t != 0x0)
4416 t = 0x400 - t;
4417 }
4418 *q_value = t;
4419 #endif
4420 }
halrf_delay_10us(u16 v1)4421 void halrf_delay_10us(u16 v1)
4422 {
4423 u16 i = 0;
4424
4425 for (i = 0; i < v1; i++)
4426 ODM_delay_us(10);
4427 }
4428
4429