1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __COMMON_C2H_H__ 16*4882a593Smuzhiyun #define __COMMON_C2H_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define C2H_TYPE_REG 0 19*4882a593Smuzhiyun #define C2H_TYPE_PKT 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * C2H event format: 23*4882a593Smuzhiyun * Fields TRIGGER PAYLOAD SEQ PLEN ID 24*4882a593Smuzhiyun * BITS [127:120] [119:16] [15:8] [7:4] [3:0] 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define C2H_ID(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4) 27*4882a593Smuzhiyun #define C2H_PLEN(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4) 28*4882a593Smuzhiyun #define C2H_SEQ(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8) 29*4882a593Smuzhiyun #define C2H_PAYLOAD(_c2h) (((u8*)(_c2h)) + 2) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define SET_C2H_ID(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val) 32*4882a593Smuzhiyun #define SET_C2H_PLEN(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val) 33*4882a593Smuzhiyun #define SET_C2H_SEQ(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * C2H event format: 37*4882a593Smuzhiyun * Fields TRIGGER PLEN PAYLOAD SEQ ID 38*4882a593Smuzhiyun * BITS [127:120] [119:112] [111:16] [15:8] [7:0] 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define C2H_ID_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8) 41*4882a593Smuzhiyun #define C2H_SEQ_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8) 42*4882a593Smuzhiyun #define C2H_PAYLOAD_88XX(_c2h) (((u8*)(_c2h)) + 2) 43*4882a593Smuzhiyun #define C2H_PLEN_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8) 44*4882a593Smuzhiyun #define C2H_TRIGGER_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define SET_C2H_ID_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val) 47*4882a593Smuzhiyun #define SET_C2H_SEQ_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val) 48*4882a593Smuzhiyun #define SET_C2H_PLEN_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun typedef enum _C2H_EVT { 51*4882a593Smuzhiyun C2H_DBG = 0x00, 52*4882a593Smuzhiyun C2H_LB = 0x01, 53*4882a593Smuzhiyun C2H_TXBF = 0x02, 54*4882a593Smuzhiyun C2H_CCX_TX_RPT = 0x03, 55*4882a593Smuzhiyun C2H_AP_REQ_TXRPT = 0x04, 56*4882a593Smuzhiyun C2H_FW_SCAN_COMPLETE = 0x7, 57*4882a593Smuzhiyun C2H_BT_INFO = 0x09, 58*4882a593Smuzhiyun C2H_BT_MP_INFO = 0x0B, 59*4882a593Smuzhiyun C2H_RA_RPT = 0x0C, 60*4882a593Smuzhiyun C2H_SPC_STAT = 0x0D, 61*4882a593Smuzhiyun C2H_RA_PARA_RPT = 0x0E, 62*4882a593Smuzhiyun C2H_FW_CHNL_SWITCH_COMPLETE = 0x10, 63*4882a593Smuzhiyun C2H_IQK_FINISH = 0x11, 64*4882a593Smuzhiyun C2H_MAILBOX_STATUS = 0x15, 65*4882a593Smuzhiyun C2H_P2P_RPORT = 0x16, 66*4882a593Smuzhiyun C2H_MCC = 0x17, 67*4882a593Smuzhiyun C2H_MAC_HIDDEN_RPT = 0x19, 68*4882a593Smuzhiyun C2H_MAC_HIDDEN_RPT_2 = 0x1A, 69*4882a593Smuzhiyun C2H_BCN_EARLY_RPT = 0x1E, 70*4882a593Smuzhiyun C2H_DEFEATURE_DBG = 0x22, 71*4882a593Smuzhiyun C2H_CUSTOMER_STR_RPT = 0x24, 72*4882a593Smuzhiyun C2H_CUSTOMER_STR_RPT_2 = 0x25, 73*4882a593Smuzhiyun C2H_WLAN_INFO = 0x27, 74*4882a593Smuzhiyun #ifdef RTW_PER_CMD_SUPPORT_FW 75*4882a593Smuzhiyun C2H_PER_RATE_RPT = 0x2c, 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun C2H_LPS_STATUS_RPT = 0x32, 78*4882a593Smuzhiyun C2H_SET_TXPWR_FINISH = 0x70, 79*4882a593Smuzhiyun C2H_DEFEATURE_RSVD = 0xFD, 80*4882a593Smuzhiyun C2H_EXTEND = 0xff, 81*4882a593Smuzhiyun } C2H_EVT; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun typedef enum _EXTEND_C2H_EVT { 84*4882a593Smuzhiyun EXTEND_C2H_DBG_PRINT = 0 85*4882a593Smuzhiyun } EXTEND_C2H_EVT; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define C2H_REG_LEN 16 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* C2H_IQK_FINISH, 0x11 */ 90*4882a593Smuzhiyun #define IQK_OFFLOAD_LEN 1 91*4882a593Smuzhiyun void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len); 92*4882a593Smuzhiyun int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms); 93*4882a593Smuzhiyun #define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #ifdef CONFIG_RTW_MAC_HIDDEN_RPT 96*4882a593Smuzhiyun /* C2H_MAC_HIDDEN_RPT, 0x19 */ 97*4882a593Smuzhiyun #define MAC_HIDDEN_RPT_LEN 8 98*4882a593Smuzhiyun int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* C2H_MAC_HIDDEN_RPT_2, 0x1A */ 101*4882a593Smuzhiyun #define MAC_HIDDEN_RPT_2_LEN 5 102*4882a593Smuzhiyun int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); 103*4882a593Smuzhiyun int hal_read_mac_hidden_rpt(_adapter *adapter); 104*4882a593Smuzhiyun #else 105*4882a593Smuzhiyun #define hal_read_mac_hidden_rpt(adapter) _SUCCESS 106*4882a593Smuzhiyun #endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* C2H_DEFEATURE_DBG, 0x22 */ 109*4882a593Smuzhiyun #define DEFEATURE_DBG_LEN 1 110*4882a593Smuzhiyun int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #ifdef CONFIG_RTW_CUSTOMER_STR 113*4882a593Smuzhiyun /* C2H_CUSTOMER_STR_RPT, 0x24 */ 114*4882a593Smuzhiyun #define CUSTOMER_STR_RPT_LEN 8 115*4882a593Smuzhiyun int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* C2H_CUSTOMER_STR_RPT_2, 0x25 */ 118*4882a593Smuzhiyun #define CUSTOMER_STR_RPT_2_LEN 8 119*4882a593Smuzhiyun int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); 120*4882a593Smuzhiyun #endif /* CONFIG_RTW_CUSTOMER_STR */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #ifdef RTW_PER_CMD_SUPPORT_FW 123*4882a593Smuzhiyun /* C2H_PER_RATE_RPT, 0x2c */ 124*4882a593Smuzhiyun int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len); 125*4882a593Smuzhiyun #endif 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #ifdef CONFIG_LPS_ACK 128*4882a593Smuzhiyun /* C2H_LPS_STATUS_RPT, 0x32 */ 129*4882a593Smuzhiyun #define LPS_STATUS_RPT_LEN 2 130*4882a593Smuzhiyun int c2h_lps_status_rpt(PADAPTER adapter, u8 *data, u8 len); 131*4882a593Smuzhiyun #endif /* CONFIG_LPS_ACK */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX 134*4882a593Smuzhiyun /* C2H_SET_TXPWR_FINISH, 0x70 */ 135*4882a593Smuzhiyun #define SET_TXPWR_FINISH_LEN 1 136*4882a593Smuzhiyun void c2h_txpwr_idx_offload_done(_adapter *adapter, u8 *data, u8 len); 137*4882a593Smuzhiyun int c2h_txpwr_idx_offload_wait(_adapter *adapter); 138*4882a593Smuzhiyun #endif 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun void rtw_hal_bcn_early_rpt_c2h_handler(_adapter *adapter); 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif /* __COMMON_C2H_H__ */ 143