1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTW_MP_C_
16 #include <drv_types.h>
17 #ifdef PLATFORM_FREEBSD
18 #include <sys/unistd.h> /* for RFHIGHPID */
19 #endif
20
21 #include "../hal/phydm/phydm_precomp.h"
22 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
23 #include <rtw_bt_mp.h>
24 #endif
25
26 #ifdef CONFIG_MP_VHT_HW_TX_MODE
27 #define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
28 #define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
29 #define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
30
rtfloor(float x)31 int rtfloor(float x)
32 {
33 int i = x - 2;
34 while
35 (++i <= x - 1)
36 ;
37 return i;
38 }
39 #endif
40
41 #ifdef CONFIG_MP_INCLUDED
read_macreg(_adapter * padapter,u32 addr,u32 sz)42 u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
43 {
44 u32 val = 0;
45
46 switch (sz) {
47 case 1:
48 val = rtw_read8(padapter, addr);
49 break;
50 case 2:
51 val = rtw_read16(padapter, addr);
52 break;
53 case 4:
54 val = rtw_read32(padapter, addr);
55 break;
56 default:
57 val = 0xffffffff;
58 break;
59 }
60
61 return val;
62
63 }
64
write_macreg(_adapter * padapter,u32 addr,u32 val,u32 sz)65 void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
66 {
67 switch (sz) {
68 case 1:
69 rtw_write8(padapter, addr, (u8)val);
70 break;
71 case 2:
72 rtw_write16(padapter, addr, (u16)val);
73 break;
74 case 4:
75 rtw_write32(padapter, addr, val);
76 break;
77 default:
78 break;
79 }
80
81 }
82
read_bbreg(_adapter * padapter,u32 addr,u32 bitmask)83 u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
84 {
85 return rtw_hal_read_bbreg(padapter, addr, bitmask);
86 }
87
write_bbreg(_adapter * padapter,u32 addr,u32 bitmask,u32 val)88 void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
89 {
90 rtw_hal_write_bbreg(padapter, addr, bitmask, val);
91 }
92
_read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask)93 u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
94 {
95 return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
96 }
97
_write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask,u32 val)98 void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
99 {
100 rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
101 }
102
read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr)103 u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
104 {
105 return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
106 }
107
write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 val)108 void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
109 {
110 _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
111 }
112
_init_mp_priv_(struct mp_priv * pmp_priv)113 static void _init_mp_priv_(struct mp_priv *pmp_priv)
114 {
115 WLAN_BSSID_EX *pnetwork;
116
117 _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
118
119 pmp_priv->mode = MP_OFF;
120
121 pmp_priv->channel = 1;
122 pmp_priv->bandwidth = CHANNEL_WIDTH_20;
123 pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
124 pmp_priv->rateidx = RATE_1M;
125 pmp_priv->txpoweridx = 0x2A;
126
127 pmp_priv->antenna_tx = ANTENNA_A;
128 pmp_priv->antenna_rx = ANTENNA_AB;
129
130 pmp_priv->check_mp_pkt = 0;
131
132 pmp_priv->tx_pktcount = 0;
133
134 pmp_priv->rx_bssidpktcount = 0;
135 pmp_priv->rx_pktcount = 0;
136 pmp_priv->rx_crcerrpktcount = 0;
137
138 pmp_priv->network_macaddr[0] = 0x00;
139 pmp_priv->network_macaddr[1] = 0xE0;
140 pmp_priv->network_macaddr[2] = 0x4C;
141 pmp_priv->network_macaddr[3] = 0x87;
142 pmp_priv->network_macaddr[4] = 0x66;
143 pmp_priv->network_macaddr[5] = 0x55;
144
145 pmp_priv->bSetRxBssid = _FALSE;
146 pmp_priv->bRTWSmbCfg = _FALSE;
147 pmp_priv->bloopback = _FALSE;
148
149 pmp_priv->bloadefusemap = _FALSE;
150 pmp_priv->brx_filter_beacon = _FALSE;
151 pmp_priv->mplink_brx = _FALSE;
152
153 pnetwork = &pmp_priv->mp_network.network;
154 _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
155
156 pnetwork->Ssid.SsidLength = 8;
157 _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
158
159 pmp_priv->tx.payload = MP_TX_Payload_default_random;
160 #ifdef CONFIG_80211N_HT
161 pmp_priv->tx.attrib.ht_en = 1;
162 #endif
163
164 pmp_priv->mpt_ctx.mpt_rate_index = 1;
165
166 }
167
168
mp_init_xmit_attrib(struct mp_tx * pmptx,PADAPTER padapter)169 static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
170 {
171 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
172
173 struct pkt_attrib *pattrib;
174
175 /* init xmitframe attribute */
176 pattrib = &pmptx->attrib;
177 _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
178 _rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
179
180 pattrib->ether_type = 0x8712;
181 #if 0
182 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
183 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
184 #endif
185 _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
186
187 /* pattrib->dhcp_pkt = 0;
188 * pattrib->pktlen = 0; */
189 pattrib->ack_policy = 0;
190 /* pattrib->pkt_hdrlen = ETH_HLEN; */
191 pattrib->hdrlen = WLAN_HDR_A3_LEN;
192 pattrib->subtype = WIFI_DATA;
193 pattrib->priority = 0;
194 pattrib->qsel = pattrib->priority;
195 /* do_queue_select(padapter, pattrib); */
196 pattrib->nr_frags = 1;
197 pattrib->encrypt = 0;
198 pattrib->bswenc = _FALSE;
199 pattrib->qos_en = _FALSE;
200
201 pattrib->pktlen = 1500;
202
203 if (pHalData->rf_type == RF_2T2R)
204 pattrib->raid = RATEID_IDX_BGN_40M_2SS;
205 else
206 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
207
208 #ifdef CONFIG_80211AC_VHT
209 if (pHalData->rf_type == RF_1T1R)
210 pattrib->raid = RATEID_IDX_VHT_1SS;
211 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
212 pattrib->raid = RATEID_IDX_VHT_2SS;
213 else if (pHalData->rf_type == RF_3T3R)
214 pattrib->raid = RATEID_IDX_VHT_3SS;
215 else
216 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
217 #endif
218 }
219
init_mp_priv(PADAPTER padapter)220 s32 init_mp_priv(PADAPTER padapter)
221 {
222 struct mp_priv *pmppriv = &padapter->mppriv;
223 PHAL_DATA_TYPE pHalData;
224
225 pHalData = GET_HAL_DATA(padapter);
226
227 _init_mp_priv_(pmppriv);
228 pmppriv->papdater = padapter;
229 if (IS_HARDWARE_TYPE_8822C(padapter))
230 pmppriv->mp_dm = 1;/* default enable dpk tracking */
231 else
232 pmppriv->mp_dm = 0;
233
234 pmppriv->tx.stop = 1;
235 pmppriv->bSetTxPower = 0; /*for manually set tx power*/
236 pmppriv->bTxBufCkFail = _FALSE;
237 pmppriv->pktInterval = 0;
238 pmppriv->pktLength = 1000;
239 pmppriv->bprocess_mp_mode = _FALSE;
240 pmppriv->efuse_update_file= _FALSE;
241 pmppriv->efuse_update_on = _FALSE;
242
243 mp_init_xmit_attrib(&pmppriv->tx, padapter);
244
245 switch (GET_HAL_RFPATH(padapter)) {
246 case RF_1T1R:
247 pmppriv->antenna_tx = ANTENNA_A;
248 pmppriv->antenna_rx = ANTENNA_A;
249 break;
250 case RF_1T2R:
251 default:
252 pmppriv->antenna_tx = ANTENNA_A;
253 pmppriv->antenna_rx = ANTENNA_AB;
254 break;
255 case RF_2T2R:
256 pmppriv->antenna_tx = ANTENNA_AB;
257 pmppriv->antenna_rx = ANTENNA_AB;
258 break;
259 case RF_2T4R:
260 pmppriv->antenna_tx = ANTENNA_BC;
261 pmppriv->antenna_rx = ANTENNA_ABCD;
262 break;
263 }
264
265 pHalData->AntennaRxPath = pmppriv->antenna_rx;
266 pHalData->antenna_tx_path = pmppriv->antenna_tx;
267
268 return _SUCCESS;
269 }
270
free_mp_priv(struct mp_priv * pmp_priv)271 void free_mp_priv(struct mp_priv *pmp_priv)
272 {
273 if (pmp_priv->pallocated_mp_xmitframe_buf) {
274 rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
275 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
276 }
277 pmp_priv->pmp_xmtframe_buf = NULL;
278 }
279
280 #if 0
281 static void PHY_IQCalibrate_default(
282 PADAPTER pAdapter,
283 BOOLEAN bReCovery
284 )
285 {
286 RTW_INFO("%s\n", __func__);
287 }
288
289 static void PHY_LCCalibrate_default(
290 PADAPTER pAdapter
291 )
292 {
293 RTW_INFO("%s\n", __func__);
294 }
295
296 static void PHY_SetRFPathSwitch_default(
297 PADAPTER pAdapter,
298 BOOLEAN bMain
299 )
300 {
301 RTW_INFO("%s\n", __func__);
302 }
303 #endif
304
mpt_InitHWConfig(PADAPTER Adapter)305 void mpt_InitHWConfig(PADAPTER Adapter)
306 {
307 PHAL_DATA_TYPE hal;
308
309 hal = GET_HAL_DATA(Adapter);
310
311 if (IS_HARDWARE_TYPE_8723B(Adapter)) {
312 /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
313 /* TODO: A better solution is configure it according EFUSE during the run-time. */
314
315 phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */
316 phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */
317 phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */
318 phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */
319 phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */
320 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */
321 phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */
322 phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */
323 phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
324
325 /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
326 phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */
327 phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
328 phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */
329
330 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
331 phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/
332 } else if (IS_HARDWARE_TYPE_8821(Adapter)) {
333 /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
334 <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/
335 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/
336 phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/
337 } else if (IS_HARDWARE_TYPE_8188ES(Adapter))
338 phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
339 #ifdef CONFIG_RTL8814A
340 else if (IS_HARDWARE_TYPE_8814A(Adapter))
341 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
342 #endif
343
344 #ifdef CONFIG_RTL8812A
345 else if (IS_HARDWARE_TYPE_8812(Adapter)) {
346 rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
347 rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
348 }
349 #endif
350
351
352 #ifdef CONFIG_RTL8822B
353 else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
354 u32 tmp_reg = 0;
355
356 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
357 /* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
358 phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
359 RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
360 phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
361 RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
362 phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
363 RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
364 }
365 #endif /* CONFIG_RTL8822B */
366 #ifdef CONFIG_RTL8821C
367 else if (IS_HARDWARE_TYPE_8821C(Adapter))
368 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
369 #endif /* CONFIG_RTL8821C */
370 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
371 else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
372 if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
373 RTW_INFO("%s() Active large power detection\n", __func__);
374 phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
375 }
376 }
377 #endif
378 #if defined(CONFIG_RTL8822C)
379 else if( IS_HARDWARE_TYPE_8822C(Adapter)) {
380 rtw_write16(Adapter, REG_RXFLTMAP1_8822C, 0x2000);
381 /* 0x7D8[31] : time out enable when cca is not assert
382 0x60D[7:0] : time out value (Unit : us)*/
383 rtw_write8(Adapter, 0x7db, 0xc0);
384 RTW_INFO(" 0x7d8 = 0x%x\n", rtw_read8(Adapter, 0x7d8));
385 rtw_write8(Adapter, 0x60d, 0x0c);
386 RTW_INFO(" 0x60d = 0x%x\n", rtw_read8(Adapter, 0x60d));
387 phy_set_bb_reg(Adapter, 0x1c44, BIT10, 0x1);
388 RTW_INFO(" 0x1c44 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1c44, bMaskDWord));
389 }
390 #endif
391 #if defined(CONFIG_RTL8814B)
392 else if(IS_HARDWARE_TYPE_8814B(Adapter))
393 {
394 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814B, 0x2000);
395 }
396 #endif
397 #if defined(CONFIG_RTL8723F)
398 /* todo: 8723F not verify yet */
399 else if (IS_HARDWARE_TYPE_8723F(Adapter)) {
400 /* 8723F mac is similar with 8723D,
401 * but can't find 8723D here.
402 */
403 }
404 #endif
405 }
406
PHY_IQCalibrate(PADAPTER padapter,u8 bReCovery)407 static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
408 {
409 halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
410 }
411
PHY_LCCalibrate(PADAPTER padapter)412 static void PHY_LCCalibrate(PADAPTER padapter)
413 {
414 halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
415 }
416
PHY_QueryRFPathSwitch(PADAPTER padapter)417 static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
418 {
419 u8 bmain = 0;
420 /*
421 if (IS_HARDWARE_TYPE_8723B(padapter)) {
422 #ifdef CONFIG_RTL8723B
423 bmain = PHY_QueryRFPathSwitch_8723B(padapter);
424 #endif
425 } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
426 #ifdef CONFIG_RTL8188E
427 bmain = PHY_QueryRFPathSwitch_8188E(padapter);
428 #endif
429 } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
430 #ifdef CONFIG_RTL8814A
431 bmain = PHY_QueryRFPathSwitch_8814A(padapter);
432 #endif
433 } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
434 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
435 bmain = PHY_QueryRFPathSwitch_8812A(padapter);
436 #endif
437 } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
438 #ifdef CONFIG_RTL8192E
439 bmain = PHY_QueryRFPathSwitch_8192E(padapter);
440 #endif
441 } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
442 #ifdef CONFIG_RTL8703B
443 bmain = PHY_QueryRFPathSwitch_8703B(padapter);
444 #endif
445 } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
446 #ifdef CONFIG_RTL8188F
447 bmain = PHY_QueryRFPathSwitch_8188F(padapter);
448 #endif
449 } else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {
450 #ifdef CONFIG_RTL8188GTV
451 bmain = PHY_QueryRFPathSwitch_8188GTV(padapter);
452 #endif
453 } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
454 #ifdef CONFIG_RTL8822B
455 bmain = PHY_QueryRFPathSwitch_8822B(padapter);
456 #endif
457 } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
458 #ifdef CONFIG_RTL8723D
459 bmain = PHY_QueryRFPathSwitch_8723D(padapter);
460 #endif
461 } else
462 */
463
464 if (IS_HARDWARE_TYPE_8821C(padapter)) {
465 #ifdef CONFIG_RTL8821C
466 bmain = phy_query_rf_path_switch_8821c(padapter);
467 #endif
468 }
469
470 return bmain;
471 }
472
PHY_SetRFPathSwitch(PADAPTER padapter,BOOLEAN bMain)473 static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
474
475 PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
476 struct dm_struct *phydm = &hal->odmpriv;
477
478 if (IS_HARDWARE_TYPE_8723B(padapter)) {
479 #ifdef CONFIG_RTL8723B
480 phy_set_rf_path_switch_8723b(phydm, bMain);
481 #endif
482 } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
483 #ifdef CONFIG_RTL8188E
484 phy_set_rf_path_switch_8188e(phydm, bMain);
485 #endif
486 } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
487 #ifdef CONFIG_RTL8814A
488 phy_set_rf_path_switch_8814a(phydm, bMain);
489 #endif
490 } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
491 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
492 phy_set_rf_path_switch_8812a(phydm, bMain);
493 #endif
494 } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
495 #ifdef CONFIG_RTL8192E
496 phy_set_rf_path_switch_8192e(phydm, bMain);
497 #endif
498 } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
499 #ifdef CONFIG_RTL8703B
500 phy_set_rf_path_switch_8703b(phydm, bMain);
501 #endif
502 } else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {
503 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
504 phy_set_rf_path_switch_8188f(phydm, bMain);
505 #endif
506 } else if (IS_HARDWARE_TYPE_8192F(padapter)) {
507 #ifdef CONFIG_RTL8192F
508 phy_set_rf_path_switch_8192f(padapter, bMain);
509 #endif
510 } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
511 #ifdef CONFIG_RTL8822B
512 phy_set_rf_path_switch_8822b(phydm, bMain);
513 #endif
514 } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
515 #ifdef CONFIG_RTL8723D
516 phy_set_rf_path_switch_8723d(phydm, bMain);
517 #endif
518 } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
519 #ifdef CONFIG_RTL8821C
520 phy_set_rf_path_switch_8821c(phydm, bMain);
521 #endif
522 } else if (IS_HARDWARE_TYPE_8822C(padapter)) {
523 #ifdef CONFIG_RTL8822C
524 phy_set_rf_path_switch_8822c(phydm, bMain);
525 #endif
526 } else if (IS_HARDWARE_TYPE_8814B(padapter)) {
527 #ifdef CONFIG_RTL8814B
528 /* phy_set_rf_path_switch_8814b(phydm, bMain); */
529 #endif
530 } else if (IS_HARDWARE_TYPE_8723F(padapter)) {
531 #ifdef CONFIG_RTL8723F
532 phy_set_rf_path_switch_8723f(phydm, bMain);
533 #endif
534 }
535 }
536
537
phy_switch_rf_path_set(PADAPTER padapter,u8 * prf_set_State)538 static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
539 #ifdef CONFIG_RTL8821C
540 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
541 struct dm_struct *p_dm = &pHalData->odmpriv;
542
543 if (IS_HARDWARE_TYPE_8821C(padapter)) {
544 config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
545 /* Do IQK when switching to BTG/WLG, requested by RF Binson */
546 if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
547 PHY_IQCalibrate(padapter, FALSE);
548 }
549 #endif
550
551 }
552
553
554 #ifdef CONFIG_ANTENNA_DIVERSITY
rtw_mp_set_antdiv(PADAPTER padapter,BOOLEAN bMain)555 u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
556 {
557 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
558 u8 cur_ant, change_ant;
559
560 if (!pHalData->AntDivCfg)
561 return _FALSE;
562 /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
563 change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
564
565 RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
566 rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
567
568 return _TRUE;
569 }
570 #endif
571
572 s32
MPT_InitializeAdapter(PADAPTER pAdapter,u8 Channel)573 MPT_InitializeAdapter(
574 PADAPTER pAdapter,
575 u8 Channel
576 )
577 {
578 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
579 s32 rtStatus = _SUCCESS;
580 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
581 u32 ledsetting;
582
583 pMptCtx->bMptDrvUnload = _FALSE;
584 pMptCtx->bMassProdTest = _FALSE;
585 pMptCtx->bMptIndexEven = _TRUE; /* default gain index is -6.0db */
586 pMptCtx->h2cReqNum = 0x0;
587 /* init for BT MP */
588 #if defined(CONFIG_RTL8723B)
589 pMptCtx->bMPh2c_timeout = _FALSE;
590 pMptCtx->MptH2cRspEvent = _FALSE;
591 pMptCtx->MptBtC2hEvent = _FALSE;
592 _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
593 rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
594 #endif
595
596 mpt_InitHWConfig(pAdapter);
597
598 #ifdef CONFIG_RTL8723B
599 rtl8723b_InitAntenna_Selection(pAdapter);
600 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
601
602 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
603 phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
604 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
605
606 if (pHalData->PackageType == PACKAGE_DEFAULT)
607 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
608 else
609 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
610
611 }
612 /*set ant to wifi side in mp mode*/
613 rtw_write16(pAdapter, 0x870, 0x300);
614 rtw_write16(pAdapter, 0x860, 0x110);
615 #endif
616
617 pMptCtx->bMptWorkItemInProgress = _FALSE;
618 pMptCtx->CurrMptAct = NULL;
619 pMptCtx->mpt_rf_path = RF_PATH_A;
620 /* ------------------------------------------------------------------------- */
621 /* Don't accept any packets */
622 rtw_write32(pAdapter, REG_RCR, 0);
623
624 /* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
625 /* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
626
627 /* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
628 ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
629
630
631 PHY_LCCalibrate(pAdapter);
632 PHY_IQCalibrate(pAdapter, _FALSE);
633 /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */
634
635 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
636
637 pMptCtx->backup0xc50 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
638 pMptCtx->backup0xc58 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
639 pMptCtx->backup0xc30 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
640 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
641 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
642 #ifdef CONFIG_RTL8188E
643 rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
644 rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
645 #endif
646 #ifdef CONFIG_RTL8814A
647 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
648 pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u8)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
649 pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u8)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
650 pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u8)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
651 pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u8)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
652 }
653 #endif
654 return rtStatus;
655 }
656
657 /*-----------------------------------------------------------------------------
658 * Function: MPT_DeInitAdapter()
659 *
660 * Overview: Extra DeInitialization for Mass Production Test.
661 *
662 * Input: PADAPTER pAdapter
663 *
664 * Output: NONE
665 *
666 * Return: NONE
667 *
668 * Revised History:
669 * When Who Remark
670 * 05/08/2007 MHC Create Version 0.
671 * 05/18/2007 MHC Add normal driver MPHalt code.
672 *
673 *---------------------------------------------------------------------------*/
674 void
MPT_DeInitAdapter(PADAPTER pAdapter)675 MPT_DeInitAdapter(
676 PADAPTER pAdapter
677 )
678 {
679 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
680
681 pMptCtx->bMptDrvUnload = _TRUE;
682 #if defined(CONFIG_RTL8723B)
683 _rtw_free_sema(&(pMptCtx->MPh2c_Sema));
684 _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
685 #endif
686 #if defined(CONFIG_RTL8723B)
687 phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */
688 #endif
689 #if 0 /* for Windows */
690 PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
691
692 while (pMptCtx->bMptWorkItemInProgress) {
693 if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
694 break;
695 }
696 NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
697 #endif
698 }
699
mpt_ProStartTest(PADAPTER padapter)700 static u8 mpt_ProStartTest(PADAPTER padapter)
701 {
702 PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
703
704 pMptCtx->bMassProdTest = _TRUE;
705 pMptCtx->is_start_cont_tx = _FALSE;
706 pMptCtx->bCckContTx = _FALSE;
707 pMptCtx->bOfdmContTx = _FALSE;
708 pMptCtx->bSingleCarrier = _FALSE;
709 pMptCtx->is_carrier_suppression = _FALSE;
710 pMptCtx->is_single_tone = _FALSE;
711 pMptCtx->HWTxmode = PACKETS_TX;
712
713 return _SUCCESS;
714 }
715
716 /*
717 * General use
718 */
SetPowerTracking(PADAPTER padapter,u8 enable)719 s32 SetPowerTracking(PADAPTER padapter, u8 enable)
720 {
721
722 hal_mpt_SetPowerTracking(padapter, enable);
723 return 0;
724 }
725
GetPowerTracking(PADAPTER padapter,u8 * enable)726 void GetPowerTracking(PADAPTER padapter, u8 *enable)
727 {
728 hal_mpt_GetPowerTracking(padapter, enable);
729 }
730
rtw_mp_trigger_iqk(PADAPTER padapter)731 void rtw_mp_trigger_iqk(PADAPTER padapter)
732 {
733 PHY_IQCalibrate(padapter, _FALSE);
734 }
735
rtw_mp_trigger_lck(PADAPTER padapter)736 void rtw_mp_trigger_lck(PADAPTER padapter)
737 {
738 PHY_LCCalibrate(padapter);
739 }
740
rtw_mp_trigger_dpk(PADAPTER padapter)741 void rtw_mp_trigger_dpk(PADAPTER padapter)
742 {
743 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
744 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
745
746 halrf_dpk_trigger(pDM_Odm);
747 }
748
init_mp_data(PADAPTER padapter)749 static void init_mp_data(PADAPTER padapter)
750 {
751 u8 v8;
752 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
753 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
754
755 /*disable BCN*/
756 #ifdef CONFIG_PROTSEL_PORT
757 rtw_hal_hw_port_disable(padapter);
758 #else
759 v8 = rtw_read8(padapter, REG_BCN_CTRL);
760 v8 &= ~EN_BCN_FUNCTION;
761 rtw_write8(padapter, REG_BCN_CTRL, v8);
762 #endif
763
764 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
765 }
766
767
MPT_PwrCtlDM(PADAPTER padapter,u32 trk_type)768 void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type)
769 {
770 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
771 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
772 u32 rf_ability;
773
774 padapter->mppriv.tssitrk_on = trk_type == 3;
775
776 if (trk_type == 0) { /* thermal PwrTrk off*/
777 struct txpwrtrack_cfg c;
778 u8 chnl = 0 ;
779
780 RTW_INFO("in Thermal tracking off\n");
781 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
782 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
783 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
784 halrf_set_pwr_track(pDM_Odm, FALSE);
785 pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
786 if (IS_HARDWARE_TYPE_8822C(padapter))
787 padapter->mppriv.mp_dm = 1; /* default enable dpk tracking */
788 else
789 padapter->mppriv.mp_dm = 0;
790
791 _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
792 configure_txpower_track(pDM_Odm, &c);
793 odm_clear_txpowertracking_state(pDM_Odm);
794 if (*c.odm_tx_pwr_track_set_pwr) {
795 if (pDM_Odm->support_ic_type == ODM_RTL8188F)
796 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
797 else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
798 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
799 SetTxPower(padapter);
800 } else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {
801 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
802 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);
803 } else {
804 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
805 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
806 }
807 }
808 return ;
809 }
810
811 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
812 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
813 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
814 if (trk_type == 1 || trk_type == 3) /* Thermal PwrTrk ON , TSSI PwrTrk ON */
815 halrf_set_pwr_track(pDM_Odm, TRUE);
816 else
817 halrf_set_pwr_track(pDM_Odm, false);/* TSSI K */
818 pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
819 padapter->mppriv.mp_dm = 1;
820
821 }
822
823
mp_join(PADAPTER padapter,u8 mode)824 u32 mp_join(PADAPTER padapter, u8 mode)
825 {
826 WLAN_BSSID_EX bssid;
827 struct sta_info *psta;
828 u32 length;
829 _irqL irqL;
830 s32 res = _SUCCESS;
831
832 struct mp_priv *pmppriv = &padapter->mppriv;
833 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
834 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
835 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
836 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
837 WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
838
839 /* 1. initialize a new WLAN_BSSID_EX */
840 _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
841 RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
842 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
843 pmppriv->network_macaddr[5]);
844 _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
845
846 if (mode == WIFI_FW_ADHOC_STATE) {
847 bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
848 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
849 bssid.InfrastructureMode = Ndis802_11IBSS;
850 bssid.IELength = 0;
851 bssid.Configuration.DSConfig = pmppriv->channel;
852
853 } else if (mode == WIFI_FW_STATION_STATE) {
854 bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
855 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
856 bssid.InfrastructureMode = Ndis802_11Infrastructure;
857 bssid.IELength = 0;
858 }
859
860 length = get_WLAN_BSSID_EX_sz(&bssid);
861 if (length % 4)
862 bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
863 else
864 bssid.Length = length;
865
866 _enter_critical_bh(&pmlmepriv->lock, &irqL);
867
868 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
869 goto end_of_mp_start_test;
870
871 /* init mp_start_test status */
872 if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
873 rtw_disassoc_cmd(padapter, 500, 0);
874 rtw_indicate_disconnect(padapter, 0, _FALSE);
875 rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
876 }
877 pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
878 /*pmlmepriv->fw_state = WIFI_MP_STATE;*/
879 init_fwstate(pmlmepriv, WIFI_MP_STATE);
880
881 set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
882
883 /* 3 2. create a new psta for mp driver */
884 /* clear psta in the cur_network, if any */
885 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
886 if (psta)
887 rtw_free_stainfo(padapter, psta);
888
889 psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
890 if (psta == NULL) {
891 /*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
892 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
893 res = _FAIL;
894 goto end_of_mp_start_test;
895 }
896 if (mode == WIFI_FW_ADHOC_STATE)
897 set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
898 else
899 set_fwstate(pmlmepriv, WIFI_STATION_STATE);
900 /* 3 3. join psudo AdHoc */
901 tgt_network->join_res = 1;
902 tgt_network->aid = psta->cmn.aid = 1;
903
904 _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
905 rtw_update_registrypriv_dev_network(padapter);
906 _rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
907 _rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
908
909 rtw_indicate_connect(padapter);
910 _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
911 set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
912
913 end_of_mp_start_test:
914
915 _exit_critical_bh(&pmlmepriv->lock, &irqL);
916
917 if (1) { /* (res == _SUCCESS) */
918 /* set MSR to WIFI_FW_ADHOC_STATE */
919 if (mode == WIFI_FW_ADHOC_STATE) {
920 /* set msr to WIFI_FW_ADHOC_STATE */
921 pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
922 Set_MSR(padapter, (pmlmeinfo->state & 0x3));
923 rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
924 rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
925 pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
926 } else {
927 Set_MSR(padapter, WIFI_FW_STATION_STATE);
928
929 RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
930 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
931 pmppriv->network_macaddr[5]);
932
933 rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
934 }
935 }
936
937 return res;
938 }
939 /* This function initializes the DUT to the MP test mode */
mp_start_test(PADAPTER padapter)940 s32 mp_start_test(PADAPTER padapter)
941 {
942 struct mp_priv *pmppriv = &padapter->mppriv;
943 #ifdef CONFIG_PCI_HCI
944 PHAL_DATA_TYPE hal;
945 #endif
946 s32 res = _SUCCESS;
947
948 padapter->registrypriv.mp_mode = 1;
949
950 init_mp_data(padapter);
951 #ifdef CONFIG_RTL8814A
952 rtl8814_InitHalDm(padapter);
953 #endif /* CONFIG_RTL8814A */
954 #ifdef CONFIG_RTL8812A
955 rtl8812_InitHalDm(padapter);
956 #endif /* CONFIG_RTL8812A */
957 #ifdef CONFIG_RTL8723B
958 rtl8723b_InitHalDm(padapter);
959 #endif /* CONFIG_RTL8723B */
960 #ifdef CONFIG_RTL8703B
961 rtl8703b_InitHalDm(padapter);
962 #endif /* CONFIG_RTL8703B */
963 #ifdef CONFIG_RTL8192E
964 rtl8192e_InitHalDm(padapter);
965 #endif
966 #ifdef CONFIG_RTL8188F
967 rtl8188f_InitHalDm(padapter);
968 #endif
969 #ifdef CONFIG_RTL8188GTV
970 rtl8188gtv_InitHalDm(padapter);
971 #endif
972 #ifdef CONFIG_RTL8188E
973 rtl8188e_InitHalDm(padapter);
974 #endif
975 #ifdef CONFIG_RTL8723D
976 rtl8723d_InitHalDm(padapter);
977 #endif /* CONFIG_RTL8723D */
978
979 #ifdef CONFIG_PCI_HCI
980 hal = GET_HAL_DATA(padapter);
981 hal->pci_backdoor_ctrl = 0;
982 rtw_pci_aspm_config(padapter);
983 #endif
984
985
986 /* 3 0. update mp_priv */
987 switch (GET_HAL_RFPATH(padapter)) {
988 case RF_1T1R:
989 pmppriv->antenna_tx = ANTENNA_A;
990 pmppriv->antenna_rx = ANTENNA_A;
991 break;
992 case RF_1T2R:
993 default:
994 pmppriv->antenna_tx = ANTENNA_A;
995 pmppriv->antenna_rx = ANTENNA_AB;
996 break;
997 case RF_2T2R:
998 pmppriv->antenna_tx = ANTENNA_AB;
999 pmppriv->antenna_rx = ANTENNA_AB;
1000 break;
1001 case RF_2T4R:
1002 pmppriv->antenna_tx = ANTENNA_AB;
1003 pmppriv->antenna_rx = ANTENNA_ABCD;
1004 break;
1005 }
1006
1007 mpt_ProStartTest(padapter);
1008
1009 mp_join(padapter, WIFI_FW_ADHOC_STATE);
1010
1011 return res;
1012 }
1013 /* ------------------------------------------------------------------------------
1014 * This function change the DUT from the MP test mode into normal mode */
mp_stop_test(PADAPTER padapter)1015 void mp_stop_test(PADAPTER padapter)
1016 {
1017 struct mp_priv *pmppriv = &padapter->mppriv;
1018 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1019 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
1020 struct sta_info *psta;
1021 #ifdef CONFIG_PCI_HCI
1022 struct registry_priv *registry_par = &padapter->registrypriv;
1023 PHAL_DATA_TYPE hal;
1024 #endif
1025
1026 _irqL irqL;
1027
1028 if (pmppriv->mode == MP_ON) {
1029 pmppriv->bSetTxPower = 0;
1030 _enter_critical_bh(&pmlmepriv->lock, &irqL);
1031 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
1032 goto end_of_mp_stop_test;
1033
1034 /* 3 1. disconnect psudo AdHoc */
1035 rtw_indicate_disconnect(padapter, 0, _FALSE);
1036
1037 /* 3 2. clear psta used in mp test mode.
1038 * rtw_free_assoc_resources(padapter, _TRUE); */
1039 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
1040 if (psta)
1041 rtw_free_stainfo(padapter, psta);
1042
1043 /* 3 3. return to normal state (default:station mode) */
1044 /*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
1045 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
1046
1047 /* flush the cur_network */
1048 _rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
1049
1050 _clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
1051
1052 end_of_mp_stop_test:
1053
1054 _exit_critical_bh(&pmlmepriv->lock, &irqL);
1055
1056 #ifdef CONFIG_PCI_HCI
1057 hal = GET_HAL_DATA(padapter);
1058 hal->pci_backdoor_ctrl = registry_par->pci_aspm_config;
1059 rtw_pci_aspm_config(padapter);
1060 #endif
1061
1062 #ifdef CONFIG_RTL8812A
1063 rtl8812_InitHalDm(padapter);
1064 #endif
1065 #ifdef CONFIG_RTL8723B
1066 rtl8723b_InitHalDm(padapter);
1067 #endif
1068 #ifdef CONFIG_RTL8703B
1069 rtl8703b_InitHalDm(padapter);
1070 #endif
1071 #ifdef CONFIG_RTL8192E
1072 rtl8192e_InitHalDm(padapter);
1073 #endif
1074 #ifdef CONFIG_RTL8188F
1075 rtl8188f_InitHalDm(padapter);
1076 #endif
1077 #ifdef CONFIG_RTL8188GTV
1078 rtl8188gtv_InitHalDm(padapter);
1079 #endif
1080 #ifdef CONFIG_RTL8723D
1081 rtl8723d_InitHalDm(padapter);
1082 #endif
1083 }
1084 }
1085 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1086 #if 0
1087 /* #ifdef CONFIG_USB_HCI */
1088 static void mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
1089 {
1090 u8 eRFPath;
1091 u32 rfReg0x26;
1092 struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
1093
1094
1095 if (RateIdx < MPT_RATE_6M) /* CCK rate,for 88cu */
1096 rfReg0x26 = 0xf400;
1097 else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
1098 if ((4 == Channel) || (8 == Channel) || (12 == Channel))
1099 rfReg0x26 = 0xf000;
1100 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1101 rfReg0x26 = 0xf400;
1102 else
1103 rfReg0x26 = 0x4f200;
1104 } else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
1105 /* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
1106
1107 if (CHANNEL_WIDTH_20 == BandWidthID) {
1108 if ((4 == Channel) || (8 == Channel))
1109 rfReg0x26 = 0xf000;
1110 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1111 rfReg0x26 = 0xf400;
1112 else
1113 rfReg0x26 = 0x4f200;
1114 } else {
1115 if ((4 == Channel) || (8 == Channel))
1116 rfReg0x26 = 0xf000;
1117 else if ((5 == Channel) || (7 == Channel))
1118 rfReg0x26 = 0xf400;
1119 else
1120 rfReg0x26 = 0x4f200;
1121 }
1122 }
1123
1124 for (eRFPath = 0; eRFPath < hal_spec->rf_reg_path_num; eRFPath++)
1125 write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
1126 }
1127 #endif
1128 /*-----------------------------------------------------------------------------
1129 * Function: mpt_SwitchRfSetting
1130 *
1131 * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
1132 *
1133 * Input: PADAPTER pAdapter
1134 *
1135 * Output: NONE
1136 *
1137 * Return: NONE
1138 *
1139 * Revised History:
1140 * When Who Remark
1141 * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
1142 * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
1143 *
1144 *---------------------------------------------------------------------------*/
1145 #if 0
1146 static void mpt_SwitchRfSetting(PADAPTER pAdapter)
1147 {
1148 hal_mpt_SwitchRfSetting(pAdapter);
1149 }
1150
1151 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1152 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1153 static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
1154 {
1155 hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
1156 }
1157 #endif
1158
1159 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1160
1161 /*
1162 * SetChannel
1163 * Description
1164 * Use H2C command to change channel,
1165 * not only modify rf register, but also other setting need to be done.
1166 */
SetChannel(PADAPTER pAdapter)1167 void SetChannel(PADAPTER pAdapter)
1168 {
1169 hal_mpt_SetChannel(pAdapter);
1170 }
1171
1172 /*
1173 * Notice
1174 * Switch bandwitdth may change center frequency(channel)
1175 */
SetBandwidth(PADAPTER pAdapter)1176 void SetBandwidth(PADAPTER pAdapter)
1177 {
1178 hal_mpt_SetBandwidth(pAdapter);
1179
1180 }
1181
SetAntenna(PADAPTER pAdapter)1182 void SetAntenna(PADAPTER pAdapter)
1183 {
1184 hal_mpt_SetAntenna(pAdapter);
1185 }
1186
SetTxPower(PADAPTER pAdapter)1187 int SetTxPower(PADAPTER pAdapter)
1188 {
1189
1190 hal_mpt_SetTxPower(pAdapter);
1191 return _TRUE;
1192 }
1193
SetTxAGCOffset(PADAPTER pAdapter,u32 ulTxAGCOffset)1194 void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
1195 {
1196 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
1197
1198 TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
1199 TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
1200 TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
1201
1202 tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
1203 write_bbreg(pAdapter, rFPGA0_TxGainStage,
1204 (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
1205 }
1206
SetDataRate(PADAPTER pAdapter)1207 void SetDataRate(PADAPTER pAdapter)
1208 {
1209 hal_mpt_SetDataRate(pAdapter);
1210 }
1211
MP_PHY_SetRFPathSwitch(PADAPTER pAdapter,BOOLEAN bMain)1212 void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
1213 {
1214
1215 PHY_SetRFPathSwitch(pAdapter, bMain);
1216
1217 }
1218
mp_phy_switch_rf_path_set(PADAPTER pAdapter,u8 * pstate)1219 void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
1220 {
1221
1222 phy_switch_rf_path_set(pAdapter, pstate);
1223
1224 }
1225
MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)1226 u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
1227 {
1228 return PHY_QueryRFPathSwitch(pAdapter);
1229 }
1230
SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1231 s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1232 {
1233 return hal_mpt_SetThermalMeter(pAdapter, target_ther);
1234 }
1235
1236 #if 0
1237 static void TriggerRFThermalMeter(PADAPTER pAdapter)
1238 {
1239 hal_mpt_TriggerRFThermalMeter(pAdapter);
1240 }
1241
1242 static u8 ReadRFThermalMeter(PADAPTER pAdapter)
1243 {
1244 return hal_mpt_ReadRFThermalMeter(pAdapter);
1245 }
1246 #endif
1247
GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1248 void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value)
1249 {
1250 hal_mpt_GetThermalMeter(pAdapter, rfpath, value);
1251 }
1252
SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1253 void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1254 {
1255 PhySetTxPowerLevel(pAdapter);
1256 hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
1257 }
1258
SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1259 void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1260 {
1261 PhySetTxPowerLevel(pAdapter);
1262 hal_mpt_SetSingleToneTx(pAdapter, bStart);
1263 }
1264
SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1265 void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1266 {
1267 PhySetTxPowerLevel(pAdapter);
1268 hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
1269 }
1270
SetContinuousTx(PADAPTER pAdapter,u8 bStart)1271 void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1272 {
1273 PhySetTxPowerLevel(pAdapter);
1274 hal_mpt_SetContinuousTx(pAdapter, bStart);
1275 }
1276
1277
PhySetTxPowerLevel(PADAPTER pAdapter)1278 void PhySetTxPowerLevel(PADAPTER pAdapter)
1279 {
1280 struct mp_priv *pmp_priv = &pAdapter->mppriv;
1281
1282
1283 if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
1284 rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
1285 }
1286
1287 /* ------------------------------------------------------------------------------ */
dump_mpframe(PADAPTER padapter,struct xmit_frame * pmpframe)1288 static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
1289 {
1290 rtw_hal_mgnt_xmit(padapter, pmpframe);
1291 }
1292
alloc_mp_xmitframe(struct xmit_priv * pxmitpriv)1293 static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
1294 {
1295 struct xmit_frame *pmpframe;
1296 struct xmit_buf *pxmitbuf;
1297
1298 pmpframe = rtw_alloc_xmitframe(pxmitpriv, 0);
1299 if (pmpframe == NULL)
1300 return NULL;
1301
1302 pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
1303 if (pxmitbuf == NULL) {
1304 rtw_free_xmitframe(pxmitpriv, pmpframe);
1305 return NULL;
1306 }
1307
1308 pmpframe->frame_tag = MP_FRAMETAG;
1309
1310 pmpframe->pxmitbuf = pxmitbuf;
1311
1312 pmpframe->buf_addr = pxmitbuf->pbuf;
1313
1314 pxmitbuf->priv_data = pmpframe;
1315
1316 return pmpframe;
1317
1318 }
1319
1320 #ifdef CONFIG_PCI_HCI
check_nic_enough_desc(_adapter * padapter,struct pkt_attrib * pattrib)1321 static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
1322 {
1323 u32 prio;
1324 struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
1325 struct rtw_tx_ring *ring;
1326
1327 switch (pattrib->qsel) {
1328 case 0:
1329 case 3:
1330 prio = BE_QUEUE_INX;
1331 break;
1332 case 1:
1333 case 2:
1334 prio = BK_QUEUE_INX;
1335 break;
1336 case 4:
1337 case 5:
1338 prio = VI_QUEUE_INX;
1339 break;
1340 case 6:
1341 case 7:
1342 prio = VO_QUEUE_INX;
1343 break;
1344 default:
1345 prio = BE_QUEUE_INX;
1346 break;
1347 }
1348
1349 ring = &pxmitpriv->tx_ring[prio];
1350
1351 /*
1352 * for now we reserve two free descriptor as a safety boundary
1353 * between the tail and the head
1354 */
1355 if ((ring->entries - ring->qlen) >= 2)
1356 return _TRUE;
1357 else
1358 return _FALSE;
1359 }
1360 #endif
1361
mp_xmit_packet_thread(thread_context context)1362 static thread_return mp_xmit_packet_thread(thread_context context)
1363 {
1364 struct xmit_frame *pxmitframe;
1365 struct mp_tx *pmptx;
1366 struct mp_priv *pmp_priv;
1367 struct xmit_priv *pxmitpriv;
1368 PADAPTER padapter;
1369
1370 pmp_priv = (struct mp_priv *)context;
1371 pmptx = &pmp_priv->tx;
1372 padapter = pmp_priv->papdater;
1373 pxmitpriv = &(padapter->xmitpriv);
1374
1375 thread_enter("RTW_MP_THREAD");
1376
1377 RTW_INFO("%s:pkTx Start\n", __func__);
1378 while (1) {
1379 pxmitframe = alloc_mp_xmitframe(pxmitpriv);
1380 #ifdef CONFIG_PCI_HCI
1381 if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
1382 rtw_usleep_os(1000);
1383 continue;
1384 }
1385 #endif
1386 if (pxmitframe == NULL) {
1387 if (pmptx->stop ||
1388 RTW_CANNOT_RUN(padapter))
1389 goto exit;
1390 else {
1391 rtw_usleep_os(10);
1392 continue;
1393 }
1394 }
1395 _rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
1396 _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
1397
1398
1399 rtw_usleep_os(padapter->mppriv.pktInterval);
1400 dump_mpframe(padapter, pxmitframe);
1401
1402 pmptx->sended++;
1403 pmp_priv->tx_pktcount++;
1404
1405 if (pmptx->stop ||
1406 RTW_CANNOT_RUN(padapter))
1407 goto exit;
1408 if ((pmptx->count != 0) &&
1409 (pmptx->count == pmptx->sended))
1410 goto exit;
1411
1412 flush_signals_thread();
1413 }
1414
1415 exit:
1416 /* RTW_INFO("%s:pkTx Exit\n", __func__); */
1417 rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
1418 pmptx->pallocated_buf = NULL;
1419 pmptx->stop = 1;
1420
1421 thread_exit(NULL);
1422 return 0;
1423 }
1424
fill_txdesc_for_mp(PADAPTER padapter,u8 * ptxdesc)1425 void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
1426 {
1427 struct mp_priv *pmp_priv = &padapter->mppriv;
1428 _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
1429 }
1430
1431 #if defined(CONFIG_RTL8188E)
fill_tx_desc_8188e(PADAPTER padapter)1432 void fill_tx_desc_8188e(PADAPTER padapter)
1433 {
1434 struct mp_priv *pmp_priv = &padapter->mppriv;
1435 struct tx_desc *desc = (struct tx_desc *)&(pmp_priv->tx.desc);
1436 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1437 u32 pkt_size = pattrib->last_txcmdsz;
1438 s32 bmcast = IS_MCAST(pattrib->ra);
1439 /* offset 0 */
1440 #if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
1441 desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1442 desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
1443 desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
1444 if (bmcast)
1445 desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
1446
1447 desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
1448 #endif
1449
1450 desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
1451 desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
1452 desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
1453 /* offset 8 */
1454 /* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
1455
1456 desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
1457 desc->txdw4 |= cpu_to_le32(HW_SSN);
1458
1459 desc->txdw4 |= cpu_to_le32(USERATE);
1460 desc->txdw4 |= cpu_to_le32(DISDATAFB);
1461
1462 if (pmp_priv->preamble) {
1463 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1464 desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
1465 }
1466
1467 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1468 desc->txdw4 |= cpu_to_le32(DATA_BW);
1469
1470 /* offset 20 */
1471 desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
1472
1473 if (pmp_priv->preamble) {
1474 if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
1475 desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
1476 }
1477
1478 desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
1479 desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit */
1480
1481
1482 }
1483 #endif
1484
1485 #if defined(CONFIG_RTL8814A)
fill_tx_desc_8814a(PADAPTER padapter)1486 void fill_tx_desc_8814a(PADAPTER padapter)
1487 {
1488 struct mp_priv *pmp_priv = &padapter->mppriv;
1489 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1490 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1491
1492 u32 pkt_size = pattrib->last_txcmdsz;
1493 s32 bmcast = IS_MCAST(pattrib->ra);
1494 u8 offset;
1495
1496 /* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
1497 SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
1498 /* SET_TX_DESC_OWN_(pDesc, 1); */
1499
1500 SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
1501
1502 offset = TXDESC_SIZE + OFFSET_SZ;
1503
1504 SET_TX_DESC_OFFSET_8814A(pDesc, offset);
1505 #if defined(CONFIG_PCI_HCI)
1506 SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
1507 #else
1508 SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
1509 #endif
1510
1511 if (bmcast)
1512 SET_TX_DESC_BMC_8814A(pDesc, 1);
1513
1514 SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
1515 SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
1516
1517 /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1518 SET_TX_DESC_QUEUE_SEL_8814A(pDesc, pattrib->qsel);
1519 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1520
1521 if (pmp_priv->preamble)
1522 SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
1523
1524 if (!pattrib->qos_en) {
1525 SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
1526 } else
1527 SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
1528
1529 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1530 SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
1531 else {
1532 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1533 SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
1534 }
1535
1536 SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
1537 SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
1538 SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
1539
1540 }
1541 #endif
1542
1543 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
fill_tx_desc_8812a(PADAPTER padapter)1544 void fill_tx_desc_8812a(PADAPTER padapter)
1545 {
1546 struct mp_priv *pmp_priv = &padapter->mppriv;
1547 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1548 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1549
1550 u32 pkt_size = pattrib->last_txcmdsz;
1551 s32 bmcast = IS_MCAST(pattrib->ra);
1552 u8 data_rate, pwr_status, offset;
1553
1554 SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
1555 SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
1556 SET_TX_DESC_OWN_8812(pDesc, 1);
1557
1558 SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
1559
1560 offset = TXDESC_SIZE + OFFSET_SZ;
1561
1562 SET_TX_DESC_OFFSET_8812(pDesc, offset);
1563
1564 #if defined(CONFIG_PCI_HCI)
1565 SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
1566 #else
1567 SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
1568 #endif
1569 if (bmcast)
1570 SET_TX_DESC_BMC_8812(pDesc, 1);
1571
1572 SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
1573 SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
1574
1575 /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1576 SET_TX_DESC_QUEUE_SEL_8812(pDesc, pattrib->qsel);
1577 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1578
1579 if (!pattrib->qos_en) {
1580 SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
1581 } else
1582 SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
1583
1584 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1585 SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
1586 else {
1587 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1588 SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
1589 }
1590
1591 SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
1592 SET_TX_DESC_USE_RATE_8812(pDesc, 1);
1593 SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
1594
1595 }
1596 #endif
1597 #if defined(CONFIG_RTL8192E)
fill_tx_desc_8192e(PADAPTER padapter)1598 void fill_tx_desc_8192e(PADAPTER padapter)
1599 {
1600 struct mp_priv *pmp_priv = &padapter->mppriv;
1601 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1602 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1603
1604 u32 pkt_size = pattrib->last_txcmdsz;
1605 s32 bmcast = IS_MCAST(pattrib->ra);
1606 u8 data_rate, pwr_status, offset;
1607
1608
1609 SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
1610
1611 offset = TXDESC_SIZE + OFFSET_SZ;
1612
1613 SET_TX_DESC_OFFSET_92E(pDesc, offset);
1614 #if defined(CONFIG_PCI_HCI) /* 8192EE */
1615
1616 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
1617 #else /* 8192EU 8192ES */
1618 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
1619 #endif
1620
1621 if (bmcast)
1622 SET_TX_DESC_BMC_92E(pDesc, 1);
1623
1624 SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
1625 SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
1626
1627
1628 SET_TX_DESC_QUEUE_SEL_92E(pDesc, pattrib->qsel);
1629 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1630
1631 if (!pattrib->qos_en) {
1632 SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
1633 SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
1634 } else
1635 SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
1636
1637 if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
1638 SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
1639 else {
1640 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1641 SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
1642 }
1643
1644 /* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
1645
1646 SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
1647 SET_TX_DESC_USE_RATE_92E(pDesc, 1);
1648 SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
1649
1650 }
1651 #endif
1652
1653 #if defined(CONFIG_RTL8723B)
fill_tx_desc_8723b(PADAPTER padapter)1654 void fill_tx_desc_8723b(PADAPTER padapter)
1655 {
1656 struct mp_priv *pmp_priv = &padapter->mppriv;
1657 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1658 u8 *ptxdesc = pmp_priv->tx.desc;
1659
1660 SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
1661 SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
1662 SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
1663
1664 SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
1665 SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
1666 SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
1667 SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
1668 SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
1669
1670 if (pmp_priv->preamble) {
1671 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1672 SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
1673 }
1674
1675 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1676 SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
1677
1678 SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
1679
1680 SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
1681 SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
1682 }
1683 #endif
1684
1685 #if defined(CONFIG_RTL8703B)
fill_tx_desc_8703b(PADAPTER padapter)1686 void fill_tx_desc_8703b(PADAPTER padapter)
1687 {
1688 struct mp_priv *pmp_priv = &padapter->mppriv;
1689 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1690 u8 *ptxdesc = pmp_priv->tx.desc;
1691
1692 SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
1693 SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
1694 SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
1695
1696 SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
1697 SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
1698 SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
1699 SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
1700 SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
1701
1702 if (pmp_priv->preamble) {
1703 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1704 SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
1705 }
1706
1707 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1708 SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
1709
1710 SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
1711
1712 SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
1713 SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
1714 }
1715 #endif
1716
1717 #if defined(CONFIG_RTL8188F)
fill_tx_desc_8188f(PADAPTER padapter)1718 void fill_tx_desc_8188f(PADAPTER padapter)
1719 {
1720 struct mp_priv *pmp_priv = &padapter->mppriv;
1721 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1722 u8 *ptxdesc = pmp_priv->tx.desc;
1723
1724 SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
1725 SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
1726 SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
1727
1728 SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
1729 SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
1730 SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
1731 SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
1732 SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
1733
1734 if (pmp_priv->preamble)
1735 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1736 SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
1737
1738 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1739 SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
1740
1741 SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
1742
1743 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
1744 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
1745 }
1746 #endif
1747
1748 #if defined(CONFIG_RTL8188GTV)
fill_tx_desc_8188gtv(PADAPTER padapter)1749 void fill_tx_desc_8188gtv(PADAPTER padapter)
1750 {
1751 struct mp_priv *pmp_priv = &padapter->mppriv;
1752 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1753 u8 *ptxdesc = pmp_priv->tx.desc;
1754
1755 SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);
1756 SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);
1757 SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);
1758
1759 SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);
1760 SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);
1761 SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);
1762 SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);
1763 SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);
1764
1765 if (pmp_priv->preamble)
1766 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1767 SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);
1768
1769 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1770 SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);
1771
1772 SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);
1773
1774 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);
1775 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);
1776 }
1777 #endif
1778
1779 #if defined(CONFIG_RTL8723D)
fill_tx_desc_8723d(PADAPTER padapter)1780 void fill_tx_desc_8723d(PADAPTER padapter)
1781 {
1782 struct mp_priv *pmp_priv = &padapter->mppriv;
1783 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1784 u8 *ptxdesc = pmp_priv->tx.desc;
1785
1786 SET_TX_DESC_BK_8723D(ptxdesc, 1);
1787 SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
1788 SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
1789
1790 SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
1791 SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
1792 SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
1793 SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
1794 SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
1795
1796 if (pmp_priv->preamble) {
1797 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1798 SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
1799 }
1800
1801 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1802 SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
1803
1804 SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
1805
1806 SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
1807 SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
1808 }
1809 #endif
1810
1811 #if defined(CONFIG_RTL8710B)
fill_tx_desc_8710b(PADAPTER padapter)1812 void fill_tx_desc_8710b(PADAPTER padapter)
1813 {
1814 struct mp_priv *pmp_priv = &padapter->mppriv;
1815 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1816 u8 *ptxdesc = pmp_priv->tx.desc;
1817
1818 SET_TX_DESC_BK_8710B(ptxdesc, 1);
1819 SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);
1820 SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);
1821
1822 SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);
1823 SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);
1824 SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);
1825 SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);
1826 SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);
1827
1828 if (pmp_priv->preamble) {
1829 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1830 SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);
1831 }
1832
1833 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1834 SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);
1835
1836 SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);
1837
1838 SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);
1839 SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);
1840 }
1841 #endif
1842
1843 #if defined(CONFIG_RTL8192F)
fill_tx_desc_8192f(PADAPTER padapter)1844 void fill_tx_desc_8192f(PADAPTER padapter)
1845 {
1846 struct mp_priv *pmp_priv = &padapter->mppriv;
1847 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1848 u8 *ptxdesc = pmp_priv->tx.desc;
1849
1850 SET_TX_DESC_BK_8192F(ptxdesc, 1);
1851 SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);
1852 SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);
1853
1854 SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);
1855 SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);
1856 SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);
1857 SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);
1858 SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);
1859
1860 if (pmp_priv->preamble) {
1861 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1862 SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);
1863 }
1864
1865 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1866 SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);
1867
1868 SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);
1869
1870 SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);
1871 SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);
1872 }
1873
1874 #endif
Rtw_MPSetMacTxEDCA(PADAPTER padapter)1875 static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
1876 {
1877
1878 rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
1879 /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
1880 phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
1881 /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
1882 phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
1883 /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
1884 /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
1885 /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
1886 RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
1887
1888 }
1889
SetPacketTx(PADAPTER padapter)1890 void SetPacketTx(PADAPTER padapter)
1891 {
1892 u8 *ptr, *pkt_start, *pkt_end;
1893 u32 pkt_size = 0, i = 0, idx = 0, tmp_idx = 0;
1894 struct rtw_ieee80211_hdr *hdr;
1895 u8 payload;
1896 s32 bmcast;
1897 struct pkt_attrib *pattrib;
1898 struct mp_priv *pmp_priv;
1899
1900 pmp_priv = &padapter->mppriv;
1901
1902 if (pmp_priv->tx.stop)
1903 return;
1904 pmp_priv->tx.sended = 0;
1905 pmp_priv->tx.stop = 0;
1906 pmp_priv->tx_pktcount = 0;
1907
1908 /* 3 1. update_attrib() */
1909 pattrib = &pmp_priv->tx.attrib;
1910 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
1911 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
1912 _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
1913 bmcast = IS_MCAST(pattrib->ra);
1914 if (bmcast)
1915 pattrib->psta = rtw_get_bcmc_stainfo(padapter);
1916 else
1917 pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
1918
1919 if (pattrib->psta == NULL) {
1920 RTW_INFO("%s:psta = NULL !!\n", __func__);
1921 return;
1922 }
1923
1924 pattrib->mac_id = pattrib->psta->cmn.mac_id;
1925 pattrib->mbssid = 0;
1926
1927 pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
1928
1929 /* 3 2. allocate xmit buffer */
1930 pkt_size = pattrib->last_txcmdsz;
1931
1932 if (pmp_priv->tx.pallocated_buf)
1933 rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
1934 pmp_priv->tx.write_size = pkt_size;
1935 pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
1936 pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
1937 if (pmp_priv->tx.pallocated_buf == NULL) {
1938 RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
1939 return;
1940 }
1941 pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
1942 ptr = pmp_priv->tx.buf;
1943
1944 _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
1945 pkt_start = ptr;
1946 pkt_end = pkt_start + pkt_size;
1947
1948 /* 3 3. init TX descriptor */
1949 #if defined(CONFIG_RTL8188E)
1950 if (IS_HARDWARE_TYPE_8188E(padapter))
1951 fill_tx_desc_8188e(padapter);
1952 #endif
1953
1954 #if defined(CONFIG_RTL8814A)
1955 if (IS_HARDWARE_TYPE_8814A(padapter))
1956 fill_tx_desc_8814a(padapter);
1957 #endif /* defined(CONFIG_RTL8814A) */
1958
1959 #if defined(CONFIG_RTL8822B)
1960 if (IS_HARDWARE_TYPE_8822B(padapter))
1961 rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
1962 #endif /* CONFIG_RTL8822B */
1963
1964 #if defined(CONFIG_RTL8822C)
1965 if (IS_HARDWARE_TYPE_8822C(padapter))
1966 rtl8822c_prepare_mp_txdesc(padapter, pmp_priv);
1967 #endif /* CONFIG_RTL8822C */
1968
1969 #if defined(CONFIG_RTL8821C)
1970 if (IS_HARDWARE_TYPE_8821C(padapter))
1971 rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
1972 #endif /* CONFIG_RTL8821C */
1973
1974 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1975 if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
1976 fill_tx_desc_8812a(padapter);
1977 #endif
1978
1979 #if defined(CONFIG_RTL8192E)
1980 if (IS_HARDWARE_TYPE_8192E(padapter))
1981 fill_tx_desc_8192e(padapter);
1982 #endif
1983 #if defined(CONFIG_RTL8723B)
1984 if (IS_HARDWARE_TYPE_8723B(padapter))
1985 fill_tx_desc_8723b(padapter);
1986 #endif
1987 #if defined(CONFIG_RTL8703B)
1988 if (IS_HARDWARE_TYPE_8703B(padapter))
1989 fill_tx_desc_8703b(padapter);
1990 #endif
1991
1992 #if defined(CONFIG_RTL8188F)
1993 if (IS_HARDWARE_TYPE_8188F(padapter))
1994 fill_tx_desc_8188f(padapter);
1995 #endif
1996
1997 #if defined(CONFIG_RTL8188GTV)
1998 if (IS_HARDWARE_TYPE_8188GTV(padapter))
1999 fill_tx_desc_8188gtv(padapter);
2000 #endif
2001
2002 #if defined(CONFIG_RTL8723D)
2003 if (IS_HARDWARE_TYPE_8723D(padapter))
2004 fill_tx_desc_8723d(padapter);
2005 #endif
2006 #if defined(CONFIG_RTL8192F)
2007 if (IS_HARDWARE_TYPE_8192F(padapter))
2008 fill_tx_desc_8192f(padapter);
2009 #endif
2010
2011 #if defined(CONFIG_RTL8710B)
2012 if (IS_HARDWARE_TYPE_8710B(padapter))
2013 fill_tx_desc_8710b(padapter);
2014 #endif
2015
2016 #if defined(CONFIG_RTL8814B)
2017 if (IS_HARDWARE_TYPE_8814B(padapter))
2018 rtl8814b_prepare_mp_txdesc(padapter, pmp_priv);
2019 #endif /* CONFIG_RTL8814B */
2020
2021 #if defined(CONFIG_RTL8723F)
2022 if (IS_HARDWARE_TYPE_8723F(padapter))
2023 rtl8723f_prepare_mp_txdesc(padapter, pmp_priv);
2024 #endif /* CONFIG_RTL8723F */
2025
2026 /* 3 4. make wlan header, make_wlanhdr() */
2027 hdr = (struct rtw_ieee80211_hdr *)pkt_start;
2028 set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
2029
2030 _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
2031 _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
2032 _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
2033
2034 /* 3 5. make payload */
2035 ptr = pkt_start + pattrib->hdrlen;
2036
2037 if (pmp_priv->mplink_btx == _TRUE) {
2038 _rtw_memcpy(ptr, pmp_priv->mplink_buf, pkt_end - ptr);
2039 } else {
2040 switch (pmp_priv->tx.payload) {
2041 case MP_TX_Payload_00:
2042 RTW_INFO("MP packet tx 0x00 payload!\n");
2043 payload = 0x00;
2044 _rtw_memset(ptr, 0x00, pkt_end - ptr);
2045 break;
2046 case MP_TX_Payload_5a:
2047 RTW_INFO("MP packet tx 0x5a payload!\n");
2048 payload = 0x5a;
2049 _rtw_memset(ptr, 0x5a, pkt_end - ptr);
2050 break;
2051 case MP_TX_Payload_a5:
2052 RTW_INFO("MP packet tx 0xa5 payload!\n");
2053 payload = 0xa5;
2054 _rtw_memset(ptr, 0xa5, pkt_end - ptr);
2055 break;
2056 case MP_TX_Payload_ff:
2057 RTW_INFO("MP packet tx 0xff payload!\n");
2058 payload = 0xff;
2059 _rtw_memset(ptr, 0xff, pkt_end - ptr);
2060 break;
2061 case MP_TX_Payload_prbs9:
2062 RTW_INFO("MP packet tx PRBS9 payload!\n");
2063 while (idx <= pkt_end - ptr) {
2064 int start = 0x02;
2065 int a = start;
2066
2067 for (i = 0;; i++) {
2068 int newbit = (((a >> 8) ^ (a >> 4)) & 1);
2069 a = ((a << 1) | newbit) & 0x1ff;
2070 RTW_DBG("%x ", a);
2071 ptr[idx + i] = a;
2072
2073 if (a == start) {
2074 RTW_INFO("payload repetition period is %d , end %d\n", i , idx);
2075 tmp_idx += i;
2076 break;
2077 }
2078 if (idx + i >= (pkt_end - ptr)) {
2079 tmp_idx += (idx + i);
2080 RTW_INFO(" repetition period payload end curr ptr %d\n", idx + i);
2081 break;
2082 }
2083 }
2084 idx = tmp_idx;
2085 }
2086 break;
2087 case MP_TX_Payload_default_random:
2088 RTW_INFO("MP packet tx default random payload!\n");
2089 for (i = 0; i < pkt_end - ptr; i++)
2090 ptr[i] = rtw_random32() % 0xFF;
2091 break;
2092 default:
2093 RTW_INFO("Config payload type default use 0x%x\n!", pmp_priv->tx.payload);
2094 _rtw_memset(ptr, pmp_priv->tx.payload, pkt_end - ptr);
2095 break;
2096 }
2097 }
2098 /* 3 6. start thread */
2099 #ifdef PLATFORM_LINUX
2100 pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
2101 if (IS_ERR(pmp_priv->tx.PktTxThread)) {
2102 RTW_ERR("Create PktTx Thread Fail !!!!!\n");
2103 pmp_priv->tx.PktTxThread = NULL;
2104 }
2105 #endif
2106 #ifdef PLATFORM_FREEBSD
2107 {
2108 struct proc *p;
2109 struct thread *td;
2110 pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
2111 &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
2112
2113 if (pmp_priv->tx.PktTxThread < 0)
2114 RTW_INFO("Create PktTx Thread Fail !!!!!\n");
2115 }
2116 #endif
2117
2118 Rtw_MPSetMacTxEDCA(padapter);
2119 return;
2120 }
2121
SetPacketRx(PADAPTER pAdapter,u8 bStartRx,u8 bAB)2122 void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
2123 {
2124 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
2125 struct mp_priv *pmppriv = &pAdapter->mppriv;
2126
2127
2128 if (bStartRx) {
2129 #ifdef CONFIG_RTL8723B
2130 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */
2131 write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry */
2132 #endif
2133 pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
2134 pHalData->ReceiveConfig |= RCR_ACRC32;
2135 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
2136
2137 if (pmppriv->bSetRxBssid == _TRUE) {
2138 RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
2139 MAC_ARG(pmppriv->network_macaddr));
2140 pHalData->ReceiveConfig = 0;
2141 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
2142 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
2143
2144 #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
2145 /* todo: 8723F */
2146 write_bbreg(pAdapter, 0x550, BIT3, bEnable);
2147 #endif
2148 rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2149 pmppriv->brx_filter_beacon = _TRUE;
2150
2151 } else {
2152 pHalData->ReceiveConfig |= RCR_ADF;
2153 /* Accept all data frames */
2154 rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
2155 }
2156
2157 if (bAB)
2158 pHalData->ReceiveConfig |= RCR_AB;
2159 } else {
2160 #ifdef CONFIG_RTL8723B
2161 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state)*/
2162 write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry */
2163 #endif
2164 pHalData->ReceiveConfig = 0;
2165 rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2166 }
2167
2168 rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
2169 }
2170
ResetPhyRxPktCount(PADAPTER pAdapter)2171 void ResetPhyRxPktCount(PADAPTER pAdapter)
2172 {
2173 u32 i, phyrx_set = 0;
2174
2175 for (i = 0; i <= 0xF; i++) {
2176 phyrx_set = 0;
2177 phyrx_set |= _RXERR_RPT_SEL(i); /* select */
2178 phyrx_set |= RXERR_RPT_RST; /* set counter to zero */
2179 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2180 }
2181 }
2182
GetPhyRxPktCounts(PADAPTER pAdapter,u32 selbit)2183 static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
2184 {
2185 /* selection */
2186 u32 phyrx_set = 0, count = 0;
2187
2188 phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
2189 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2190
2191 /* Read packet count */
2192 count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
2193
2194 return count;
2195 }
2196
GetPhyRxPktReceived(PADAPTER pAdapter)2197 u32 GetPhyRxPktReceived(PADAPTER pAdapter)
2198 {
2199 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2200
2201 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
2202 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
2203 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
2204
2205 return OFDM_cnt + CCK_cnt + HT_cnt;
2206 }
2207
GetPhyRxPktCRC32Error(PADAPTER pAdapter)2208 u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
2209 {
2210 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2211
2212 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
2213 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
2214 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
2215
2216 return OFDM_cnt + CCK_cnt + HT_cnt;
2217 }
2218
2219 struct psd_init_regs {
2220 /* 3 wire */
2221 int reg_88c;
2222 int reg_c00;
2223 int reg_e00;
2224 int reg_1800;
2225 int reg_1a00;
2226 /* cck */
2227 int reg_800;
2228 int reg_808;
2229 };
2230
rtw_mp_psd_init(PADAPTER padapter,struct psd_init_regs * regs)2231 static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)
2232 {
2233 HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter);
2234
2235 switch (phal_data->rf_type) {
2236 /* 1R */
2237 case RF_1T1R:
2238 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2239 /* 11AC 1R PSD Setting 3wire & cck off */
2240 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2241 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2242 regs->reg_808 = rtw_read32(padapter, 0x808);
2243 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2244 } else {
2245 /* 11N 3-wire off 1 */
2246 regs->reg_88c = rtw_read32(padapter, 0x88C);
2247 phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);
2248 /* 11N CCK off */
2249 regs->reg_800 = rtw_read32(padapter, 0x800);
2250 phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2251 }
2252 break;
2253
2254 /* 2R */
2255 case RF_1T2R:
2256 case RF_2T2R:
2257 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2258 /* 11AC 2R PSD Setting 3wire & cck off */
2259 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2260 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2261 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2262 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2263 regs->reg_808 = rtw_read32(padapter, 0x808);
2264 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2265 } else {
2266 /* 11N 3-wire off 2 */
2267 regs->reg_88c = rtw_read32(padapter, 0x88C);
2268 phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);
2269 /* 11N CCK off */
2270 regs->reg_800 = rtw_read32(padapter, 0x800);
2271 phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2272 }
2273 break;
2274
2275 /* 3R */
2276 case RF_2T3R:
2277 case RF_3T3R:
2278 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2279 /* 11AC 3R PSD Setting 3wire & cck off */
2280 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2281 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2282 regs->reg_1800 = rtw_read32(padapter, 0x1800);
2283 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2284 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2285 phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2286 regs->reg_808 = rtw_read32(padapter, 0x808);
2287 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2288 } else {
2289 RTW_ERR("%s: 11n don't support 3R\n", __func__);
2290 return -1;
2291 }
2292 break;
2293
2294 /* 4R */
2295 case RF_2T4R:
2296 case RF_3T4R:
2297 case RF_4T4R:
2298 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2299 /* 11AC 4R PSD Setting 3wire & cck off */
2300 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2301 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2302 regs->reg_1800 = rtw_read32(padapter, 0x1800);
2303 regs->reg_1a00 = rtw_read32(padapter, 0x1A00);
2304 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2305 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2306 phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2307 phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);
2308 regs->reg_808 = rtw_read32(padapter, 0x808);
2309 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2310 } else {
2311 RTW_ERR("%s: 11n don't support 4R\n", __func__);
2312 return -1;
2313 }
2314 break;
2315
2316 default:
2317 RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2318 return -1;
2319 }
2320
2321 /* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */
2322 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))
2323 phy_set_bb_reg(padapter, 0x910, 0xC000, 3);
2324 else
2325 phy_set_bb_reg(padapter, 0x808, 0xC000, 3);
2326
2327 RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type);
2328 return 0;
2329 }
2330
rtw_mp_psd_close(PADAPTER padapter,struct psd_init_regs * regs)2331 static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)
2332 {
2333 HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter);
2334
2335
2336 if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2337 /* 11n 3wire restore */
2338 rtw_write32(padapter, 0x88C, regs->reg_88c);
2339 /* 11n cck restore */
2340 rtw_write32(padapter, 0x800, regs->reg_800);
2341 RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type);
2342 return 0;
2343 }
2344
2345 /* 11ac 3wire restore */
2346 switch (phal_data->rf_type) {
2347 case RF_1T1R:
2348 rtw_write32(padapter, 0xC00, regs->reg_c00);
2349 break;
2350 case RF_1T2R:
2351 case RF_2T2R:
2352 rtw_write32(padapter, 0xC00, regs->reg_c00);
2353 rtw_write32(padapter, 0xE00, regs->reg_e00);
2354 break;
2355 case RF_2T3R:
2356 case RF_3T3R:
2357 rtw_write32(padapter, 0xC00, regs->reg_c00);
2358 rtw_write32(padapter, 0xE00, regs->reg_e00);
2359 rtw_write32(padapter, 0x1800, regs->reg_1800);
2360 break;
2361 case RF_2T4R:
2362 case RF_3T4R:
2363 case RF_4T4R:
2364 rtw_write32(padapter, 0xC00, regs->reg_c00);
2365 rtw_write32(padapter, 0xE00, regs->reg_e00);
2366 rtw_write32(padapter, 0x1800, regs->reg_1800);
2367 rtw_write32(padapter, 0x1A00, regs->reg_1a00);
2368 break;
2369 default:
2370 RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2371 break;
2372 }
2373
2374 /* 11ac cck restore */
2375 rtw_write32(padapter, 0x808, regs->reg_808);
2376 RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type);
2377 return 0;
2378 }
2379
2380 /* reg 0x808[9:0]: FFT data x
2381 * reg 0x808[22]: 0 --> 1 to get 1 FFT data y
2382 * reg 0x8B4[15:0]: FFT data y report */
rtw_GetPSDData(PADAPTER pAdapter,u32 point)2383 static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
2384 {
2385 u32 psd_val = 0;
2386
2387 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) \
2388 || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2389
2390 u16 psd_reg = 0x910;
2391 u16 psd_regL = 0xF44;
2392 #else
2393 u16 psd_reg = 0x808;
2394 u16 psd_regL = 0x8B4;
2395 #endif
2396
2397 psd_val = rtw_read32(pAdapter, psd_reg);
2398
2399 psd_val &= 0xFFBFFC00;
2400 psd_val |= point;
2401
2402 rtw_write32(pAdapter, psd_reg, psd_val);
2403 rtw_mdelay_os(1);
2404 psd_val |= 0x00400000;
2405
2406 rtw_write32(pAdapter, psd_reg, psd_val);
2407 rtw_mdelay_os(1);
2408
2409 psd_val = rtw_read32(pAdapter, psd_regL);
2410 #if defined(CONFIG_RTL8821C)
2411 psd_val = (psd_val & 0x00FFFFFF) / 32;
2412 #else
2413 psd_val &= 0x0000FFFF;
2414 #endif
2415
2416 return psd_val;
2417 }
2418
2419 /*
2420 * pts start_point_min stop_point_max
2421 * 128 64 64 + 128 = 192
2422 * 256 128 128 + 256 = 384
2423 * 512 256 256 + 512 = 768
2424 * 1024 512 512 + 1024 = 1536
2425 *
2426 */
mp_query_psd(PADAPTER pAdapter,u8 * data)2427 u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
2428 {
2429 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2430 struct dm_struct *p_dm = adapter_to_phydm(pAdapter);
2431
2432 u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
2433 u32 psd_data = 0;
2434 struct psd_init_regs regs = {};
2435 int psd_analysis = 0;
2436 char *pdata = NULL;
2437
2438
2439 #ifdef PLATFORM_LINUX
2440 if (!netif_running(pAdapter->pnetdev)) {
2441 return 0;
2442 }
2443 #endif
2444
2445 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
2446 return 0;
2447 }
2448
2449 if (strlen(data) == 0) { /* default value */
2450 psd_pts = 128;
2451 psd_start = 64;
2452 psd_stop = 128;
2453 } else if (strncmp(data, "analysis,", 9) == 0) {
2454 if (rtw_mp_psd_init(pAdapter, ®s) != 0)
2455 return 0;
2456 psd_analysis = 1;
2457 sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2458 } else
2459 sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2460
2461 data[0] = '\0';
2462 pdata = data;
2463
2464 if (psd_stop > 1920 || psd_stop < 1) {
2465 rtw_warn_on(1);
2466 psd_stop = 1920;
2467 }
2468
2469 if (IS_HARDWARE_TYPE_8822C(pAdapter) || IS_HARDWARE_TYPE_8723F(pAdapter)) {
2470 u32 *psdbuf = rtw_zmalloc(sizeof(u32)*256);
2471
2472 if (psdbuf == NULL) {
2473 RTW_INFO("%s: psd buf malloc fail!!\n", __func__);
2474 return 0;
2475 }
2476
2477 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_POINT, psd_pts);
2478 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_START_POINT, psd_start);
2479 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_STOP_POINT, psd_stop);
2480 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_AVERAGE, 0x20000);
2481
2482 halrf_psd_init(p_dm);
2483 #ifdef CONFIG_LONG_DELAY_ISSUE
2484 rtw_msleep_os(100);
2485 #else
2486 rtw_mdelay_os(10);
2487 #endif
2488 halrf_psd_query(p_dm, psdbuf, 256);
2489
2490 i = 0;
2491 while (i < 256) {
2492 pdata += sprintf(pdata, "%x ", (psdbuf[i]));
2493 i++;
2494 }
2495
2496 if (psdbuf)
2497 rtw_mfree(psdbuf, sizeof(u32)*256);
2498
2499 } else {
2500 i = psd_start;
2501
2502 while (i < psd_stop) {
2503 if (i >= psd_pts)
2504 psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
2505 else
2506 psd_data = rtw_GetPSDData(pAdapter, i);
2507
2508 pdata += sprintf(pdata, "%x ", psd_data);
2509 i++;
2510 }
2511
2512 }
2513
2514 #ifdef CONFIG_LONG_DELAY_ISSUE
2515 rtw_msleep_os(100);
2516 #else
2517 rtw_mdelay_os(100);
2518 #endif
2519
2520 if (psd_analysis)
2521 rtw_mp_psd_close(pAdapter, ®s);
2522
2523 return strlen(data) + 1;
2524 }
2525
2526
2527 #if 0
2528 void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
2529 {
2530 int i, res;
2531 _adapter *padapter = pxmitpriv->adapter;
2532 struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
2533 struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
2534
2535 u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2536 u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2537 if (padapter->registrypriv.mp_mode == 0) {
2538 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2539 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2540 } else {
2541 max_xmit_extbuf_size = 6000;
2542 num_xmit_extbuf = 8;
2543 }
2544
2545 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2546 for (i = 0; i < num_xmit_extbuf; i++) {
2547 rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
2548
2549 pxmitbuf++;
2550 }
2551
2552 if (pxmitpriv->pallocated_xmit_extbuf)
2553 rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2554
2555 if (padapter->registrypriv.mp_mode == 0) {
2556 max_xmit_extbuf_size = 6000;
2557 num_xmit_extbuf = 8;
2558 } else {
2559 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2560 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2561 }
2562
2563 /* Init xmit extension buff */
2564 _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
2565
2566 pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2567
2568 if (pxmitpriv->pallocated_xmit_extbuf == NULL) {
2569 res = _FAIL;
2570 goto exit;
2571 }
2572
2573 pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
2574
2575 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2576
2577 for (i = 0; i < num_xmit_extbuf; i++) {
2578 _rtw_init_listhead(&pxmitbuf->list);
2579
2580 pxmitbuf->priv_data = NULL;
2581 pxmitbuf->padapter = padapter;
2582 pxmitbuf->buf_tag = XMITBUF_MGNT;
2583
2584 res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
2585 if (res == _FAIL) {
2586 res = _FAIL;
2587 goto exit;
2588 }
2589
2590 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2591 pxmitbuf->phead = pxmitbuf->pbuf;
2592 pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
2593 pxmitbuf->len = 0;
2594 pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
2595 #endif
2596
2597 rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
2598 #ifdef DBG_XMIT_BUF_EXT
2599 pxmitbuf->no = i;
2600 #endif
2601 pxmitbuf++;
2602
2603 }
2604
2605 pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
2606
2607 exit:
2608 ;
2609 }
2610 #endif
2611
2612 u8
mpt_to_mgnt_rate(u32 MptRateIdx)2613 mpt_to_mgnt_rate(
2614 u32 MptRateIdx
2615 )
2616 {
2617 /* Mapped to MGN_XXX defined in MgntGen.h */
2618 switch (MptRateIdx) {
2619 /* CCK rate. */
2620 case MPT_RATE_1M:
2621 return MGN_1M;
2622 case MPT_RATE_2M:
2623 return MGN_2M;
2624 case MPT_RATE_55M:
2625 return MGN_5_5M;
2626 case MPT_RATE_11M:
2627 return MGN_11M;
2628
2629 /* OFDM rate. */
2630 case MPT_RATE_6M:
2631 return MGN_6M;
2632 case MPT_RATE_9M:
2633 return MGN_9M;
2634 case MPT_RATE_12M:
2635 return MGN_12M;
2636 case MPT_RATE_18M:
2637 return MGN_18M;
2638 case MPT_RATE_24M:
2639 return MGN_24M;
2640 case MPT_RATE_36M:
2641 return MGN_36M;
2642 case MPT_RATE_48M:
2643 return MGN_48M;
2644 case MPT_RATE_54M:
2645 return MGN_54M;
2646
2647 /* HT rate. */
2648 case MPT_RATE_MCS0:
2649 return MGN_MCS0;
2650 case MPT_RATE_MCS1:
2651 return MGN_MCS1;
2652 case MPT_RATE_MCS2:
2653 return MGN_MCS2;
2654 case MPT_RATE_MCS3:
2655 return MGN_MCS3;
2656 case MPT_RATE_MCS4:
2657 return MGN_MCS4;
2658 case MPT_RATE_MCS5:
2659 return MGN_MCS5;
2660 case MPT_RATE_MCS6:
2661 return MGN_MCS6;
2662 case MPT_RATE_MCS7:
2663 return MGN_MCS7;
2664 case MPT_RATE_MCS8:
2665 return MGN_MCS8;
2666 case MPT_RATE_MCS9:
2667 return MGN_MCS9;
2668 case MPT_RATE_MCS10:
2669 return MGN_MCS10;
2670 case MPT_RATE_MCS11:
2671 return MGN_MCS11;
2672 case MPT_RATE_MCS12:
2673 return MGN_MCS12;
2674 case MPT_RATE_MCS13:
2675 return MGN_MCS13;
2676 case MPT_RATE_MCS14:
2677 return MGN_MCS14;
2678 case MPT_RATE_MCS15:
2679 return MGN_MCS15;
2680 case MPT_RATE_MCS16:
2681 return MGN_MCS16;
2682 case MPT_RATE_MCS17:
2683 return MGN_MCS17;
2684 case MPT_RATE_MCS18:
2685 return MGN_MCS18;
2686 case MPT_RATE_MCS19:
2687 return MGN_MCS19;
2688 case MPT_RATE_MCS20:
2689 return MGN_MCS20;
2690 case MPT_RATE_MCS21:
2691 return MGN_MCS21;
2692 case MPT_RATE_MCS22:
2693 return MGN_MCS22;
2694 case MPT_RATE_MCS23:
2695 return MGN_MCS23;
2696 case MPT_RATE_MCS24:
2697 return MGN_MCS24;
2698 case MPT_RATE_MCS25:
2699 return MGN_MCS25;
2700 case MPT_RATE_MCS26:
2701 return MGN_MCS26;
2702 case MPT_RATE_MCS27:
2703 return MGN_MCS27;
2704 case MPT_RATE_MCS28:
2705 return MGN_MCS28;
2706 case MPT_RATE_MCS29:
2707 return MGN_MCS29;
2708 case MPT_RATE_MCS30:
2709 return MGN_MCS30;
2710 case MPT_RATE_MCS31:
2711 return MGN_MCS31;
2712
2713 /* VHT rate. */
2714 case MPT_RATE_VHT1SS_MCS0:
2715 return MGN_VHT1SS_MCS0;
2716 case MPT_RATE_VHT1SS_MCS1:
2717 return MGN_VHT1SS_MCS1;
2718 case MPT_RATE_VHT1SS_MCS2:
2719 return MGN_VHT1SS_MCS2;
2720 case MPT_RATE_VHT1SS_MCS3:
2721 return MGN_VHT1SS_MCS3;
2722 case MPT_RATE_VHT1SS_MCS4:
2723 return MGN_VHT1SS_MCS4;
2724 case MPT_RATE_VHT1SS_MCS5:
2725 return MGN_VHT1SS_MCS5;
2726 case MPT_RATE_VHT1SS_MCS6:
2727 return MGN_VHT1SS_MCS6;
2728 case MPT_RATE_VHT1SS_MCS7:
2729 return MGN_VHT1SS_MCS7;
2730 case MPT_RATE_VHT1SS_MCS8:
2731 return MGN_VHT1SS_MCS8;
2732 case MPT_RATE_VHT1SS_MCS9:
2733 return MGN_VHT1SS_MCS9;
2734 case MPT_RATE_VHT2SS_MCS0:
2735 return MGN_VHT2SS_MCS0;
2736 case MPT_RATE_VHT2SS_MCS1:
2737 return MGN_VHT2SS_MCS1;
2738 case MPT_RATE_VHT2SS_MCS2:
2739 return MGN_VHT2SS_MCS2;
2740 case MPT_RATE_VHT2SS_MCS3:
2741 return MGN_VHT2SS_MCS3;
2742 case MPT_RATE_VHT2SS_MCS4:
2743 return MGN_VHT2SS_MCS4;
2744 case MPT_RATE_VHT2SS_MCS5:
2745 return MGN_VHT2SS_MCS5;
2746 case MPT_RATE_VHT2SS_MCS6:
2747 return MGN_VHT2SS_MCS6;
2748 case MPT_RATE_VHT2SS_MCS7:
2749 return MGN_VHT2SS_MCS7;
2750 case MPT_RATE_VHT2SS_MCS8:
2751 return MGN_VHT2SS_MCS8;
2752 case MPT_RATE_VHT2SS_MCS9:
2753 return MGN_VHT2SS_MCS9;
2754 case MPT_RATE_VHT3SS_MCS0:
2755 return MGN_VHT3SS_MCS0;
2756 case MPT_RATE_VHT3SS_MCS1:
2757 return MGN_VHT3SS_MCS1;
2758 case MPT_RATE_VHT3SS_MCS2:
2759 return MGN_VHT3SS_MCS2;
2760 case MPT_RATE_VHT3SS_MCS3:
2761 return MGN_VHT3SS_MCS3;
2762 case MPT_RATE_VHT3SS_MCS4:
2763 return MGN_VHT3SS_MCS4;
2764 case MPT_RATE_VHT3SS_MCS5:
2765 return MGN_VHT3SS_MCS5;
2766 case MPT_RATE_VHT3SS_MCS6:
2767 return MGN_VHT3SS_MCS6;
2768 case MPT_RATE_VHT3SS_MCS7:
2769 return MGN_VHT3SS_MCS7;
2770 case MPT_RATE_VHT3SS_MCS8:
2771 return MGN_VHT3SS_MCS8;
2772 case MPT_RATE_VHT3SS_MCS9:
2773 return MGN_VHT3SS_MCS9;
2774 case MPT_RATE_VHT4SS_MCS0:
2775 return MGN_VHT4SS_MCS0;
2776 case MPT_RATE_VHT4SS_MCS1:
2777 return MGN_VHT4SS_MCS1;
2778 case MPT_RATE_VHT4SS_MCS2:
2779 return MGN_VHT4SS_MCS2;
2780 case MPT_RATE_VHT4SS_MCS3:
2781 return MGN_VHT4SS_MCS3;
2782 case MPT_RATE_VHT4SS_MCS4:
2783 return MGN_VHT4SS_MCS4;
2784 case MPT_RATE_VHT4SS_MCS5:
2785 return MGN_VHT4SS_MCS5;
2786 case MPT_RATE_VHT4SS_MCS6:
2787 return MGN_VHT4SS_MCS6;
2788 case MPT_RATE_VHT4SS_MCS7:
2789 return MGN_VHT4SS_MCS7;
2790 case MPT_RATE_VHT4SS_MCS8:
2791 return MGN_VHT4SS_MCS8;
2792 case MPT_RATE_VHT4SS_MCS9:
2793 return MGN_VHT4SS_MCS9;
2794
2795 case MPT_RATE_LAST: /* fully automatiMGN_VHT2SS_MCS1; */
2796 default:
2797 RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
2798 return 0x0;
2799 }
2800 }
2801
2802
HwRateToMPTRate(u8 rate)2803 u8 HwRateToMPTRate(u8 rate)
2804 {
2805 u8 ret_rate = MGN_1M;
2806
2807 switch (rate) {
2808 case DESC_RATE1M:
2809 ret_rate = MPT_RATE_1M;
2810 break;
2811 case DESC_RATE2M:
2812 ret_rate = MPT_RATE_2M;
2813 break;
2814 case DESC_RATE5_5M:
2815 ret_rate = MPT_RATE_55M;
2816 break;
2817 case DESC_RATE11M:
2818 ret_rate = MPT_RATE_11M;
2819 break;
2820 case DESC_RATE6M:
2821 ret_rate = MPT_RATE_6M;
2822 break;
2823 case DESC_RATE9M:
2824 ret_rate = MPT_RATE_9M;
2825 break;
2826 case DESC_RATE12M:
2827 ret_rate = MPT_RATE_12M;
2828 break;
2829 case DESC_RATE18M:
2830 ret_rate = MPT_RATE_18M;
2831 break;
2832 case DESC_RATE24M:
2833 ret_rate = MPT_RATE_24M;
2834 break;
2835 case DESC_RATE36M:
2836 ret_rate = MPT_RATE_36M;
2837 break;
2838 case DESC_RATE48M:
2839 ret_rate = MPT_RATE_48M;
2840 break;
2841 case DESC_RATE54M:
2842 ret_rate = MPT_RATE_54M;
2843 break;
2844 case DESC_RATEMCS0:
2845 ret_rate = MPT_RATE_MCS0;
2846 break;
2847 case DESC_RATEMCS1:
2848 ret_rate = MPT_RATE_MCS1;
2849 break;
2850 case DESC_RATEMCS2:
2851 ret_rate = MPT_RATE_MCS2;
2852 break;
2853 case DESC_RATEMCS3:
2854 ret_rate = MPT_RATE_MCS3;
2855 break;
2856 case DESC_RATEMCS4:
2857 ret_rate = MPT_RATE_MCS4;
2858 break;
2859 case DESC_RATEMCS5:
2860 ret_rate = MPT_RATE_MCS5;
2861 break;
2862 case DESC_RATEMCS6:
2863 ret_rate = MPT_RATE_MCS6;
2864 break;
2865 case DESC_RATEMCS7:
2866 ret_rate = MPT_RATE_MCS7;
2867 break;
2868 case DESC_RATEMCS8:
2869 ret_rate = MPT_RATE_MCS8;
2870 break;
2871 case DESC_RATEMCS9:
2872 ret_rate = MPT_RATE_MCS9;
2873 break;
2874 case DESC_RATEMCS10:
2875 ret_rate = MPT_RATE_MCS10;
2876 break;
2877 case DESC_RATEMCS11:
2878 ret_rate = MPT_RATE_MCS11;
2879 break;
2880 case DESC_RATEMCS12:
2881 ret_rate = MPT_RATE_MCS12;
2882 break;
2883 case DESC_RATEMCS13:
2884 ret_rate = MPT_RATE_MCS13;
2885 break;
2886 case DESC_RATEMCS14:
2887 ret_rate = MPT_RATE_MCS14;
2888 break;
2889 case DESC_RATEMCS15:
2890 ret_rate = MPT_RATE_MCS15;
2891 break;
2892 case DESC_RATEMCS16:
2893 ret_rate = MPT_RATE_MCS16;
2894 break;
2895 case DESC_RATEMCS17:
2896 ret_rate = MPT_RATE_MCS17;
2897 break;
2898 case DESC_RATEMCS18:
2899 ret_rate = MPT_RATE_MCS18;
2900 break;
2901 case DESC_RATEMCS19:
2902 ret_rate = MPT_RATE_MCS19;
2903 break;
2904 case DESC_RATEMCS20:
2905 ret_rate = MPT_RATE_MCS20;
2906 break;
2907 case DESC_RATEMCS21:
2908 ret_rate = MPT_RATE_MCS21;
2909 break;
2910 case DESC_RATEMCS22:
2911 ret_rate = MPT_RATE_MCS22;
2912 break;
2913 case DESC_RATEMCS23:
2914 ret_rate = MPT_RATE_MCS23;
2915 break;
2916 case DESC_RATEMCS24:
2917 ret_rate = MPT_RATE_MCS24;
2918 break;
2919 case DESC_RATEMCS25:
2920 ret_rate = MPT_RATE_MCS25;
2921 break;
2922 case DESC_RATEMCS26:
2923 ret_rate = MPT_RATE_MCS26;
2924 break;
2925 case DESC_RATEMCS27:
2926 ret_rate = MPT_RATE_MCS27;
2927 break;
2928 case DESC_RATEMCS28:
2929 ret_rate = MPT_RATE_MCS28;
2930 break;
2931 case DESC_RATEMCS29:
2932 ret_rate = MPT_RATE_MCS29;
2933 break;
2934 case DESC_RATEMCS30:
2935 ret_rate = MPT_RATE_MCS30;
2936 break;
2937 case DESC_RATEMCS31:
2938 ret_rate = MPT_RATE_MCS31;
2939 break;
2940 case DESC_RATEVHTSS1MCS0:
2941 ret_rate = MPT_RATE_VHT1SS_MCS0;
2942 break;
2943 case DESC_RATEVHTSS1MCS1:
2944 ret_rate = MPT_RATE_VHT1SS_MCS1;
2945 break;
2946 case DESC_RATEVHTSS1MCS2:
2947 ret_rate = MPT_RATE_VHT1SS_MCS2;
2948 break;
2949 case DESC_RATEVHTSS1MCS3:
2950 ret_rate = MPT_RATE_VHT1SS_MCS3;
2951 break;
2952 case DESC_RATEVHTSS1MCS4:
2953 ret_rate = MPT_RATE_VHT1SS_MCS4;
2954 break;
2955 case DESC_RATEVHTSS1MCS5:
2956 ret_rate = MPT_RATE_VHT1SS_MCS5;
2957 break;
2958 case DESC_RATEVHTSS1MCS6:
2959 ret_rate = MPT_RATE_VHT1SS_MCS6;
2960 break;
2961 case DESC_RATEVHTSS1MCS7:
2962 ret_rate = MPT_RATE_VHT1SS_MCS7;
2963 break;
2964 case DESC_RATEVHTSS1MCS8:
2965 ret_rate = MPT_RATE_VHT1SS_MCS8;
2966 break;
2967 case DESC_RATEVHTSS1MCS9:
2968 ret_rate = MPT_RATE_VHT1SS_MCS9;
2969 break;
2970 case DESC_RATEVHTSS2MCS0:
2971 ret_rate = MPT_RATE_VHT2SS_MCS0;
2972 break;
2973 case DESC_RATEVHTSS2MCS1:
2974 ret_rate = MPT_RATE_VHT2SS_MCS1;
2975 break;
2976 case DESC_RATEVHTSS2MCS2:
2977 ret_rate = MPT_RATE_VHT2SS_MCS2;
2978 break;
2979 case DESC_RATEVHTSS2MCS3:
2980 ret_rate = MPT_RATE_VHT2SS_MCS3;
2981 break;
2982 case DESC_RATEVHTSS2MCS4:
2983 ret_rate = MPT_RATE_VHT2SS_MCS4;
2984 break;
2985 case DESC_RATEVHTSS2MCS5:
2986 ret_rate = MPT_RATE_VHT2SS_MCS5;
2987 break;
2988 case DESC_RATEVHTSS2MCS6:
2989 ret_rate = MPT_RATE_VHT2SS_MCS6;
2990 break;
2991 case DESC_RATEVHTSS2MCS7:
2992 ret_rate = MPT_RATE_VHT2SS_MCS7;
2993 break;
2994 case DESC_RATEVHTSS2MCS8:
2995 ret_rate = MPT_RATE_VHT2SS_MCS8;
2996 break;
2997 case DESC_RATEVHTSS2MCS9:
2998 ret_rate = MPT_RATE_VHT2SS_MCS9;
2999 break;
3000 case DESC_RATEVHTSS3MCS0:
3001 ret_rate = MPT_RATE_VHT3SS_MCS0;
3002 break;
3003 case DESC_RATEVHTSS3MCS1:
3004 ret_rate = MPT_RATE_VHT3SS_MCS1;
3005 break;
3006 case DESC_RATEVHTSS3MCS2:
3007 ret_rate = MPT_RATE_VHT3SS_MCS2;
3008 break;
3009 case DESC_RATEVHTSS3MCS3:
3010 ret_rate = MPT_RATE_VHT3SS_MCS3;
3011 break;
3012 case DESC_RATEVHTSS3MCS4:
3013 ret_rate = MPT_RATE_VHT3SS_MCS4;
3014 break;
3015 case DESC_RATEVHTSS3MCS5:
3016 ret_rate = MPT_RATE_VHT3SS_MCS5;
3017 break;
3018 case DESC_RATEVHTSS3MCS6:
3019 ret_rate = MPT_RATE_VHT3SS_MCS6;
3020 break;
3021 case DESC_RATEVHTSS3MCS7:
3022 ret_rate = MPT_RATE_VHT3SS_MCS7;
3023 break;
3024 case DESC_RATEVHTSS3MCS8:
3025 ret_rate = MPT_RATE_VHT3SS_MCS8;
3026 break;
3027 case DESC_RATEVHTSS3MCS9:
3028 ret_rate = MPT_RATE_VHT3SS_MCS9;
3029 break;
3030 case DESC_RATEVHTSS4MCS0:
3031 ret_rate = MPT_RATE_VHT4SS_MCS0;
3032 break;
3033 case DESC_RATEVHTSS4MCS1:
3034 ret_rate = MPT_RATE_VHT4SS_MCS1;
3035 break;
3036 case DESC_RATEVHTSS4MCS2:
3037 ret_rate = MPT_RATE_VHT4SS_MCS2;
3038 break;
3039 case DESC_RATEVHTSS4MCS3:
3040 ret_rate = MPT_RATE_VHT4SS_MCS3;
3041 break;
3042 case DESC_RATEVHTSS4MCS4:
3043 ret_rate = MPT_RATE_VHT4SS_MCS4;
3044 break;
3045 case DESC_RATEVHTSS4MCS5:
3046 ret_rate = MPT_RATE_VHT4SS_MCS5;
3047 break;
3048 case DESC_RATEVHTSS4MCS6:
3049 ret_rate = MPT_RATE_VHT4SS_MCS6;
3050 break;
3051 case DESC_RATEVHTSS4MCS7:
3052 ret_rate = MPT_RATE_VHT4SS_MCS7;
3053 break;
3054 case DESC_RATEVHTSS4MCS8:
3055 ret_rate = MPT_RATE_VHT4SS_MCS8;
3056 break;
3057 case DESC_RATEVHTSS4MCS9:
3058 ret_rate = MPT_RATE_VHT4SS_MCS9;
3059 break;
3060
3061 default:
3062 RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
3063 break;
3064 }
3065 return ret_rate;
3066 }
3067
rtw_mpRateParseFunc(PADAPTER pAdapter,u8 * targetStr)3068 u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
3069 {
3070 u16 i = 0;
3071 u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
3072 "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
3073 "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
3074 "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
3075 "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
3076 "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
3077 "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
3078 "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
3079 "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
3080 };
3081
3082 for (i = 0; i <= 83; i++) {
3083 if (strcmp(targetStr, rateindex_Array[i]) == 0) {
3084 RTW_INFO("%s , index = %d\n", __func__ , i);
3085 return i;
3086 }
3087 }
3088
3089 printk("%s ,please input a Data RATE String as:", __func__);
3090 for (i = 0; i <= 83; i++) {
3091 printk("%s ", rateindex_Array[i]);
3092 if (i % 10 == 0)
3093 printk("\n");
3094 }
3095 return _FAIL;
3096 }
3097
rtw_mp_mode_check(PADAPTER pAdapter)3098 u8 rtw_mp_mode_check(PADAPTER pAdapter)
3099 {
3100 PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
3101
3102 if (primary_adapter->registrypriv.mp_mode == 1 || primary_adapter->mppriv.bprocess_mp_mode == _TRUE)
3103 return _TRUE;
3104 else
3105 return _FALSE;
3106 }
3107
rtw_is_mp_tssitrk_on(_adapter * adapter)3108 bool rtw_is_mp_tssitrk_on(_adapter *adapter)
3109 {
3110 _adapter *primary_adapter = GET_PRIMARY_ADAPTER(adapter);
3111
3112 return primary_adapter->mppriv.tssitrk_on;
3113 }
3114
mpt_ProQueryCalTxPower(PADAPTER pAdapter,u8 RfPath)3115 u32 mpt_ProQueryCalTxPower(
3116 PADAPTER pAdapter,
3117 u8 RfPath
3118 )
3119 {
3120
3121 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3122 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
3123
3124 u32 TxPower = 1;
3125 struct txpwr_idx_comp tic;
3126 u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
3127 RATE_SECTION rs = mgn_rate_to_rs(mgn_rate);
3128
3129 TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, rs, mgn_rate
3130 , pHalData->current_channel_bw, pHalData->current_band_type, pHalData->current_channel, 0, &tic);
3131
3132 dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RfPath
3133 , pHalData->current_channel_bw, pHalData->current_channel
3134 , mgn_rate, TxPower, &tic);
3135
3136 pAdapter->mppriv.txpoweridx = (u8)TxPower;
3137 if (RfPath == RF_PATH_A)
3138 pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
3139 else if (RfPath == RF_PATH_B)
3140 pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
3141 else if (RfPath == RF_PATH_C)
3142 pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
3143 else if (RfPath == RF_PATH_D)
3144 pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower;
3145 hal_mpt_SetTxPower(pAdapter);
3146
3147 return TxPower;
3148 }
3149
mpt_get_tx_power_finalabs_val(PADAPTER padapter,u8 rf_path)3150 u32 mpt_get_tx_power_finalabs_val(PADAPTER padapter, u8 rf_path)
3151 {
3152 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3153 PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx);
3154
3155 u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
3156 u32 powerdbm = 0;
3157
3158 powerdbm = phy_get_tx_power_final_absolute_value(padapter, rf_path, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel);
3159
3160 RTW_INFO("bw=%d, ch=%d, rateid=%d, TSSI Power(dBm):%d\n",
3161 pHalData->current_channel_bw, pHalData->current_channel, mgn_rate ,powerdbm);
3162
3163 return powerdbm;
3164 }
3165
3166 #ifdef CONFIG_MP_VHT_HW_TX_MODE
dump_buf(u8 * buf,u32 len)3167 static inline void dump_buf(u8 *buf, u32 len)
3168 {
3169 u32 i;
3170
3171 RTW_INFO("-----------------Len %d----------------\n", len);
3172 for (i = 0; i < len; i++)
3173 RTW_INFO("%2.2x-", *(buf + i));
3174 RTW_INFO("\n");
3175 }
3176
ByteToBit(u8 * out,bool * in,u8 in_size)3177 void ByteToBit(
3178 u8 *out,
3179 bool *in,
3180 u8 in_size)
3181 {
3182 u8 i = 0, j = 0;
3183
3184 for (i = 0; i < in_size; i++) {
3185 for (j = 0; j < 8; j++) {
3186 if (in[8 * i + j])
3187 out[i] |= (1 << j);
3188 }
3189 }
3190 }
3191
3192
CRC16_generator(bool * out,bool * in,u8 in_size)3193 void CRC16_generator(
3194 bool *out,
3195 bool *in,
3196 u8 in_size
3197 )
3198 {
3199 u8 i = 0;
3200 bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
3201
3202 for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
3203 temp = in[i] ^ reg[15];
3204 reg[15] = reg[14];
3205 reg[14] = reg[13];
3206 reg[13] = reg[12];
3207 reg[12] = reg[11];
3208 reg[11] = reg[10];
3209 reg[10] = reg[9];
3210 reg[9] = reg[8];
3211 reg[8] = reg[7];
3212
3213 reg[7] = reg[6];
3214 reg[6] = reg[5];
3215 reg[5] = reg[4];
3216 reg[4] = reg[3];
3217 reg[3] = reg[2];
3218 reg[2] = reg[1];
3219 reg[1] = reg[0];
3220 reg[12] = reg[12] ^ temp;
3221 reg[5] = reg[5] ^ temp;
3222 reg[0] = temp;
3223 }
3224 for (i = 0; i < 16; i++) /* take one's complement and bit reverse*/
3225 out[i] = 1 - reg[15 - i];
3226 }
3227
3228
3229
3230 /*========================================
3231 SFD SIGNAL SERVICE LENGTH CRC
3232 16 bit 8 bit 8 bit 16 bit 16 bit
3233 ========================================*/
CCK_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3234 void CCK_generator(
3235 PRT_PMAC_TX_INFO pPMacTxInfo,
3236 PRT_PMAC_PKT_INFO pPMacPktInfo
3237 )
3238 {
3239 double ratio = 0;
3240 bool crc16_in[32] = {0}, crc16_out[16] = {0};
3241 bool LengthExtBit;
3242 double LengthExact;
3243 double LengthPSDU;
3244 u8 i;
3245 u32 PacketLength = pPMacTxInfo->PacketLength;
3246
3247 if (pPMacTxInfo->bSPreamble)
3248 pPMacTxInfo->SFD = 0x05CF;
3249 else
3250 pPMacTxInfo->SFD = 0xF3A0;
3251
3252 switch (pPMacPktInfo->MCS) {
3253 case 0:
3254 pPMacTxInfo->SignalField = 0xA;
3255 ratio = 8;
3256 /*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
3257 crc16_in[1] = crc16_in[3] = 1;
3258 break;
3259 case 1:
3260 pPMacTxInfo->SignalField = 0x14;
3261 ratio = 4;
3262 /*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
3263 crc16_in[2] = crc16_in[4] = 1;
3264 break;
3265 case 2:
3266 pPMacTxInfo->SignalField = 0x37;
3267 ratio = 8.0 / 5.5;
3268 /*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
3269 crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
3270 break;
3271 case 3:
3272 pPMacTxInfo->SignalField = 0x6E;
3273 ratio = 8.0 / 11.0;
3274 /*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
3275 crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
3276 break;
3277 }
3278
3279 LengthExact = PacketLength * ratio;
3280 LengthPSDU = ceil(LengthExact);
3281
3282 if ((pPMacPktInfo->MCS == 3) &&
3283 ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
3284 LengthExtBit = 1;
3285 else
3286 LengthExtBit = 0;
3287
3288
3289 pPMacTxInfo->LENGTH = (u32)LengthPSDU;
3290 /* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
3291 for (i = 0; i < 16; i++)
3292 crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
3293
3294 if (LengthExtBit == 0) {
3295 pPMacTxInfo->ServiceField = 0x0;
3296 /* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
3297 } else {
3298 pPMacTxInfo->ServiceField = 0x80;
3299 /*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
3300 crc16_in[15] = 1;
3301 }
3302
3303 CRC16_generator(crc16_out, crc16_in, 32);
3304
3305 _rtw_memset(pPMacTxInfo->CRC16, 0, 2);
3306 ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
3307
3308 }
3309
3310
PMAC_Get_Pkt_Param(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3311 void PMAC_Get_Pkt_Param(
3312 PRT_PMAC_TX_INFO pPMacTxInfo,
3313 PRT_PMAC_PKT_INFO pPMacPktInfo)
3314 {
3315
3316 u8 TX_RATE_HEX = 0, MCS = 0;
3317 u8 TX_RATE = pPMacTxInfo->TX_RATE;
3318
3319 /* TX_RATE & Nss */
3320 if (MPT_IS_2SS_RATE(TX_RATE))
3321 pPMacPktInfo->Nss = 2;
3322 else if (MPT_IS_3SS_RATE(TX_RATE))
3323 pPMacPktInfo->Nss = 3;
3324 else if (MPT_IS_4SS_RATE(TX_RATE))
3325 pPMacPktInfo->Nss = 4;
3326 else
3327 pPMacPktInfo->Nss = 1;
3328
3329 RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
3330
3331 /* MCS & TX_RATE_HEX*/
3332 if (MPT_IS_CCK_RATE(TX_RATE)) {
3333 switch (TX_RATE) {
3334 case MPT_RATE_1M:
3335 TX_RATE_HEX = MCS = 0;
3336 break;
3337 case MPT_RATE_2M:
3338 TX_RATE_HEX = MCS = 1;
3339 break;
3340 case MPT_RATE_55M:
3341 TX_RATE_HEX = MCS = 2;
3342 break;
3343 case MPT_RATE_11M:
3344 TX_RATE_HEX = MCS = 3;
3345 break;
3346 }
3347 } else if (MPT_IS_OFDM_RATE(TX_RATE)) {
3348 MCS = TX_RATE - MPT_RATE_6M;
3349 TX_RATE_HEX = MCS + 4;
3350 } else if (MPT_IS_HT_RATE(TX_RATE)) {
3351 MCS = TX_RATE - MPT_RATE_MCS0;
3352 TX_RATE_HEX = MCS + 12;
3353 } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3354 TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
3355
3356 if (MPT_IS_VHT_2S_RATE(TX_RATE))
3357 MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
3358 else if (MPT_IS_VHT_3S_RATE(TX_RATE))
3359 MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
3360 else if (MPT_IS_VHT_4S_RATE(TX_RATE))
3361 MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
3362 else
3363 MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
3364 }
3365
3366 pPMacPktInfo->MCS = MCS;
3367 pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
3368
3369 RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
3370 /* mSTBC & Nsts*/
3371 pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
3372 if (pPMacTxInfo->bSTBC) {
3373 if (pPMacPktInfo->Nss == 1) {
3374 pPMacTxInfo->m_STBC = 2;
3375 pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
3376 } else
3377 pPMacTxInfo->m_STBC = 1;
3378 } else
3379 pPMacTxInfo->m_STBC = 1;
3380 }
3381
3382
LDPC_parameter_generator(u32 N_pld_int,u32 N_CBPSS,u32 N_SS,u32 R,u32 m_STBC,u32 N_TCB_int)3383 u32 LDPC_parameter_generator(
3384 u32 N_pld_int,
3385 u32 N_CBPSS,
3386 u32 N_SS,
3387 u32 R,
3388 u32 m_STBC,
3389 u32 N_TCB_int
3390 )
3391 {
3392 double CR = 0.;
3393 double N_pld = (double)N_pld_int;
3394 double N_TCB = (double)N_TCB_int;
3395 double N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
3396 double L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
3397 double N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
3398 double R_eff = 0.;
3399 u32 VHTSIGA2B3 = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
3400
3401 if (R == 0)
3402 CR = 0.5;
3403 else if (R == 1)
3404 CR = 2. / 3.;
3405 else if (R == 2)
3406 CR = 3. / 4.;
3407 else if (R == 3)
3408 CR = 5. / 6.;
3409
3410 if (N_TCB <= 648.) {
3411 N_CW = 1.;
3412 if (N_TCB >= N_pld + 912.*(1. - CR))
3413 L_LDPC = 1296.;
3414 else
3415 L_LDPC = 648.;
3416 } else if (N_TCB <= 1296.) {
3417 N_CW = 1.;
3418 if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
3419 L_LDPC = 1944.;
3420 else
3421 L_LDPC = 1296.;
3422 } else if (N_TCB <= 1944.) {
3423 N_CW = 1.;
3424 L_LDPC = 1944.;
3425 } else if (N_TCB <= 2592.) {
3426 N_CW = 2.;
3427 if (N_TCB >= N_pld + 2916.*(1. - CR))
3428 L_LDPC = 1944.;
3429 else
3430 L_LDPC = 1296.;
3431 } else {
3432 N_CW = ceil(N_pld / 1944. / CR);
3433 L_LDPC = 1944.;
3434 }
3435 /* Number of information bits per CW*/
3436 K_LDPC = L_LDPC * CR;
3437 /* Number of shortening bits max(0, (N_CW * L_LDPC * R) - N_pld)*/
3438 N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
3439 /* Number of shortening bits per CW N_spcw = rtfloor(N_shrt/N_CW)*/
3440 N_spcw = rtfloor(N_shrt / N_CW);
3441 /* The first N_fshrt CWs shorten 1 bit more*/
3442 N_fshrt = (double)((int)N_shrt % (int)N_CW);
3443 /* Number of data bits for the last N_CW-N_fshrt CWs*/
3444 L_LDPC_info = K_LDPC - N_spcw;
3445 /* Number of puncturing bits*/
3446 N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3447 if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
3448 (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
3449 /*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
3450 VHTSIGA2B3 = 1;
3451 N_TCB += (double)N_CBPSS * N_SS * m_STBC;
3452 N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3453 } else
3454 VHTSIGA2B3 = 0;
3455
3456 return VHTSIGA2B3;
3457 } /* function end of LDPC_parameter_generator */
3458
3459 /*========================================
3460 Data field of PPDU
3461 Get N_sym and SIGA2BB3
3462 ========================================*/
PMAC_Nsym_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3463 void PMAC_Nsym_generator(
3464 PRT_PMAC_TX_INFO pPMacTxInfo,
3465 PRT_PMAC_PKT_INFO pPMacPktInfo)
3466 {
3467 u32 SIGA2B3 = 0;
3468 u8 TX_RATE = pPMacTxInfo->TX_RATE;
3469
3470 u32 R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
3471 double CR = 0;
3472 u32 N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
3473 u32 N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
3474 int D_R = 0;
3475
3476 RTW_INFO("TX_RATE = %d\n", TX_RATE);
3477 /* N_SD*/
3478 if (pPMacTxInfo->BandWidth == 0)
3479 N_SD = 52;
3480 else if (pPMacTxInfo->BandWidth == 1)
3481 N_SD = 108;
3482 else
3483 N_SD = 234;
3484
3485 if (MPT_IS_HT_RATE(TX_RATE)) {
3486 u8 MCS_temp;
3487
3488 if (pPMacPktInfo->MCS > 23)
3489 MCS_temp = pPMacPktInfo->MCS - 24;
3490 else if (pPMacPktInfo->MCS > 15)
3491 MCS_temp = pPMacPktInfo->MCS - 16;
3492 else if (pPMacPktInfo->MCS > 7)
3493 MCS_temp = pPMacPktInfo->MCS - 8;
3494 else
3495 MCS_temp = pPMacPktInfo->MCS;
3496
3497 R = R_list[MCS_temp];
3498
3499 switch (R) {
3500 case 0:
3501 CR = .5;
3502 break;
3503 case 1:
3504 CR = 2. / 3.;
3505 break;
3506 case 2:
3507 CR = 3. / 4.;
3508 break;
3509 case 3:
3510 CR = 5. / 6.;
3511 break;
3512 }
3513
3514 N_BPSC = N_BPSC_list[MCS_temp];
3515 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3516 N_DBPS = (u32)((double)N_CBPS * CR);
3517
3518 if (pPMacTxInfo->bLDPC == FALSE) {
3519 N_ES = (u32)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
3520 RTW_INFO("N_ES = %d\n", N_ES);
3521
3522 /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3523 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
3524 (double)(N_DBPS * pPMacTxInfo->m_STBC));
3525
3526 } else {
3527 N_ES = 1;
3528 /* N_pld = length * 8 + 16*/
3529 N_pld = pPMacTxInfo->PacketLength * 8 + 16;
3530 RTW_INFO("N_pld = %d\n", N_pld);
3531 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(N_pld) /
3532 (double)(N_DBPS * pPMacTxInfo->m_STBC));
3533 RTW_INFO("N_SYM = %d\n", N_SYM);
3534 /* N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
3535 N_TCB = N_CBPS * N_SYM;
3536 RTW_INFO("N_TCB = %d\n", N_TCB);
3537 SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3538 RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
3539 N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3540 RTW_INFO("N_SYM = %d\n", N_SYM);
3541 }
3542 } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3543 R = R_list[pPMacPktInfo->MCS];
3544
3545 switch (R) {
3546 case 0:
3547 CR = .5;
3548 break;
3549 case 1:
3550 CR = 2. / 3.;
3551 break;
3552 case 2:
3553 CR = 3. / 4.;
3554 break;
3555 case 3:
3556 CR = 5. / 6.;
3557 break;
3558 }
3559 N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
3560 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3561 N_DBPS = (u32)((double)N_CBPS * CR);
3562 if (pPMacTxInfo->bLDPC == FALSE) {
3563 if (pPMacTxInfo->bSGI)
3564 N_ES = (u32)ceil((double)(N_DBPS) / 3.6 / 600.);
3565 else
3566 N_ES = (u32)ceil((double)(N_DBPS) / 4. / 600.);
3567 /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3568 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3569 SIGA2B3 = 0;
3570 } else {
3571 N_ES = 1;
3572 /* N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
3573 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3574 /* N_avbits = N_sys_init * N_CBPS*/
3575 N_TCB = N_CBPS * N_SYM;
3576 /* N_pld = N_sys_init * N_DBPS*/
3577 N_pld = N_SYM * N_DBPS;
3578 SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3579 N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3580 }
3581
3582 switch (R) {
3583 case 0:
3584 D_R = 2;
3585 break;
3586 case 1:
3587 D_R = 3;
3588 break;
3589 case 2:
3590 D_R = 4;
3591 break;
3592 case 3:
3593 D_R = 6;
3594 break;
3595 }
3596
3597 if (((N_CBPS / N_ES) % D_R) != 0) {
3598 RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3599 return;
3600 }
3601
3602 RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3603 }
3604
3605 pPMacPktInfo->N_sym = N_SYM;
3606 pPMacPktInfo->SIGA2B3 = SIGA2B3;
3607 }
3608
3609 /*========================================
3610 L-SIG Rate R Length P Tail
3611 4b 1b 12b 1b 6b
3612 ========================================*/
3613
L_SIG_generator(u32 N_SYM,PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3614 void L_SIG_generator(
3615 u32 N_SYM, /* Max: 750*/
3616 PRT_PMAC_TX_INFO pPMacTxInfo,
3617 PRT_PMAC_PKT_INFO pPMacPktInfo)
3618 {
3619 u8 sig_bi[24] = {0}; /* 24 BIT*/
3620 u32 mode, LENGTH;
3621 int i;
3622
3623 if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
3624 mode = pPMacPktInfo->MCS;
3625 LENGTH = pPMacTxInfo->PacketLength;
3626 } else {
3627 u8 N_LTF;
3628 double T_data;
3629 u32 OFDM_symbol;
3630
3631 mode = 0;
3632
3633 /* Table 20-13 Num of HT-DLTFs request*/
3634 if (pPMacPktInfo->Nsts <= 2)
3635 N_LTF = pPMacPktInfo->Nsts;
3636 else
3637 N_LTF = 4;
3638
3639 if (pPMacTxInfo->bSGI)
3640 T_data = 3.6;
3641 else
3642 T_data = 4.0;
3643
3644 /*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
3645 if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
3646 OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
3647 else
3648 OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
3649
3650 RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
3651 LENGTH = OFDM_symbol * 3 - 3;
3652 RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
3653
3654 }
3655 /* Rate Field*/
3656 switch (mode) {
3657 case 0:
3658 sig_bi[0] = 1;
3659 sig_bi[1] = 1;
3660 sig_bi[2] = 0;
3661 sig_bi[3] = 1;
3662 break;
3663 case 1:
3664 sig_bi[0] = 1;
3665 sig_bi[1] = 1;
3666 sig_bi[2] = 1;
3667 sig_bi[3] = 1;
3668 break;
3669 case 2:
3670 sig_bi[0] = 0;
3671 sig_bi[1] = 1;
3672 sig_bi[2] = 0;
3673 sig_bi[3] = 1;
3674 break;
3675 case 3:
3676 sig_bi[0] = 0;
3677 sig_bi[1] = 1;
3678 sig_bi[2] = 1;
3679 sig_bi[3] = 1;
3680 break;
3681 case 4:
3682 sig_bi[0] = 1;
3683 sig_bi[1] = 0;
3684 sig_bi[2] = 0;
3685 sig_bi[3] = 1;
3686 break;
3687 case 5:
3688 sig_bi[0] = 1;
3689 sig_bi[1] = 0;
3690 sig_bi[2] = 1;
3691 sig_bi[3] = 1;
3692 break;
3693 case 6:
3694 sig_bi[0] = 0;
3695 sig_bi[1] = 0;
3696 sig_bi[2] = 0;
3697 sig_bi[3] = 1;
3698 break;
3699 case 7:
3700 sig_bi[0] = 0;
3701 sig_bi[1] = 0;
3702 sig_bi[2] = 1;
3703 sig_bi[3] = 1;
3704 break;
3705 }
3706 /*Reserved bit*/
3707 sig_bi[4] = 0;
3708
3709 /* Length Field*/
3710 for (i = 0; i < 12; i++)
3711 sig_bi[i + 5] = (LENGTH >> i) & 1;
3712
3713 /* Parity Bit*/
3714 sig_bi[17] = 0;
3715 for (i = 0; i < 17; i++)
3716 sig_bi[17] = sig_bi[17] + sig_bi[i];
3717
3718 sig_bi[17] %= 2;
3719
3720 /* Tail Field*/
3721 for (i = 18; i < 24; i++)
3722 sig_bi[i] = 0;
3723
3724 /* dump_buf(sig_bi,24);*/
3725 _rtw_memset(pPMacTxInfo->LSIG, 0, 3);
3726 ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
3727 }
3728
3729
CRC8_generator(bool * out,bool * in,u8 in_size)3730 void CRC8_generator(
3731 bool *out,
3732 bool *in,
3733 u8 in_size
3734 )
3735 {
3736 u8 i = 0;
3737 bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
3738
3739 for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
3740 temp = in[i] ^ reg[7];
3741 reg[7] = reg[6];
3742 reg[6] = reg[5];
3743 reg[5] = reg[4];
3744 reg[4] = reg[3];
3745 reg[3] = reg[2];
3746 reg[2] = reg[1] ^ temp;
3747 reg[1] = reg[0] ^ temp;
3748 reg[0] = temp;
3749 }
3750 for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
3751 out[i] = reg[7 - i] ^ 1;
3752 }
3753
3754 /*/================================================================================
3755 HT-SIG1 MCS CW Length 24BIT + 24BIT
3756 7b 1b 16b
3757 HT-SIG2 Smoothing Not sounding Rsvd AGG STBC FEC SGI N_ELTF CRC Tail
3758 1b 1b 1b 1b 2b 1b 1b 2b 8b 6b
3759 ================================================================================*/
HT_SIG_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3760 void HT_SIG_generator(
3761 PRT_PMAC_TX_INFO pPMacTxInfo,
3762 PRT_PMAC_PKT_INFO pPMacPktInfo
3763 )
3764 {
3765 u32 i;
3766 bool sig_bi[48] = {0}, crc8[8] = {0};
3767 /* MCS Field*/
3768 for (i = 0; i < 7; i++)
3769 sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
3770 /* Packet BW Setting*/
3771 sig_bi[7] = pPMacTxInfo->BandWidth;
3772 /* HT-Length Field*/
3773 for (i = 0; i < 16; i++)
3774 sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
3775 /* Smoothing; 1->allow smoothing*/
3776 sig_bi[24] = 1;
3777 /*Not Sounding*/
3778 sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
3779 /*Reserved bit*/
3780 sig_bi[26] = 1;
3781 /*/Aggregate*/
3782 sig_bi[27] = 0;
3783 /*STBC Field*/
3784 if (pPMacTxInfo->bSTBC) {
3785 sig_bi[28] = 1;
3786 sig_bi[29] = 0;
3787 } else {
3788 sig_bi[28] = 0;
3789 sig_bi[29] = 0;
3790 }
3791 /*Advance Coding, 0: BCC, 1: LDPC*/
3792 sig_bi[30] = pPMacTxInfo->bLDPC;
3793 /* Short GI*/
3794 sig_bi[31] = pPMacTxInfo->bSGI;
3795 /* N_ELTFs*/
3796 if (pPMacTxInfo->NDP_sound == FALSE) {
3797 sig_bi[32] = 0;
3798 sig_bi[33] = 0;
3799 } else {
3800 int N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
3801
3802 for (i = 0; i < 2; i++)
3803 sig_bi[32 + i] = (N_ELTF >> i) % 2;
3804 }
3805 /* CRC-8*/
3806 CRC8_generator(crc8, sig_bi, 34);
3807
3808 for (i = 0; i < 8; i++)
3809 sig_bi[34 + i] = crc8[i];
3810
3811 /*Tail*/
3812 for (i = 42; i < 48; i++)
3813 sig_bi[i] = 0;
3814
3815 _rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
3816 ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
3817 }
3818
3819
3820 /*======================================================================================
3821 VHT-SIG-A1
3822 BW Reserved STBC G_ID SU_Nsts P_AID TXOP_PS_NOT_ALLOW Reserved
3823 2b 1b 1b 6b 3b 9b 1b 2b 1b
3824 VHT-SIG-A2
3825 SGI SGI_Nsym SU/MU coding LDPC_Extra SU_NCS Beamformed Reserved CRC Tail
3826 1b 1b 1b 1b 4b 1b 1b 8b 6b
3827 ======================================================================================*/
VHT_SIG_A_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3828 void VHT_SIG_A_generator(
3829 PRT_PMAC_TX_INFO pPMacTxInfo,
3830 PRT_PMAC_PKT_INFO pPMacPktInfo)
3831 {
3832 u32 i;
3833 bool sig_bi[48], crc8[8];
3834
3835 _rtw_memset(sig_bi, 0, 48);
3836 _rtw_memset(crc8, 0, 8);
3837
3838 /* BW Setting*/
3839 for (i = 0; i < 2; i++)
3840 sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
3841 /* Reserved Bit*/
3842 sig_bi[2] = 1;
3843 /*STBC Field*/
3844 sig_bi[3] = pPMacTxInfo->bSTBC;
3845 /*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
3846 for (i = 0; i < 6; i++)
3847 sig_bi[4 + i] = 0;
3848 /* N_STS/Partial AID*/
3849 for (i = 0; i < 12; i++) {
3850 if (i < 3)
3851 sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
3852 else
3853 sig_bi[10 + i] = 0;
3854 }
3855 /*TXOP_PS_NOT_ALLPWED*/
3856 sig_bi[22] = 0;
3857 /*Reserved Bits*/
3858 sig_bi[23] = 1;
3859 /*Short GI*/
3860 sig_bi[24] = pPMacTxInfo->bSGI;
3861 if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
3862 sig_bi[25] = 1;
3863 else
3864 sig_bi[25] = 0;
3865 /* SU/MU[0] Coding*/
3866 sig_bi[26] = pPMacTxInfo->bLDPC; /* 0:BCC, 1:LDPC */
3867 sig_bi[27] = pPMacPktInfo->SIGA2B3; /*/ Record Extra OFDM Symols is added or not when LDPC is used*/
3868 /*SU MCS/MU[1-3] Coding*/
3869 for (i = 0; i < 4; i++)
3870 sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
3871 /*SU Beamform */
3872 sig_bi[32] = 0; /*packet.TXBF_en;*/
3873 /*Reserved Bit*/
3874 sig_bi[33] = 1;
3875 /*CRC-8*/
3876 CRC8_generator(crc8, sig_bi, 34);
3877 for (i = 0; i < 8; i++)
3878 sig_bi[34 + i] = crc8[i];
3879 /*Tail*/
3880 for (i = 42; i < 48; i++)
3881 sig_bi[i] = 0;
3882
3883 _rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
3884 ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
3885 }
3886
3887 /*======================================================================================
3888 VHT-SIG-B
3889 Length Resesrved Trail
3890 17/19/21 BIT 3/2/2 BIT 6b
3891 ======================================================================================*/
VHT_SIG_B_generator(PRT_PMAC_TX_INFO pPMacTxInfo)3892 void VHT_SIG_B_generator(
3893 PRT_PMAC_TX_INFO pPMacTxInfo)
3894 {
3895 bool sig_bi[32], crc8_bi[8];
3896 u32 i, len, res, tail = 6, total_len, crc8_in_len;
3897 u32 sigb_len;
3898
3899 _rtw_memset(sig_bi, 0, 32);
3900 _rtw_memset(crc8_bi, 0, 8);
3901
3902 /*Sounding Packet*/
3903 if (pPMacTxInfo->NDP_sound == 1) {
3904 if (pPMacTxInfo->BandWidth == 0) {
3905 bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3906
3907 _rtw_memcpy(sig_bi, sigb_temp, 26);
3908 } else if (pPMacTxInfo->BandWidth == 1) {
3909 bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
3910
3911 _rtw_memcpy(sig_bi, sigb_temp, 27);
3912 } else if (pPMacTxInfo->BandWidth == 2) {
3913 bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3914
3915 _rtw_memcpy(sig_bi, sigb_temp, 29);
3916 }
3917 } else { /* Not NDP Sounding*/
3918 bool *sigb_temp[29] = {0};
3919
3920 if (pPMacTxInfo->BandWidth == 0) {
3921 len = 17;
3922 res = 3;
3923 } else if (pPMacTxInfo->BandWidth == 1) {
3924 len = 19;
3925 res = 2;
3926 } else if (pPMacTxInfo->BandWidth == 2) {
3927 len = 21;
3928 res = 2;
3929 } else {
3930 len = 21;
3931 res = 2;
3932 }
3933 total_len = len + res + tail;
3934 crc8_in_len = len + res;
3935
3936 /*Length Field*/
3937 sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
3938
3939 for (i = 0; i < len; i++)
3940 sig_bi[i] = (sigb_len >> i) & 0x1;
3941 /*Reserved Field*/
3942 for (i = 0; i < res; i++)
3943 sig_bi[len + i] = 1;
3944 /* CRC-8*/
3945 CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
3946
3947 /* Tail */
3948 for (i = 0; i < tail; i++)
3949 sig_bi[len + res + i] = 0;
3950 }
3951
3952 _rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
3953 ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
3954
3955 pPMacTxInfo->VHT_SIG_B_CRC = 0;
3956 ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
3957 }
3958
3959 /*=======================
3960 VHT Delimiter
3961 =======================*/
VHT_Delimiter_generator(PRT_PMAC_TX_INFO pPMacTxInfo)3962 void VHT_Delimiter_generator(
3963 PRT_PMAC_TX_INFO pPMacTxInfo
3964 )
3965 {
3966 bool sig_bi[32] = {0}, crc8[8] = {0};
3967 u32 crc8_in_len = 16;
3968 u32 PacketLength = pPMacTxInfo->PacketLength;
3969 int j;
3970
3971 /* Delimiter[0]: EOF*/
3972 sig_bi[0] = 1;
3973 /* Delimiter[1]: Reserved*/
3974 sig_bi[1] = 0;
3975 /* Delimiter[3:2]: MPDU Length High*/
3976 sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
3977 sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
3978 /* Delimiter[15:4]: MPDU Length Low*/
3979 for (j = 4; j < 16; j++)
3980 sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
3981 CRC8_generator(crc8, sig_bi, crc8_in_len);
3982 for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
3983 sig_bi[j] = crc8[j - 16];
3984 for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
3985 sig_bi[j] = (78 >> (j - 24)) % 2;
3986
3987 _rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
3988 ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
3989 }
3990
3991 #endif
3992 #endif
3993