xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/include/rtw_mp.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef _RTW_MP_H_
16*4882a593Smuzhiyun #define _RTW_MP_H_
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define RTWPRIV_VER_INFO	1
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define MAX_MP_XMITBUF_SZ	2048
21*4882a593Smuzhiyun #define NR_MP_XMITFRAME		8
22*4882a593Smuzhiyun #define MP_READ_REG_MAX_OFFSET 0x4FFF
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun struct mp_xmit_frame {
25*4882a593Smuzhiyun 	_list	list;
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	struct pkt_attrib attrib;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	_pkt *pkt;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	int frame_tag;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	_adapter *padapter;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	/* insert urb, irp, and irpcnt info below... */
38*4882a593Smuzhiyun 	/* max frag_cnt = 8 */
39*4882a593Smuzhiyun 	u8 *mem_addr;
40*4882a593Smuzhiyun 	u32 sz[8];
41*4882a593Smuzhiyun 	u8 bpending[8];
42*4882a593Smuzhiyun 	sint ac_tag[8];
43*4882a593Smuzhiyun 	sint last[8];
44*4882a593Smuzhiyun 	uint irpcnt;
45*4882a593Smuzhiyun 	uint fragcnt;
46*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun struct mp_wiparam {
52*4882a593Smuzhiyun 	u32 bcompleted;
53*4882a593Smuzhiyun 	u32 act_type;
54*4882a593Smuzhiyun 	u32 io_offset;
55*4882a593Smuzhiyun 	u32 io_value;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun typedef void(*wi_act_func)(void *padapter);
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun struct mp_tx {
61*4882a593Smuzhiyun 	u8 stop;
62*4882a593Smuzhiyun 	u32 count, sended;
63*4882a593Smuzhiyun 	u8 payload;
64*4882a593Smuzhiyun 	struct pkt_attrib attrib;
65*4882a593Smuzhiyun 	/* struct tx_desc desc; */
66*4882a593Smuzhiyun 	/* u8 resvdtx[7]; */
67*4882a593Smuzhiyun 	u8 desc[TXDESC_SIZE];
68*4882a593Smuzhiyun 	u8 *pallocated_buf;
69*4882a593Smuzhiyun 	u8 *buf;
70*4882a593Smuzhiyun 	u32 buf_size, write_size;
71*4882a593Smuzhiyun 	_thread_hdl_ PktTxThread;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define MP_MAX_LINES		1000
75*4882a593Smuzhiyun #define MP_MAX_LINES_BYTES	256
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun typedef struct _RT_PMAC_PKT_INFO {
79*4882a593Smuzhiyun 	u8			MCS;
80*4882a593Smuzhiyun 	u8			Nss;
81*4882a593Smuzhiyun 	u8			Nsts;
82*4882a593Smuzhiyun 	u32			N_sym;
83*4882a593Smuzhiyun 	u8			SIGA2B3;
84*4882a593Smuzhiyun } RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun typedef struct _RT_PMAC_TX_INFO {
87*4882a593Smuzhiyun 	u8			bEnPMacTx:1;		/* 0: Disable PMac 1: Enable PMac */
88*4882a593Smuzhiyun 	u8			Mode:3;				/* 0: Packet TX 3:Continuous TX */
89*4882a593Smuzhiyun 	u8			Ntx:4;				/* 0-7 */
90*4882a593Smuzhiyun 	u8			TX_RATE;			/* MPT_RATE_E */
91*4882a593Smuzhiyun 	u8			TX_RATE_HEX;
92*4882a593Smuzhiyun 	u8			TX_SC;
93*4882a593Smuzhiyun 	u8			bSGI:1;
94*4882a593Smuzhiyun 	u8			bSPreamble:1;
95*4882a593Smuzhiyun 	u8			bSTBC:1;
96*4882a593Smuzhiyun 	u8			bLDPC:1;
97*4882a593Smuzhiyun 	u8			NDP_sound:1;
98*4882a593Smuzhiyun 	u8			BandWidth:3;		/* 0: 20 1:40 2:80Mhz */
99*4882a593Smuzhiyun 	u8			m_STBC;			/* bSTBC + 1 */
100*4882a593Smuzhiyun 	u16			PacketPeriod;
101*4882a593Smuzhiyun 	u32		PacketCount;
102*4882a593Smuzhiyun 	u32		PacketLength;
103*4882a593Smuzhiyun 	u8			PacketPattern;
104*4882a593Smuzhiyun 	u16			SFD;
105*4882a593Smuzhiyun 	u8			SignalField;
106*4882a593Smuzhiyun 	u8			ServiceField;
107*4882a593Smuzhiyun 	u16			LENGTH;
108*4882a593Smuzhiyun 	u8			CRC16[2];
109*4882a593Smuzhiyun 	u8			LSIG[3];
110*4882a593Smuzhiyun 	u8			HT_SIG[6];
111*4882a593Smuzhiyun 	u8			VHT_SIG_A[6];
112*4882a593Smuzhiyun 	u8			VHT_SIG_B[4];
113*4882a593Smuzhiyun 	u8			VHT_SIG_B_CRC;
114*4882a593Smuzhiyun 	u8			VHT_Delimiter[4];
115*4882a593Smuzhiyun 	u8			MacAddress[6];
116*4882a593Smuzhiyun } RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun typedef void (*MPT_WORK_ITEM_HANDLER)(void *Adapter);
120*4882a593Smuzhiyun typedef struct _MPT_CONTEXT {
121*4882a593Smuzhiyun 	/* Indicate if we have started Mass Production Test. */
122*4882a593Smuzhiyun 	BOOLEAN			bMassProdTest;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* Indicate if the driver is unloading or unloaded. */
125*4882a593Smuzhiyun 	BOOLEAN			bMptDrvUnload;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	_sema			MPh2c_Sema;
128*4882a593Smuzhiyun 	_timer			MPh2c_timeout_timer;
129*4882a593Smuzhiyun 	/* Event used to sync H2c for BT control */
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	BOOLEAN		MptH2cRspEvent;
132*4882a593Smuzhiyun 	BOOLEAN		MptBtC2hEvent;
133*4882a593Smuzhiyun 	BOOLEAN		bMPh2c_timeout;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* 8190 PCI does not support NDIS_WORK_ITEM. */
136*4882a593Smuzhiyun 	/* Work Item for Mass Production Test. */
137*4882a593Smuzhiyun 	/* NDIS_WORK_ITEM	MptWorkItem;
138*4882a593Smuzhiyun 	*	RT_WORK_ITEM		MptWorkItem; */
139*4882a593Smuzhiyun 	/* Event used to sync the case unloading driver and MptWorkItem is still in progress.
140*4882a593Smuzhiyun 	*	NDIS_EVENT		MptWorkItemEvent; */
141*4882a593Smuzhiyun 	/* To protect the following variables.
142*4882a593Smuzhiyun 	*	NDIS_SPIN_LOCK		MptWorkItemSpinLock; */
143*4882a593Smuzhiyun 	/* Indicate a MptWorkItem is scheduled and not yet finished. */
144*4882a593Smuzhiyun 	BOOLEAN			bMptWorkItemInProgress;
145*4882a593Smuzhiyun 	/* An instance which implements function and context of MptWorkItem. */
146*4882a593Smuzhiyun 	MPT_WORK_ITEM_HANDLER	CurrMptAct;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	/* 1=Start, 0=Stop from UI. */
149*4882a593Smuzhiyun 	u32			MptTestStart;
150*4882a593Smuzhiyun 	/* _TEST_MODE, defined in MPT_Req2.h */
151*4882a593Smuzhiyun 	u32			MptTestItem;
152*4882a593Smuzhiyun 	/* Variable needed in each implementation of CurrMptAct. */
153*4882a593Smuzhiyun 	u32			MptActType;	/* Type of action performed in CurrMptAct. */
154*4882a593Smuzhiyun 	/* The Offset of IO operation is depend of MptActType. */
155*4882a593Smuzhiyun 	u32			MptIoOffset;
156*4882a593Smuzhiyun 	/* The Value of IO operation is depend of MptActType. */
157*4882a593Smuzhiyun 	u32			MptIoValue;
158*4882a593Smuzhiyun 	/* The RfPath of IO operation is depend of MptActType. */
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	u32			mpt_rf_path;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	WIRELESS_MODE		MptWirelessModeToSw;	/* Wireless mode to switch. */
164*4882a593Smuzhiyun 	u8			MptChannelToSw;	/* Channel to switch. */
165*4882a593Smuzhiyun 	u8			MptInitGainToSet;	/* Initial gain to set. */
166*4882a593Smuzhiyun 	/* u32			bMptAntennaA;		 */ /* TRUE if we want to use antenna A. */
167*4882a593Smuzhiyun 	u32			MptBandWidth;		/* bandwidth to switch. */
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	u32			mpt_rate_index;/* rate index. */
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	/* Register value kept for Single Carrier Tx test. */
172*4882a593Smuzhiyun 	u8			btMpCckTxPower;
173*4882a593Smuzhiyun 	/* Register value kept for Single Carrier Tx test. */
174*4882a593Smuzhiyun 	u8			btMpOfdmTxPower;
175*4882a593Smuzhiyun 	/* For MP Tx Power index */
176*4882a593Smuzhiyun 	u8			TxPwrLevel[4];	/* rf-A, rf-B*/
177*4882a593Smuzhiyun 	u32			RegTxPwrLimit;
178*4882a593Smuzhiyun 	/* Content of RCR Regsiter for Mass Production Test. */
179*4882a593Smuzhiyun 	u32			MptRCR;
180*4882a593Smuzhiyun 	/* TRUE if we only receive packets with specific pattern. */
181*4882a593Smuzhiyun 	BOOLEAN			bMptFilterPattern;
182*4882a593Smuzhiyun 	/* Rx OK count, statistics used in Mass Production Test. */
183*4882a593Smuzhiyun 	u32			MptRxOkCnt;
184*4882a593Smuzhiyun 	/* Rx CRC32 error count, statistics used in Mass Production Test. */
185*4882a593Smuzhiyun 	u32			MptRxCrcErrCnt;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	BOOLEAN			bCckContTx;	/* TRUE if we are in CCK Continuous Tx test. */
188*4882a593Smuzhiyun 	BOOLEAN			bOfdmContTx;	/* TRUE if we are in OFDM Continuous Tx test. */
189*4882a593Smuzhiyun 		/* TRUE if we have start Continuous Tx test. */
190*4882a593Smuzhiyun 	BOOLEAN			is_start_cont_tx;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	/* TRUE if we are in Single Carrier Tx test. */
193*4882a593Smuzhiyun 	BOOLEAN			bSingleCarrier;
194*4882a593Smuzhiyun 	/* TRUE if we are in Carrier Suppression Tx Test. */
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	BOOLEAN			is_carrier_suppression;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	/* TRUE if we are in Single Tone Tx test. */
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	BOOLEAN			is_single_tone;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	/* ACK counter asked by K.Y.. */
204*4882a593Smuzhiyun 	BOOLEAN			bMptEnableAckCounter;
205*4882a593Smuzhiyun 	u32			MptAckCounter;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* SD3 Willis For 8192S to save 1T/2T RF table for ACUT	Only fro ACUT delete later ~~~! */
208*4882a593Smuzhiyun 	/* s8		BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */
209*4882a593Smuzhiyun 	/* s8			BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */
210*4882a593Smuzhiyun 	/* s32			RfReadLine[2]; */
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	u8		APK_bound[2];	/* for APK	path A/path B */
213*4882a593Smuzhiyun 	BOOLEAN		bMptIndexEven;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	u8		backup0xc50;
216*4882a593Smuzhiyun 	u8		backup0xc58;
217*4882a593Smuzhiyun 	u8		backup0xc30;
218*4882a593Smuzhiyun 	u8		backup0x52_RF_A;
219*4882a593Smuzhiyun 	u8		backup0x52_RF_B;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	u32			backup0x58_RF_A;
222*4882a593Smuzhiyun 	u32			backup0x58_RF_B;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	u8			h2cReqNum;
225*4882a593Smuzhiyun 	u8			c2hBuf[32];
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	u8          btInBuf[100];
228*4882a593Smuzhiyun 	u32			mptOutLen;
229*4882a593Smuzhiyun 	u8          mptOutBuf[100];
230*4882a593Smuzhiyun 	RT_PMAC_TX_INFO	PMacTxInfo;
231*4882a593Smuzhiyun 	RT_PMAC_PKT_INFO	PMacPktInfo;
232*4882a593Smuzhiyun 	u8 HWTxmode;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	BOOLEAN			bldpc;
235*4882a593Smuzhiyun 	BOOLEAN			bstbc;
236*4882a593Smuzhiyun } MPT_CONTEXT, *PMPT_CONTEXT;
237*4882a593Smuzhiyun /* #endif */
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun /* #define RTPRIV_IOCTL_MP					( SIOCIWFIRSTPRIV + 0x17) */
241*4882a593Smuzhiyun enum {
242*4882a593Smuzhiyun 	WRITE_REG = 1,
243*4882a593Smuzhiyun 	READ_REG,
244*4882a593Smuzhiyun 	WRITE_RF,
245*4882a593Smuzhiyun 	READ_RF,
246*4882a593Smuzhiyun 	MP_START,
247*4882a593Smuzhiyun 	MP_STOP,
248*4882a593Smuzhiyun 	MP_RATE,
249*4882a593Smuzhiyun 	MP_CHANNEL,
250*4882a593Smuzhiyun 	MP_CHL_OFFSET,
251*4882a593Smuzhiyun 	MP_BANDWIDTH,
252*4882a593Smuzhiyun 	MP_TXPOWER,
253*4882a593Smuzhiyun 	MP_ANT_TX,
254*4882a593Smuzhiyun 	MP_ANT_RX,
255*4882a593Smuzhiyun 	MP_CTX,
256*4882a593Smuzhiyun 	MP_QUERY,
257*4882a593Smuzhiyun 	MP_ARX,
258*4882a593Smuzhiyun 	MP_PSD,
259*4882a593Smuzhiyun 	MP_PWRTRK,
260*4882a593Smuzhiyun 	MP_THER,
261*4882a593Smuzhiyun 	MP_IOCTL,
262*4882a593Smuzhiyun 	EFUSE_GET,
263*4882a593Smuzhiyun 	EFUSE_SET,
264*4882a593Smuzhiyun 	MP_RESET_STATS,
265*4882a593Smuzhiyun 	MP_DUMP,
266*4882a593Smuzhiyun 	MP_PHYPARA,
267*4882a593Smuzhiyun 	MP_SetRFPathSwh,
268*4882a593Smuzhiyun 	MP_QueryDrvStats,
269*4882a593Smuzhiyun 	CTA_TEST,
270*4882a593Smuzhiyun 	MP_DISABLE_BT_COEXIST,
271*4882a593Smuzhiyun 	MP_PwrCtlDM,
272*4882a593Smuzhiyun 	MP_GETVER,
273*4882a593Smuzhiyun 	MP_MON,
274*4882a593Smuzhiyun 	EFUSE_BT_MASK,
275*4882a593Smuzhiyun 	EFUSE_MASK,
276*4882a593Smuzhiyun 	EFUSE_FILE,
277*4882a593Smuzhiyun 	EFUSE_FILE_STORE,
278*4882a593Smuzhiyun 	MP_TX,
279*4882a593Smuzhiyun 	MP_RX,
280*4882a593Smuzhiyun 	MP_IQK,
281*4882a593Smuzhiyun 	MP_LCK,
282*4882a593Smuzhiyun 	MP_HW_TX_MODE,
283*4882a593Smuzhiyun 	MP_GET_TXPOWER_INX,
284*4882a593Smuzhiyun 	MP_CUSTOMER_STR,
285*4882a593Smuzhiyun 	MP_PWRLMT,
286*4882a593Smuzhiyun 	MP_PWRBYRATE,
287*4882a593Smuzhiyun 	BT_EFUSE_FILE,
288*4882a593Smuzhiyun 	MP_SetBT,
289*4882a593Smuzhiyun 	MP_SWRFPath,
290*4882a593Smuzhiyun 	MP_LINK,
291*4882a593Smuzhiyun 	MP_DPK_TRK,
292*4882a593Smuzhiyun 	MP_DPK,
293*4882a593Smuzhiyun 	MP_GET_TSSIDE,
294*4882a593Smuzhiyun 	MP_SET_TSSIDE,
295*4882a593Smuzhiyun 	MP_NULL,
296*4882a593Smuzhiyun #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
297*4882a593Smuzhiyun 	VENDOR_IE_SET ,
298*4882a593Smuzhiyun 	VENDOR_IE_GET ,
299*4882a593Smuzhiyun #endif
300*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
301*4882a593Smuzhiyun 	MP_WOW_ENABLE,
302*4882a593Smuzhiyun 	MP_WOW_SET_PATTERN,
303*4882a593Smuzhiyun #endif
304*4882a593Smuzhiyun #ifdef CONFIG_AP_WOWLAN
305*4882a593Smuzhiyun 	MP_AP_WOW_ENABLE,
306*4882a593Smuzhiyun #endif
307*4882a593Smuzhiyun 	MP_SD_IREAD,
308*4882a593Smuzhiyun 	MP_SD_IWRITE,
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun struct mp_priv {
312*4882a593Smuzhiyun 	_adapter *papdater;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	/* Testing Flag */
315*4882a593Smuzhiyun 	u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	u32 prev_fw_state;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	/* OID cmd handler */
320*4882a593Smuzhiyun 	struct mp_wiparam workparam;
321*4882a593Smuzhiyun 	/*	u8 act_in_progress; */
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	/* Tx Section */
324*4882a593Smuzhiyun 	u8 TID;
325*4882a593Smuzhiyun 	u32 tx_pktcount;
326*4882a593Smuzhiyun 	u32 pktInterval;
327*4882a593Smuzhiyun 	u32 pktLength;
328*4882a593Smuzhiyun 	struct mp_tx tx;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	/* Rx Section */
331*4882a593Smuzhiyun 	u32 rx_bssidpktcount;
332*4882a593Smuzhiyun 	u32 rx_pktcount;
333*4882a593Smuzhiyun 	u32 rx_pktcount_filter_out;
334*4882a593Smuzhiyun 	u32 rx_crcerrpktcount;
335*4882a593Smuzhiyun 	u32 rx_pktloss;
336*4882a593Smuzhiyun 	BOOLEAN  rx_bindicatePkt;
337*4882a593Smuzhiyun 	struct recv_stat rxstat;
338*4882a593Smuzhiyun 	BOOLEAN brx_filter_beacon;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	/* RF/BB relative */
341*4882a593Smuzhiyun 	u8 channel;
342*4882a593Smuzhiyun 	u8 bandwidth;
343*4882a593Smuzhiyun 	u8 prime_channel_offset;
344*4882a593Smuzhiyun 	u8 txpoweridx;
345*4882a593Smuzhiyun 	u8 rateidx;
346*4882a593Smuzhiyun 	u32 preamble;
347*4882a593Smuzhiyun 	/*	u8 modem; */
348*4882a593Smuzhiyun 	u32 CrystalCap;
349*4882a593Smuzhiyun 	/*	u32 curr_crystalcap; */
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	u16 antenna_tx;
352*4882a593Smuzhiyun 	u16 antenna_rx;
353*4882a593Smuzhiyun 	/*	u8 curr_rfpath; */
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	u8 check_mp_pkt;
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	u8 bSetTxPower;
358*4882a593Smuzhiyun 	/*	uint ForcedDataRate; */
359*4882a593Smuzhiyun 	u8 mp_dm;
360*4882a593Smuzhiyun 	u8 mac_filter[ETH_ALEN];
361*4882a593Smuzhiyun 	u8 bmac_filter;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	/* RF PATH Setting for WLG WLA BTG BT */
364*4882a593Smuzhiyun 	u8 rf_path_cfg;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	struct wlan_network mp_network;
367*4882a593Smuzhiyun 	NDIS_802_11_MAC_ADDRESS network_macaddr;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	u8 *pallocated_mp_xmitframe_buf;
370*4882a593Smuzhiyun 	u8 *pmp_xmtframe_buf;
371*4882a593Smuzhiyun 	_queue free_mp_xmitqueue;
372*4882a593Smuzhiyun 	u32 free_mp_xmitframe_cnt;
373*4882a593Smuzhiyun 	BOOLEAN bSetRxBssid;
374*4882a593Smuzhiyun 	BOOLEAN bTxBufCkFail;
375*4882a593Smuzhiyun 	BOOLEAN bRTWSmbCfg;
376*4882a593Smuzhiyun 	BOOLEAN bloopback;
377*4882a593Smuzhiyun 	BOOLEAN bloadefusemap;
378*4882a593Smuzhiyun 	BOOLEAN bloadBTefusemap;
379*4882a593Smuzhiyun 	BOOLEAN bprocess_mp_mode;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	MPT_CONTEXT	mpt_ctx;
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	u8		*TXradomBuffer;
384*4882a593Smuzhiyun 	u8		CureFuseBTCoex;
385*4882a593Smuzhiyun     u8		mplink_buf[2048];
386*4882a593Smuzhiyun     u32		mplink_rx_len;
387*4882a593Smuzhiyun 	BOOLEAN mplink_brx;
388*4882a593Smuzhiyun 	BOOLEAN mplink_btx;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	bool tssitrk_on;
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun typedef struct _IOCMD_STRUCT_ {
394*4882a593Smuzhiyun 	u8	cmdclass;
395*4882a593Smuzhiyun 	u16	value;
396*4882a593Smuzhiyun 	u8	index;
397*4882a593Smuzhiyun } IOCMD_STRUCT;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun struct rf_reg_param {
400*4882a593Smuzhiyun 	u32 path;
401*4882a593Smuzhiyun 	u32 offset;
402*4882a593Smuzhiyun 	u32 value;
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun struct bb_reg_param {
406*4882a593Smuzhiyun 	u32 offset;
407*4882a593Smuzhiyun 	u32 value;
408*4882a593Smuzhiyun };
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun typedef struct _MP_FIRMWARE {
411*4882a593Smuzhiyun 	FIRMWARE_SOURCE eFWSource;
412*4882a593Smuzhiyun #ifdef CONFIG_EMBEDDED_FWIMG
413*4882a593Smuzhiyun 	u8		*szFwBuffer;
414*4882a593Smuzhiyun #else
415*4882a593Smuzhiyun 	u8			szFwBuffer[0x8000];
416*4882a593Smuzhiyun #endif
417*4882a593Smuzhiyun 	u32		ulFwLength;
418*4882a593Smuzhiyun } RT_MP_FIRMWARE, *PRT_MP_FIRMWARE;
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun /* *********************************************************************** */
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun #define LOWER	_TRUE
426*4882a593Smuzhiyun #define RAISE	_FALSE
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun /* Hardware Registers */
429*4882a593Smuzhiyun #if 0
430*4882a593Smuzhiyun #if 0
431*4882a593Smuzhiyun #define IOCMD_CTRL_REG			0x102502C0
432*4882a593Smuzhiyun #define IOCMD_DATA_REG			0x102502C4
433*4882a593Smuzhiyun #else
434*4882a593Smuzhiyun #define IOCMD_CTRL_REG			0x10250370
435*4882a593Smuzhiyun #define IOCMD_DATA_REG			0x10250374
436*4882a593Smuzhiyun #endif
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun #define IOCMD_GET_THERMAL_METER		0xFD000028
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun #define IOCMD_CLASS_BB_RF		0xF0
441*4882a593Smuzhiyun #define IOCMD_BB_READ_IDX		0x00
442*4882a593Smuzhiyun #define IOCMD_BB_WRITE_IDX		0x01
443*4882a593Smuzhiyun #define IOCMD_RF_READ_IDX		0x02
444*4882a593Smuzhiyun #define IOCMD_RF_WRIT_IDX		0x03
445*4882a593Smuzhiyun #endif
446*4882a593Smuzhiyun #define BB_REG_BASE_ADDR		0x800
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun /* MP variables */
449*4882a593Smuzhiyun #if 0
450*4882a593Smuzhiyun #define _2MAC_MODE_	0
451*4882a593Smuzhiyun #define _LOOPBOOK_MODE_	1
452*4882a593Smuzhiyun #endif
453*4882a593Smuzhiyun typedef enum _MP_MODE_ {
454*4882a593Smuzhiyun 	MP_OFF,
455*4882a593Smuzhiyun 	MP_ON,
456*4882a593Smuzhiyun 	MP_ERR,
457*4882a593Smuzhiyun 	MP_CONTINUOUS_TX,
458*4882a593Smuzhiyun 	MP_SINGLE_CARRIER_TX,
459*4882a593Smuzhiyun 	MP_CARRIER_SUPPRISSION_TX,
460*4882a593Smuzhiyun 	MP_SINGLE_TONE_TX,
461*4882a593Smuzhiyun 	MP_PACKET_TX,
462*4882a593Smuzhiyun 	MP_PACKET_RX
463*4882a593Smuzhiyun } MP_MODE;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun typedef enum _TEST_MODE {
466*4882a593Smuzhiyun 	TEST_NONE                 ,
467*4882a593Smuzhiyun 	PACKETS_TX                ,
468*4882a593Smuzhiyun 	PACKETS_RX                ,
469*4882a593Smuzhiyun 	CONTINUOUS_TX             ,
470*4882a593Smuzhiyun 	OFDM_Single_Tone_TX       ,
471*4882a593Smuzhiyun 	CCK_Carrier_Suppression_TX
472*4882a593Smuzhiyun } TEST_MODE;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun typedef enum _MPT_BANDWIDTH {
476*4882a593Smuzhiyun 	MPT_BW_20MHZ = 0,
477*4882a593Smuzhiyun 	MPT_BW_40MHZ_DUPLICATE = 1,
478*4882a593Smuzhiyun 	MPT_BW_40MHZ_ABOVE = 2,
479*4882a593Smuzhiyun 	MPT_BW_40MHZ_BELOW = 3,
480*4882a593Smuzhiyun 	MPT_BW_40MHZ = 4,
481*4882a593Smuzhiyun 	MPT_BW_80MHZ = 5,
482*4882a593Smuzhiyun 	MPT_BW_80MHZ_20_ABOVE = 6,
483*4882a593Smuzhiyun 	MPT_BW_80MHZ_20_BELOW = 7,
484*4882a593Smuzhiyun 	MPT_BW_80MHZ_20_BOTTOM = 8,
485*4882a593Smuzhiyun 	MPT_BW_80MHZ_20_TOP = 9,
486*4882a593Smuzhiyun 	MPT_BW_80MHZ_40_ABOVE = 10,
487*4882a593Smuzhiyun 	MPT_BW_80MHZ_40_BELOW = 11,
488*4882a593Smuzhiyun } MPT_BANDWIDTHE, *PMPT_BANDWIDTH;
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun #define MAX_RF_PATH_NUMS	RF_PATH_MAX
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun extern u8 mpdatarate[NumRates];
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun /* MP set force data rate base on the definition. */
496*4882a593Smuzhiyun typedef enum _MPT_RATE_INDEX {
497*4882a593Smuzhiyun 	/* CCK rate. */
498*4882a593Smuzhiyun 	MPT_RATE_1M = 1 ,	/* 0 */
499*4882a593Smuzhiyun 	MPT_RATE_2M,
500*4882a593Smuzhiyun 	MPT_RATE_55M,
501*4882a593Smuzhiyun 	MPT_RATE_11M,	/* 3 */
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	/* OFDM rate. */
504*4882a593Smuzhiyun 	MPT_RATE_6M,	/* 4 */
505*4882a593Smuzhiyun 	MPT_RATE_9M,
506*4882a593Smuzhiyun 	MPT_RATE_12M,
507*4882a593Smuzhiyun 	MPT_RATE_18M,
508*4882a593Smuzhiyun 	MPT_RATE_24M,
509*4882a593Smuzhiyun 	MPT_RATE_36M,
510*4882a593Smuzhiyun 	MPT_RATE_48M,
511*4882a593Smuzhiyun 	MPT_RATE_54M,	/* 11 */
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	/* HT rate. */
514*4882a593Smuzhiyun 	MPT_RATE_MCS0,	/* 12 */
515*4882a593Smuzhiyun 	MPT_RATE_MCS1,
516*4882a593Smuzhiyun 	MPT_RATE_MCS2,
517*4882a593Smuzhiyun 	MPT_RATE_MCS3,
518*4882a593Smuzhiyun 	MPT_RATE_MCS4,
519*4882a593Smuzhiyun 	MPT_RATE_MCS5,
520*4882a593Smuzhiyun 	MPT_RATE_MCS6,
521*4882a593Smuzhiyun 	MPT_RATE_MCS7,	/* 19 */
522*4882a593Smuzhiyun 	MPT_RATE_MCS8,
523*4882a593Smuzhiyun 	MPT_RATE_MCS9,
524*4882a593Smuzhiyun 	MPT_RATE_MCS10,
525*4882a593Smuzhiyun 	MPT_RATE_MCS11,
526*4882a593Smuzhiyun 	MPT_RATE_MCS12,
527*4882a593Smuzhiyun 	MPT_RATE_MCS13,
528*4882a593Smuzhiyun 	MPT_RATE_MCS14,
529*4882a593Smuzhiyun 	MPT_RATE_MCS15,	/* 27 */
530*4882a593Smuzhiyun 	MPT_RATE_MCS16,
531*4882a593Smuzhiyun 	MPT_RATE_MCS17, /*  #29 */
532*4882a593Smuzhiyun 	MPT_RATE_MCS18,
533*4882a593Smuzhiyun 	MPT_RATE_MCS19,
534*4882a593Smuzhiyun 	MPT_RATE_MCS20,
535*4882a593Smuzhiyun 	MPT_RATE_MCS21,
536*4882a593Smuzhiyun 	MPT_RATE_MCS22, /*  #34 */
537*4882a593Smuzhiyun 	MPT_RATE_MCS23,
538*4882a593Smuzhiyun 	MPT_RATE_MCS24,
539*4882a593Smuzhiyun 	MPT_RATE_MCS25,
540*4882a593Smuzhiyun 	MPT_RATE_MCS26,
541*4882a593Smuzhiyun 	MPT_RATE_MCS27, /*  #39 */
542*4882a593Smuzhiyun 	MPT_RATE_MCS28, /*  #40 */
543*4882a593Smuzhiyun 	MPT_RATE_MCS29, /*  #41 */
544*4882a593Smuzhiyun 	MPT_RATE_MCS30, /*  #42 */
545*4882a593Smuzhiyun 	MPT_RATE_MCS31, /*  #43 */
546*4882a593Smuzhiyun 	/* VHT rate. Total: 20*/
547*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS0 = 100,/*  #44*/
548*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS1, /*  # */
549*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS2,
550*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS3,
551*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS4,
552*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS5,
553*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS6, /*  # */
554*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS7,
555*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS8,
556*4882a593Smuzhiyun 	MPT_RATE_VHT1SS_MCS9, /* #53 */
557*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS0, /* #54 */
558*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS1,
559*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS2,
560*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS3,
561*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS4,
562*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS5,
563*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS6,
564*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS7,
565*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS8,
566*4882a593Smuzhiyun 	MPT_RATE_VHT2SS_MCS9, /* #63 */
567*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS0,
568*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS1,
569*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS2,
570*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS3,
571*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS4,
572*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS5,
573*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS6, /*  #126 */
574*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS7,
575*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS8,
576*4882a593Smuzhiyun 	MPT_RATE_VHT3SS_MCS9,
577*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS0,
578*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS1, /*  #131 */
579*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS2,
580*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS3,
581*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS4,
582*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS5,
583*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS6, /*  #136 */
584*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS7,
585*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS8,
586*4882a593Smuzhiyun 	MPT_RATE_VHT4SS_MCS9,
587*4882a593Smuzhiyun 	MPT_RATE_LAST
588*4882a593Smuzhiyun } MPT_RATE_E, *PMPT_RATE_E;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun #define MAX_TX_PWR_INDEX_N_MODE 64	/* 0x3F */
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun #define MPT_IS_CCK_RATE(_value)		(MPT_RATE_1M <= _value && _value <= MPT_RATE_11M)
593*4882a593Smuzhiyun #define MPT_IS_OFDM_RATE(_value)	(MPT_RATE_6M <= _value && _value <= MPT_RATE_54M)
594*4882a593Smuzhiyun #define MPT_IS_HT_RATE(_value)		(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31)
595*4882a593Smuzhiyun #define MPT_IS_HT_1S_RATE(_value)	(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7)
596*4882a593Smuzhiyun #define MPT_IS_HT_2S_RATE(_value)	(MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15)
597*4882a593Smuzhiyun #define MPT_IS_HT_3S_RATE(_value)	(MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23)
598*4882a593Smuzhiyun #define MPT_IS_HT_4S_RATE(_value)	(MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31)
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun #define MPT_IS_VHT_RATE(_value)		(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
601*4882a593Smuzhiyun #define MPT_IS_VHT_1S_RATE(_value)	(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9)
602*4882a593Smuzhiyun #define MPT_IS_VHT_2S_RATE(_value)	(MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9)
603*4882a593Smuzhiyun #define MPT_IS_VHT_3S_RATE(_value)	(MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9)
604*4882a593Smuzhiyun #define MPT_IS_VHT_4S_RATE(_value)	(MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun #define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \
607*4882a593Smuzhiyun 	(MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9))
608*4882a593Smuzhiyun #define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \
609*4882a593Smuzhiyun 	(MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9))
610*4882a593Smuzhiyun #define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \
611*4882a593Smuzhiyun 	(MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9))
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun typedef enum _POWER_MODE_ {
614*4882a593Smuzhiyun 	POWER_LOW = 0,
615*4882a593Smuzhiyun 	POWER_NORMAL
616*4882a593Smuzhiyun } POWER_MODE;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun /* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */
619*4882a593Smuzhiyun typedef enum _OFDM_TX_MODE {
620*4882a593Smuzhiyun 	OFDM_ALL_OFF		= 0,
621*4882a593Smuzhiyun 	OFDM_ContinuousTx	= 1,
622*4882a593Smuzhiyun 	OFDM_SingleCarrier	= 2,
623*4882a593Smuzhiyun 	OFDM_SingleTone	= 4,
624*4882a593Smuzhiyun } OFDM_TX_MODE;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun #define RX_PKT_BROADCAST	1
628*4882a593Smuzhiyun #define RX_PKT_DEST_ADDR	2
629*4882a593Smuzhiyun #define RX_PKT_PHY_MATCH	3
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun typedef enum _ENCRY_CTRL_STATE_ {
632*4882a593Smuzhiyun 	HW_CONTROL,		/* hw encryption& decryption */
633*4882a593Smuzhiyun 	SW_CONTROL,		/* sw encryption& decryption */
634*4882a593Smuzhiyun 	HW_ENCRY_SW_DECRY,	/* hw encryption & sw decryption */
635*4882a593Smuzhiyun 	SW_ENCRY_HW_DECRY	/* sw encryption & hw decryption */
636*4882a593Smuzhiyun } ENCRY_CTRL_STATE;
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun typedef enum	_MPT_TXPWR_DEF {
639*4882a593Smuzhiyun 	MPT_CCK,
640*4882a593Smuzhiyun 	MPT_OFDM, /* L and HT OFDM */
641*4882a593Smuzhiyun 	MPT_OFDM_AND_HT,
642*4882a593Smuzhiyun 	MPT_HT,
643*4882a593Smuzhiyun 	MPT_VHT
644*4882a593Smuzhiyun } MPT_TXPWR_DEF;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun #define IS_MPT_HT_RATE(_rate)			(_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31)
648*4882a593Smuzhiyun #define IS_MPT_VHT_RATE(_rate)			(_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9)
649*4882a593Smuzhiyun #define IS_MPT_CCK_RATE(_rate)			(_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M)
650*4882a593Smuzhiyun #define IS_MPT_OFDM_RATE(_rate)			(_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M)
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun typedef enum _mp_tx_pkt_payload{
653*4882a593Smuzhiyun 	MP_TX_Payload_00 = 0,
654*4882a593Smuzhiyun 	MP_TX_Payload_a5,
655*4882a593Smuzhiyun 	MP_TX_Payload_5a,
656*4882a593Smuzhiyun 	MP_TX_Payload_ff,
657*4882a593Smuzhiyun 	MP_TX_Payload_prbs9,
658*4882a593Smuzhiyun 	MP_TX_Payload_default_random
659*4882a593Smuzhiyun } mp_tx_pkt_payload;
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun /*************************************************************************/
662*4882a593Smuzhiyun #if 0
663*4882a593Smuzhiyun extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);
664*4882a593Smuzhiyun extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);
665*4882a593Smuzhiyun #endif
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun extern s32 init_mp_priv(PADAPTER padapter);
668*4882a593Smuzhiyun extern void free_mp_priv(struct mp_priv *pmp_priv);
669*4882a593Smuzhiyun extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel);
670*4882a593Smuzhiyun extern void MPT_DeInitAdapter(PADAPTER padapter);
671*4882a593Smuzhiyun extern s32 mp_start_test(PADAPTER padapter);
672*4882a593Smuzhiyun extern void mp_stop_test(PADAPTER padapter);
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask);
675*4882a593Smuzhiyun extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz);
678*4882a593Smuzhiyun extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz);
679*4882a593Smuzhiyun extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask);
680*4882a593Smuzhiyun extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);
681*4882a593Smuzhiyun extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr);
682*4882a593Smuzhiyun extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val);
683*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY
684*4882a593Smuzhiyun u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain);
685*4882a593Smuzhiyun #endif
686*4882a593Smuzhiyun void	SetChannel(PADAPTER pAdapter);
687*4882a593Smuzhiyun void	SetBandwidth(PADAPTER pAdapter);
688*4882a593Smuzhiyun int	SetTxPower(PADAPTER pAdapter);
689*4882a593Smuzhiyun void	SetAntenna(PADAPTER pAdapter);
690*4882a593Smuzhiyun void	SetDataRate(PADAPTER pAdapter);
691*4882a593Smuzhiyun void	SetAntenna(PADAPTER pAdapter);
692*4882a593Smuzhiyun s32	SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
693*4882a593Smuzhiyun void	GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value);
694*4882a593Smuzhiyun void	SetContinuousTx(PADAPTER pAdapter, u8 bStart);
695*4882a593Smuzhiyun void	SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
696*4882a593Smuzhiyun void	SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
697*4882a593Smuzhiyun void	SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
698*4882a593Smuzhiyun void	PhySetTxPowerLevel(PADAPTER pAdapter);
699*4882a593Smuzhiyun void	fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc);
700*4882a593Smuzhiyun void	SetPacketTx(PADAPTER padapter);
701*4882a593Smuzhiyun void	SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB);
702*4882a593Smuzhiyun void	ResetPhyRxPktCount(PADAPTER pAdapter);
703*4882a593Smuzhiyun u32	GetPhyRxPktReceived(PADAPTER pAdapter);
704*4882a593Smuzhiyun u32	GetPhyRxPktCRC32Error(PADAPTER pAdapter);
705*4882a593Smuzhiyun s32	SetPowerTracking(PADAPTER padapter, u8 enable);
706*4882a593Smuzhiyun void	GetPowerTracking(PADAPTER padapter, u8 *enable);
707*4882a593Smuzhiyun u32	mp_query_psd(PADAPTER pAdapter, u8 *data);
708*4882a593Smuzhiyun void	rtw_mp_trigger_iqk(PADAPTER padapter);
709*4882a593Smuzhiyun void	rtw_mp_trigger_lck(PADAPTER padapter);
710*4882a593Smuzhiyun void	rtw_mp_trigger_dpk(PADAPTER padapter);
711*4882a593Smuzhiyun u8 rtw_mp_mode_check(PADAPTER padapter);
712*4882a593Smuzhiyun bool rtw_is_mp_tssitrk_on(_adapter *adapter);
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun void hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
715*4882a593Smuzhiyun s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable);
716*4882a593Smuzhiyun void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable);
717*4882a593Smuzhiyun void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
718*4882a593Smuzhiyun void hal_mpt_SetChannel(PADAPTER pAdapter);
719*4882a593Smuzhiyun void hal_mpt_SetBandwidth(PADAPTER pAdapter);
720*4882a593Smuzhiyun void hal_mpt_SetTxPower(PADAPTER pAdapter);
721*4882a593Smuzhiyun void hal_mpt_SetDataRate(PADAPTER pAdapter);
722*4882a593Smuzhiyun void hal_mpt_SetAntenna(PADAPTER pAdapter);
723*4882a593Smuzhiyun s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
724*4882a593Smuzhiyun void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter);
725*4882a593Smuzhiyun u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path);
726*4882a593Smuzhiyun void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value);
727*4882a593Smuzhiyun void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart);
728*4882a593Smuzhiyun void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
729*4882a593Smuzhiyun void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
730*4882a593Smuzhiyun void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
731*4882a593Smuzhiyun u8 mpt_ProSetPMacTx(PADAPTER	Adapter);
732*4882a593Smuzhiyun void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain);
733*4882a593Smuzhiyun void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate);
734*4882a593Smuzhiyun u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter);
735*4882a593Smuzhiyun u32 mpt_ProQueryCalTxPower(PADAPTER	pAdapter, u8 RfPath);
736*4882a593Smuzhiyun void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type);
737*4882a593Smuzhiyun u8 mpt_to_mgnt_rate(u32	MptRateIdx);
738*4882a593Smuzhiyun u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr);
739*4882a593Smuzhiyun u32 mp_join(PADAPTER padapter, u8 mode);
740*4882a593Smuzhiyun u32 hal_mpt_query_phytxok(PADAPTER	pAdapter);
741*4882a593Smuzhiyun u32 mpt_get_tx_power_finalabs_val(PADAPTER	padapter, u8 rf_path);
742*4882a593Smuzhiyun void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path);
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun void
746*4882a593Smuzhiyun PMAC_Get_Pkt_Param(
747*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo,
748*4882a593Smuzhiyun 	PRT_PMAC_PKT_INFO	pPMacPktInfo
749*4882a593Smuzhiyun );
750*4882a593Smuzhiyun void
751*4882a593Smuzhiyun CCK_generator(
752*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo,
753*4882a593Smuzhiyun 	PRT_PMAC_PKT_INFO	pPMacPktInfo
754*4882a593Smuzhiyun );
755*4882a593Smuzhiyun void
756*4882a593Smuzhiyun PMAC_Nsym_generator(
757*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo,
758*4882a593Smuzhiyun 	PRT_PMAC_PKT_INFO	pPMacPktInfo
759*4882a593Smuzhiyun );
760*4882a593Smuzhiyun void
761*4882a593Smuzhiyun L_SIG_generator(
762*4882a593Smuzhiyun 	u32	N_SYM,		/* Max: 750*/
763*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo,
764*4882a593Smuzhiyun 	PRT_PMAC_PKT_INFO	pPMacPktInfo
765*4882a593Smuzhiyun );
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun void HT_SIG_generator(
768*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo,
769*4882a593Smuzhiyun 	PRT_PMAC_PKT_INFO	pPMacPktInfo);
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun void VHT_SIG_A_generator(
772*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo,
773*4882a593Smuzhiyun 	PRT_PMAC_PKT_INFO	pPMacPktInfo);
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun void VHT_SIG_B_generator(
776*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo);
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun void VHT_Delimiter_generator(
779*4882a593Smuzhiyun 	PRT_PMAC_TX_INFO	pPMacTxInfo);
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun int rtw_mp_write_reg(struct net_device *dev,
783*4882a593Smuzhiyun 		struct iw_request_info *info,
784*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
785*4882a593Smuzhiyun int rtw_mp_read_reg(struct net_device *dev,
786*4882a593Smuzhiyun 		struct iw_request_info *info,
787*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
788*4882a593Smuzhiyun int rtw_mp_write_rf(struct net_device *dev,
789*4882a593Smuzhiyun 		struct iw_request_info *info,
790*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
791*4882a593Smuzhiyun int rtw_mp_read_rf(struct net_device *dev,
792*4882a593Smuzhiyun 		struct iw_request_info *info,
793*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
794*4882a593Smuzhiyun int rtw_mp_start(struct net_device *dev,
795*4882a593Smuzhiyun 		struct iw_request_info *info,
796*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
797*4882a593Smuzhiyun int rtw_mp_stop(struct net_device *dev,
798*4882a593Smuzhiyun 		struct iw_request_info *info,
799*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
800*4882a593Smuzhiyun int rtw_mp_rate(struct net_device *dev,
801*4882a593Smuzhiyun 		struct iw_request_info *info,
802*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
803*4882a593Smuzhiyun int rtw_mp_channel(struct net_device *dev,
804*4882a593Smuzhiyun 		struct iw_request_info *info,
805*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
806*4882a593Smuzhiyun int rtw_mp_ch_offset(struct net_device *dev,
807*4882a593Smuzhiyun 		struct iw_request_info *info,
808*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
809*4882a593Smuzhiyun int rtw_mp_bandwidth(struct net_device *dev,
810*4882a593Smuzhiyun 		struct iw_request_info *info,
811*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
812*4882a593Smuzhiyun int rtw_mp_txpower_index(struct net_device *dev,
813*4882a593Smuzhiyun 		struct iw_request_info *info,
814*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
815*4882a593Smuzhiyun int rtw_mp_txpower(struct net_device *dev,
816*4882a593Smuzhiyun 		struct iw_request_info *info,
817*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
818*4882a593Smuzhiyun int rtw_mp_txpower(struct net_device *dev,
819*4882a593Smuzhiyun 		struct iw_request_info *info,
820*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
821*4882a593Smuzhiyun int rtw_mp_ant_tx(struct net_device *dev,
822*4882a593Smuzhiyun 		struct iw_request_info *info,
823*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
824*4882a593Smuzhiyun int rtw_mp_ant_rx(struct net_device *dev,
825*4882a593Smuzhiyun 		struct iw_request_info *info,
826*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
827*4882a593Smuzhiyun int rtw_set_ctx_destAddr(struct net_device *dev,
828*4882a593Smuzhiyun 		struct iw_request_info *info,
829*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
830*4882a593Smuzhiyun int rtw_mp_ctx(struct net_device *dev,
831*4882a593Smuzhiyun 		struct iw_request_info *info,
832*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
833*4882a593Smuzhiyun int rtw_mp_disable_bt_coexist(struct net_device *dev,
834*4882a593Smuzhiyun 		struct iw_request_info *info,
835*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
836*4882a593Smuzhiyun int rtw_mp_disable_bt_coexist(struct net_device *dev,
837*4882a593Smuzhiyun 		struct iw_request_info *info,
838*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
839*4882a593Smuzhiyun int rtw_mp_arx(struct net_device *dev,
840*4882a593Smuzhiyun 		struct iw_request_info *info,
841*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
842*4882a593Smuzhiyun int rtw_mp_trx_query(struct net_device *dev,
843*4882a593Smuzhiyun 		struct iw_request_info *info,
844*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
845*4882a593Smuzhiyun int rtw_mp_pwrtrk(struct net_device *dev,
846*4882a593Smuzhiyun 		struct iw_request_info *info,
847*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
848*4882a593Smuzhiyun int rtw_mp_psd(struct net_device *dev,
849*4882a593Smuzhiyun 		struct iw_request_info *info,
850*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
851*4882a593Smuzhiyun int rtw_mp_thermal(struct net_device *dev,
852*4882a593Smuzhiyun 		struct iw_request_info *info,
853*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
854*4882a593Smuzhiyun int rtw_mp_reset_stats(struct net_device *dev,
855*4882a593Smuzhiyun 		struct iw_request_info *info,
856*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
857*4882a593Smuzhiyun int rtw_mp_dump(struct net_device *dev,
858*4882a593Smuzhiyun 		struct iw_request_info *info,
859*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
860*4882a593Smuzhiyun int rtw_mp_phypara(struct net_device *dev,
861*4882a593Smuzhiyun 		struct iw_request_info *info,
862*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
863*4882a593Smuzhiyun int rtw_mp_SetRFPath(struct net_device *dev,
864*4882a593Smuzhiyun 		struct iw_request_info *info,
865*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
866*4882a593Smuzhiyun int rtw_mp_switch_rf_path(struct net_device *dev,
867*4882a593Smuzhiyun 			struct iw_request_info *info,
868*4882a593Smuzhiyun 			struct iw_point *wrqu, char *extra);
869*4882a593Smuzhiyun int rtw_mp_link(struct net_device *dev,
870*4882a593Smuzhiyun 		struct iw_request_info *info,
871*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
872*4882a593Smuzhiyun int rtw_mp_QueryDrv(struct net_device *dev,
873*4882a593Smuzhiyun 		struct iw_request_info *info,
874*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
875*4882a593Smuzhiyun int rtw_mp_PwrCtlDM(struct net_device *dev,
876*4882a593Smuzhiyun 		struct iw_request_info *info,
877*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
878*4882a593Smuzhiyun int rtw_mp_getver(struct net_device *dev,
879*4882a593Smuzhiyun 		struct iw_request_info *info,
880*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
881*4882a593Smuzhiyun int rtw_mp_mon(struct net_device *dev,
882*4882a593Smuzhiyun 		struct iw_request_info *info,
883*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
884*4882a593Smuzhiyun int rtw_mp_pwrlmt(struct net_device *dev,
885*4882a593Smuzhiyun 		struct iw_request_info *info,
886*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
887*4882a593Smuzhiyun int rtw_mp_pwrbyrate(struct net_device *dev,
888*4882a593Smuzhiyun 		struct iw_request_info *info,
889*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
890*4882a593Smuzhiyun int rtw_mp_dpk_track(struct net_device *dev,
891*4882a593Smuzhiyun 			struct iw_request_info *info,
892*4882a593Smuzhiyun 			union iwreq_data *wrqu, char *extra);
893*4882a593Smuzhiyun int rtw_mp_dpk(struct net_device *dev,
894*4882a593Smuzhiyun 			struct iw_request_info *info,
895*4882a593Smuzhiyun 			union iwreq_data *wrqu, char *extra);
896*4882a593Smuzhiyun int rtw_efuse_mask_file(struct net_device *dev,
897*4882a593Smuzhiyun 		struct iw_request_info *info,
898*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
899*4882a593Smuzhiyun int rtw_bt_efuse_mask_file(struct net_device *dev,
900*4882a593Smuzhiyun 		struct iw_request_info *info,
901*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
902*4882a593Smuzhiyun int rtw_efuse_file_map(struct net_device *dev,
903*4882a593Smuzhiyun 		struct iw_request_info *info,
904*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
905*4882a593Smuzhiyun int rtw_efuse_file_map_store(struct net_device *dev,
906*4882a593Smuzhiyun 		struct iw_request_info *info,
907*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
908*4882a593Smuzhiyun int rtw_bt_efuse_file_map(struct net_device *dev,
909*4882a593Smuzhiyun 		struct iw_request_info *info,
910*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
911*4882a593Smuzhiyun int rtw_mp_SetBT(struct net_device *dev,
912*4882a593Smuzhiyun 		struct iw_request_info *info,
913*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
914*4882a593Smuzhiyun int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra);
915*4882a593Smuzhiyun int rtw_mp_tx(struct net_device *dev,
916*4882a593Smuzhiyun 		struct iw_request_info *info,
917*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
918*4882a593Smuzhiyun int rtw_mp_rx(struct net_device *dev,
919*4882a593Smuzhiyun 		struct iw_request_info *info,
920*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
921*4882a593Smuzhiyun int rtw_mp_hwtx(struct net_device *dev,
922*4882a593Smuzhiyun 		struct iw_request_info *info,
923*4882a593Smuzhiyun 		union iwreq_data *wrqu, char *extra);
924*4882a593Smuzhiyun u8 HwRateToMPTRate(u8 rate);
925*4882a593Smuzhiyun int rtw_mp_iqk(struct net_device *dev,
926*4882a593Smuzhiyun 		 struct iw_request_info *info,
927*4882a593Smuzhiyun 		 struct iw_point *wrqu, char *extra);
928*4882a593Smuzhiyun int rtw_mp_lck(struct net_device *dev,
929*4882a593Smuzhiyun 		struct iw_request_info *info,
930*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
931*4882a593Smuzhiyun int rtw_mp_get_tsside(struct net_device *dev,
932*4882a593Smuzhiyun 		struct iw_request_info *info,
933*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
934*4882a593Smuzhiyun int rtw_mp_set_tsside(struct net_device *dev,
935*4882a593Smuzhiyun 		struct iw_request_info *info,
936*4882a593Smuzhiyun 		struct iw_point *wrqu, char *extra);
937*4882a593Smuzhiyun #endif /* _RTW_MP_H_ */
938