1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8723D_XMIT_H__ 16*4882a593Smuzhiyun #define __RTL8723D_XMIT_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MAX_TID (15) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef __INC_HAL8723DDESC_H 23*4882a593Smuzhiyun #define __INC_HAL8723DDESC_H 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define RX_STATUS_DESC_SIZE_8723D 24 26*4882a593Smuzhiyun #define RX_DRV_INFO_SIZE_UNIT_8723D 8 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* DWORD 0 */ 30*4882a593Smuzhiyun #define SET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc, __Value) \ 31*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) 32*4882a593Smuzhiyun #define SET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc, __Value) \ 33*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) 34*4882a593Smuzhiyun #define SET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc, __Value) \ 35*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc) \ 38*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) 39*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_CRC32_8723D(__pRxStatusDesc) \ 40*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) 41*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_ICV_8723D(__pRxStatusDesc) \ 42*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) 43*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(__pRxStatusDesc) \ 44*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) 45*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_SECURITY_8723D(__pRxStatusDesc) \ 46*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) 47*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_QOS_8723D(__pRxStatusDesc) \ 48*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) 49*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_SHIFT_8723D(__pRxStatusDesc) \ 50*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) 51*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_PHY_STATUS_8723D(__pRxStatusDesc) \ 52*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) 53*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_SWDEC_8723D(__pRxStatusDesc) \ 54*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) 55*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc) \ 56*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) 57*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc) \ 58*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* DWORD 1 */ 61*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_MACID_8723D(__pRxDesc) \ 62*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) 63*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_TID_8723D(__pRxDesc) \ 64*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) 65*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_AMSDU_8723D(__pRxDesc) \ 66*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) 67*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_RXID_MATCH_8723D(__pRxDesc) \ 68*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) 69*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_PAGGR_8723D(__pRxDesc) \ 70*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) 71*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_A1_FIT_8723D(__pRxDesc) \ 72*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) 73*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_CHKERR_8723D(__pRxDesc) \ 74*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) 75*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_IPVER_8723D(__pRxDesc) \ 76*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) 77*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_IS_TCPUDP__8723D(__pRxDesc) \ 78*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) 79*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_CHK_VLD_8723D(__pRxDesc) \ 80*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) 81*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_PAM_8723D(__pRxDesc) \ 82*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) 83*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_PWR_8723D(__pRxDesc) \ 84*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) 85*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_MORE_DATA_8723D(__pRxDesc) \ 86*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) 87*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_MORE_FRAG_8723D(__pRxDesc) \ 88*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) 89*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_TYPE_8723D(__pRxDesc) \ 90*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) 91*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_MC_8723D(__pRxDesc) \ 92*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) 93*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_BC_8723D(__pRxDesc) \ 94*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* DWORD 2 */ 97*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_SEQ_8723D(__pRxStatusDesc) \ 98*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) 99*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_FRAG_8723D(__pRxStatusDesc) \ 100*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) 101*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_RX_IS_QOS_8723D(__pRxStatusDesc) \ 102*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) 103*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723D(__pRxStatusDesc) \ 104*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) 105*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_RPT_SEL_8723D(__pRxStatusDesc) \ 106*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) 107*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_FCS_OK_8723D(__pRxStatusDesc) \ 108*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* DWORD 3 */ 111*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_RX_RATE_8723D(__pRxStatusDesc) \ 112*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) 113*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_HTC_8723D(__pRxStatusDesc) \ 114*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) 115*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_EOSP_8723D(__pRxStatusDesc) \ 116*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) 117*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_BSSID_FIT_8723D(__pRxStatusDesc) \ 118*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) 119*4882a593Smuzhiyun #ifdef CONFIG_USB_RX_AGGREGATION 120*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723D(__pRxStatusDesc) \ 121*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) 122*4882a593Smuzhiyun #endif 123*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_PATTERN_MATCH_8723D(__pRxDesc) \ 124*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) 125*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_UNICAST_MATCH_8723D(__pRxDesc) \ 126*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) 127*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_MAGIC_MATCH_8723D(__pRxDesc) \ 128*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* DWORD 6 */ 131*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_MATCH_ID_8723D(__pRxDesc) \ 132*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* DWORD 5 */ 135*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_TSFL_8723D(__pRxStatusDesc) \ 136*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc) \ 139*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) 140*4882a593Smuzhiyun #define GET_RX_STATUS_DESC_BUFF_ADDR64_8723D(__pRxDesc) \ 141*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define SET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc, __Value) \ 144*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* Dword 0, rsvd: bit26, bit28 */ 148*4882a593Smuzhiyun #define GET_TX_DESC_OWN_8723D(__pTxDesc)\ 149*4882a593Smuzhiyun LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define SET_TX_DESC_PKT_SIZE_8723D(__pTxDesc, __Value) \ 152*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) 153*4882a593Smuzhiyun #define SET_TX_DESC_OFFSET_8723D(__pTxDesc, __Value) \ 154*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) 155*4882a593Smuzhiyun #define SET_TX_DESC_BMC_8723D(__pTxDesc, __Value) \ 156*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) 157*4882a593Smuzhiyun #define SET_TX_DESC_HTC_8723D(__pTxDesc, __Value) \ 158*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) 159*4882a593Smuzhiyun #define SET_TX_DESC_AMSDU_PAD_EN_8723D(__pTxDesc, __Value) \ 160*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) 161*4882a593Smuzhiyun #define SET_TX_DESC_NO_ACM_8723D(__pTxDesc, __Value) \ 162*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) 163*4882a593Smuzhiyun #define SET_TX_DESC_GF_8723D(__pTxDesc, __Value) \ 164*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* Dword 1 */ 167*4882a593Smuzhiyun #define SET_TX_DESC_MACID_8723D(__pTxDesc, __Value) \ 168*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) 169*4882a593Smuzhiyun #define SET_TX_DESC_QUEUE_SEL_8723D(__pTxDesc, __Value) \ 170*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) 171*4882a593Smuzhiyun #define SET_TX_DESC_RDG_NAV_EXT_8723D(__pTxDesc, __Value) \ 172*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) 173*4882a593Smuzhiyun #define SET_TX_DESC_LSIG_TXOP_EN_8723D(__pTxDesc, __Value) \ 174*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) 175*4882a593Smuzhiyun #define SET_TX_DESC_PIFS_8723D(__pTxDesc, __Value) \ 176*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) 177*4882a593Smuzhiyun #define SET_TX_DESC_RATE_ID_8723D(__pTxDesc, __Value) \ 178*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) 179*4882a593Smuzhiyun #define SET_TX_DESC_EN_DESC_ID_8723D(__pTxDesc, __Value) \ 180*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) 181*4882a593Smuzhiyun #define SET_TX_DESC_SEC_TYPE_8723D(__pTxDesc, __Value) \ 182*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) 183*4882a593Smuzhiyun #define SET_TX_DESC_PKT_OFFSET_8723D(__pTxDesc, __Value) \ 184*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) 185*4882a593Smuzhiyun #define SET_TX_DESC_MORE_DATA_8723D(__pTxDesc, __Value) \ 186*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* Dword 2 remove P_AID, G_ID field*/ 189*4882a593Smuzhiyun #define SET_TX_DESC_CCA_RTS_8723D(__pTxDesc, __Value) \ 190*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) 191*4882a593Smuzhiyun #define SET_TX_DESC_AGG_ENABLE_8723D(__pTxDesc, __Value) \ 192*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) 193*4882a593Smuzhiyun #define SET_TX_DESC_RDG_ENABLE_8723D(__pTxDesc, __Value) \ 194*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) 195*4882a593Smuzhiyun #define SET_TX_DESC_NULL0_8723D(__pTxDesc, __Value) \ 196*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) 197*4882a593Smuzhiyun #define SET_TX_DESC_NULL1_8723D(__pTxDesc, __Value) \ 198*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) 199*4882a593Smuzhiyun #define SET_TX_DESC_BK_8723D(__pTxDesc, __Value) \ 200*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) 201*4882a593Smuzhiyun #define SET_TX_DESC_MORE_FRAG_8723D(__pTxDesc, __Value) \ 202*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) 203*4882a593Smuzhiyun #define SET_TX_DESC_RAW_8723D(__pTxDesc, __Value) \ 204*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) 205*4882a593Smuzhiyun #define SET_TX_DESC_CCX_8723D(__pTxDesc, __Value) \ 206*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) 207*4882a593Smuzhiyun #define SET_TX_DESC_AMPDU_DENSITY_8723D(__pTxDesc, __Value) \ 208*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) 209*4882a593Smuzhiyun #define SET_TX_DESC_BT_INT_8723D(__pTxDesc, __Value) \ 210*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) 211*4882a593Smuzhiyun #define SET_TX_DESC_FTM_EN_8723D(__pTxDesc, __Value) \ 212*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* Dword 3 */ 215*4882a593Smuzhiyun #define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \ 216*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) 217*4882a593Smuzhiyun #define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \ 218*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) 219*4882a593Smuzhiyun #define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \ 220*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) 221*4882a593Smuzhiyun #define SET_TX_DESC_DISABLE_FB_8723D(__pTxDesc, __Value) \ 222*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) 223*4882a593Smuzhiyun #define SET_TX_DESC_CTS2SELF_8723D(__pTxDesc, __Value) \ 224*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) 225*4882a593Smuzhiyun #define SET_TX_DESC_RTS_ENABLE_8723D(__pTxDesc, __Value) \ 226*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) 227*4882a593Smuzhiyun #define SET_TX_DESC_HW_RTS_ENABLE_8723D(__pTxDesc, __Value) \ 228*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) 229*4882a593Smuzhiyun #define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \ 230*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value) 231*4882a593Smuzhiyun #define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \ 232*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) 233*4882a593Smuzhiyun #define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \ 234*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) 235*4882a593Smuzhiyun #define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \ 236*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) 237*4882a593Smuzhiyun #define SET_TX_DESC_AMPDU_MAX_TIME_8723D(__pTxDesc, __Value) \ 238*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* Dword 4 */ 241*4882a593Smuzhiyun #define SET_TX_DESC_TX_RATE_8723D(__pTxDesc, __Value) \ 242*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) 243*4882a593Smuzhiyun #define SET_TX_DESC_TX_TRY_RATE_8723D(__pTxDesc, __Value) \ 244*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) 245*4882a593Smuzhiyun #define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \ 246*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) 247*4882a593Smuzhiyun #define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \ 248*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) 249*4882a593Smuzhiyun #define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(__pTxDesc, __Value) \ 250*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) 251*4882a593Smuzhiyun #define SET_TX_DESC_DATA_RETRY_LIMIT_8723D(__pTxDesc, __Value) \ 252*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) 253*4882a593Smuzhiyun #define SET_TX_DESC_RTS_RATE_8723D(__pTxDesc, __Value) \ 254*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) 255*4882a593Smuzhiyun #define SET_TX_DESC_PCTS_EN_8723D(__pTxDesc, __Value) \ 256*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) 257*4882a593Smuzhiyun #define SET_TX_DESC_PCTS_MASK_IDX_8723D(__pTxDesc, __Value) \ 258*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun /* Dword 5 */ 261*4882a593Smuzhiyun #define SET_TX_DESC_DATA_SC_8723D(__pTxDesc, __Value) \ 262*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) 263*4882a593Smuzhiyun #define SET_TX_DESC_DATA_SHORT_8723D(__pTxDesc, __Value) \ 264*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) 265*4882a593Smuzhiyun #define SET_TX_DESC_DATA_BW_8723D(__pTxDesc, __Value) \ 266*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) 267*4882a593Smuzhiyun #define SET_TX_DESC_DATA_STBC_8723D(__pTxDesc, __Value) \ 268*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) 269*4882a593Smuzhiyun #define SET_TX_DESC_RTS_STBC_8723D(__pTxDesc, __Value) \ 270*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) 271*4882a593Smuzhiyun #define SET_TX_DESC_RTS_SHORT_8723D(__pTxDesc, __Value) \ 272*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) 273*4882a593Smuzhiyun #define SET_TX_DESC_RTS_SC_8723D(__pTxDesc, __Value) \ 274*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) 275*4882a593Smuzhiyun #define SET_TX_DESC_PATH_A_EN_8723D(__pTxDesc, __Value) \ 276*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value) 277*4882a593Smuzhiyun #define SET_TX_DESC_TXPWR_OF_SET_8723D(__pTxDesc, __Value) \ 278*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun /* Dword 6 */ 281*4882a593Smuzhiyun #define SET_TX_DESC_SW_DEFINE_8723D(__pTxDesc, __Value) \ 282*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) 283*4882a593Smuzhiyun #define SET_TX_DESC_MBSSID_8723D(__pTxDesc, __Value) \ 284*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) 285*4882a593Smuzhiyun #define SET_TX_DESC_RF_SEL_8723D(__pTxDesc, __Value) \ 286*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /* Dword 7 */ 289*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 290*4882a593Smuzhiyun #define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \ 291*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) 292*4882a593Smuzhiyun #endif 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 295*4882a593Smuzhiyun #define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \ 296*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) 297*4882a593Smuzhiyun #endif 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI 300*4882a593Smuzhiyun #define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \ 301*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value) 302*4882a593Smuzhiyun #endif 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) \ 305*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* Dword 8 */ 308*4882a593Smuzhiyun #define SET_TX_DESC_RTS_RC_8723D(__pTxDesc, __Value) \ 309*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) 310*4882a593Smuzhiyun #define SET_TX_DESC_BAR_RC_8723D(__pTxDesc, __Value) \ 311*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) 312*4882a593Smuzhiyun #define SET_TX_DESC_DATA_RC_8723D(__pTxDesc, __Value) \ 313*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) 314*4882a593Smuzhiyun #define SET_TX_DESC_HWSEQ_EN_8723D(__pTxDesc, __Value) \ 315*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) 316*4882a593Smuzhiyun #define SET_TX_DESC_NEXTHEADPAGE_8723D(__pTxDesc, __Value) \ 317*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) 318*4882a593Smuzhiyun #define SET_TX_DESC_TAILPAGE_8723D(__pTxDesc, __Value) \ 319*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun /* Dword 9 */ 322*4882a593Smuzhiyun #define SET_TX_DESC_PADDING_LEN_8723D(__pTxDesc, __Value) \ 323*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) 324*4882a593Smuzhiyun #define SET_TX_DESC_SEQ_8723D(__pTxDesc, __Value) \ 325*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) 326*4882a593Smuzhiyun #define SET_TX_DESC_FINAL_DATA_RATE_8723D(__pTxDesc, __Value) \ 327*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value) 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun #define SET_EARLYMODE_PKTNUM_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) 331*4882a593Smuzhiyun #define SET_EARLYMODE_LEN0_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) 332*4882a593Smuzhiyun #define SET_EARLYMODE_LEN1_1_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) 333*4882a593Smuzhiyun #define SET_EARLYMODE_LEN1_2_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) 334*4882a593Smuzhiyun #define SET_EARLYMODE_LEN2_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) 335*4882a593Smuzhiyun #define SET_EARLYMODE_LEN3_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /*-----------------------------------------------------------------*/ 339*4882a593Smuzhiyun /* RTL8723D TX BUFFER DESC */ 340*4882a593Smuzhiyun /*-----------------------------------------------------------------*/ 341*4882a593Smuzhiyun #ifdef CONFIG_64BIT_DMA 342*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu) 343*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu) 344*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu) 345*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu) 346*4882a593Smuzhiyun #else 347*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) 348*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) 349*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) 350*4882a593Smuzhiyun #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */ 351*4882a593Smuzhiyun #endif 352*4882a593Smuzhiyun /* ********************************************************* */ 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun /* 64 bits -- 32 bits */ 355*4882a593Smuzhiyun /* ======= ======= */ 356*4882a593Smuzhiyun /* Dword 0 0 */ 357*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_LEN_0_8723D(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu) 358*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_PSB_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) 359*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_OWN_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun /* Dword 1 1 */ 362*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) 363*4882a593Smuzhiyun #define GET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) 364*4882a593Smuzhiyun /* Dword 2 NA */ 365*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value) 366*4882a593Smuzhiyun #ifdef CONFIG_64BIT_DMA 367*4882a593Smuzhiyun #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32) 368*4882a593Smuzhiyun #else 369*4882a593Smuzhiyun #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) 0 370*4882a593Smuzhiyun #endif 371*4882a593Smuzhiyun /* Dword 3 NA */ 372*4882a593Smuzhiyun /* RESERVED 0 */ 373*4882a593Smuzhiyun /* Dword 4 2 */ 374*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_LEN_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value) 375*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_AMSDU_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value) 376*4882a593Smuzhiyun /* Dword 5 3 */ 377*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_LOW_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value) 378*4882a593Smuzhiyun /* Dword 6 NA */ 379*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_HIGH_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value) 380*4882a593Smuzhiyun /* Dword 7 NA */ 381*4882a593Smuzhiyun /*RESERVED 0 */ 382*4882a593Smuzhiyun /* Dword 8 4 */ 383*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_LEN_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value) 384*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_AMSDU_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value) 385*4882a593Smuzhiyun /* Dword 9 5 */ 386*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_LOW_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value) 387*4882a593Smuzhiyun /* Dword 10 NA */ 388*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_HIGH_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value) 389*4882a593Smuzhiyun /* Dword 11 NA */ 390*4882a593Smuzhiyun /*RESERVED 0 */ 391*4882a593Smuzhiyun /* Dword 12 6 */ 392*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_LEN_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value) 393*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_AMSDU_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value) 394*4882a593Smuzhiyun /* Dword 13 7 */ 395*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_LOW_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value) 396*4882a593Smuzhiyun /* Dword 14 NA */ 397*4882a593Smuzhiyun #define SET_TX_BUFF_DESC_ADDR_HIGH_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value) 398*4882a593Smuzhiyun /* Dword 15 NA */ 399*4882a593Smuzhiyun /*RESERVED 0 */ 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun #endif 403*4882a593Smuzhiyun /* ----------------------------------------------------------- 404*4882a593Smuzhiyun * 405*4882a593Smuzhiyun * Rate 406*4882a593Smuzhiyun * 407*4882a593Smuzhiyun * ----------------------------------------------------------- 408*4882a593Smuzhiyun * CCK Rates, TxHT = 0 */ 409*4882a593Smuzhiyun #define DESC8723D_RATE1M 0x00 410*4882a593Smuzhiyun #define DESC8723D_RATE2M 0x01 411*4882a593Smuzhiyun #define DESC8723D_RATE5_5M 0x02 412*4882a593Smuzhiyun #define DESC8723D_RATE11M 0x03 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun /* OFDM Rates, TxHT = 0 */ 415*4882a593Smuzhiyun #define DESC8723D_RATE6M 0x04 416*4882a593Smuzhiyun #define DESC8723D_RATE9M 0x05 417*4882a593Smuzhiyun #define DESC8723D_RATE12M 0x06 418*4882a593Smuzhiyun #define DESC8723D_RATE18M 0x07 419*4882a593Smuzhiyun #define DESC8723D_RATE24M 0x08 420*4882a593Smuzhiyun #define DESC8723D_RATE36M 0x09 421*4882a593Smuzhiyun #define DESC8723D_RATE48M 0x0a 422*4882a593Smuzhiyun #define DESC8723D_RATE54M 0x0b 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun /* MCS Rates, TxHT = 1 */ 425*4882a593Smuzhiyun #define DESC8723D_RATEMCS0 0x0c 426*4882a593Smuzhiyun #define DESC8723D_RATEMCS1 0x0d 427*4882a593Smuzhiyun #define DESC8723D_RATEMCS2 0x0e 428*4882a593Smuzhiyun #define DESC8723D_RATEMCS3 0x0f 429*4882a593Smuzhiyun #define DESC8723D_RATEMCS4 0x10 430*4882a593Smuzhiyun #define DESC8723D_RATEMCS5 0x11 431*4882a593Smuzhiyun #define DESC8723D_RATEMCS6 0x12 432*4882a593Smuzhiyun #define DESC8723D_RATEMCS7 0x13 433*4882a593Smuzhiyun #define DESC8723D_RATEMCS8 0x14 434*4882a593Smuzhiyun #define DESC8723D_RATEMCS9 0x15 435*4882a593Smuzhiyun #define DESC8723D_RATEMCS10 0x16 436*4882a593Smuzhiyun #define DESC8723D_RATEMCS11 0x17 437*4882a593Smuzhiyun #define DESC8723D_RATEMCS12 0x18 438*4882a593Smuzhiyun #define DESC8723D_RATEMCS13 0x19 439*4882a593Smuzhiyun #define DESC8723D_RATEMCS14 0x1a 440*4882a593Smuzhiyun #define DESC8723D_RATEMCS15 0x1b 441*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS0 0x2c 442*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS1 0x2d 443*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS2 0x2e 444*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS3 0x2f 445*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS4 0x30 446*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS5 0x31 447*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS6 0x32 448*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS7 0x33 449*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS8 0x34 450*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS1MCS9 0x35 451*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS0 0x36 452*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS1 0x37 453*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS2 0x38 454*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS3 0x39 455*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS4 0x3a 456*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS5 0x3b 457*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS6 0x3c 458*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS7 0x3d 459*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS8 0x3e 460*4882a593Smuzhiyun #define DESC8723D_RATEVHTSS2MCS9 0x3f 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun #define RX_HAL_IS_CCK_RATE_8723D(pDesc)\ 464*4882a593Smuzhiyun (GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE1M || \ 465*4882a593Smuzhiyun GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE2M || \ 466*4882a593Smuzhiyun GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE5_5M || \ 467*4882a593Smuzhiyun GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE11M) 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH 470*4882a593Smuzhiyun struct tx_desc; 471*4882a593Smuzhiyun #endif 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); 474*4882a593Smuzhiyun void rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); 475*4882a593Smuzhiyun void rtl8723d_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); 476*4882a593Smuzhiyun void rtl8723d_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); 477*4882a593Smuzhiyun void rtl8723d_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); 478*4882a593Smuzhiyun void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); 481*4882a593Smuzhiyun void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 484*4882a593Smuzhiyun s32 rtl8723ds_init_xmit_priv(PADAPTER padapter); 485*4882a593Smuzhiyun void rtl8723ds_free_xmit_priv(PADAPTER padapter); 486*4882a593Smuzhiyun s32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 487*4882a593Smuzhiyun s32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 488*4882a593Smuzhiyun s32 rtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 489*4882a593Smuzhiyun s32 rtl8723ds_xmit_buf_handler(PADAPTER padapter); 490*4882a593Smuzhiyun thread_return rtl8723ds_xmit_thread(thread_context context); 491*4882a593Smuzhiyun #define hal_xmit_handler rtl8723ds_xmit_buf_handler 492*4882a593Smuzhiyun #endif 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 495*4882a593Smuzhiyun s32 rtl8723du_xmit_buf_handler(PADAPTER padapter); 496*4882a593Smuzhiyun #define hal_xmit_handler rtl8723du_xmit_buf_handler 497*4882a593Smuzhiyun s32 rtl8723du_init_xmit_priv(PADAPTER padapter); 498*4882a593Smuzhiyun void rtl8723du_free_xmit_priv(PADAPTER padapter); 499*4882a593Smuzhiyun s32 rtl8723du_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 500*4882a593Smuzhiyun s32 rtl8723du_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 501*4882a593Smuzhiyun s32 rtl8723du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 502*4882a593Smuzhiyun void rtl8723du_xmit_tasklet(void *priv); 503*4882a593Smuzhiyun s32 rtl8723du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 504*4882a593Smuzhiyun void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); 505*4882a593Smuzhiyun #endif 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 508*4882a593Smuzhiyun s32 rtl8723de_init_xmit_priv(PADAPTER padapter); 509*4882a593Smuzhiyun void rtl8723de_free_xmit_priv(PADAPTER padapter); 510*4882a593Smuzhiyun struct xmit_buf *rtl8723de_dequeue_xmitbuf(struct rtw_tx_ring *ring); 511*4882a593Smuzhiyun void rtl8723de_xmitframe_resume(_adapter *padapter); 512*4882a593Smuzhiyun s32 rtl8723de_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 513*4882a593Smuzhiyun s32 rtl8723de_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 514*4882a593Smuzhiyun s32 rtl8723de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 515*4882a593Smuzhiyun void rtl8723de_xmit_tasklet(void *priv); 516*4882a593Smuzhiyun #endif 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun u8 BWMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib); 519*4882a593Smuzhiyun u8 SCMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib); 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun #endif 522