1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8710B_SPEC_H__ 16 #define __RTL8710B_SPEC_H__ 17 18 #include <drv_conf.h> 19 20 21 #define HAL_NAV_UPPER_UNIT_8710B 128 /* micro-second */ 22 23 /* ----------------------------------------------------- 24 * 25 * 0x0000h ~ 0x00FFh System Configuration 26 * 27 * ----------------------------------------------------- */ 28 #define REG_SYS_ISO_CTRL_8710B 0x0000 /* 2 Byte */ 29 #define REG_APS_FSMCO_8710B 0x0004 /* 4 Byte */ 30 #define REG_SYS_CLKR_8710B 0x0008 /* 2 Byte */ 31 #define REG_9346CR_8710B 0x000A /* 2 Byte */ 32 #define REG_EE_VPD_8710B 0x000C /* 2 Byte */ 33 #define REG_AFE_MISC_8710B 0x0010 /* 1 Byte */ 34 #define REG_SPS0_CTRL_8710B 0x0011 /* 7 Byte */ 35 #define REG_SPS_OCP_CFG_8710B 0x0018 /* 4 Byte */ 36 #define REG_RSV_CTRL_8710B 0x001C /* 3 Byte */ 37 #define REG_RF_CTRL_8710B 0x001F /* 1 Byte */ 38 #define REG_LPLDO_CTRL_8710B 0x0023 /* 1 Byte */ 39 #define REG_AFE_XTAL_CTRL_8710B 0x0024 /* 4 Byte */ 40 #define REG_AFE_PLL_CTRL_8710B 0x0028 /* 4 Byte */ 41 #define REG_MAC_PLL_CTRL_EXT_8710B 0x002c /* 4 Byte */ 42 #define REG_EFUSE_CTRL_8710B 0x0030 43 #define REG_EFUSE_TEST_8710B 0x0034 44 #define REG_PWR_DATA_8710B 0x0038 45 #define REG_CAL_TIMER_8710B 0x003C 46 #define REG_ACLK_MON_8710B 0x003E 47 #define REG_GPIO_MUXCFG_8710B 0x0040 48 #define REG_GPIO_IO_SEL_8710B 0x0042 49 #define REG_MAC_PINMUX_CFG_8710B 0x0043 50 #define REG_GPIO_PIN_CTRL_8710B 0x0044 51 #define REG_GPIO_INTM_8710B 0x0048 52 #define REG_LEDCFG0_8710B 0x004C 53 #define REG_LEDCFG1_8710B 0x004D 54 #define REG_LEDCFG2_8710B 0x004E 55 #define REG_LEDCFG3_8710B 0x004F 56 #define REG_FSIMR_8710B 0x0050 57 #define REG_FSISR_8710B 0x0054 58 #define REG_HSIMR_8710B 0x0058 59 #define REG_HSISR_8710B 0x005c 60 #define REG_GPIO_EXT_CTRL 0x0060 61 #define REG_PAD_CTRL1_8710B 0x0064 62 #define REG_MULTI_FUNC_CTRL_8710B 0x0068 63 #define REG_GPIO_STATUS_8710B 0x006C 64 #define REG_SDIO_CTRL_8710B 0x0070 65 #define REG_OPT_CTRL_8710B 0x0074 66 #define REG_AFE_CTRL_4_8710B 0x0078 67 #define REG_MCUFWDL_8710B 0x0080 68 #define REG_8051FW_CTRL_8710B 0x0080 69 #define REG_HMEBOX_DBG_0_8710B 0x0088 70 #define REG_HMEBOX_DBG_1_8710B 0x008A 71 #define REG_HMEBOX_DBG_2_8710B 0x008C 72 #define REG_HMEBOX_DBG_3_8710B 0x008E 73 #define REG_WLLPS_CTRL 0x0090 74 75 #define REG_PMC_DBG_CTRL2_8710B 0x00CC 76 #define REG_EFUSE_BURN_GNT_8710B 0x00CF 77 #define REG_HPON_FSM_8710B 0x00EC 78 #define REG_SYS_CFG1_8710B 0x00F0 79 #define REG_SYS_CFG_8710B 0x00FC 80 #define REG_ROM_VERSION 0x00FD 81 82 /* ----------------------------------------------------- 83 * 84 * 0x0100h ~ 0x01FFh MACTOP General Configuration 85 * 86 * ----------------------------------------------------- */ 87 #define REG_C2HEVT_CMD_ID_8710B 0x01A0 88 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 89 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 90 #define REG_C2HEVT_CMD_LEN_8710B 0x01AE 91 #define REG_C2HEVT_CLEAR_8710B 0x01AF 92 #define REG_MCUTST_1_8710B 0x01C0 93 #define REG_WOWLAN_WAKE_REASON 0x01C7 94 #define REG_FMETHR_8710B 0x01C8 95 #define REG_HMETFR_8710B 0x01CC 96 #define REG_HMEBOX_0_8710B 0x01D0 97 #define REG_HMEBOX_1_8710B 0x01D4 98 #define REG_HMEBOX_2_8710B 0x01D8 99 #define REG_HMEBOX_3_8710B 0x01DC 100 #define REG_LLT_INIT_8710B 0x01E0 101 #define REG_HMEBOX_EXT0_8710B 0x01F0 102 #define REG_HMEBOX_EXT1_8710B 0x01F4 103 #define REG_HMEBOX_EXT2_8710B 0x01F8 104 #define REG_HMEBOX_EXT3_8710B 0x01FC 105 106 /* ----------------------------------------------------- 107 * 108 * 0x0200h ~ 0x027Fh TXDMA Configuration 109 * 110 * ----------------------------------------------------- */ 111 #define REG_RQPN_8710B 0x0200 112 #define REG_FIFOPAGE_8710B 0x0204 113 #define REG_DWBCN0_CTRL_8710B REG_TDECTRL 114 #define REG_TXDMA_OFFSET_CHK_8710B 0x020C 115 #define REG_TXDMA_STATUS_8710B 0x0210 116 #define REG_RQPN_NPQ_8710B 0x0214 117 #define REG_DWBCN1_CTRL_8710B 0x0228 118 119 120 /* ----------------------------------------------------- 121 * 122 * 0x0280h ~ 0x02FFh RXDMA Configuration 123 * 124 * ----------------------------------------------------- */ 125 #define REG_RXDMA_AGG_PG_TH_8710B 0x0280 126 #define REG_FW_UPD_RDPTR_8710B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 127 #define REG_RXDMA_CONTROL_8710B 0x0286 /* Control the RX DMA. */ 128 #define REG_RXDMA_STATUS_8710B 0x0288 129 #define REG_RXDMA_MODE_CTRL_8710B 0x0290 130 #define REG_EARLY_MODE_CONTROL_8710B 0x02BC 131 #define REG_RSVD5_8710B 0x02F0 132 #define REG_RSVD6_8710B 0x02F4 133 134 /* ----------------------------------------------------- 135 * 136 * 0x0300h ~ 0x03FFh PCIe 137 * 138 * ----------------------------------------------------- */ 139 #define REG_PCIE_CTRL_REG_8710B 0x0300 140 #define REG_INT_MIG_8710B 0x0304 /* Interrupt Migration */ 141 #define REG_BCNQ_TXBD_DESA_8710B 0x0308 /* TX Beacon Descriptor Address */ 142 #define REG_MGQ_TXBD_DESA_8710B 0x0310 /* TX Manage Queue Descriptor Address */ 143 #define REG_VOQ_TXBD_DESA_8710B 0x0318 /* TX VO Queue Descriptor Address */ 144 #define REG_VIQ_TXBD_DESA_8710B 0x0320 /* TX VI Queue Descriptor Address */ 145 #define REG_BEQ_TXBD_DESA_8710B 0x0328 /* TX BE Queue Descriptor Address */ 146 #define REG_BKQ_TXBD_DESA_8710B 0x0330 /* TX BK Queue Descriptor Address */ 147 #define REG_RXQ_RXBD_DESA_8710B 0x0338 /* RX Queue Descriptor Address */ 148 #define REG_HI0Q_TXBD_DESA_8710B 0x0340 149 #define REG_HI1Q_TXBD_DESA_8710B 0x0348 150 #define REG_HI2Q_TXBD_DESA_8710B 0x0350 151 #define REG_HI3Q_TXBD_DESA_8710B 0x0358 152 #define REG_HI4Q_TXBD_DESA_8710B 0x0360 153 #define REG_HI5Q_TXBD_DESA_8710B 0x0368 154 #define REG_HI6Q_TXBD_DESA_8710B 0x0370 155 #define REG_HI7Q_TXBD_DESA_8710B 0x0378 156 #define REG_MGQ_TXBD_NUM_8710B 0x0380 157 #define REG_RX_RXBD_NUM_8710B 0x0382 158 #define REG_VOQ_TXBD_NUM_8710B 0x0384 159 #define REG_VIQ_TXBD_NUM_8710B 0x0386 160 #define REG_BEQ_TXBD_NUM_8710B 0x0388 161 #define REG_BKQ_TXBD_NUM_8710B 0x038A 162 #define REG_HI0Q_TXBD_NUM_8710B 0x038C 163 #define REG_HI1Q_TXBD_NUM_8710B 0x038E 164 #define REG_HI2Q_TXBD_NUM_8710B 0x0390 165 #define REG_HI3Q_TXBD_NUM_8710B 0x0392 166 #define REG_HI4Q_TXBD_NUM_8710B 0x0394 167 #define REG_HI5Q_TXBD_NUM_8710B 0x0396 168 #define REG_HI6Q_TXBD_NUM_8710B 0x0398 169 #define REG_HI7Q_TXBD_NUM_8710B 0x039A 170 #define REG_TSFTIMER_HCI_8710B 0x039C 171 #define REG_BD_RW_PTR_CLR_8710B 0x039C 172 173 /* Read Write Point */ 174 #define REG_VOQ_TXBD_IDX_8710B 0x03A0 175 #define REG_VIQ_TXBD_IDX_8710B 0x03A4 176 #define REG_BEQ_TXBD_IDX_8710B 0x03A8 177 #define REG_BKQ_TXBD_IDX_8710B 0x03AC 178 #define REG_MGQ_TXBD_IDX_8710B 0x03B0 179 #define REG_RXQ_TXBD_IDX_8710B 0x03B4 180 #define REG_HI0Q_TXBD_IDX_8710B 0x03B8 181 #define REG_HI1Q_TXBD_IDX_8710B 0x03BC 182 #define REG_HI2Q_TXBD_IDX_8710B 0x03C0 183 #define REG_HI3Q_TXBD_IDX_8710B 0x03C4 184 #define REG_HI4Q_TXBD_IDX_8710B 0x03C8 185 #define REG_HI5Q_TXBD_IDX_8710B 0x03CC 186 #define REG_HI6Q_TXBD_IDX_8710B 0x03D0 187 #define REG_HI7Q_TXBD_IDX_8710B 0x03D4 188 189 #define REG_PCIE_HCPWM_8710BE 0x03D8 /* ?????? */ 190 #define REG_PCIE_HRPWM_8710BE 0x03DC /* PCIe RPWM ?????? */ 191 #define REG_DBI_WDATA_V1_8710B 0x03E8 192 #define REG_DBI_RDATA_V1_8710B 0x03EC 193 #define REG_DBI_FLAG_V1_8710B 0x03F0 194 #define REG_MDIO_V1_8710B 0x03F4 195 #define REG_PCIE_MIX_CFG_8710B 0x03F8 196 #define REG_HCI_MIX_CFG_8710B 0x03FC 197 198 /* ----------------------------------------------------- 199 * 200 * 0x0400h ~ 0x047Fh Protocol Configuration 201 * 202 * ----------------------------------------------------- */ 203 #define REG_VOQ_INFORMATION_8710B 0x0400 204 #define REG_VIQ_INFORMATION_8710B 0x0404 205 #define REG_BEQ_INFORMATION_8710B 0x0408 206 #define REG_BKQ_INFORMATION_8710B 0x040C 207 #define REG_MGQ_INFORMATION_8710B 0x0410 208 #define REG_HGQ_INFORMATION_8710B 0x0414 209 #define REG_BCNQ_INFORMATION_8710B 0x0418 210 #define REG_TXPKT_EMPTY_8710B 0x041A 211 212 #define REG_FWHW_TXQ_CTRL_8710B 0x0420 213 #define REG_HWSEQ_CTRL_8710B 0x0423 214 #define REG_TXPKTBUF_BCNQ_BDNY_8710B 0x0424 215 #define REG_TXPKTBUF_MGQ_BDNY_8710B 0x0425 216 #define REG_LIFECTRL_CTRL_8710B 0x0426 217 #define REG_MULTI_BCNQ_OFFSET_8710B 0x0427 218 #define REG_SPEC_SIFS_8710B 0x0428 219 #define REG_RL_8710B 0x042A 220 #define REG_TXBF_CTRL_8710B 0x042C 221 #define REG_DARFRC_8710B 0x0430 222 #define REG_RARFRC_8710B 0x0438 223 #define REG_RRSR_8710B 0x0440 224 #define REG_ARFR0_8710B 0x0444 225 #define REG_ARFR1_8710B 0x044C 226 #define REG_CCK_CHECK_8710B 0x0454 227 #define REG_AMPDU_MAX_TIME_8710B 0x0456 228 #define REG_TXPKTBUF_BCNQ_BDNY1_8710B 0x0457 229 230 #define REG_AMPDU_MAX_LENGTH_8710B 0x0458 231 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B 0x045D 232 #define REG_NDPA_OPT_CTRL_8710B 0x045F 233 #define REG_FAST_EDCA_CTRL_8710B 0x0460 234 #define REG_RD_RESP_PKT_TH_8710B 0x0463 235 #define REG_DATA_SC_8710B 0x0483 236 #ifdef CONFIG_WOWLAN 237 #define REG_TXPKTBUF_IV_LOW 0x0484 238 #define REG_TXPKTBUF_IV_HIGH 0x0488 239 #endif 240 #define REG_TXRPT_START_OFFSET 0x04AC 241 #define REG_POWER_STAGE1_8710B 0x04B4 242 #define REG_POWER_STAGE2_8710B 0x04B8 243 #define REG_AMPDU_BURST_MODE_8710B 0x04BC 244 #define REG_PKT_VO_VI_LIFE_TIME_8710B 0x04C0 245 #define REG_PKT_BE_BK_LIFE_TIME_8710B 0x04C2 246 #define REG_STBC_SETTING_8710B 0x04C4 247 #define REG_HT_SINGLE_AMPDU_8710B 0x04C7 248 #define REG_PROT_MODE_CTRL_8710B 0x04C8 249 #define REG_MAX_AGGR_NUM_8710B 0x04CA 250 #define REG_RTS_MAX_AGGR_NUM_8710B 0x04CB 251 #define REG_BAR_MODE_CTRL_8710B 0x04CC 252 #define REG_RA_TRY_RATE_AGG_LMT_8710B 0x04CF 253 #define REG_MACID_PKT_DROP0_8710B 0x04D0 254 #define REG_MACID_PKT_SLEEP_8710B 0x04D4 255 256 /* ----------------------------------------------------- 257 * 258 * 0x0500h ~ 0x05FFh EDCA Configuration 259 * 260 * ----------------------------------------------------- */ 261 #define REG_EDCA_VO_PARAM_8710B 0x0500 262 #define REG_EDCA_VI_PARAM_8710B 0x0504 263 #define REG_EDCA_BE_PARAM_8710B 0x0508 264 #define REG_EDCA_BK_PARAM_8710B 0x050C 265 #define REG_BCNTCFG_8710B 0x0510 266 #define REG_PIFS_8710B 0x0512 267 #define REG_RDG_PIFS_8710B 0x0513 268 #define REG_SIFS_CTX_8710B 0x0514 269 #define REG_SIFS_TRX_8710B 0x0516 270 #define REG_AGGR_BREAK_TIME_8710B 0x051A 271 #define REG_SLOT_8710B 0x051B 272 #define REG_TX_PTCL_CTRL_8710B 0x0520 273 #define REG_TXPAUSE_8710B 0x0522 274 #define REG_DIS_TXREQ_CLR_8710B 0x0523 275 #define REG_RD_CTRL_8710B 0x0524 276 /* 277 * Format for offset 540h-542h: 278 * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 279 * [7:4]: Reserved. 280 * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 281 * [23:20]: Reserved 282 * Description: 283 * | 284 * |<--Setup--|--Hold------------>| 285 * --------------|---------------------- 286 * | 287 * TBTT 288 * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 289 * Described by Designer Tim and Bruce, 2011-01-14. 290 * */ 291 #define REG_TBTT_PROHIBIT_8710B 0x0540 292 #define REG_RD_NAV_NXT_8710B 0x0544 293 #define REG_NAV_PROT_LEN_8710B 0x0546 294 #define REG_BCN_CTRL_8710B 0x0550 295 #define REG_BCN_CTRL_1_8710B 0x0551 296 #define REG_MBID_NUM_8710B 0x0552 297 #define REG_DUAL_TSF_RST_8710B 0x0553 298 #define REG_BCN_INTERVAL_8710B 0x0554 299 #define REG_DRVERLYINT_8710B 0x0558 300 #define REG_BCNDMATIM_8710B 0x0559 301 #define REG_ATIMWND_8710B 0x055A 302 #define REG_USTIME_TSF_8710B 0x055C 303 #define REG_BCN_MAX_ERR_8710B 0x055D 304 #define REG_RXTSF_OFFSET_CCK_8710B 0x055E 305 #define REG_RXTSF_OFFSET_OFDM_8710B 0x055F 306 #define REG_TSFTR_8710B 0x0560 307 #define REG_CTWND_8710B 0x0572 308 #define REG_SECONDARY_CCA_CTRL_8710B 0x0577 309 #define REG_PSTIMER_8710B 0x0580 310 #define REG_TIMER0_8710B 0x0584 311 #define REG_TIMER1_8710B 0x0588 312 #define REG_ACMHWCTRL_8710B 0x05C0 313 #define REG_SCH_TXCMD_8710B 0x05F8 314 315 /* ----------------------------------------------------- 316 * 317 * 0x0600h ~ 0x07FFh WMAC Configuration 318 * 319 * ----------------------------------------------------- */ 320 #define REG_MAC_CR_8710B 0x0600 321 #define REG_TCR_8710B 0x0604 322 #define REG_RCR_8710B 0x0608 323 #define REG_RX_PKT_LIMIT_8710B 0x060C 324 #define REG_RX_DLK_TIME_8710B 0x060D 325 #define REG_RX_DRVINFO_SZ_8710B 0x060F 326 327 #define REG_MACID_8710B 0x0610 328 #define REG_BSSID_8710B 0x0618 329 #define REG_MAR_8710B 0x0620 330 #define REG_MBIDCAMCFG_8710B 0x0628 331 #define REG_WOWLAN_GTK_DBG1 0x630 332 #define REG_WOWLAN_GTK_DBG2 0x634 333 334 #define REG_USTIME_EDCA_8710B 0x0638 335 #define REG_MAC_SPEC_SIFS_8710B 0x063A 336 #define REG_RESP_SIFP_CCK_8710B 0x063C 337 #define REG_RESP_SIFS_OFDM_8710B 0x063E 338 #define REG_ACKTO_8710B 0x0640 339 #define REG_CTS2TO_8710B 0x0641 340 #define REG_EIFS_8710B 0x0642 341 342 #define REG_NAV_UPPER_8710B 0x0652 /* unit of 128 */ 343 #define REG_TRXPTCL_CTL_8710B 0x0668 344 345 /* Security */ 346 #define REG_CAMCMD_8710B 0x0670 347 #define REG_CAMWRITE_8710B 0x0674 348 #define REG_CAMREAD_8710B 0x0678 349 #define REG_CAMDBG_8710B 0x067C 350 #define REG_SECCFG_8710B 0x0680 351 352 /* Power */ 353 #define REG_WOW_CTRL_8710B 0x0690 354 #define REG_PS_RX_INFO_8710B 0x0692 355 #define REG_UAPSD_TID_8710B 0x0693 356 #define REG_WKFMCAM_CMD_8710B 0x0698 357 #define REG_WKFMCAM_NUM_8710B 0x0698 358 #define REG_WKFMCAM_RWD_8710B 0x069C 359 #define REG_RXFLTMAP0_8710B 0x06A0 360 #define REG_RXFLTMAP1_8710B 0x06A2 361 #define REG_RXFLTMAP2_8710B 0x06A4 362 #define REG_BCN_PSR_RPT_8710B 0x06A8 363 #define REG_BT_COEX_TABLE_8710B 0x06C0 364 #define REG_BFMER0_INFO_8710B 0x06E4 365 #define REG_BFMER1_INFO_8710B 0x06EC 366 #define REG_CSI_RPT_PARAM_BW20_8710B 0x06F4 367 #define REG_CSI_RPT_PARAM_BW40_8710B 0x06F8 368 #define REG_CSI_RPT_PARAM_BW80_8710B 0x06FC 369 370 /* Hardware Port 2 */ 371 #define REG_MACID1_8710B 0x0700 372 #define REG_BSSID1_8710B 0x0708 373 #define REG_BFMEE_SEL_8710B 0x0714 374 #define REG_SND_PTCL_CTRL_8710B 0x0718 375 376 /* LTR */ 377 #define REG_LTR_CTRL_BASIC_8710B 0x07A4 378 #define REG_LTR_IDLE_LATENCY_V1_8710B 0x0798 379 #define REG_LTR_ACTIVE_LATENCY_V1_8710B 0x079C 380 381 /* LTE_COEX */ 382 #define REG_LTECOEX_CTRL 0x07C0 383 #define REG_LTECOEX_WRITE_DATA 0x07C4 384 #define REG_LTECOEX_READ_DATA 0x07C8 385 #define REG_LTECOEX_PATH_CONTROL 0x70 386 387 /* Other */ 388 #define REG_USB_ACCESS_TIMEOUT 0xFE4C 389 390 /* ----------------------------------------------------- 391 * SYSON_REG_SPEC 392 * ----------------------------------------------------- */ 393 #define SYSON_REG_BASE_ADDR_8710B 0x40000000 394 #define REG_SYS_XTAL_CTRL0 0x0060 395 #define REG_SYS_SYSTEM_CFG0 0x1F0 396 #define REG_SYS_SYSTEM_CFG1 0x1F4 397 #define REG_SYS_SYSTEM_CFG2 0x1F8 398 #define REG_SYS_EEPROM_CTRL0 0x0E0 399 400 401 /* ----------------------------------------------------- 402 * Indirect_R/W_SPEC 403 * ----------------------------------------------------- */ 404 #define NORMAL_REG_READ_OFFSET 0x83000000 405 #define NORMAL_REG_WRITE_OFFSET 0x84000000 406 #define EFUSE_READ_OFFSET 0x85000000 407 #define EFUSE_WRITE_OFFSET 0x86000000 408 409 410 /* ----------------------------------------------------- 411 * PAGE0_WLANON_REG_SPEC 412 * ----------------------------------------------------- */ 413 #define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset. 414 415 416 417 /* **************************************************************************** 418 * 8723 Regsiter Bit and Content definition 419 * **************************************************************************** */ 420 421 /* ----------------------------------------------------- 422 * REG_SYS_SYSTEM_CFG0 423 * ----------------------------------------------------- */ 424 #define BIT_RTL_ID_8710B BIT(16) 425 426 #define BIT_MASK_CHIP_VER_8710B 0xf 427 #define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B) 428 429 #define BIT_SHIFT_VENDOR_ID_8710B 4 430 #define BIT_MASK_VENDOR_ID_8710B 0xf 431 #define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B) 432 433 /* ----------------------------------------------------- 434 * REG_SYS_SYSTEM_CFG1 435 * ----------------------------------------------------- */ 436 #define BIT_SPSLDO_SEL_8710B BIT(25) 437 438 /* ----------------------------------------------------- 439 * REG_SYS_SYSTEM_CFG2 440 * ----------------------------------------------------- */ 441 #define BIT_MASK_RF_RL_ID_8710B 0xf 442 #define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B) 443 444 /* ----------------------------------------------------- 445 * REG_SYS_SYSTEM_CFG2 446 * ----------------------------------------------------- */ 447 #define BIT_EERPOMSEL_8710B BIT(4) 448 #define BIT_AUTOLOAD_SUS_8710B BIT(5) 449 450 451 /* ----------------------------------------------------- 452 * Other 453 * ----------------------------------------------------- */ 454 455 456 #define BIT_USB_RXDMA_AGG_EN BIT(31) 457 #define RXDMA_AGG_MODE_EN BIT(1) 458 459 #ifdef CONFIG_WOWLAN 460 #define RXPKT_RELEASE_POLL BIT(16) 461 #define RXDMA_IDLE BIT(17) 462 #define RW_RELEASE_EN BIT(18) 463 #endif 464 465 /* 2 HSISR 466 * interrupt mask which needs to clear */ 467 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ 468 HSISR_SPS_OCP_INT |\ 469 HSISR_RON_INT |\ 470 HSISR_PDNINT |\ 471 HSISR_GPIO9_INT) 472 473 #ifdef CONFIG_RF_POWER_TRIM 474 #ifdef CONFIG_RTL8710B 475 #define EEPROM_RF_GAIN_OFFSET 0xC1 476 #endif 477 478 #define EEPROM_RF_GAIN_VAL 0x1F6 479 #endif /*CONFIG_RF_POWER_TRIM*/ 480 481 #endif /* __RTL8710B_SPEC_H__ */ 482