xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/include/hal_com.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __HAL_COMMON_H__
16*4882a593Smuzhiyun #define __HAL_COMMON_H__
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "HalVerDef.h"
19*4882a593Smuzhiyun #include "hal_pg.h"
20*4882a593Smuzhiyun #include "hal_phy.h"
21*4882a593Smuzhiyun #include "hal_phy_reg.h"
22*4882a593Smuzhiyun #include "hal_com_reg.h"
23*4882a593Smuzhiyun #include "hal_com_phycfg.h"
24*4882a593Smuzhiyun #include "../hal/hal_com_c2h.h"
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /*------------------------------ Tx Desc definition Macro ------------------------*/
27*4882a593Smuzhiyun /* #pragma mark -- Tx Desc related definition. -- */
28*4882a593Smuzhiyun /* ----------------------------------------------------------------------------
29*4882a593Smuzhiyun  * -----------------------------------------------------------
30*4882a593Smuzhiyun  *	Rate
31*4882a593Smuzhiyun  * -----------------------------------------------------------
32*4882a593Smuzhiyun  * CCK Rates, TxHT = 0 */
33*4882a593Smuzhiyun #define DESC_RATE1M					0x00
34*4882a593Smuzhiyun #define DESC_RATE2M					0x01
35*4882a593Smuzhiyun #define DESC_RATE5_5M				0x02
36*4882a593Smuzhiyun #define DESC_RATE11M				0x03
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* OFDM Rates, TxHT = 0 */
39*4882a593Smuzhiyun #define DESC_RATE6M					0x04
40*4882a593Smuzhiyun #define DESC_RATE9M					0x05
41*4882a593Smuzhiyun #define DESC_RATE12M				0x06
42*4882a593Smuzhiyun #define DESC_RATE18M				0x07
43*4882a593Smuzhiyun #define DESC_RATE24M				0x08
44*4882a593Smuzhiyun #define DESC_RATE36M				0x09
45*4882a593Smuzhiyun #define DESC_RATE48M				0x0a
46*4882a593Smuzhiyun #define DESC_RATE54M				0x0b
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* MCS Rates, TxHT = 1 */
49*4882a593Smuzhiyun #define DESC_RATEMCS0				0x0c
50*4882a593Smuzhiyun #define DESC_RATEMCS1				0x0d
51*4882a593Smuzhiyun #define DESC_RATEMCS2				0x0e
52*4882a593Smuzhiyun #define DESC_RATEMCS3				0x0f
53*4882a593Smuzhiyun #define DESC_RATEMCS4				0x10
54*4882a593Smuzhiyun #define DESC_RATEMCS5				0x11
55*4882a593Smuzhiyun #define DESC_RATEMCS6				0x12
56*4882a593Smuzhiyun #define DESC_RATEMCS7				0x13
57*4882a593Smuzhiyun #define DESC_RATEMCS8				0x14
58*4882a593Smuzhiyun #define DESC_RATEMCS9				0x15
59*4882a593Smuzhiyun #define DESC_RATEMCS10				0x16
60*4882a593Smuzhiyun #define DESC_RATEMCS11				0x17
61*4882a593Smuzhiyun #define DESC_RATEMCS12				0x18
62*4882a593Smuzhiyun #define DESC_RATEMCS13				0x19
63*4882a593Smuzhiyun #define DESC_RATEMCS14				0x1a
64*4882a593Smuzhiyun #define DESC_RATEMCS15				0x1b
65*4882a593Smuzhiyun #define DESC_RATEMCS16				0x1C
66*4882a593Smuzhiyun #define DESC_RATEMCS17				0x1D
67*4882a593Smuzhiyun #define DESC_RATEMCS18				0x1E
68*4882a593Smuzhiyun #define DESC_RATEMCS19				0x1F
69*4882a593Smuzhiyun #define DESC_RATEMCS20				0x20
70*4882a593Smuzhiyun #define DESC_RATEMCS21				0x21
71*4882a593Smuzhiyun #define DESC_RATEMCS22				0x22
72*4882a593Smuzhiyun #define DESC_RATEMCS23				0x23
73*4882a593Smuzhiyun #define DESC_RATEMCS24				0x24
74*4882a593Smuzhiyun #define DESC_RATEMCS25				0x25
75*4882a593Smuzhiyun #define DESC_RATEMCS26				0x26
76*4882a593Smuzhiyun #define DESC_RATEMCS27				0x27
77*4882a593Smuzhiyun #define DESC_RATEMCS28				0x28
78*4882a593Smuzhiyun #define DESC_RATEMCS29				0x29
79*4882a593Smuzhiyun #define DESC_RATEMCS30				0x2A
80*4882a593Smuzhiyun #define DESC_RATEMCS31				0x2B
81*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS0		0x2C
82*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS1		0x2D
83*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS2		0x2E
84*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS3		0x2F
85*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS4		0x30
86*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS5		0x31
87*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS6		0x32
88*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS7		0x33
89*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS8		0x34
90*4882a593Smuzhiyun #define DESC_RATEVHTSS1MCS9		0x35
91*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS0		0x36
92*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS1		0x37
93*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS2		0x38
94*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS3		0x39
95*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS4		0x3A
96*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS5		0x3B
97*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS6		0x3C
98*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS7		0x3D
99*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS8		0x3E
100*4882a593Smuzhiyun #define DESC_RATEVHTSS2MCS9		0x3F
101*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS0		0x40
102*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS1		0x41
103*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS2		0x42
104*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS3		0x43
105*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS4		0x44
106*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS5		0x45
107*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS6		0x46
108*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS7		0x47
109*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS8		0x48
110*4882a593Smuzhiyun #define DESC_RATEVHTSS3MCS9		0x49
111*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS0		0x4A
112*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS1		0x4B
113*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS2		0x4C
114*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS3		0x4D
115*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS4		0x4E
116*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS5		0x4F
117*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS6		0x50
118*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS7		0x51
119*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS8		0x52
120*4882a593Smuzhiyun #define DESC_RATEVHTSS4MCS9		0x53
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun #define IS_CCK_HRATE(_rate)		((_rate) <= DESC_RATE11M)
123*4882a593Smuzhiyun #define IS_OFDM_HRATE(_rate)	((_rate) >= DESC_RATE6M && (_rate) <= DESC_RATE54M)
124*4882a593Smuzhiyun #define IS_LEGACY_HRATE(_rate)	((_rate) <= DESC_RATE54M)
125*4882a593Smuzhiyun #define IS_HT_HRATE(_rate)		((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS31)
126*4882a593Smuzhiyun #define IS_VHT_HRATE(_rate)		((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #define IS_HT1SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS7)
129*4882a593Smuzhiyun #define IS_HT2SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS8 && (_rate) <= DESC_RATEMCS15)
130*4882a593Smuzhiyun #define IS_HT3SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS16 && (_rate) <= DESC_RATEMCS23)
131*4882a593Smuzhiyun #define IS_HT4SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS24 && (_rate) <= DESC_RATEMCS31)
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #define IS_VHT1SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS1MCS9)
134*4882a593Smuzhiyun #define IS_VHT2SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS2MCS0 && (_rate) <= DESC_RATEVHTSS2MCS9)
135*4882a593Smuzhiyun #define IS_VHT3SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS3MCS0 && (_rate) <= DESC_RATEVHTSS3MCS9)
136*4882a593Smuzhiyun #define IS_VHT4SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS4MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun #define IS_1SS_HRATE(_rate)	(IS_CCK_HRATE((_rate)) || IS_OFDM_HRATE((_rate)) || IS_HT1SS_HRATE((_rate)) || IS_VHT1SS_HRATE((_rate)))
139*4882a593Smuzhiyun #define IS_2SS_HRATE(_rate)	(IS_HT2SS_HRATE((_rate)) || IS_VHT2SS_HRATE((_rate)))
140*4882a593Smuzhiyun #define IS_3SS_HRATE(_rate)	(IS_HT3SS_HRATE((_rate)) || IS_VHT3SS_HRATE((_rate)))
141*4882a593Smuzhiyun #define IS_4SS_HRATE(_rate)	(IS_HT4SS_HRATE((_rate)) || IS_VHT4SS_HRATE((_rate)))
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define HRARE_SS_NUM(_rate) (IS_1SS_HRATE(_rate) ? 1 : (IS_2SS_HRATE(_rate) ? 2 : (IS_3SS_HRATE(_rate) ? 3 : (IS_4SS_HRATE(_rate) ? 4 : 0))))
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun #define HDATA_RATE(rate)\
146*4882a593Smuzhiyun 	(rate == DESC_RATE1M) ? "CCK_1M" :\
147*4882a593Smuzhiyun 	(rate == DESC_RATE2M) ? "CCK_2M" :\
148*4882a593Smuzhiyun 	(rate == DESC_RATE5_5M) ? "CCK5_5M" :\
149*4882a593Smuzhiyun 	(rate == DESC_RATE11M) ? "CCK_11M" :\
150*4882a593Smuzhiyun 	(rate == DESC_RATE6M) ? "OFDM_6M" :\
151*4882a593Smuzhiyun 	(rate == DESC_RATE9M) ? "OFDM_9M" :\
152*4882a593Smuzhiyun 	(rate == DESC_RATE12M) ? "OFDM_12M" :\
153*4882a593Smuzhiyun 	(rate == DESC_RATE18M) ? "OFDM_18M" :\
154*4882a593Smuzhiyun 	(rate == DESC_RATE24M) ? "OFDM_24M" :\
155*4882a593Smuzhiyun 	(rate == DESC_RATE36M) ? "OFDM_36M" :\
156*4882a593Smuzhiyun 	(rate == DESC_RATE48M) ? "OFDM_48M" :\
157*4882a593Smuzhiyun 	(rate == DESC_RATE54M) ? "OFDM_54M" :\
158*4882a593Smuzhiyun 	(rate == DESC_RATEMCS0) ? "MCS0" :\
159*4882a593Smuzhiyun 	(rate == DESC_RATEMCS1) ? "MCS1" :\
160*4882a593Smuzhiyun 	(rate == DESC_RATEMCS2) ? "MCS2" :\
161*4882a593Smuzhiyun 	(rate == DESC_RATEMCS3) ? "MCS3" :\
162*4882a593Smuzhiyun 	(rate == DESC_RATEMCS4) ? "MCS4" :\
163*4882a593Smuzhiyun 	(rate == DESC_RATEMCS5) ? "MCS5" :\
164*4882a593Smuzhiyun 	(rate == DESC_RATEMCS6) ? "MCS6" :\
165*4882a593Smuzhiyun 	(rate == DESC_RATEMCS7) ? "MCS7" :\
166*4882a593Smuzhiyun 	(rate == DESC_RATEMCS8) ? "MCS8" :\
167*4882a593Smuzhiyun 	(rate == DESC_RATEMCS9) ? "MCS9" :\
168*4882a593Smuzhiyun 	(rate == DESC_RATEMCS10) ? "MCS10" :\
169*4882a593Smuzhiyun 	(rate == DESC_RATEMCS11) ? "MCS11" :\
170*4882a593Smuzhiyun 	(rate == DESC_RATEMCS12) ? "MCS12" :\
171*4882a593Smuzhiyun 	(rate == DESC_RATEMCS13) ? "MCS13" :\
172*4882a593Smuzhiyun 	(rate == DESC_RATEMCS14) ? "MCS14" :\
173*4882a593Smuzhiyun 	(rate == DESC_RATEMCS15) ? "MCS15" :\
174*4882a593Smuzhiyun 	(rate == DESC_RATEMCS16) ? "MCS16" :\
175*4882a593Smuzhiyun 	(rate == DESC_RATEMCS17) ? "MCS17" :\
176*4882a593Smuzhiyun 	(rate == DESC_RATEMCS18) ? "MCS18" :\
177*4882a593Smuzhiyun 	(rate == DESC_RATEMCS19) ? "MCS19" :\
178*4882a593Smuzhiyun 	(rate == DESC_RATEMCS20) ? "MCS20" :\
179*4882a593Smuzhiyun 	(rate == DESC_RATEMCS21) ? "MCS21" :\
180*4882a593Smuzhiyun 	(rate == DESC_RATEMCS22) ? "MCS22" :\
181*4882a593Smuzhiyun 	(rate == DESC_RATEMCS23) ? "MCS23" :\
182*4882a593Smuzhiyun 	(rate == DESC_RATEMCS24) ? "MCS24" :\
183*4882a593Smuzhiyun 	(rate == DESC_RATEMCS25) ? "MCS25" :\
184*4882a593Smuzhiyun 	(rate == DESC_RATEMCS26) ? "MCS26" :\
185*4882a593Smuzhiyun 	(rate == DESC_RATEMCS27) ? "MCS27" :\
186*4882a593Smuzhiyun 	(rate == DESC_RATEMCS28) ? "MCS28" :\
187*4882a593Smuzhiyun 	(rate == DESC_RATEMCS29) ? "MCS29" :\
188*4882a593Smuzhiyun 	(rate == DESC_RATEMCS30) ? "MCS30" :\
189*4882a593Smuzhiyun 	(rate == DESC_RATEMCS31) ? "MCS31" :\
190*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS0) ? "VHTSS1MCS0" :\
191*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS1) ? "VHTSS1MCS1" :\
192*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS2) ? "VHTSS1MCS2" :\
193*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS3) ? "VHTSS1MCS3" :\
194*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS4) ? "VHTSS1MCS4" :\
195*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS5) ? "VHTSS1MCS5" :\
196*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS6) ? "VHTSS1MCS6" :\
197*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS7) ? "VHTSS1MCS7" :\
198*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS8) ? "VHTSS1MCS8" :\
199*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS1MCS9) ? "VHTSS1MCS9" :\
200*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS0) ? "VHTSS2MCS0" :\
201*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS1) ? "VHTSS2MCS1" :\
202*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS2) ? "VHTSS2MCS2" :\
203*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS3) ? "VHTSS2MCS3" :\
204*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS4) ? "VHTSS2MCS4" :\
205*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS5) ? "VHTSS2MCS5" :\
206*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS6) ? "VHTSS2MCS6" :\
207*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS7) ? "VHTSS2MCS7" :\
208*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS8) ? "VHTSS2MCS8" :\
209*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" :\
210*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS0) ? "VHTSS3MCS0" :\
211*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS1) ? "VHTSS3MCS1" :\
212*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS2) ? "VHTSS3MCS2" :\
213*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS3) ? "VHTSS3MCS3" :\
214*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS4) ? "VHTSS3MCS4" :\
215*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS5) ? "VHTSS3MCS5" :\
216*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS6) ? "VHTSS3MCS6" :\
217*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS7) ? "VHTSS3MCS7" :\
218*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\
219*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" :\
220*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS0) ? "VHTSS4MCS0" :\
221*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS1) ? "VHTSS4MCS1" :\
222*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS2) ? "VHTSS4MCS2" :\
223*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS3) ? "VHTSS4MCS3" :\
224*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS4) ? "VHTSS4MCS4" :\
225*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS5) ? "VHTSS4MCS5" :\
226*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS6) ? "VHTSS4MCS6" :\
227*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS7) ? "VHTSS4MCS7" :\
228*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS8) ? "VHTSS4MCS8" :\
229*4882a593Smuzhiyun 	(rate == DESC_RATEVHTSS4MCS9) ? "VHTSS4MCS9" :\
230*4882a593Smuzhiyun 	"UNKNOWN"
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun enum {
233*4882a593Smuzhiyun 	UP_LINK,
234*4882a593Smuzhiyun 	DOWN_LINK,
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun typedef enum _RT_MEDIA_STATUS {
237*4882a593Smuzhiyun 	RT_MEDIA_DISCONNECT = 0,
238*4882a593Smuzhiyun 	RT_MEDIA_CONNECT       = 1
239*4882a593Smuzhiyun } RT_MEDIA_STATUS;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun #define MAX_DLFW_PAGE_SIZE			4096	/* @ page : 4k bytes */
242*4882a593Smuzhiyun typedef enum _FIRMWARE_SOURCE {
243*4882a593Smuzhiyun 	FW_SOURCE_IMG_FILE = 0,
244*4882a593Smuzhiyun 	FW_SOURCE_HEADER_FILE = 1,		/* from header file */
245*4882a593Smuzhiyun } FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun typedef enum _CH_SW_USE_CASE {
248*4882a593Smuzhiyun 	CH_SW_USE_CASE_TDLS		= 0,
249*4882a593Smuzhiyun 	CH_SW_USE_CASE_MCC		= 1
250*4882a593Smuzhiyun } CH_SW_USE_CASE;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun typedef enum _WAKEUP_REASON{
253*4882a593Smuzhiyun 	RX_PAIRWISEKEY					= 0x01,
254*4882a593Smuzhiyun 	RX_GTK							= 0x02,
255*4882a593Smuzhiyun 	RX_FOURWAY_HANDSHAKE			= 0x03,
256*4882a593Smuzhiyun 	RX_DISASSOC						= 0x04,
257*4882a593Smuzhiyun 	RX_DEAUTH						= 0x08,
258*4882a593Smuzhiyun 	RX_ARP_REQUEST					= 0x09,
259*4882a593Smuzhiyun 	FW_DECISION_DISCONNECT			= 0x10,
260*4882a593Smuzhiyun 	RX_MAGIC_PKT					= 0x21,
261*4882a593Smuzhiyun 	RX_UNICAST_PKT					= 0x22,
262*4882a593Smuzhiyun 	RX_PATTERN_PKT					= 0x23,
263*4882a593Smuzhiyun 	RTD3_SSID_MATCH					= 0x24,
264*4882a593Smuzhiyun 	RX_REALWOW_V2_WAKEUP_PKT		= 0x30,
265*4882a593Smuzhiyun 	RX_REALWOW_V2_ACK_LOST			= 0x31,
266*4882a593Smuzhiyun 	ENABLE_FAIL_DMA_IDLE			= 0x40,
267*4882a593Smuzhiyun 	ENABLE_FAIL_DMA_PAUSE			= 0x41,
268*4882a593Smuzhiyun 	RTIME_FAIL_DMA_IDLE				= 0x42,
269*4882a593Smuzhiyun 	RTIME_FAIL_DMA_PAUSE			= 0x43,
270*4882a593Smuzhiyun 	RX_PNO							= 0x55,
271*4882a593Smuzhiyun 	AP_OFFLOAD_WAKEUP				= 0x66,
272*4882a593Smuzhiyun 	CLK_32K_UNLOCK					= 0xFD,
273*4882a593Smuzhiyun 	CLK_32K_LOCK					= 0xFE
274*4882a593Smuzhiyun }WAKEUP_REASON;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun /*
277*4882a593Smuzhiyun  * Queue Select Value in TxDesc
278*4882a593Smuzhiyun  *   */
279*4882a593Smuzhiyun #define QSLT_BK							0x2/* 0x01 */
280*4882a593Smuzhiyun #define QSLT_BE							0x0
281*4882a593Smuzhiyun #define QSLT_VI							0x5/* 0x4 */
282*4882a593Smuzhiyun #define QSLT_VO							0x7/* 0x6 */
283*4882a593Smuzhiyun #define QSLT_BEACON						0x10
284*4882a593Smuzhiyun #define QSLT_HIGH						0x11
285*4882a593Smuzhiyun #define QSLT_MGNT						0x12
286*4882a593Smuzhiyun #define QSLT_CMD						0x13
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
289*4882a593Smuzhiyun  * #define MAX_TX_QUEUE		9 */
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun #define TX_SELE_HQ			BIT(0)		/* High Queue */
292*4882a593Smuzhiyun #define TX_SELE_LQ			BIT(1)		/* Low Queue */
293*4882a593Smuzhiyun #define TX_SELE_NQ			BIT(2)		/* Normal Queue */
294*4882a593Smuzhiyun #define TX_SELE_EQ			BIT(3)		/* Extern Queue */
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun #define PageNum_128(_Len)		(u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
297*4882a593Smuzhiyun #define PageNum_256(_Len)		(u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))
298*4882a593Smuzhiyun #define PageNum_512(_Len)		(u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))
299*4882a593Smuzhiyun #define PageNum(_Len, _Size)		(u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun struct dbg_rx_counter {
302*4882a593Smuzhiyun 	u32	rx_pkt_ok;
303*4882a593Smuzhiyun 	u32	rx_pkt_crc_error;
304*4882a593Smuzhiyun 	u32	rx_pkt_drop;
305*4882a593Smuzhiyun 	u32	rx_ofdm_fa;
306*4882a593Smuzhiyun 	u32	rx_cck_fa;
307*4882a593Smuzhiyun 	u32	rx_ht_fa;
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun u8 rtw_hal_get_port(_adapter *adapter);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun #ifdef CONFIG_MBSSID_CAM
313*4882a593Smuzhiyun 	/*#define DBG_MBID_CAM_DUMP*/
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	void rtw_mbid_cam_init(struct dvobj_priv *dvobj);
316*4882a593Smuzhiyun 	void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);
317*4882a593Smuzhiyun 	void rtw_mbid_cam_reset(_adapter *adapter);
318*4882a593Smuzhiyun 	u8 rtw_get_max_mbid_cam_id(_adapter *adapter);
319*4882a593Smuzhiyun 	u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
320*4882a593Smuzhiyun 	int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
321*4882a593Smuzhiyun 	int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
322*4882a593Smuzhiyun 	void rtw_mi_set_mbid_cam(_adapter *adapter);
323*4882a593Smuzhiyun 	u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
324*4882a593Smuzhiyun 	void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);
325*4882a593Smuzhiyun 	void rtw_mbid_cam_enable(_adapter *adapter);
326*4882a593Smuzhiyun #endif
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun #ifdef CONFIG_MI_WITH_MBSSID_CAM
329*4882a593Smuzhiyun 	void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
330*4882a593Smuzhiyun 	void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
331*4882a593Smuzhiyun 	#ifdef CONFIG_SWTIMER_BASED_TXBCN
332*4882a593Smuzhiyun 	u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
333*4882a593Smuzhiyun 	#endif
334*4882a593Smuzhiyun 	void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
335*4882a593Smuzhiyun #endif
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
338*4882a593Smuzhiyun void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
339*4882a593Smuzhiyun void rtw_reset_mac_rx_counters(_adapter *padapter);
340*4882a593Smuzhiyun void rtw_reset_phy_rx_counters(_adapter *padapter);
341*4882a593Smuzhiyun void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun #ifdef DBG_RX_COUNTER_DUMP
344*4882a593Smuzhiyun 	#define DUMP_DRV_RX_COUNTER	BIT0
345*4882a593Smuzhiyun 	#define DUMP_MAC_RX_COUNTER	BIT1
346*4882a593Smuzhiyun 	#define DUMP_PHY_RX_COUNTER	BIT2
347*4882a593Smuzhiyun 	#define DUMP_DRV_TRX_COUNTER_DATA	BIT3
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);
350*4882a593Smuzhiyun 	void rtw_dump_rx_counters(_adapter *padapter);
351*4882a593Smuzhiyun #endif
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun void dump_chip_info(HAL_VERSION	ChipVersion);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun #define BAND_CAP_2G			BIT0
356*4882a593Smuzhiyun #define BAND_CAP_5G			BIT1
357*4882a593Smuzhiyun #define BAND_CAP_BIT_NUM	2
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun #define BW_CAP_5M		BIT0
360*4882a593Smuzhiyun #define BW_CAP_10M		BIT1
361*4882a593Smuzhiyun #define BW_CAP_20M		BIT2
362*4882a593Smuzhiyun #define BW_CAP_40M		BIT3
363*4882a593Smuzhiyun #define BW_CAP_80M		BIT4
364*4882a593Smuzhiyun #define BW_CAP_160M		BIT5
365*4882a593Smuzhiyun #define BW_CAP_80_80M	BIT6
366*4882a593Smuzhiyun #define BW_CAP_BIT_NUM	7
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun #define PROTO_CAP_11B		BIT0
369*4882a593Smuzhiyun #define PROTO_CAP_11G		BIT1
370*4882a593Smuzhiyun #define PROTO_CAP_11N		BIT2
371*4882a593Smuzhiyun #define PROTO_CAP_11AC		BIT3
372*4882a593Smuzhiyun #define PROTO_CAP_BIT_NUM	4
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun #define WL_FUNC_P2P			BIT0
375*4882a593Smuzhiyun #define WL_FUNC_MIRACAST	BIT1
376*4882a593Smuzhiyun #define WL_FUNC_TDLS		BIT2
377*4882a593Smuzhiyun #define WL_FUNC_FTM			BIT3
378*4882a593Smuzhiyun #define WL_FUNC_BIT_NUM		4
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun #define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */
381*4882a593Smuzhiyun #define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/
382*4882a593Smuzhiyun #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun int hal_spec_init(_adapter *adapter);
385*4882a593Smuzhiyun void dump_hal_spec(void *sel, _adapter *adapter);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun bool hal_chk_band_cap(_adapter *adapter, u8 cap);
388*4882a593Smuzhiyun bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
389*4882a593Smuzhiyun bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
390*4882a593Smuzhiyun bool hal_is_band_support(_adapter *adapter, u8 band);
391*4882a593Smuzhiyun bool hal_is_bw_support(_adapter *adapter, u8 bw);
392*4882a593Smuzhiyun bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
393*4882a593Smuzhiyun bool hal_is_mimo_support(_adapter *adapter);
394*4882a593Smuzhiyun u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun bool hal_chk_wl_func(_adapter *adapter, u8 func);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun void hal_com_config_channel_plan(
399*4882a593Smuzhiyun 		PADAPTER padapter,
400*4882a593Smuzhiyun 		char *hw_alpha2,
401*4882a593Smuzhiyun 		u8 hw_chplan,
402*4882a593Smuzhiyun 		char *sw_alpha2,
403*4882a593Smuzhiyun 		u8 sw_chplan,
404*4882a593Smuzhiyun 		BOOLEAN AutoLoadFail
405*4882a593Smuzhiyun );
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
408*4882a593Smuzhiyun #ifdef RTW_HALMAC
409*4882a593Smuzhiyun void rtw_hal_hw_port_enable(_adapter *adapter);
410*4882a593Smuzhiyun void rtw_hal_hw_port_disable(_adapter *adapter);
411*4882a593Smuzhiyun #endif
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun BOOLEAN
414*4882a593Smuzhiyun HAL_IsLegalChannel(
415*4882a593Smuzhiyun 		PADAPTER	Adapter,
416*4882a593Smuzhiyun 		u32			Channel
417*4882a593Smuzhiyun );
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun u8	MRateToHwRate(u8 rate);
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun u8	hw_rate_to_m_rate(u8 rate);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun void	HalSetBrateCfg(
424*4882a593Smuzhiyun 		PADAPTER		Adapter,
425*4882a593Smuzhiyun 		u8			*mBratesOS,
426*4882a593Smuzhiyun 		u16			*pBrateCfg);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun BOOLEAN
429*4882a593Smuzhiyun Hal_MappingOutPipe(
430*4882a593Smuzhiyun 		PADAPTER	pAdapter,
431*4882a593Smuzhiyun 		u8		NumOutPipe
432*4882a593Smuzhiyun );
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun void rtw_dump_fw_info(void *sel, _adapter *adapter);
435*4882a593Smuzhiyun void rtw_restore_hw_port_cfg(_adapter *adapter);
436*4882a593Smuzhiyun void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
437*4882a593Smuzhiyun void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun void rtw_init_hal_com_default_value(PADAPTER Adapter);
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_REG
442*4882a593Smuzhiyun void c2h_evt_clear(_adapter *adapter);
443*4882a593Smuzhiyun s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
444*4882a593Smuzhiyun #endif
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_PKT
447*4882a593Smuzhiyun void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);
448*4882a593Smuzhiyun void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);
449*4882a593Smuzhiyun #endif
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);
454*4882a593Smuzhiyun s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);
455*4882a593Smuzhiyun s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);
456*4882a593Smuzhiyun void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun /* access HW only */
459*4882a593Smuzhiyun u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
460*4882a593Smuzhiyun void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
461*4882a593Smuzhiyun void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
462*4882a593Smuzhiyun void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
463*4882a593Smuzhiyun void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);
464*4882a593Smuzhiyun bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
469*4882a593Smuzhiyun u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
470*4882a593Smuzhiyun void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
471*4882a593Smuzhiyun void rtw_hal_rcr_set_chk_bssid_act_non(_adapter *adapter);
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun void rtw_iface_enable_tsf_update(_adapter *adapter);
474*4882a593Smuzhiyun void rtw_iface_disable_tsf_update(_adapter *adapter);
475*4882a593Smuzhiyun void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
476*4882a593Smuzhiyun void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun #if CONFIG_TX_AC_LIFETIME
479*4882a593Smuzhiyun #define TX_ACLT_CONF_DEFAULT	0
480*4882a593Smuzhiyun #define TX_ACLT_CONF_AP_M2U		1
481*4882a593Smuzhiyun #define TX_ACLT_CONF_MESH		2
482*4882a593Smuzhiyun #define TX_ACLT_CONF_NUM		3
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun extern const char *const _tx_aclt_conf_str[];
485*4882a593Smuzhiyun #define tx_aclt_conf_str(conf) (((conf) >= TX_ACLT_CONF_NUM) ? _tx_aclt_conf_str[TX_ACLT_CONF_NUM] : _tx_aclt_conf_str[(conf)])
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun struct tx_aclt_conf_t {
488*4882a593Smuzhiyun 	u8 en;
489*4882a593Smuzhiyun 	u32 vo_vi;
490*4882a593Smuzhiyun 	u32 be_bk;
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj);
494*4882a593Smuzhiyun void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num);
495*4882a593Smuzhiyun void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj);
496*4882a593Smuzhiyun void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num);
497*4882a593Smuzhiyun void rtw_hal_update_tx_aclt(_adapter *adapter);
498*4882a593Smuzhiyun #endif
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun void hw_var_port_switch(_adapter *adapter);
501*4882a593Smuzhiyun void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val);
502*4882a593Smuzhiyun u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
503*4882a593Smuzhiyun void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
504*4882a593Smuzhiyun void rtw_hal_check_rxfifo_full(_adapter *adapter);
505*4882a593Smuzhiyun void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
508*4882a593Smuzhiyun u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun u32
511*4882a593Smuzhiyun MapCharToHexDigit(
512*4882a593Smuzhiyun 		char	chTmp
513*4882a593Smuzhiyun );
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun BOOLEAN
516*4882a593Smuzhiyun GetHexValueFromString(
517*4882a593Smuzhiyun 			char		*szStr,
518*4882a593Smuzhiyun 			u32			*pu4bVal,
519*4882a593Smuzhiyun 			u32			*pu4bMove
520*4882a593Smuzhiyun );
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun BOOLEAN
523*4882a593Smuzhiyun GetFractionValueFromString(
524*4882a593Smuzhiyun 			char	*szStr,
525*4882a593Smuzhiyun 			u8		*pInteger,
526*4882a593Smuzhiyun 			u8		*pFraction,
527*4882a593Smuzhiyun 			u32		*pu4bMove
528*4882a593Smuzhiyun );
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun BOOLEAN
531*4882a593Smuzhiyun IsCommentString(
532*4882a593Smuzhiyun 			char		*szStr
533*4882a593Smuzhiyun );
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun BOOLEAN
536*4882a593Smuzhiyun ParseQualifiedString(
537*4882a593Smuzhiyun 		char *In,
538*4882a593Smuzhiyun 		u32 *Start,
539*4882a593Smuzhiyun 		char *Out,
540*4882a593Smuzhiyun 		char LeftQualifier,
541*4882a593Smuzhiyun 		char RightQualifier
542*4882a593Smuzhiyun );
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun BOOLEAN
545*4882a593Smuzhiyun GetU1ByteIntegerFromStringInDecimal(
546*4882a593Smuzhiyun 			char *Str,
547*4882a593Smuzhiyun 			u8 *pInt
548*4882a593Smuzhiyun );
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun BOOLEAN
551*4882a593Smuzhiyun isAllSpaceOrTab(
552*4882a593Smuzhiyun 	u8	*data,
553*4882a593Smuzhiyun 	u8	size
554*4882a593Smuzhiyun );
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun void linked_info_dump(_adapter *padapter, u8 benable);
557*4882a593Smuzhiyun #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
558*4882a593Smuzhiyun 	void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
559*4882a593Smuzhiyun 	void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
560*4882a593Smuzhiyun #endif
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun #ifdef DBG_RX_DFRAME_RAW_DATA
563*4882a593Smuzhiyun 	void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
564*4882a593Smuzhiyun #endif
565*4882a593Smuzhiyun void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
566*4882a593Smuzhiyun #define		HWSET_MAX_SIZE			1024
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun #ifdef CONFIG_EFUSE_CONFIG_FILE
569*4882a593Smuzhiyun u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
570*4882a593Smuzhiyun u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
571*4882a593Smuzhiyun #endif /* CONFIG_EFUSE_CONFIG_FILE */
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun int hal_efuse_macaddr_offset(_adapter *adapter);
574*4882a593Smuzhiyun int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
575*4882a593Smuzhiyun void rtw_dump_cur_efuse(PADAPTER padapter);
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun #ifdef CONFIG_RF_POWER_TRIM
578*4882a593Smuzhiyun 	void rtw_bb_rf_gain_offset(_adapter *padapter);
579*4882a593Smuzhiyun #endif /*CONFIG_RF_POWER_TRIM*/
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
582*4882a593Smuzhiyun u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
585*4882a593Smuzhiyun u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
586*4882a593Smuzhiyun #ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
587*4882a593Smuzhiyun void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx);
588*4882a593Smuzhiyun #endif
589*4882a593Smuzhiyun void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
590*4882a593Smuzhiyun u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun #ifdef CONFIG_TSF_RESET_OFFLOAD
593*4882a593Smuzhiyun int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
594*4882a593Smuzhiyun #endif
595*4882a593Smuzhiyun u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun #ifdef CONFIG_TDLS
598*4882a593Smuzhiyun 	#ifdef CONFIG_TDLS_CH_SW
599*4882a593Smuzhiyun 		s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
600*4882a593Smuzhiyun 	#endif
601*4882a593Smuzhiyun #endif
602*4882a593Smuzhiyun #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
603*4882a593Smuzhiyun s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);
604*4882a593Smuzhiyun #endif
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode);
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun #ifdef CONFIG_GPIO_API
609*4882a593Smuzhiyun 	u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);
610*4882a593Smuzhiyun 	int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);
611*4882a593Smuzhiyun 	int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);
612*4882a593Smuzhiyun 	int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));
613*4882a593Smuzhiyun 	int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);
614*4882a593Smuzhiyun #endif
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
617*4882a593Smuzhiyun void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
618*4882a593Smuzhiyun void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
621*4882a593Smuzhiyun void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
622*4882a593Smuzhiyun void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
623*4882a593Smuzhiyun void rtw_hal_set_input_gpio(_adapter *padapter, u8 index);
624*4882a593Smuzhiyun #define GPIO_OUTPUT_LOW		0
625*4882a593Smuzhiyun #define GPIO_OUTPUT_HIGH	1
626*4882a593Smuzhiyun #endif
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
629*4882a593Smuzhiyun 	extern char *rtw_phy_file_path;
630*4882a593Smuzhiyun 	extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
631*4882a593Smuzhiyun 	#define GetLineFromBuffer(buffer)   strsep(&buffer, "\r\n")
632*4882a593Smuzhiyun #endif
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun void update_IOT_info(_adapter *padapter);
635*4882a593Smuzhiyun #ifdef CONFIG_RTS_FULL_BW
636*4882a593Smuzhiyun void rtw_set_rts_bw(_adapter *padapter);
637*4882a593Smuzhiyun #endif/*CONFIG_RTS_FULL_BW*/
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun void ResumeTxBeacon(_adapter *padapter);
640*4882a593Smuzhiyun void StopTxBeacon(_adapter *padapter);
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY
643*4882a593Smuzhiyun 	u8	rtw_hal_antdiv_before_linked(_adapter *padapter);
644*4882a593Smuzhiyun 	void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
645*4882a593Smuzhiyun #endif
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun #ifdef DBG_SEC_CAM_MOVE
648*4882a593Smuzhiyun 	void rtw_hal_move_sta_gk_to_dk(_adapter *adapter);
649*4882a593Smuzhiyun 	void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);
650*4882a593Smuzhiyun #endif
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun #ifdef CONFIG_LPS_PG
653*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
654*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
655*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
656*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
657*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
658*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/
659*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
660*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
661*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
662*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
663*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
664*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
665*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
666*4882a593Smuzhiyun #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
667*4882a593Smuzhiyun enum lps_pg_hdl_id {
668*4882a593Smuzhiyun 	LPS_PG_INFO_CFG = 0,
669*4882a593Smuzhiyun 	LPS_PG_REDLEMEM,
670*4882a593Smuzhiyun 	LPS_PG_PHYDM_DIS,
671*4882a593Smuzhiyun 	LPS_PG_PHYDM_EN,
672*4882a593Smuzhiyun };
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter);
675*4882a593Smuzhiyun u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
676*4882a593Smuzhiyun #endif
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
679*4882a593Smuzhiyun void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);
680*4882a593Smuzhiyun void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,
681*4882a593Smuzhiyun 				u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap);
684*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
685*4882a593Smuzhiyun struct rtl_wow_pattern {
686*4882a593Smuzhiyun 	u16	crc;
687*4882a593Smuzhiyun 	u8	type;
688*4882a593Smuzhiyun 	u32	mask[4];
689*4882a593Smuzhiyun };
690*4882a593Smuzhiyun void rtw_wow_pattern_cam_dump(_adapter *adapter);
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
693*4882a593Smuzhiyun #ifdef CONFIG_WOW_PATTERN_HW_CAM
694*4882a593Smuzhiyun void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context);
695*4882a593Smuzhiyun #endif
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun struct rtw_ndp_info {
698*4882a593Smuzhiyun 	u8 enable:1;
699*4882a593Smuzhiyun 	u8 check_remote_ip:1; /* Need to Check Sender IP or not */
700*4882a593Smuzhiyun 	u8 rsvd:6;
701*4882a593Smuzhiyun 	u8 num_of_target_ip; /* Number of Check IP which NA query IP */
702*4882a593Smuzhiyun 	u8 target_link_addr[6]; /* DUT's MAC address */
703*4882a593Smuzhiyun 	u8 remote_ipv6_addr[16]; /* Just respond IP */
704*4882a593Smuzhiyun 	u8 target_ipv6_addr[16]; /* target IP */
705*4882a593Smuzhiyun };
706*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \
707*4882a593Smuzhiyun 	SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)
708*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \
709*4882a593Smuzhiyun 	SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)
710*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \
711*4882a593Smuzhiyun 	SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)
712*4882a593Smuzhiyun #define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \
713*4882a593Smuzhiyun 	SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)
714*4882a593Smuzhiyun #endif /*CONFIG_WOWLAN*/
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun #ifdef CONFIG_PROC_DEBUG
717*4882a593Smuzhiyun void rtw_dump_phy_cap(void *sel, _adapter *adapter);
718*4882a593Smuzhiyun #endif
719*4882a593Smuzhiyun void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);
720*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_FIFO_DUMP
721*4882a593Smuzhiyun void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);
722*4882a593Smuzhiyun #endif
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
725*4882a593Smuzhiyun s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
726*4882a593Smuzhiyun s32 rtw_set_default_port_id(_adapter *adapter);
727*4882a593Smuzhiyun s32 rtw_set_ps_rsvd_page(_adapter *adapter);
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun #define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)
730*4882a593Smuzhiyun #define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun /*void rtw_search_default_port(_adapter *adapter);*/
733*4882a593Smuzhiyun #endif
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS
736*4882a593Smuzhiyun #ifdef RTW_HALMAC
737*4882a593Smuzhiyun void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);
738*4882a593Smuzhiyun #endif
739*4882a593Smuzhiyun #endif
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun #ifdef RTW_CHANNEL_SWITCH_OFFLOAD
742*4882a593Smuzhiyun void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw);
743*4882a593Smuzhiyun #endif
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun s16 translate_dbm_to_percentage(s16 signal);
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_MULTI_BCN
748*4882a593Smuzhiyun void rtw_ap_multi_bcn_cfg(_adapter *adapter);
749*4882a593Smuzhiyun #endif
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun #ifdef CONFIG_SWTIMER_BASED_TXBCN
752*4882a593Smuzhiyun #ifdef CONFIG_BCN_RECOVERY
753*4882a593Smuzhiyun u8 rtw_ap_bcn_recovery(_adapter *padapter);
754*4882a593Smuzhiyun #endif
755*4882a593Smuzhiyun #ifdef CONFIG_BCN_XMIT_PROTECT
756*4882a593Smuzhiyun u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
757*4882a593Smuzhiyun #endif
758*4882a593Smuzhiyun #endif /*CONFIG_SWTIMER_BASED_TXBCN*/
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun #ifdef CONFIG_FW_HANDLE_TXBCN
761*4882a593Smuzhiyun void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
762*4882a593Smuzhiyun void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
763*4882a593Smuzhiyun #endif
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
766*4882a593Smuzhiyun 			 enum bb_path *tx, enum bb_path *rx);
767*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING
768*4882a593Smuzhiyun #ifdef RTW_BEAMFORMING_VERSION_2
769*4882a593Smuzhiyun void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
770*4882a593Smuzhiyun #endif
771*4882a593Smuzhiyun #endif
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun u8 phy_get_current_tx_num(PADAPTER pAdapter, u8 Rate);
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun #ifdef CONFIG_RTL8812A
776*4882a593Smuzhiyun u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );
777*4882a593Smuzhiyun #endif
778*4882a593Smuzhiyun 
779*4882a593Smuzhiyun #ifdef CONFIG_PROTSEL_PORT
780*4882a593Smuzhiyun void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel);
781*4882a593Smuzhiyun bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len);
782*4882a593Smuzhiyun void rtw_leave_protsel_port(_adapter *padapter);
783*4882a593Smuzhiyun #else
rtw_enter_protsel_port(_adapter * padapter,u8 port_sel)784*4882a593Smuzhiyun static inline void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel) {}
rtw_assert_protsel_port(_adapter * padapter,u32 addr,u8 len)785*4882a593Smuzhiyun static inline bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len) {return true; }
rtw_leave_protsel_port(_adapter * padapter)786*4882a593Smuzhiyun static inline void rtw_leave_protsel_port(_adapter *padapter) {}
787*4882a593Smuzhiyun #endif
788*4882a593Smuzhiyun #ifdef CONFIG_PROTSEL_ATIMDTIM
789*4882a593Smuzhiyun void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel);
790*4882a593Smuzhiyun bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len);
791*4882a593Smuzhiyun void rtw_leave_protsel_atimdtim(_adapter *padapter);
792*4882a593Smuzhiyun #else
rtw_enter_protsel_atimdtim(_adapter * padapter,u8 port_sel)793*4882a593Smuzhiyun static inline void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel) {}
rtw_assert_protsel_atimdtim(_adapter * padapter,u32 addr,u8 len)794*4882a593Smuzhiyun static inline bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len) {return true; }
rtw_leave_protsel_atimdtim(_adapter * padapter)795*4882a593Smuzhiyun static inline void rtw_leave_protsel_atimdtim(_adapter *padapter) {}
796*4882a593Smuzhiyun #endif
797*4882a593Smuzhiyun #ifdef CONFIG_PROTSEL_MACSLEEP
798*4882a593Smuzhiyun void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel);
799*4882a593Smuzhiyun bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len);
800*4882a593Smuzhiyun void rtw_leave_protsel_macsleep(_adapter *padapter);
801*4882a593Smuzhiyun #else
rtw_enter_protsel_macsleep(_adapter * padapter,u8 port_sel)802*4882a593Smuzhiyun static inline void rtw_enter_protsel_macsleep(_adapter *padapter, u8 port_sel) {}
rtw_assert_protsel_macsleep(_adapter * padapter,u32 addr,u8 len)803*4882a593Smuzhiyun static inline bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len) {return true; }
rtw_leave_protsel_macsleep(_adapter * padapter)804*4882a593Smuzhiyun static inline void rtw_leave_protsel_macsleep(_adapter *padapter) {}
805*4882a593Smuzhiyun #endif
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun #ifndef RTW_HALMAC
808*4882a593Smuzhiyun void rtw_hal_init_sifs_backup(_adapter *adapter);
809*4882a593Smuzhiyun #endif
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun #endif /* __HAL_COMMON_H__ */
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