1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _SDIO_HALINIT_C_
16
17 #include <rtl8188f_hal.h>
18 #include "hal_com_h2c.h"
19
20 /*
21 * Description:
22 * Call power on sequence to enable card
23 *
24 * Return:
25 * _SUCCESS enable success
26 * _FAIL enable fail
27 */
CardEnable(PADAPTER padapter)28 static u8 CardEnable(PADAPTER padapter)
29 {
30 u8 bMacPwrCtrlOn;
31 u8 ret = _FAIL;
32
33 bMacPwrCtrlOn = _FALSE;
34 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
35 if (bMacPwrCtrlOn == _FALSE) {
36 u8 hci_sus_state;
37
38 /* RSV_CTRL 0x1C[7:0] = 0x00 */
39 /* unlock ISO/CLK/Power control register */
40 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
41
42 hci_sus_state = HCI_SUS_LEAVING;
43 rtw_hal_set_hwreg(padapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
44 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8188F_card_enable_flow);
45 if (ret == _SUCCESS) {
46 bMacPwrCtrlOn = _TRUE;
47 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
48 hci_sus_state = HCI_SUS_LEAVE;
49 rtw_hal_set_hwreg(padapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
50 } else {
51 hci_sus_state = HCI_SUS_ERR;
52 rtw_hal_set_hwreg(padapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
53 }
54 } else
55 ret = _SUCCESS;
56
57 return ret;
58 }
59
_InitPowerOn_8188FS(PADAPTER padapter)60 static u32 _InitPowerOn_8188FS(PADAPTER padapter)
61 {
62 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
63 struct registry_priv *regsty = dvobj_to_regsty(dvobj);
64 u8 value8;
65 u16 value16;
66 u32 value32;
67 u8 ret;
68 u8 pwron_chk_cnt = 0;
69 /* u8 bMacPwrCtrlOn; */
70
71 _init_power_on:
72
73 /* check to apply user defined pll_ref_clk_sel */
74 if ((regsty->pll_ref_clk_sel & 0x0F) != 0x0F)
75 rtl8188f_set_pll_ref_clk_sel(padapter, regsty->pll_ref_clk_sel);
76
77 #ifdef CONFIG_EXT_CLK
78 /* Use external crystal(XTAL) */
79 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8188F + 2);
80 value8 |= BIT(7);
81 rtw_write8(padapter, REG_PAD_CTRL1_8188F + 2, value8);
82
83 /* CLK_REQ High active or Low Active */
84 /* Request GPIO polarity: */
85 /* 0: low active */
86 /* 1: high active */
87 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
88 value8 |= BIT(5);
89 rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
90 #endif /* CONFIG_EXT_CLK */
91
92 /* only cmd52 can be used before power on(card enable) */
93 ret = CardEnable(padapter);
94 if (ret == _FALSE) {
95 return _FAIL;
96 }
97
98 rtw_write8(padapter, REG_CR, 0x00);
99 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
100 value16 = rtw_read16(padapter, REG_CR);
101 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
102 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
103 rtw_write16(padapter, REG_CR, value16);
104
105
106 /* PowerOnCheck() */
107 ret = sdio_power_on_check(padapter);
108 pwron_chk_cnt++;
109 if (_FAIL == ret) {
110 if (pwron_chk_cnt > 1) {
111 RTW_INFO("Failed to init Power On!\n");
112 return _FAIL;
113 }
114 RTW_INFO("Power on Fail! do it again\n");
115 goto _init_power_on;
116 }
117
118 return _SUCCESS;
119 }
120
_InitQueueReservedPage(PADAPTER padapter)121 static void _InitQueueReservedPage(PADAPTER padapter)
122 {
123 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
124 struct registry_priv *pregistrypriv = &padapter->registrypriv;
125 u32 outEPNum = (u32)pHalData->OutEpNumber;
126 u32 numHQ = 0;
127 u32 numLQ = 0;
128 u32 numNQ = 0;
129 u32 numPubQ;
130 u32 value32;
131 u8 value8;
132 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
133
134 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
135 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8188F : NORMAL_PAGE_NUM_HPQ_8188F;
136
137 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
138 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8188F : NORMAL_PAGE_NUM_LPQ_8188F;
139
140 /* NOTE: This step shall be proceed before writting REG_RQPN. */
141 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
142 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8188F : NORMAL_PAGE_NUM_NPQ_8188F;
143
144 numPubQ = TX_TOTAL_PAGE_NUMBER_8188F - numHQ - numLQ - numNQ;
145
146 value8 = (u8)_NPQ(numNQ);
147 rtw_write8(padapter, REG_RQPN_NPQ, value8);
148
149 /* TX DMA */
150 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
151 rtw_write32(padapter, REG_RQPN, value32);
152
153 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ, SDIO_TX_DIV_NUM);
154
155 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
156 rtw_hal_sdio_avail_page_threshold_init(padapter);
157 #endif
158 }
159
_InitTxBufferBoundary(PADAPTER padapter)160 static void _InitTxBufferBoundary(PADAPTER padapter)
161 {
162 struct registry_priv *pregistrypriv = &padapter->registrypriv;
163 #ifdef CONFIG_CONCURRENT_MODE
164 u8 val8;
165 #endif /* CONFIG_CONCURRENT_MODE */
166
167 /* u16 txdmactrl; */
168 u8 txpktbuf_bndy;
169
170 if (!pregistrypriv->wifi_spec)
171 txpktbuf_bndy = TX_PAGE_BOUNDARY_8188F;
172 else {
173 /* for WMM */
174 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8188F;
175 }
176
177 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8188F, txpktbuf_bndy);
178 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8188F, txpktbuf_bndy);
179 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F, txpktbuf_bndy);
180 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
181 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
182
183 #ifdef CONFIG_CONCURRENT_MODE
184 val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8188F + WOWLAN_PAGE_NUM_8188F;
185 rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
186 rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 1, val8); /* BCN1_HEAD */
187
188 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2);
189 val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
190 rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8);
191 #endif /* CONFIG_CONCURRENT_MODE */
192 }
193
194 static void
_InitNormalChipRegPriority(PADAPTER Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)195 _InitNormalChipRegPriority(
196 PADAPTER Adapter,
197 u16 beQ,
198 u16 bkQ,
199 u16 viQ,
200 u16 voQ,
201 u16 mgtQ,
202 u16 hiQ
203 )
204 {
205 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
206
207 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
208 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
209 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
210
211 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
212 }
213
214 static void
_InitNormalChipOneOutEpPriority(PADAPTER Adapter)215 _InitNormalChipOneOutEpPriority(
216 PADAPTER Adapter
217 )
218 {
219 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
220
221 u16 value = 0;
222 switch (pHalData->OutEpQueueSel) {
223 case TX_SELE_HQ:
224 value = QUEUE_HIGH;
225 break;
226 case TX_SELE_LQ:
227 value = QUEUE_LOW;
228 break;
229 case TX_SELE_NQ:
230 value = QUEUE_NORMAL;
231 break;
232 default:
233 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
234 break;
235 }
236
237 _InitNormalChipRegPriority(Adapter,
238 value,
239 value,
240 value,
241 value,
242 value,
243 value
244 );
245
246 }
247
248 static void
_InitNormalChipTwoOutEpPriority(PADAPTER Adapter)249 _InitNormalChipTwoOutEpPriority(
250 PADAPTER Adapter
251 )
252 {
253 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
254 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
255 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
256
257
258 u16 valueHi = 0;
259 u16 valueLow = 0;
260
261 switch (pHalData->OutEpQueueSel) {
262 case (TX_SELE_HQ | TX_SELE_LQ):
263 valueHi = QUEUE_HIGH;
264 valueLow = QUEUE_LOW;
265 break;
266 case (TX_SELE_NQ | TX_SELE_LQ):
267 valueHi = QUEUE_NORMAL;
268 valueLow = QUEUE_LOW;
269 break;
270 case (TX_SELE_HQ | TX_SELE_NQ):
271 valueHi = QUEUE_HIGH;
272 valueLow = QUEUE_NORMAL;
273 break;
274 default:
275 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
276 break;
277 }
278
279 if (!pregistrypriv->wifi_spec) {
280 beQ = valueLow;
281 bkQ = valueLow;
282 viQ = valueHi;
283 voQ = valueHi;
284 mgtQ = valueHi;
285 hiQ = valueHi;
286 } else { /* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
287 beQ = valueLow;
288 bkQ = valueHi;
289 viQ = valueHi;
290 voQ = valueLow;
291 mgtQ = valueHi;
292 hiQ = valueHi;
293 }
294
295 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
296
297 }
298
299 static void
_InitNormalChipThreeOutEpPriority(PADAPTER padapter)300 _InitNormalChipThreeOutEpPriority(
301 PADAPTER padapter
302 )
303 {
304 struct registry_priv *pregistrypriv = &padapter->registrypriv;
305 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
306
307 if (!pregistrypriv->wifi_spec) { /* typical setting */
308 beQ = QUEUE_LOW;
309 bkQ = QUEUE_LOW;
310 viQ = QUEUE_NORMAL;
311 voQ = QUEUE_HIGH;
312 mgtQ = QUEUE_HIGH;
313 hiQ = QUEUE_HIGH;
314 } else { /* for WMM */
315 beQ = QUEUE_LOW;
316 bkQ = QUEUE_NORMAL;
317 viQ = QUEUE_NORMAL;
318 voQ = QUEUE_HIGH;
319 mgtQ = QUEUE_HIGH;
320 hiQ = QUEUE_HIGH;
321 }
322 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
323 }
324
325 static void
_InitNormalChipQueuePriority(PADAPTER Adapter)326 _InitNormalChipQueuePriority(
327 PADAPTER Adapter
328 )
329 {
330 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
331
332 switch (pHalData->OutEpNumber) {
333 case 1:
334 _InitNormalChipOneOutEpPriority(Adapter);
335 break;
336 case 2:
337 _InitNormalChipTwoOutEpPriority(Adapter);
338 break;
339 case 3:
340 _InitNormalChipThreeOutEpPriority(Adapter);
341 break;
342 default:
343 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
344 break;
345 }
346
347
348 }
349
_InitQueuePriority(PADAPTER padapter)350 static void _InitQueuePriority(PADAPTER padapter)
351 {
352 _InitNormalChipQueuePriority(padapter);
353 }
354
_InitPageBoundary(PADAPTER padapter)355 static void _InitPageBoundary(PADAPTER padapter)
356 {
357 /* RX Page Boundary */
358 u16 rxff_bndy = RX_DMA_BOUNDARY_8188F;
359
360 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
361 }
362
_InitTransferPageSize(PADAPTER padapter)363 static void _InitTransferPageSize(PADAPTER padapter)
364 {
365 /* Tx page size is always 128. */
366
367 u8 value8;
368 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
369 rtw_write8(padapter, REG_PBP, value8);
370 }
371
_InitDriverInfoSize(PADAPTER padapter,u8 drvInfoSize)372 void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
373 {
374 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
375 }
376
_InitNetworkType(PADAPTER padapter)377 void _InitNetworkType(PADAPTER padapter)
378 {
379 u32 value32;
380
381 value32 = rtw_read32(padapter, REG_CR);
382
383 /* TODO: use the other function to set network type
384 * value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
385 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
386
387 rtw_write32(padapter, REG_CR, value32);
388 }
389
_InitWMACSetting(PADAPTER padapter)390 void _InitWMACSetting(PADAPTER padapter)
391 {
392 PHAL_DATA_TYPE pHalData;
393 u16 value16;
394 u32 rcr;
395
396 pHalData = GET_HAL_DATA(padapter);
397
398 rcr = 0
399 | RCR_APM | RCR_AM | RCR_AB
400 | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF
401 | RCR_HTC_LOC_CTRL
402 | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC
403 #ifdef CONFIG_RX_PACKET_APPEND_FCS
404 | RCR_APPFCS
405 #endif
406 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
407 | RCR_AAP
408 | RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF
409 #endif
410 ;
411 rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&rcr);
412
413 /* Accept all multicast address */
414 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
415 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
416
417 /* Accept all data frames */
418 value16 = 0xFFFF;
419 rtw_write16(padapter, REG_RXFLTMAP2, value16);
420
421 /* 2010.09.08 hpfan */
422 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
423 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
424 value16 = 0x400;
425 rtw_write16(padapter, REG_RXFLTMAP1, value16);
426
427 /* Accept all management frames */
428 value16 = 0xFFFF;
429 rtw_write16(padapter, REG_RXFLTMAP0, value16);
430 }
431
_InitAdaptiveCtrl(PADAPTER padapter)432 void _InitAdaptiveCtrl(PADAPTER padapter)
433 {
434 u16 value16;
435 u32 value32;
436
437 /* Response Rate Set */
438 value32 = rtw_read32(padapter, REG_RRSR);
439 value32 &= ~RATE_BITMAP_ALL;
440 value32 |= RATE_RRSR_CCK_ONLY_1M;
441
442 rtw_phydm_set_rrsr(padapter, value32, TRUE);
443
444
445 /* CF-END Threshold */
446 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
447
448 /* Retry Limit */
449 value16 = BIT_LRL(RL_VAL_STA) | BIT_SRL(RL_VAL_STA);
450 rtw_write16(padapter, REG_RETRY_LIMIT, value16);
451 }
452
_InitEDCA(PADAPTER padapter)453 void _InitEDCA(PADAPTER padapter)
454 {
455 /* TXOP */
456 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
457 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
458 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
459 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
460
461 rtw_write8(padapter, REG_USTIME_EDCA_8188F, 0x28);
462 rtw_write8(padapter, REG_USTIME_TSF_8188F, 0x28);
463 }
464
_InitRetryFunction(PADAPTER padapter)465 void _InitRetryFunction(PADAPTER padapter)
466 {
467 u8 value8;
468
469 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
470 value8 |= EN_AMPDU_RTY_NEW;
471 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
472
473 /* Set ACK timeout */
474 rtw_write8(padapter, REG_ACKTO, 0x40);
475 }
476
HalRxAggr8188FSdio(PADAPTER padapter)477 static void HalRxAggr8188FSdio(PADAPTER padapter)
478 {
479 u8 dma_time_th;
480 u8 dma_len_th;
481
482 dma_time_th = 0x01;
483 dma_len_th = 0x0f;
484
485 if (dma_len_th * 1024 > MAX_RECVBUF_SZ) {
486 RTW_PRINT("Reduce RXDMA_AGG_LEN_TH from %u to %u\n"
487 , dma_len_th, MAX_RECVBUF_SZ / 1024);
488 dma_len_th = MAX_RECVBUF_SZ / 1024;
489 }
490
491 rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, (dma_time_th << 8) | dma_len_th);
492 }
493
sdio_AggSettingRxUpdate(PADAPTER padapter)494 void sdio_AggSettingRxUpdate(PADAPTER padapter)
495 {
496 HAL_DATA_TYPE *pHalData;
497 u8 valueDMA;
498 u8 valueRxAggCtrl = 0;
499 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */
500 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */
501
502 pHalData = GET_HAL_DATA(padapter);
503
504 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
505 valueDMA |= RXDMA_AGG_EN;
506 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
507
508 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
509 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
510 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
511 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8188F, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
512 }
513
_initSdioAggregationSetting(PADAPTER padapter)514 void _initSdioAggregationSetting(PADAPTER padapter)
515 {
516 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
517
518 /* Tx aggregation setting
519 * sdio_AggSettingTxUpdate(padapter); */
520
521 /* Rx aggregation setting */
522 HalRxAggr8188FSdio(padapter);
523
524 sdio_AggSettingRxUpdate(padapter);
525 }
526
527 #if 0
528 static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
529 {
530 PHAL_DATA_TYPE pHalData;
531 u8 valueDMA;
532 u8 valueRxAggCtrl;
533
534
535 pHalData = GET_HAL_DATA(padapter);
536
537 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
538 valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8188F);
539
540 if (_TRUE == enable) {
541 valueDMA |= RXDMA_AGG_EN;
542 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
543 } else {
544 valueDMA &= ~RXDMA_AGG_EN;
545 valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
546 }
547
548 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
549 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8188F, valueRxAggCtrl);
550 }
551 #endif
552
_InitInterrupt(PADAPTER padapter)553 void _InitInterrupt(PADAPTER padapter)
554 {
555 /* */
556 /* Initialize and enable SDIO Host Interrupt. */
557 /* */
558 InitInterrupt8188FSdio(padapter);
559
560 /* */
561 /* Initialize system Host Interrupt. */
562 /* */
563 InitSysInterrupt8188FSdio(padapter);
564 }
565
_InitRDGSetting(PADAPTER padapter)566 void _InitRDGSetting(PADAPTER padapter)
567 {
568 rtw_write8(padapter, REG_RD_CTRL, 0xFF);
569 rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
570 rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
571 }
572
_InitRFType(PADAPTER padapter)573 static void _InitRFType(PADAPTER padapter)
574 {
575 struct registry_priv *pregpriv = &padapter->registrypriv;
576 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
577
578 #if DISABLE_BB_RF
579 pHalData->rf_chip = RF_PSEUDO_11N;
580 return;
581 #endif
582 pHalData->rf_chip = RF_6052;
583
584 RTW_INFO("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
585 }
586
587 /*
588 * 2010/08/09 MH Add for power down check.
589 * */
HalDetectPwrDownMode(PADAPTER Adapter)590 static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
591 {
592 u8 tmpvalue;
593 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
594 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
595
596
597 EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
598
599 /* 2010/08/25 MH INF priority > PDN Efuse value. */
600 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
601 pHalData->pwrdown = _TRUE;
602 else
603 pHalData->pwrdown = _FALSE;
604
605 RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
606
607 return pHalData->pwrdown;
608 } /* HalDetectPwrDownMode */
609
rtl8188fs_hal_init(PADAPTER padapter)610 static u32 rtl8188fs_hal_init(PADAPTER padapter)
611 {
612 s32 ret;
613 PHAL_DATA_TYPE pHalData;
614 struct pwrctrl_priv *pwrctrlpriv;
615 struct registry_priv *pregistrypriv;
616 struct sreset_priv *psrtpriv;
617 struct dvobj_priv *psdpriv = padapter->dvobj;
618 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
619
620 rt_rf_power_state eRfPowerStateToSet;
621 u32 NavUpper = WiFiNavUpperUs;
622 u8 u1bTmp;
623 u16 value16;
624 u8 typeid;
625 u32 u4Tmp;
626
627 pHalData = GET_HAL_DATA(padapter);
628 psrtpriv = &pHalData->srestpriv;
629 pwrctrlpriv = adapter_to_pwrctl(padapter);
630 pregistrypriv = &padapter->registrypriv;
631
632 #ifdef CONFIG_SWLPS_IN_IPS
633 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
634 u8 val8, bMacPwrCtrlOn = _TRUE;
635
636 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
637
638 /* ser rpwm */
639 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
640 val8 &= 0x80;
641 val8 += 0x80;
642 val8 |= BIT(6);
643 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
644
645 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
646
647 rtw_mdelay_os(5); /* wait set rpwm already */
648
649 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8188F_leave_swlps_flow);
650 if (ret == _FALSE) {
651 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
652 return _FAIL;
653 }
654
655 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
656
657 pHalData->LastHMEBoxNum = 0;
658
659
660 return _SUCCESS;
661 }
662 #elif defined(CONFIG_FWLPS_IN_IPS)
663 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
664 && adapter_to_pwrctl(padapter)->pre_ips_type == 0) {
665 systime start_time;
666 u8 cpwm_orig, cpwm_now;
667 u8 val8, bMacPwrCtrlOn = _TRUE;
668
669 RTW_INFO("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
670
671 /* for polling cpwm */
672 cpwm_orig = 0;
673 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
674
675 /* ser rpwm */
676 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
677 val8 &= 0x80;
678 val8 += 0x80;
679 val8 |= BIT(6);
680 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
681 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
682 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
683
684 /* do polling cpwm */
685 start_time = rtw_get_current_time();
686 do {
687
688 rtw_mdelay_os(1);
689
690 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
691 if ((cpwm_orig ^ cpwm_now) & 0x80) {
692 #ifdef DBG_CHECK_FW_PS_STATE
693 RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
694 , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
695 #endif /* DBG_CHECK_FW_PS_STATE */
696 break;
697 }
698
699 if (rtw_get_passing_time_ms(start_time) > 100) {
700 RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
701 break;
702 }
703 } while (1);
704
705 rtl8188f_set_FwPwrModeInIPS_cmd(padapter, 0);
706
707 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
708
709
710 #ifdef DBG_CHECK_FW_PS_STATE
711 if (rtw_fw_ps_state(padapter) == _FAIL) {
712 RTW_INFO("after hal init, fw ps state in 32k\n");
713 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
714 }
715 #endif /* DBG_CHECK_FW_PS_STATE */
716 return _SUCCESS;
717 }
718 #endif /* CONFIG_SWLPS_IN_IPS */
719
720 /* Disable Interrupt first.
721 * rtw_hal_disable_interrupt(padapter); */
722
723 if (rtw_read8(padapter, REG_MCUFWDL) == 0xc6)
724 RTW_INFO("FW exist before power on!!\n");
725 else
726 RTW_INFO("FW does not exist before power on!!\n");
727 #ifdef DBG_CHECK_FW_PS_STATE
728 if (rtw_fw_ps_state(padapter) == _FAIL) {
729 RTW_INFO("check fw_ps_state fail before PowerOn!\n");
730 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
731 }
732 #endif
733 ret = rtw_hal_power_on(padapter);
734 if (_FAIL == ret) {
735 return _FAIL;
736 }
737 RTW_INFO("Power on ok!\n");
738
739 #ifdef DBG_CHECK_FW_PS_STATE
740 if (rtw_fw_ps_state(padapter) == _FAIL) {
741 RTW_INFO("check fw_ps_state fail after PowerOn!\n");
742 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
743 }
744 #endif
745 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
746
747 if (padapter->registrypriv.mp_mode == 0
748 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
749 || padapter->registrypriv.mp_customer_str
750 #endif
751 ){
752 ret = rtl8188f_FirmwareDownload(padapter, _FALSE);
753 if (ret != _SUCCESS) {
754 pHalData->bFWReady = _FALSE;
755 pHalData->fw_ractrl = _FALSE;
756 return ret;
757 } else {
758 pHalData->bFWReady = _TRUE;
759 pHalData->fw_ractrl = _TRUE;
760 }
761 }
762
763 /* SIC_Init(padapter); */
764
765 if (pwrctrlpriv->reg_rfoff == _TRUE)
766 pwrctrlpriv->rf_pwrstate = rf_off;
767
768 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
769 /* HW GPIO pin. Before PHY_RFConfig8192C. */
770 HalDetectPwrDownMode(padapter);
771
772 /* Set RF type for BB/RF configuration */
773 _InitRFType(padapter);
774
775 /* Save target channel */
776 /* <Roger_Notes> Current Channel will be updated again later. */
777 pHalData->current_channel = 6;
778
779 #if (HAL_MAC_ENABLE == 1)
780 ret = PHY_MACConfig8188F(padapter);
781 if (ret != _SUCCESS) {
782 return ret;
783 }
784 #endif
785 /* */
786 /* d. Initialize BB related configurations. */
787 /* */
788 #if (HAL_BB_ENABLE == 1)
789 ret = PHY_BBConfig8188F(padapter);
790 if (ret != _SUCCESS) {
791 return ret;
792 }
793 #endif
794
795 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
796 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
797 /* if(pHalData->eRFPowerState == eRfOn) */
798 {
799 #if (HAL_RF_ENABLE == 1)
800 ret = PHY_RFConfig8188F(padapter);
801 if (ret != _SUCCESS) {
802 return ret;
803 }
804 #endif
805 }
806
807 /* */
808 /* Joseph Note: Keep RfRegChnlVal for later use. */
809 /* */
810 pHalData->RfRegChnlVal[0] = phy_query_rf_reg(padapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
811 pHalData->RfRegChnlVal[1] = phy_query_rf_reg(padapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask);
812
813
814 /* if (!pHalData->bMACFuncEnable) { */
815 _InitQueueReservedPage(padapter);
816 _InitTxBufferBoundary(padapter);
817
818 /* init LLT after tx buffer boundary is defined */
819 ret = rtl8188f_InitLLTTable(padapter);
820 if (_SUCCESS != ret) {
821 RTW_INFO("%s: Failed to init LLT Table!\n", __FUNCTION__);
822 return _FAIL;
823 }
824 /* } */
825 _InitQueuePriority(padapter);
826 _InitPageBoundary(padapter);
827 _InitTransferPageSize(padapter);
828
829 /* Get Rx PHY status in order to report RSSI and others. */
830 _InitDriverInfoSize(padapter, DRVINFO_SZ);
831 _InitNetworkType(padapter);
832 _InitWMACSetting(padapter);
833 _InitAdaptiveCtrl(padapter);
834 _InitEDCA(padapter);
835 _InitRetryFunction(padapter);
836 _initSdioAggregationSetting(padapter);
837 rtl8188f_InitBeaconParameters(padapter);
838 rtl8188f_InitBeaconMaxError(padapter, _TRUE);
839 _InitInterrupt(padapter);
840 _InitBurstPktLen_8188FS(padapter);
841
842 /* YJ,TODO */
843 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8188F, 0x3); /* CCA */
844 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
845
846 invalidate_cam_all(padapter);
847
848 BBTurnOnBlock_8188F(padapter);
849
850 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
851 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
852
853 rtl8188f_InitAntenna_Selection(padapter);
854
855 /* */
856 /* Disable BAR, suggested by Scott */
857 /* 2010.04.09 add by hpfan */
858 /* */
859 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
860
861 /* HW SEQ CTRL */
862 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
863 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
864
865
866 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
867 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
868 u1bTmp &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
869 rtw_write8(padapter, REG_SYS_FUNC_EN, u1bTmp);
870
871 rtw_write8(padapter, REG_RD_CTRL, 0x0F);
872 rtw_write8(padapter, REG_RD_CTRL + 1, 0xCF);
873 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F, 0x80);
874 rtw_write32(padapter, REG_CR, 0x0b0202ff);
875 #endif
876
877 /*
878 * onfigure SDIO TxRx Control to enable Rx DMA timer masking.
879 * 2010.02.24.
880 * Only clear necessary bits 0x0[2:0] and 0x2[15:0] and keep 0x0[15:3]
881 * 2015.03.19.
882 */
883 u4Tmp = rtw_read32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL);
884 #if 0
885 u4Tmp &= 0xFFFFFFF8;
886 #else
887 u4Tmp &= 0x0000FFF8;
888 #endif
889 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, u4Tmp);
890
891
892 rtl8188f_InitHalDm(padapter);
893
894 /* DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
895
896 /* if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) */ /* The lowest Beacon Type that HW can support */
897 /* pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE; */
898
899 /* */
900 /* Update current Tx FIFO page status. */
901 /* */
902 HalQueryTxBufferStatus8188FSdio(padapter);
903 HalQueryTxOQTBufferStatus8188FSdio(padapter);
904 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
905
906 /* Enable MACTXEN/MACRXEN block */
907 u1bTmp = rtw_read8(padapter, REG_CR);
908 u1bTmp |= (MACTXEN | MACRXEN);
909 rtw_write8(padapter, REG_CR, u1bTmp);
910
911 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
912
913 #ifdef CONFIG_XMIT_ACK
914 /* ack for xmit mgmt frames. */
915 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
916 #endif /* CONFIG_XMIT_ACK */
917
918 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
919
920 #if (MP_DRIVER == 1)
921 if (padapter->registrypriv.mp_mode == 1) {
922 padapter->mppriv.channel = pHalData->current_channel;
923 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
924 } else
925 #endif /* #if (MP_DRIVER == 1) */
926 {
927 pwrctrlpriv->rf_pwrstate = rf_on;
928
929 /*phy_lc_calibrate_8188f(&pHalData->odmpriv);*/
930 halrf_lck_trigger(&pHalData->odmpriv);
931
932 pHalData->neediqk_24g = _TRUE;
933
934 odm_txpowertracking_check(&pHalData->odmpriv);
935 }
936
937
938
939 return _SUCCESS;
940 }
941
942 /*
943 * Description:
944 * RTL8188e card disable power sequence v003 which suggested by Scott.
945 *
946 * First created by tynli. 2011.01.28.
947 * */
CardDisableRTL8188FSdio(PADAPTER padapter)948 static void CardDisableRTL8188FSdio(PADAPTER padapter)
949 {
950 u8 u1bTmp;
951 u16 u2bTmp;
952 u32 u4bTmp;
953 u8 bMacPwrCtrlOn;
954 u8 hci_sus_state;
955 u8 ret = _FAIL;
956
957 /* Run LPS WL RFOFF flow */
958 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8188F_enter_lps_flow);
959 if (ret == _FAIL)
960 RTW_ERR("%s: run RF OFF flow fail!\n", __func__);
961
962 /* ==== Reset digital sequence ====== */
963
964 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
965 if ((u1bTmp & RAM_DL_SEL) && GET_HAL_DATA(padapter)->bFWReady) /* 8051 RAM code */
966 rtl8188f_FirmwareSelfReset(padapter);
967
968 /* Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli. */
969 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
970 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
971 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
972
973 /* MCUFWDL 0x80[1:0]=0 */
974 /* reset MCU ready status */
975 rtw_write8(padapter, REG_MCUFWDL, 0);
976
977 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
978
979 /* derek mod for reg 0x1d
980 * u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
981 * u1bTmp &= ~BIT(0);
982 * rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
983 * u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
984 * u1bTmp |= BIT(0);
985 * rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp); */
986
987 /* ==== Reset digital sequence end ====== */
988
989 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
990 ret = _FALSE;
991 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
992 hci_sus_state = HCI_SUS_ENTERING;
993 rtw_hal_set_hwreg(padapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
994 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8188F_card_disable_flow);
995 if (ret == _FALSE) {
996 hci_sus_state = HCI_SUS_ERR;
997 rtw_hal_set_hwreg(padapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
998 RTW_ERR("%s: run CARD DISABLE flow fail!\n", __func__);
999 } else {
1000 hci_sus_state = HCI_SUS_ENTER;
1001 rtw_hal_set_hwreg(padapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
1002 }
1003
1004 GET_HAL_DATA(padapter)->bFWReady = _FALSE;
1005 }
1006
rtl8188fs_hal_deinit(PADAPTER padapter)1007 static u32 rtl8188fs_hal_deinit(PADAPTER padapter)
1008 {
1009 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1010 struct sreset_priv *psrtpriv = &pHalData->srestpriv;
1011 struct dvobj_priv *psdpriv = padapter->dvobj;
1012 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1013
1014 #ifdef CONFIG_MP_INCLUDED
1015 if (padapter->registrypriv.mp_mode == 1)
1016 MPT_DeInitAdapter(padapter);
1017 #endif
1018
1019 if (rtw_is_hw_init_completed(padapter)) {
1020 #ifdef CONFIG_SWLPS_IN_IPS
1021 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
1022 u8 bMacPwrCtrlOn;
1023 u8 ret = _TRUE;
1024
1025 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
1026
1027 rtw_write32(padapter, 0x130, 0x0);
1028 rtw_write32(padapter, 0x138, 0x100);
1029 rtw_write8(padapter, 0x13d, 0x1);
1030
1031
1032 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1033 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1034
1035 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8188F_enter_swlps_flow);
1036 if (ret == _FALSE) {
1037 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
1038 return _FAIL;
1039 }
1040 } else
1041 #elif defined(CONFIG_FWLPS_IN_IPS)
1042 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE) {
1043 if (padapter->netif_up == _TRUE) {
1044 int cnt = 0;
1045 u8 val8 = 0;
1046
1047 RTW_INFO("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
1048
1049 rtl8188f_set_FwPwrModeInIPS_cmd(padapter, 0x1);
1050 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
1051 do {
1052 val8 = rtw_read8(padapter, REG_HMETFR);
1053 cnt++;
1054 RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1055 rtw_mdelay_os(10);
1056 } while (cnt < 100 && (val8 != 0));
1057 /* H2C done, enter 32k */
1058 if (val8 == 0) {
1059 /* ser rpwm to enter 32k */
1060 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1061 val8 += 0x80;
1062 val8 |= BIT(0);
1063 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1064 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
1065 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1066 cnt = val8 = 0;
1067 do {
1068 val8 = rtw_read8(padapter, REG_CR);
1069 cnt++;
1070 RTW_INFO("%s polling 0x100=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1071 rtw_mdelay_os(10);
1072 } while (cnt < 100 && (val8 != 0xEA));
1073 #ifdef DBG_CHECK_FW_PS_STATE
1074 if (val8 != 0xEA)
1075 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1076 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1077 #endif /* DBG_CHECK_FW_PS_STATE */
1078 } else {
1079 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1080 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1081 }
1082
1083 RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
1084 , rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
1085
1086 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1087
1088 } else {
1089 pdbgpriv->dbg_carddisable_cnt++;
1090 #ifdef DBG_CHECK_FW_PS_STATE
1091 if (rtw_fw_ps_state(padapter) == _FAIL) {
1092 RTW_INFO("card disable should leave 32k\n");
1093 pdbgpriv->dbg_carddisable_error_cnt++;
1094 }
1095 #endif /* DBG_CHECK_FW_PS_STATE */
1096 rtw_hal_power_off(padapter);
1097
1098 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1099 }
1100
1101 } else
1102 #endif /* CONFIG_SWLPS_IN_IPS */
1103 {
1104 pdbgpriv->dbg_carddisable_cnt++;
1105 #ifdef DBG_CHECK_FW_PS_STATE
1106 if (rtw_fw_ps_state(padapter) == _FAIL) {
1107 RTW_INFO("card disable should leave 32k\n");
1108 pdbgpriv->dbg_carddisable_error_cnt++;
1109 }
1110 #endif /* DBG_CHECK_FW_PS_STATE */
1111 rtw_hal_power_off(padapter);
1112 }
1113 } else
1114 pdbgpriv->dbg_deinit_fail_cnt++;
1115
1116 return _SUCCESS;
1117 }
rtl8188fs_init_default_value(PADAPTER padapter)1118 static void rtl8188fs_init_default_value(PADAPTER padapter)
1119 {
1120 PHAL_DATA_TYPE pHalData;
1121
1122
1123 pHalData = GET_HAL_DATA(padapter);
1124
1125 rtl8188f_init_default_value(padapter);
1126
1127 /* interface related variable */
1128 pHalData->SdioRxFIFOCnt = 0;
1129 }
1130
rtl8188fs_interface_configure(PADAPTER padapter)1131 static void rtl8188fs_interface_configure(PADAPTER padapter)
1132 {
1133 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1134 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1135 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1136 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
1137
1138
1139 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1140 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1141 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1142
1143 if (bWiFiConfig)
1144 pHalData->OutEpNumber = 2;
1145 else
1146 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1147
1148 switch (pHalData->OutEpNumber) {
1149 case 3:
1150 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
1151 break;
1152 case 2:
1153 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1154 break;
1155 case 1:
1156 pHalData->OutEpQueueSel = TX_SELE_HQ;
1157 break;
1158 default:
1159 break;
1160 }
1161
1162 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1163 }
1164
1165 /*
1166 * Description:
1167 * We should set Efuse cell selection to WiFi cell in default.
1168 *
1169 * Assumption:
1170 * PASSIVE_LEVEL
1171 *
1172 * Added by Roger, 2010.11.23.
1173 * */
1174 static void
_EfuseCellSel(PADAPTER padapter)1175 _EfuseCellSel(
1176 PADAPTER padapter
1177 )
1178 {
1179 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1180
1181 u32 value32;
1182
1183 /* if(INCLUDE_MULTI_FUNC_BT(padapter)) */
1184 {
1185 value32 = rtw_read32(padapter, EFUSE_TEST);
1186 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1187 rtw_write32(padapter, EFUSE_TEST, value32);
1188 }
1189 }
1190
1191 static void
_ReadRFType(PADAPTER Adapter)1192 _ReadRFType(
1193 PADAPTER Adapter
1194 )
1195 {
1196 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1197
1198 #if DISABLE_BB_RF
1199 pHalData->rf_chip = RF_PSEUDO_11N;
1200 #else
1201 pHalData->rf_chip = RF_6052;
1202 #endif
1203 }
1204
1205 static u8
_ReadEfuseInfo8188FS(PADAPTER padapter)1206 _ReadEfuseInfo8188FS(
1207 PADAPTER padapter
1208 )
1209 {
1210 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1211 u8 *hwinfo = NULL;
1212 u8 ret = _FAIL;
1213
1214 /* */
1215 /* This part read and parse the eeprom/efuse content */
1216 /* */
1217
1218 if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8188F)
1219 RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8188F!\n");
1220
1221 hwinfo = pHalData->efuse_eeprom_data;
1222
1223 Hal_InitPGData(padapter, hwinfo);
1224
1225 Hal_EfuseParseIDCode(padapter, hwinfo);
1226 Hal_EfuseParseEEPROMVer_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1227 hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
1228 Hal_EfuseParseTxPowerInfo_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1229 /* Hal_EfuseParseBoardType_8188FS(padapter, hwinfo, pHalData->bautoload_fail_flag); */
1230
1231 /* */
1232 /* Read Bluetooth co-exist and initialize */
1233 /* */
1234 /* Hal_EfuseParseBTCoexistInfo_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); */
1235 Hal_EfuseParseChnlPlan_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1236 Hal_EfuseParseXtal_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1237 Hal_EfuseParseThermalMeter_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1238 Hal_EfuseParseAntennaDiversity_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1239 Hal_EfuseParseCustomerID_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1240
1241 /* Hal_EfuseParseVoltage_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); */
1242
1243 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1244 Hal_DetectWoWMode(padapter);
1245 #endif
1246
1247 Hal_EfuseParseKFreeData_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1248
1249 if (hal_read_mac_hidden_rpt(padapter) != _SUCCESS)
1250 goto exit;
1251
1252 ret = _SUCCESS;
1253
1254 exit:
1255 return ret;
1256 }
1257
_ReadPROMContent(PADAPTER padapter)1258 static u8 _ReadPROMContent(
1259 PADAPTER padapter
1260 )
1261 {
1262 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1263 u8 eeValue;
1264 u8 ret = _FAIL;
1265
1266 eeValue = rtw_read8(padapter, REG_9346CR);
1267 /* To check system boot selection. */
1268 pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
1269 pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
1270
1271
1272 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1273
1274 if (_ReadEfuseInfo8188FS(padapter) != _SUCCESS)
1275 goto exit;
1276
1277 ret = _SUCCESS;
1278
1279 exit:
1280 return ret;
1281 }
1282
1283 /*
1284 * Description:
1285 * Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
1286 *
1287 * Assumption:
1288 * PASSIVE_LEVEL (SDIO interface)
1289 *
1290 * */
ReadAdapterInfo8188FS(PADAPTER padapter)1291 static u8 ReadAdapterInfo8188FS(PADAPTER padapter)
1292 {
1293 u8 ret = _FAIL;
1294
1295 /* Read EEPROM size before call any EEPROM function */
1296 padapter->EepromAddressSize = GetEEPROMSize8188F(padapter);
1297
1298 _EfuseCellSel(padapter);
1299 _ReadRFType(padapter);
1300 if (_ReadPROMContent(padapter) != _SUCCESS)
1301 goto exit;
1302
1303 ret = _SUCCESS;
1304
1305 exit:
1306 return ret;
1307 }
1308
1309 /*
1310 * If variable not handled here,
1311 * some variables will be processed in SetHwReg8188F()
1312 */
SetHwReg8188FS(PADAPTER padapter,u8 variable,u8 * val)1313 u8 SetHwReg8188FS(PADAPTER padapter, u8 variable, u8 *val)
1314 {
1315 PHAL_DATA_TYPE pHalData;
1316 u8 ret = _SUCCESS;
1317 u8 val8;
1318
1319
1320 pHalData = GET_HAL_DATA(padapter);
1321
1322 switch (variable) {
1323 case HW_VAR_SET_RPWM:
1324 /* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) */
1325 /* BIT0 value - 1: 32k, 0:40MHz. */
1326 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1327 /* BIT7 value - Toggle bit change. */
1328 {
1329 val8 = *val;
1330 val8 &= 0xC1;
1331 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1332 }
1333 break;
1334 case HW_VAR_SET_REQ_FW_PS: {
1335 /* driver write 0x8f[4]=1, request fw ps state */
1336 u8 req_fw_ps = 0;
1337 req_fw_ps = rtw_read8(padapter, 0x8f);
1338 req_fw_ps |= 0x10;
1339 rtw_write8(padapter, 0x8f, req_fw_ps);
1340 }
1341 break;
1342 case HW_VAR_RXDMA_AGG_PG_TH:
1343 #if 0
1344 val8 = *val;
1345
1346 /* TH=1 => invalidate RX DMA aggregation */
1347 /* TH=0 => validate RX DMA aggregation, use init value. */
1348 if (val8 == 0) {
1349 /* enable RXDMA aggregation */
1350 /* _RXAggrSwitch(padapter, _TRUE); */
1351 } else {
1352 /* disable RXDMA aggregation */
1353 /* _RXAggrSwitch(padapter, _FALSE); */
1354 }
1355 #endif
1356 break;
1357 default:
1358 ret = SetHwReg8188F(padapter, variable, val);
1359 break;
1360 }
1361
1362 return ret;
1363 }
1364
1365 /*
1366 * If variable not handled here,
1367 * some variables will be processed in GetHwReg8188F()
1368 */
GetHwReg8188FS(PADAPTER padapter,u8 variable,u8 * val)1369 void GetHwReg8188FS(PADAPTER padapter, u8 variable, u8 *val)
1370 {
1371 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1372
1373
1374 switch (variable) {
1375 case HW_VAR_CPWM:
1376 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8188F);
1377 break;
1378
1379 case HW_VAR_FW_PS_STATE: {
1380 /* read dword 0x88, driver read fw ps state */
1381 *((u16 *)val) = rtw_read16(padapter, 0x88);
1382 }
1383 break;
1384 default:
1385 GetHwReg8188F(padapter, variable, val);
1386 break;
1387 }
1388
1389 }
1390
1391 /*
1392 * Description:
1393 * Query setting of specified variable.
1394 * */
1395 u8
GetHalDefVar8188FSDIO(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)1396 GetHalDefVar8188FSDIO(
1397 PADAPTER Adapter,
1398 HAL_DEF_VARIABLE eVariable,
1399 void *pValue
1400 )
1401 {
1402 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1403 u8 bResult = _SUCCESS;
1404
1405 switch (eVariable) {
1406 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1407 #ifdef CONFIG_ANTENNA_DIVERSITY
1408 *((u8 *)pValue) = _FALSE;
1409 #endif
1410 break;
1411
1412 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1413 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1414 /* coding by Lucas@20130730 */
1415 *(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_16K;
1416 break;
1417 default:
1418 bResult = GetHalDefVar8188F(Adapter, eVariable, pValue);
1419 break;
1420 }
1421
1422 return bResult;
1423 }
1424
1425 /*
1426 * Description:
1427 * Change default setting of specified variable.
1428 * */
1429 u8
SetHalDefVar8188FSDIO(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)1430 SetHalDefVar8188FSDIO(
1431 PADAPTER Adapter,
1432 HAL_DEF_VARIABLE eVariable,
1433 void *pValue
1434 )
1435 {
1436 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1437 u8 bResult = _SUCCESS;
1438
1439 switch (eVariable) {
1440 default:
1441 bResult = SetHalDefVar8188F(Adapter, eVariable, pValue);
1442 break;
1443 }
1444
1445 return bResult;
1446 }
1447
rtl8188fs_set_hal_ops(PADAPTER padapter)1448 void rtl8188fs_set_hal_ops(PADAPTER padapter)
1449 {
1450 struct hal_ops *pHalFunc = &padapter->hal_func;
1451
1452
1453 rtl8188f_set_hal_ops(pHalFunc);
1454
1455 pHalFunc->hal_power_on = &_InitPowerOn_8188FS;
1456 pHalFunc->hal_power_off = &CardDisableRTL8188FSdio;
1457
1458 pHalFunc->hal_init = &rtl8188fs_hal_init;
1459 pHalFunc->hal_deinit = &rtl8188fs_hal_deinit;
1460
1461 pHalFunc->init_xmit_priv = &rtl8188fs_init_xmit_priv;
1462 pHalFunc->free_xmit_priv = &rtl8188fs_free_xmit_priv;
1463
1464 pHalFunc->init_recv_priv = &rtl8188fs_init_recv_priv;
1465 pHalFunc->free_recv_priv = &rtl8188fs_free_recv_priv;
1466 #ifdef CONFIG_RECV_THREAD_MODE
1467 pHalFunc->recv_hdl = rtl8188fs_recv_hdl;
1468 #endif
1469 #ifdef CONFIG_RTW_SW_LED
1470 pHalFunc->InitSwLeds = &rtl8188fs_InitSwLeds;
1471 pHalFunc->DeInitSwLeds = &rtl8188fs_DeInitSwLeds;
1472 #endif
1473 pHalFunc->init_default_value = &rtl8188fs_init_default_value;
1474 pHalFunc->intf_chip_configure = &rtl8188fs_interface_configure;
1475 pHalFunc->read_adapter_info = &ReadAdapterInfo8188FS;
1476
1477 pHalFunc->enable_interrupt = &EnableInterrupt8188FSdio;
1478 pHalFunc->disable_interrupt = &DisableInterrupt8188FSdio;
1479 pHalFunc->check_ips_status = &CheckIPSStatus;
1480
1481 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1482 pHalFunc->clear_interrupt = &ClearInterrupt8188FSdio;
1483 #endif
1484 pHalFunc->set_hw_reg_handler = &SetHwReg8188FS;
1485 pHalFunc->GetHwRegHandler = &GetHwReg8188FS;
1486 pHalFunc->get_hal_def_var_handler = &GetHalDefVar8188FSDIO;
1487 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188FSDIO;
1488
1489 pHalFunc->hal_xmit = &rtl8188fs_hal_xmit;
1490 pHalFunc->mgnt_xmit = &rtl8188fs_mgnt_xmit;
1491 pHalFunc->hal_xmitframe_enqueue = &rtl8188fs_hal_xmitframe_enqueue;
1492
1493 #ifdef CONFIG_HOSTAPD_MLME
1494 pHalFunc->hostap_mgnt_xmit_entry = NULL;
1495 #endif
1496
1497 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
1498 pHalFunc->hal_init_checkbthang_workqueue = &rtl8188fs_init_checkbthang_workqueue;
1499 pHalFunc->hal_free_checkbthang_workqueue = &rtl8188fs_free_checkbthang_workqueue;
1500 pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8188fs_cancle_checkbthang_workqueue;
1501 pHalFunc->hal_checke_bt_hang = &rtl8188fs_hal_check_bt_hang;
1502 #endif
1503
1504 }
1505