1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTL8188F_PHYCFG_C_
16
17 #include <rtl8188f_hal.h>
18
19
20 /*---------------------------Define Local Constant---------------------------*/
21 /* Channel switch:The size of command tables for switch channel*/
22 #define MAX_PRECMD_CNT 16
23 #define MAX_RFDEPENDCMD_CNT 16
24 #define MAX_POSTCMD_CNT 16
25
26 #define MAX_DOZE_WAITING_TIMES_9x 64
27
28 /*---------------------------Define Local Constant---------------------------*/
29
30
31 /*------------------------Define global variable-----------------------------*/
32
33 /*------------------------Define local variable------------------------------*/
34
35
36 /*--------------------Define export function prototype-----------------------*/
37 /* Please refer to header file */
38 /*--------------------Define export function prototype-----------------------*/
39
40 /*----------------------------Function Body----------------------------------*/
41 /* */
42 /* 1. BB register R/W API */
43 /* */
44
45 /**
46 * Function: phy_CalculateBitShift
47 *
48 * OverView: Get shifted position of the BitMask
49 *
50 * Input:
51 * u32 BitMask,
52 *
53 * Output: none
54 * Return: u32 Return the shift bit bit position of the mask
55 */
56 static u32
phy_CalculateBitShift(u32 BitMask)57 phy_CalculateBitShift(
58 u32 BitMask
59 )
60 {
61 u32 i;
62
63 for (i = 0; i <= 31; i++) {
64 if (((BitMask >> i) & 0x1) == 1)
65 break;
66 }
67
68 return i;
69 }
70
71
72 /**
73 * Function: PHY_QueryBBReg
74 *
75 * OverView: Read "sepcific bits" from BB register
76 *
77 * Input:
78 * PADAPTER Adapter,
79 * u32 RegAddr, The target address to be readback
80 * u32 BitMask The target bit position in the target address
81 * to be readback
82 * Output: None
83 * Return: u32 Data The readback register value
84 * Note: This function is equal to "GetRegSetting" in PHY programming guide
85 */
86 u32
PHY_QueryBBReg_8188F(PADAPTER Adapter,u32 RegAddr,u32 BitMask)87 PHY_QueryBBReg_8188F(
88 PADAPTER Adapter,
89 u32 RegAddr,
90 u32 BitMask
91 )
92 {
93 u32 ReturnValue = 0, OriginalValue, BitShift;
94 u16 BBWaitCounter = 0;
95
96 #if (DISABLE_BB_RF == 1)
97 return 0;
98 #endif
99
100
101 OriginalValue = rtw_read32(Adapter, RegAddr);
102 BitShift = phy_CalculateBitShift(BitMask);
103 ReturnValue = (OriginalValue & BitMask) >> BitShift;
104
105 return ReturnValue;
106
107 }
108
109
110 /**
111 * Function: PHY_SetBBReg
112 *
113 * OverView: Write "Specific bits" to BB register (page 8~)
114 *
115 * Input:
116 * PADAPTER Adapter,
117 * u32 RegAddr, The target address to be modified
118 * u32 BitMask The target bit position in the target address
119 * to be modified
120 * u32 Data The new register value in the target bit position
121 * of the target address
122 *
123 * Output: None
124 * Return: None
125 * Note: This function is equal to "PutRegSetting" in PHY programming guide
126 */
127
128 void
PHY_SetBBReg_8188F(PADAPTER Adapter,u32 RegAddr,u32 BitMask,u32 Data)129 PHY_SetBBReg_8188F(
130 PADAPTER Adapter,
131 u32 RegAddr,
132 u32 BitMask,
133 u32 Data
134 )
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
137 /*u16 BBWaitCounter = 0; */
138 u32 OriginalValue, BitShift;
139
140 #if (DISABLE_BB_RF == 1)
141 return;
142 #endif
143
144
145 if (BitMask != bMaskDWord) { /*if not "double word" write */
146 OriginalValue = rtw_read32(Adapter, RegAddr);
147 BitShift = phy_CalculateBitShift(BitMask);
148 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
149 }
150
151 rtw_write32(Adapter, RegAddr, Data);
152 }
153
154
155 /* */
156 /* 2. RF register R/W API */
157 /* */
158 static u32
phy_RFSerialRead_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset)159 phy_RFSerialRead_8188F(
160 PADAPTER Adapter,
161 enum rf_path eRFPath,
162 u32 Offset
163 )
164 {
165 u32 retValue = 0;
166 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
167 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
168 u32 NewOffset;
169 u32 tmplong, tmplong2;
170 u8 RfPiEnable = 0;
171 u32 MaskforPhySet = 0;
172 int i = 0;
173
174 _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
175 /* */
176 /* Make sure RF register offset is correct */
177 /* */
178 Offset &= 0xff;
179
180 NewOffset = Offset;
181
182 if (eRFPath == RF_PATH_A) {
183 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
184 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /*T65 RF */
185 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
186 } else {
187 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
188 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /*T65 RF */
189 phy_set_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
190 }
191
192 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
193 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
194 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
195
196 rtw_udelay_os(10);
197
198 for (i = 0; i < 2; i++)
199 rtw_udelay_os(MAX_STALL_TIME);
200 rtw_udelay_os(10);
201
202 if (eRFPath == RF_PATH_A)
203 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
204 else if (eRFPath == RF_PATH_B)
205 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
206
207 if (RfPiEnable) {
208 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
209 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
210
211 /*RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
212 } else {
213 /*Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
214 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
215
216 /*RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
217 }
218 _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
219 return retValue;
220
221 }
222
223 /**
224 * Function: phy_RFSerialWrite_8188F
225 *
226 * OverView: Write data to RF register (page 8~)
227 *
228 * Input:
229 * PADAPTER Adapter,
230 enum rf_path RFPath, Radio path of A/B/C/D
231 * u32 Offset, The target address to be read
232 * u32 Data The new register Data in the target bit position
233 * of the target to be read
234 *
235 * Output: None
236 * Return: None
237 * Note: Threre are three types of serial operations:
238 * 1. Software serial write
239 * 2. Hardware LSSI-Low Speed Serial Interface
240 * 3. Hardware HSSI-High speed
241 * serial write. Driver need to implement (1) and (2).
242 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
243 *
244 * Note: For RF8256 only
245 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
246 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
247 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
248 * programming guide" for more details.
249 * Thus, we define a sub-finction for RTL8526 register address conversion
250 * ===========================================================
251 * Register Mode RegCTL[1] RegCTL[0] Note
252 * (Reg00[12]) (Reg00[10])
253 * ===========================================================
254 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
255 * ------------------------------------------------------------------
256 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
257 * ------------------------------------------------------------------
258 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
259 * ------------------------------------------------------------------
260 *
261 * 2008/09/02 MH Add 92S RF definition
262 *
263 *
264 *
265 */
266 static void
phy_RFSerialWrite_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset,u32 Data)267 phy_RFSerialWrite_8188F(
268 PADAPTER Adapter,
269 enum rf_path eRFPath,
270 u32 Offset,
271 u32 Data
272 )
273 {
274 u32 DataAndAddr = 0;
275 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
276 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
277 u32 NewOffset;
278
279 Offset &= 0xff;
280
281 /* */
282 /* Shadow Update */
283 /* */
284 /*PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
285
286 /* */
287 /* Switch page for 8256 RF IC */
288 /* */
289 NewOffset = Offset;
290
291 /* */
292 /* Put write addr in [5:0] and write data in [31:16] */
293 /* */
294 /*DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
295 DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
296
297 /* */
298 /* Write Operation */
299 /* */
300 phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
301 /*RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
302
303 }
304
305
306 /**
307 * Function: PHY_QueryRFReg
308 *
309 * OverView: Query "Specific bits" to RF register (page 8~)
310 *
311 * Input:
312 * PADAPTER Adapter,
313 enum rf_path eRFPath, Radio path of A/B/C/D
314 * u32 RegAddr, The target address to be read
315 * u32 BitMask The target bit position in the target address
316 * to be read
317 *
318 * Output: None
319 * Return: u32 Readback value
320 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
321 */
322 u32
PHY_QueryRFReg_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)323 PHY_QueryRFReg_8188F(
324 PADAPTER Adapter,
325 enum rf_path eRFPath,
326 u32 RegAddr,
327 u32 BitMask
328 )
329 {
330 u32 Original_Value, Readback_Value, BitShift;
331
332 #if (DISABLE_BB_RF == 1)
333 return 0;
334 #endif
335
336 Original_Value = phy_RFSerialRead_8188F(Adapter, eRFPath, RegAddr);
337
338 BitShift = phy_CalculateBitShift(BitMask);
339 Readback_Value = (Original_Value & BitMask) >> BitShift;
340
341 return Readback_Value;
342 }
343
344 /**
345 * Function: PHY_SetRFReg
346 *
347 * OverView: Write "Specific bits" to RF register (page 8~)
348 *
349 * Input:
350 * PADAPTER Adapter,
351 enum rf_path eRFPath, Radio path of A/B/C/D
352 * u32 RegAddr, The target address to be modified
353 * u32 BitMask The target bit position in the target address
354 * to be modified
355 * u32 Data The new register Data in the target bit position
356 * of the target address
357 *
358 * Output: None
359 * Return: None
360 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
361 */
362 void
PHY_SetRFReg_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)363 PHY_SetRFReg_8188F(
364 PADAPTER Adapter,
365 enum rf_path eRFPath,
366 u32 RegAddr,
367 u32 BitMask,
368 u32 Data
369 )
370 {
371 u32 Original_Value, BitShift;
372
373 #if (DISABLE_BB_RF == 1)
374 return;
375 #endif
376
377 /* RF data is 12 bits only */
378 if (BitMask != bRFRegOffsetMask) {
379 Original_Value = phy_RFSerialRead_8188F(Adapter, eRFPath, RegAddr);
380 BitShift = phy_CalculateBitShift(BitMask);
381 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
382 }
383
384 phy_RFSerialWrite_8188F(Adapter, eRFPath, RegAddr, Data);
385 }
386
387
388 /* */
389 /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
390 /* */
391
392
393 /*-----------------------------------------------------------------------------
394 * Function: PHY_MACConfig8192C
395 *
396 * Overview: Condig MAC by header file or parameter file.
397 *
398 * Input: NONE
399 *
400 * Output: NONE
401 *
402 * Return: NONE
403 *
404 * Revised History:
405 * When Who Remark
406 * 08/12/2008 MHC Create Version 0.
407 *
408 *---------------------------------------------------------------------------*/
PHY_MACConfig8188F(PADAPTER Adapter)409 s32 PHY_MACConfig8188F(PADAPTER Adapter)
410 {
411 int rtStatus = _SUCCESS;
412 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
413
414 /* */
415 /* Config MAC */
416 /* */
417 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
418 rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
419 if (rtStatus == _FAIL)
420 #endif
421 {
422 #ifdef CONFIG_EMBEDDED_FWIMG
423 odm_config_mac_with_header_file(&pHalData->odmpriv);
424 rtStatus = _SUCCESS;
425 #endif/*CONFIG_EMBEDDED_FWIMG */
426 }
427
428 #ifdef RTW_SIFS_INIT_BY_CORE
429 /* Set Spec SIFS (used in NAV) */
430 rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
431 rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
432
433 /* Set SIFS for CCK */
434 rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
435
436 /* Set SIFS for OFDM */
437 rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
438
439 /* RESP_SIFS for CCK */
440 rtw_write8(Adapter, REG_RESP_SIFS_CCK, 0x08); /* SIFS_T2T_CCK (0x08) */
441 rtw_write8(Adapter, REG_RESP_SIFS_CCK + 1, 0x08); /*SIFS_R2T_CCK(0x08) */
442 /* RESP_SIFS for OFDM */
443 rtw_write8(Adapter, REG_RESP_SIFS_OFDM, 0x0a); /* SIFS_T2T_OFDM (0x0a) */
444 rtw_write8(Adapter, REG_RESP_SIFS_OFDM + 1, 0x0a); /* SIFS_R2T_OFDM(0x0a) */
445 #endif
446
447 rtw_hal_init_sifs_backup(Adapter);
448
449 return rtStatus;
450 }
451
452 /**
453 * Function: phy_InitBBRFRegisterDefinition
454 *
455 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
456 *
457 * Input:
458 * PADAPTER Adapter,
459 *
460 * Output: None
461 * Return: None
462 * Note: The initialization value is constant and it should never be changes
463 */
464 static void
phy_InitBBRFRegisterDefinition(PADAPTER Adapter)465 phy_InitBBRFRegisterDefinition(
466 PADAPTER Adapter
467 )
468 {
469 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
470
471 /* RF Interface Sowrtware Control */
472 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
473 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
474
475 /* RF Interface Output (and Enable) */
476 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
477 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
478
479 /* RF Interface (Output and) Enable */
480 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
481 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
482
483 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /*LSSI Parameter */
484 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
485
486 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /*wire control parameter2 */
487 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /*wire control parameter2 */
488
489 /* Tranceiver Readback LSSI/HSPI mode */
490 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
491 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
492 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
493 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
494
495 }
496
497 static int
phy_BB8188f_Config_ParaFile(PADAPTER Adapter)498 phy_BB8188f_Config_ParaFile(
499 PADAPTER Adapter
500 )
501 {
502 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
503 int rtStatus = _SUCCESS;
504
505 /* */
506 /* 1. Read PHY_REG.TXT BB INIT!! */
507 /* */
508 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
509 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
510 #endif
511 {
512 #ifdef CONFIG_EMBEDDED_FWIMG
513 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
514 rtStatus = _FAIL;
515 #endif
516 }
517
518 if (rtStatus != _SUCCESS) {
519 RTW_INFO("%s():Write BB Reg Fail!!", __func__);
520 goto phy_BB8190_Config_ParaFile_Fail;
521 }
522
523 #if MP_DRIVER == 1
524 if (Adapter->registrypriv.mp_mode == 1) {
525 /* */
526 /* 1.1 Read PHY_REG_MP.TXT BB INIT!! */
527 /* */
528 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
529 if (phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP) == _FAIL)
530 #endif
531 {
532 #ifdef CONFIG_EMBEDDED_FWIMG
533 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))
534 rtStatus = _FAIL;
535 #endif
536 }
537
538 if (rtStatus != _SUCCESS) {
539 RTW_INFO("%s():Write BB Reg MP Fail!!", __func__);
540 goto phy_BB8190_Config_ParaFile_Fail;
541 }
542 }
543 #endif /* #if (MP_DRIVER == 1) */
544
545 /* */
546 /* 2. Read BB AGC table Initialization */
547 /* */
548 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
549 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
550 #endif
551 {
552 #ifdef CONFIG_EMBEDDED_FWIMG
553 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
554 rtStatus = _FAIL;
555 #endif
556 }
557
558 if (rtStatus != _SUCCESS) {
559 RTW_INFO("%s():AGC Table Fail\n", __func__);
560 goto phy_BB8190_Config_ParaFile_Fail;
561 }
562
563 phy_BB8190_Config_ParaFile_Fail:
564
565 return rtStatus;
566 }
567
568
569 int
PHY_BBConfig8188F(PADAPTER Adapter)570 PHY_BBConfig8188F(
571 PADAPTER Adapter
572 )
573 {
574 int rtStatus = _SUCCESS;
575 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
576 u16 RegVal;
577 u8 TmpU1B = 0;
578 u8 value8;
579
580 phy_InitBBRFRegisterDefinition(Adapter);
581
582 /* Enable BB and RF */
583 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
584 RegVal |= BIT13 | FEN_BB_GLB_RSTn | FEN_BBRSTB;
585 rtw_write16(Adapter, REG_SYS_FUNC_EN, RegVal);
586
587 #if 0 /* TODO: [BB]. reg 948 is only use for bt_coex */
588 #ifdef CONFIG_USB_HCI
589 rtw_write32(Adapter, 0x948, 0x0); /* USB use Antenna S0 */
590 #else
591 if (pHalData->ant_path == RF_PATH_A)
592 rtw_write32(Adapter, 0x948, 0x280);
593 else
594 rtw_write32(Adapter, 0x948, 0x0);
595 #endif
596
597 #endif
598 rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
599
600 rtw_usleep_os(10);
601
602 phy_set_rf_reg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
603
604 #if 0
605 /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
606 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
607 rtw_write8(Adapter, REG_AFE_PLL_CTRL + 1, 0xdb);
608 #endif
609
610 /* Config BB and AGC */
611 rtStatus = phy_BB8188f_Config_ParaFile(Adapter);
612
613 if (rtw_phydm_set_crystal_cap(Adapter, pHalData->crystal_cap) == _FALSE) {
614 RTW_ERR("Init crystal_cap failed\n");
615 rtw_warn_on(1);
616 rtStatus = _FAIL;
617 }
618
619 return rtStatus;
620 }
621
622 #if 0
623 /* Block & Path enable */
624 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
625 #define bOFDMEN_Jaguar 0x20000000
626 #define bCCKEN_Jaguar 0x10000000
627 #define rRxPath_Jaguar 0x808 /* Rx antenna */
628 #define bRxPath_Jaguar 0xff
629 #define rTxPath_Jaguar 0x80c /* Tx antenna */
630 #define bTxPath_Jaguar 0x0fffffff
631 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
632 #define bCCK_RX_Jaguar 0x0c000000
633 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
634 void
635 PHY_BB8188F_Config_1T(
636 PADAPTER Adapter
637 )
638 {
639 /* BB OFDM RX Path_A */
640 phy_set_bb_reg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
641 /* BB OFDM TX Path_A */
642 phy_set_bb_reg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
643 /* BB CCK R/Rx Path_A */
644 phy_set_bb_reg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
645 /* MCS support */
646 phy_set_bb_reg(Adapter, 0x8bc, 0xc0000060, 0x4);
647 /* RF Path_B HSSI OFF */
648 phy_set_bb_reg(Adapter, 0xe00, 0xf, 0x4);
649 /* RF Path_B Power Down */
650 phy_set_bb_reg(Adapter, 0xe90, bMaskDWord, 0);
651 /* ADDA Path_B OFF */
652 phy_set_bb_reg(Adapter, 0xe60, bMaskDWord, 0);
653 phy_set_bb_reg(Adapter, 0xe64, bMaskDWord, 0);
654 }
655 #endif
656
657 int
PHY_RFConfig8188F(PADAPTER Adapter)658 PHY_RFConfig8188F(
659 PADAPTER Adapter
660 )
661 {
662 int rtStatus = _SUCCESS;
663
664 /* */
665 /* RF config */
666 /* */
667 rtStatus = PHY_RF6052_Config8188F(Adapter);
668
669 /*PHY_BB8188F_Config_1T(Adapter); */
670
671 return rtStatus;
672 }
673
674 /*-----------------------------------------------------------------------------
675 * Function: PHY_ConfigRFWithParaFile()
676 *
677 * Overview: This function read RF parameters from general file format, and do RF 3-wire
678 *
679 * Input: PADAPTER Adapter
680 * ps1Byte pFileName
681 * enum rf_path eRFPath
682 *
683 * Output: NONE
684 *
685 * Return: RT_STATUS_SUCCESS: configuration file exist
686 *
687 * Note: Delay may be required for RF configuration
688 *---------------------------------------------------------------------------*/
689 int
PHY_ConfigRFWithParaFile_8188F(PADAPTER Adapter,u8 * pFileName,enum rf_path eRFPath)690 PHY_ConfigRFWithParaFile_8188F(
691 PADAPTER Adapter,
692 u8 *pFileName,
693 enum rf_path eRFPath
694 )
695 {
696 return _SUCCESS;
697 }
698
699 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
phy_set_txpwr_idx_offload(_adapter * adapter)700 bool phy_set_txpwr_idx_offload(_adapter *adapter)
701 {
702 return GET_HAL_DATA(adapter)->intf_start
703 #ifdef CONFIG_MP_INCLUDED
704 && !rtw_mp_mode_check(adapter)
705 #endif
706 ;
707 }
708
rtw_hal_h2c_txpwr_idx_offload(_adapter * adapter)709 s32 rtw_hal_h2c_txpwr_idx_offload(_adapter *adapter)
710 {
711 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
712 u8 data[H2C_TXPWR_IDX_OFFLOAD_LEN] = {0};
713 s32 ret;
714
715 _rtw_memcpy(data, hal_data->txpwr_idx_offload_buf, 3);
716 SET_H2CCMD_TXPWR_IDX_EN(data, 1);
717
718 ret = rtw_hal_fill_h2c_cmd(adapter, H2C_TXPWR_IDX_OFFLOAD, H2C_TXPWR_IDX_OFFLOAD_LEN, data);
719 if (ret != _SUCCESS)
720 RTW_WARN("%s fail\n", __func__);
721
722 return ret;
723 }
724
phy_set_txpwr_offload_8188f(_adapter * adapter)725 s32 phy_set_txpwr_offload_8188f(_adapter *adapter)
726 {
727 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
728 struct submit_ctx *sctx = &hal_data->txpwr_idx_offload_sctx;
729 s32 ret = _SUCCESS;
730
731 rtw_sctx_init(sctx, 500);
732 ret = rtw_hal_h2c_txpwr_idx_offload(adapter);
733 if (ret != _SUCCESS)
734 goto exit;
735
736 /* wait till rpt done or timeout */
737 ret = c2h_txpwr_idx_offload_wait(adapter);
738
739 exit:
740 return ret;
741 }
742 #endif /* CONFIG_FW_OFFLOAD_SET_TXPWR_IDX */
743
744 /**************************************************************************************************************
745 * Description:
746 * The low-level interface to set TxAGC , called by both MP and Normal Driver.
747 *
748 * <20120830, Kordan>
749 **************************************************************************************************************/
750
751 void
PHY_SetTxPowerIndex_8188F(PADAPTER Adapter,u32 PowerIndex,enum rf_path RFPath,u8 Rate)752 PHY_SetTxPowerIndex_8188F(
753 PADAPTER Adapter,
754 u32 PowerIndex,
755 enum rf_path RFPath,
756 u8 Rate
757 )
758 {
759 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
760 if (phy_set_txpwr_idx_offload(Adapter)) {
761 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
762
763 if (Rate == MGN_11M)
764 hal_data->txpwr_idx_offload_buf[CCK] = PowerIndex;
765 else if (Rate == MGN_54M)
766 hal_data->txpwr_idx_offload_buf[OFDM] = PowerIndex;
767 else if (Rate == MGN_MCS7)
768 hal_data->txpwr_idx_offload_buf[HT_1SS] = PowerIndex;
769
770 return;
771 }
772 #endif
773
774 if (RFPath == RF_PATH_A || RFPath == RF_PATH_B) {
775 switch (Rate) {
776 case MGN_1M:
777 phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
778 break;
779 case MGN_2M:
780 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
781 break;
782 case MGN_5_5M:
783 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
784 break;
785 case MGN_11M:
786 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
787 break;
788
789 case MGN_6M:
790 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
791 break;
792 case MGN_9M:
793 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
794 break;
795 case MGN_12M:
796 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
797 break;
798 case MGN_18M:
799 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
800 break;
801
802 case MGN_24M:
803 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
804 break;
805 case MGN_36M:
806 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
807 break;
808 case MGN_48M:
809 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
810 break;
811 case MGN_54M:
812 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
813 break;
814
815 case MGN_MCS0:
816 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
817 break;
818 case MGN_MCS1:
819 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
820 break;
821 case MGN_MCS2:
822 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
823 break;
824 case MGN_MCS3:
825 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
826 break;
827
828 case MGN_MCS4:
829 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
830 break;
831 case MGN_MCS5:
832 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
833 break;
834 case MGN_MCS6:
835 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
836 break;
837 case MGN_MCS7:
838 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
839 break;
840
841 default:
842 RTW_INFO("Invalid Rate!!\n");
843 break;
844 }
845 }
846 }
847
848 void
PHY_SetTxPowerLevel8188F(PADAPTER Adapter,u8 Channel)849 PHY_SetTxPowerLevel8188F(
850 PADAPTER Adapter,
851 u8 Channel
852 )
853 {
854 phy_set_tx_power_level_by_path(Adapter, Channel, RF_PATH_A);
855 }
856
rtl8188f_set_txpwr_done(_adapter * adapter)857 void rtl8188f_set_txpwr_done(_adapter *adapter)
858 {
859 /* TODO: for not offload case */
860
861 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
862 if (phy_set_txpwr_idx_offload(adapter))
863 phy_set_txpwr_offload_8188f(adapter);
864 #endif
865 }
866
867 /* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. (Asked by David.) */
868 void
phy_SpurCalibration_8188F(PADAPTER pAdapter,u8 ToChannel,u8 threshold)869 phy_SpurCalibration_8188F(
870 PADAPTER pAdapter,
871 u8 ToChannel,
872 u8 threshold
873 )
874 {
875 u32 freq[7] = {0xFCCD, 0xFC4D, 0xFFCD, 0xFF4D, 0xFCCD, 0xFF9A, 0xFDCD}; /* {chnl 5, 6, 7, 8, 13, 14 , 11} */
876 u8 idx = 0;
877 u8 b_doNotch = FALSE;
878 u8 initial_gain;
879 BOOLEAN bHW_Ctrl = FALSE, bSW_Ctrl = FALSE, bHW_Ctrl_S1 = FALSE, bSW_Ctrl_S1 = FALSE;
880 u32 reg948;
881
882 /* add for notch */
883 u32 wlan_channel, CurrentChannel, Is40MHz;
884 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
885 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
886
887 #ifdef CONFIG_AUTO_NOTCH_FILTER
888 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x1F);
889 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
890 #endif
891
892 /* check threshold */
893 if (threshold <= 0x0)
894 threshold = 0x16;
895
896 /* RTW_INFO("===> phy_SpurCalibration_8188F: Channel = %d\n", ToChannel); */
897
898 if (ToChannel == 5)
899 idx = 0;
900 else if (ToChannel == 6)
901 idx = 1;
902 else if (ToChannel == 7)
903 idx = 2;
904 else if (ToChannel == 8)
905 idx = 3;
906 else if (ToChannel == 13)
907 idx = 4;
908 else if (ToChannel == 14)
909 idx = 5;
910 else if (ToChannel == 11)
911 idx = 6;
912 else
913 idx = 10;
914
915 reg948 = phy_query_bb_reg(pAdapter, rS0S1_PathSwitch, bMaskDWord);
916 if ((reg948 & BIT6) == 0x0)
917 bSW_Ctrl = TRUE;
918 else
919 bHW_Ctrl = TRUE;
920
921 if (bHW_Ctrl)
922 bHW_Ctrl_S1 = (phy_query_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1) ? TRUE : FALSE;
923 else if (bSW_Ctrl)
924 bSW_Ctrl_S1 = ((reg948 & BIT9) == 0x0) ? TRUE : FALSE;
925
926 /* If wlan at S1 (both HW control & SW control) and current channel=5,6,7,8,13,14 */
927 if ((bHW_Ctrl_S1 || bSW_Ctrl_S1) && (idx <= 6)) {
928 initial_gain = (u8)(odm_get_bb_reg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
929 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, BIT24, 0); /* Disable CCK block */
930 odm_write_dig(pDM_Odm, 0x30);
931 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0); /* disable 3-wire */
932
933 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* Setup PSD */
934 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD */
935
936 rtw_msleep_os(30);
937
938 if (phy_query_bb_reg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
939 b_doNotch = TRUE;
940
941 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
942
943 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0); /* enable 3-wire */
944 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, BIT24, 1); /* Enable CCK block */
945 odm_write_dig(pDM_Odm, initial_gain);
946 }
947
948 /* --- Notch Filter --- Asked by Rock */
949 if (b_doNotch) {
950 CurrentChannel = odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
951 wlan_channel = CurrentChannel & 0x0f; /*Get center frequency */
952
953 switch (wlan_channel) { /*Set notch filter */
954 case 5:
955 case 13:
956 #ifndef CONFIG_AUTO_NOTCH_FILTER
957 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xB);
958 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
959 #endif
960 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x06000000);
961 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
962 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
963 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
964 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
965 break;
966 case 6:
967 #ifndef CONFIG_AUTO_NOTCH_FILTER
968 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x4);
969 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
970 #endif
971 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000600);
972 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
973 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
974 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
975 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
976 break;
977 case 7:
978 #ifndef CONFIG_AUTO_NOTCH_FILTER
979 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x3);
980 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
981 #endif
982 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
983 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
984 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
985 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x06000000);
986 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
987 break;
988 case 8:
989 #ifndef CONFIG_AUTO_NOTCH_FILTER
990 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xA);
991 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
992 #endif
993 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
994 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
995 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
996 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000380);
997 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
998 break;
999 case 11:
1000 #ifndef CONFIG_AUTO_NOTCH_FILTER
1001 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0x19);
1002 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter*/
1003 #endif
1004 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
1005 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x04000000);
1006 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
1007 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
1008 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask*/
1009 break;
1010 case 14:
1011 #ifndef CONFIG_AUTO_NOTCH_FILTER
1012 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x5);
1013 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
1014 #endif
1015 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
1016 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
1017 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
1018 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00180000);
1019 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
1020 break;
1021 default:
1022 #ifndef CONFIG_AUTO_NOTCH_FILTER
1023 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0); /*disable notch filter */
1024 #endif
1025 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0); /*disable CSI mask function */
1026 break;
1027 } /*switch(wlan_channel) */
1028 return;
1029 }
1030
1031 #ifndef CONFIG_AUTO_NOTCH_FILTER
1032 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0); /*disable notch filter */
1033 #endif
1034 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0); /*disable CSI mask */
1035
1036 }
1037
1038 void
phy_SetRegBW_8188F(PADAPTER Adapter,enum channel_width CurrentBW)1039 phy_SetRegBW_8188F(
1040 PADAPTER Adapter,
1041 enum channel_width CurrentBW
1042 )
1043 {
1044 u16 RegRfMod_BW, u2tmp = 0;
1045 RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8188F);
1046
1047 switch (CurrentBW) {
1048 case CHANNEL_WIDTH_20:
1049 rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
1050 break;
1051
1052 case CHANNEL_WIDTH_40:
1053 u2tmp = RegRfMod_BW | BIT7;
1054 rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
1055 break;
1056
1057 case CHANNEL_WIDTH_80:
1058 u2tmp = RegRfMod_BW | BIT8;
1059 rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
1060 break;
1061
1062 default:
1063 RTW_INFO("phy_PostSetBWMode8188F(): unknown Bandwidth: %#X\n", CurrentBW);
1064 break;
1065 }
1066 }
1067
1068 u8
phy_GetSecondaryChnl_8188F(PADAPTER Adapter)1069 phy_GetSecondaryChnl_8188F(
1070 PADAPTER Adapter
1071 )
1072 {
1073 u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
1074 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1075
1076 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
1077 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1078 SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
1079 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1080 SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
1081
1082
1083 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1084 SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
1085 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1086 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1087 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1088 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1089 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1090 SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
1091
1092 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
1093
1094 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1095 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1096 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1097 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1098
1099 }
1100
1101 return (SCSettingOf40 << 4) | SCSettingOf20;
1102 }
1103
1104 void
phy_PostSetBwMode8188F(PADAPTER Adapter)1105 phy_PostSetBwMode8188F(
1106 PADAPTER Adapter
1107 )
1108 {
1109 u8 SubChnlNum = 0;
1110 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1111
1112 /* RTW_INFO("===>%s: current_channel_bw = %s Mhz\n", __func__, pHalData->current_channel_bw?"40":"20"); */
1113
1114 switch (pHalData->current_channel_bw) {
1115 case CHANNEL_WIDTH_20:
1116 /*
1117 0x800[0]=1'b0
1118 0x900[0]=1'b0
1119 0x800[10:8]=3'b111(80M)
1120 0x800[14:12]=3'b101(80M)
1121 0xCE4[31:30]=2'b00
1122 0xCE4[29:28]=2'b01
1123 0xc10[29:28]=1
1124 0x954[19]=1'b0
1125 0x954[23:20]=3
1126 */
1127 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT0, 0x0);
1128 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, BIT0, 0x0);
1129 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT10 | BIT9 | BIT8, 0x7); /* RXADC CLK */
1130 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT14 | BIT13 | BIT12, 0x5); /* TXDAC CLK */
1131 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT31 | BIT30, 0x0); /* small BW */
1132 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1133 phy_set_bb_reg(Adapter, rOFDM0_XARxAFE, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1134 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT19, 0x0); /* OFDM RX DFIR */
1135 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT23 | BIT22 | BIT21 | BIT20, 0x3); /* OFDM RX DFIR */
1136 break;
1137
1138 case CHANNEL_WIDTH_40:
1139 /*
1140 0x800[0]=1'b1
1141 0x900[0]=1'b1
1142 0x800[10:8]=3'b111(80M)
1143 0x800[14:12]=3'b101(80M)
1144 0xCE4[31:30]=2'b00
1145 0xCE4[29:28]=2'b01
1146 0xc10[29:28]: 1
1147 0x954[19]=1'b0
1148 0x954[23:20]=0x6(For ACPR)
1149
1150 0xa00[4]=1/0
1151
1152 0x483[3:0]=1/2
1153 0x440[22:21]=2'b00
1154 */
1155 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT0, 0x1);
1156 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, BIT0, 0x1);
1157 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT10 | BIT9 | BIT8, 0x7); /* RXADC CLK */
1158 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT14 | BIT13 | BIT12, 0x5); /* TXDAC CLK */
1159 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT31 | BIT30, 0x0); /* small BW */
1160 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1161 phy_set_bb_reg(Adapter, rOFDM0_XARxAFE, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1162 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT19, 0x0); /* OFDM RX DFIR */
1163 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT23 | BIT22 | BIT21 | BIT20, 0x6); /* OFDM RX DFIR */
1164
1165 phy_set_bb_reg(Adapter, rCCK0_System, BIT4, (pHalData->nCur40MhzPrimeSC >> 1)); /* primary channel (CCK RXSC) */
1166
1167 SubChnlNum = phy_GetSecondaryChnl_8188F(Adapter);
1168 phy_set_mac_reg(Adapter, REG_DATA_SC_8188F, BIT3 | BIT2 | BIT1 | BIT0, SubChnlNum); /* txsc_20 */
1169 phy_set_mac_reg(Adapter, REG_RRSR_8188F, BIT22 | BIT21, 0x0); /* RRSR_RSC */
1170
1171 if (0)
1172 RTW_INFO("%s: REG_DATA_SC_8188F(%d) nCur40MhzPrimeSC(%d)\n", __func__, SubChnlNum, pHalData->nCur40MhzPrimeSC);
1173 break;
1174
1175 default:
1176 break;
1177 }
1178
1179 /*3<3>Set RF related register */
1180 PHY_RF6052SetBandwidth8188F(Adapter, pHalData->current_channel_bw);
1181 }
1182
1183 void
phy_SwChnl8188F(PADAPTER pAdapter)1184 phy_SwChnl8188F(
1185 PADAPTER pAdapter
1186 )
1187 {
1188 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1189 u8 channelToSW = pHalData->current_channel;
1190 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1191 struct dm_struct *pDM_Odm = &pHalData->DM_OutSrc;
1192 #else /* (DM_ODM_SUPPORT_TYPE == ODM_CE) */
1193 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1194 #endif
1195
1196 if (pHalData->rf_chip == RF_PSEUDO_11N) {
1197 return;
1198 }
1199
1200 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
1201 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
1202 /* phy_set_rf_reg(pAdapter, RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0] ); */
1203
1204 /* RTW_INFO("===>phy_SwChnl8188F: Channel = %d\n", channelToSW); */
1205
1206 phy_SpurCalibration_8188F(pAdapter, channelToSW, 0x16);
1207 }
1208
1209 void
PHY_HandleSwChnlAndSetBW8188F(PADAPTER Adapter,BOOLEAN bSwitchChannel,BOOLEAN bSetBandWidth,u8 ChannelNum,enum channel_width ChnlWidth,EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,u8 CenterFrequencyIndex1)1210 PHY_HandleSwChnlAndSetBW8188F(
1211 PADAPTER Adapter,
1212 BOOLEAN bSwitchChannel,
1213 BOOLEAN bSetBandWidth,
1214 u8 ChannelNum,
1215 enum channel_width ChnlWidth,
1216 EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,
1217 EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,
1218 u8 CenterFrequencyIndex1
1219 )
1220 {
1221 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1222
1223 /*check is swchnl or setbw */
1224 if (!bSwitchChannel && !bSetBandWidth) {
1225 RTW_INFO("PHY_HandleSwChnlAndSetBW8188F: not switch channel and not set bandwidth\n");
1226 return;
1227 }
1228
1229 if (RTW_CANNOT_RUN(Adapter))
1230 return;
1231
1232 /*skip change for channel or bandwidth is the same */
1233 if (bSwitchChannel) {
1234 if (pHalData->current_channel != ChannelNum) {
1235 if (HAL_IsLegalChannel(Adapter, ChannelNum))
1236 pHalData->bSwChnl = _TRUE;
1237 }
1238 }
1239
1240 if (bSetBandWidth) {
1241 if ((pHalData->current_channel_bw != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
1242 pHalData->bSetChnlBW = _TRUE;
1243 }
1244
1245 if (Adapter->bNotifyChannelChange)
1246 RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", __func__,
1247 pHalData->bSwChnl, ChannelNum, pHalData->bSetChnlBW, ChnlWidth);
1248
1249 if (!pHalData->bSetChnlBW && !pHalData->bSwChnl)
1250 goto exit_iqk;
1251
1252 pHalData->bSwChnl = _TRUE;
1253 pHalData->bSetChnlBW = _TRUE;
1254
1255 pHalData->current_channel = ChannelNum;
1256 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
1257
1258 pHalData->current_channel_bw = ChnlWidth;
1259 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
1260 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
1261 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1262
1263 phy_SwChnl8188F(Adapter);
1264 pHalData->bSwChnl = _FALSE;
1265
1266 phy_PostSetBwMode8188F(Adapter);
1267 pHalData->bSetChnlBW = _FALSE;
1268
1269 rtw_hal_set_tx_power_level(Adapter, pHalData->current_channel);
1270
1271 exit_iqk:
1272 if (pHalData->bNeedIQK == _TRUE) {
1273 if (pHalData->neediqk_24g == _TRUE) {
1274 halrf_iqk_trigger(&pHalData->odmpriv, _FALSE);
1275 pHalData->bIQKInitialized = _TRUE;
1276 pHalData->neediqk_24g = _FALSE;
1277 }
1278 pHalData->bNeedIQK = _FALSE;
1279 }
1280 }
1281
1282 void
PHY_SetSwChnlBWMode8188F(PADAPTER Adapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)1283 PHY_SetSwChnlBWMode8188F(
1284 PADAPTER Adapter,
1285 u8 channel,
1286 enum channel_width Bandwidth,
1287 u8 Offset40,
1288 u8 Offset80
1289 )
1290 {
1291 /*RTW_INFO("%s()===>\n",__func__); */
1292
1293 PHY_HandleSwChnlAndSetBW8188F(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
1294
1295 /*RTW_INFO("<==%s()\n",__func__); */
1296 }
1297
1298 /* Set CCK and OFDM Block "ON" */
BBTurnOnBlock_8188F(_adapter * adapter)1299 void BBTurnOnBlock_8188F(_adapter *adapter)
1300 {
1301 #if (DISABLE_BB_RF)
1302 return;
1303 #endif
1304
1305 phy_set_bb_reg(adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1306 phy_set_bb_reg(adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1307 }
1308
1309