1 /******************************************************************************
2 *
3 * Copyright(c) 2016 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 /*************************************************************
16 * Description:
17 *
18 * This file is for 8812/8821/8811 TXBF mechanism
19 *
20 ************************************************************/
21 #include "mp_precomp.h"
22 #include "../phydm_precomp.h"
23
24 #ifdef PHYDM_BEAMFORMING_SUPPORT
25 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
hal_txbf_8812a_set_ndpa_rate(void * dm_void,u8 BW,u8 rate)26 void hal_txbf_8812a_set_ndpa_rate(
27 void *dm_void,
28 u8 BW,
29 u8 rate)
30 {
31 struct dm_struct *dm = (struct dm_struct *)dm_void;
32
33 odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW));
34 }
35
hal_txbf_jaguar_rf_mode(void * dm_void,struct _RT_BEAMFORMING_INFO * beam_info)36 void hal_txbf_jaguar_rf_mode(
37 void *dm_void,
38 struct _RT_BEAMFORMING_INFO *beam_info)
39 {
40 struct dm_struct *dm = (struct dm_struct *)dm_void;
41
42 if (dm->rf_type == RF_1T1R)
43 return;
44
45 PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__);
46
47 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
48 odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
49
50 if (beam_info->beamformee_su_cnt > 0) {
51 /* Paath_A */
52 odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
53 odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
54 odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
55 /* Path_B */
56 odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
57 odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
58 odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
59 } else {
60 /* Paath_A */
61 odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
62 odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
63 odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
64 /* Path_B */
65 odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
66 odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
67 odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
68 }
69
70 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
71 odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
72
73 if (beam_info->beamformee_su_cnt > 0)
74 odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33);
75 else
76 odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11);
77 }
78
hal_txbf_jaguar_download_ndpa(void * dm_void,u8 idx)79 void hal_txbf_jaguar_download_ndpa(
80 void *dm_void,
81 u8 idx)
82 {
83 struct dm_struct *dm = (struct dm_struct *)dm_void;
84 u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
85 u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
86 boolean is_send_beacon = false;
87 u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/
88 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
89 struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
90 void *adapter = dm->adapter;
91 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
92 *dm->is_fw_dw_rsvd_page_in_progress = true;
93 #endif
94 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
95
96 /* if (idx == 0) head_page = 0xFE; */
97 /* else head_page = 0xFE;*/
98 head_page = 0xFE;
99
100 phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
101
102 /*Set REG_CR bit 8. DMA beacon by SW.*/
103 u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
104 odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0)));
105
106 /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
107 tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2);
108 odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6)));
109
110 if (tmp_reg422 & BIT(6)) {
111 PHYDM_DBG(dm, DBG_TXBF,
112 "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n");
113 is_send_beacon = true;
114 }
115
116 /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/
117 odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page);
118
119 do {
120 /*@Clear beacon valid check bit.*/
121 bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
122 odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0)));
123
124 /*@download NDPA rsvd page.*/
125 if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
126 beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE);
127 else
128 beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
129
130 /*@check rsvd page download OK.*/
131 bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
132 count = 0;
133 while (!(bcn_valid_reg & BIT(0)) && count < 20) {
134 count++;
135 ODM_delay_ms(10);
136 bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
137 }
138 dl_bcn_count++;
139 } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
140
141 if (!(bcn_valid_reg & BIT(0)))
142 PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
143 __func__);
144
145 /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/
146 odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy);
147
148 /*To make sure that if there exists an adapter which would like to send beacon.*/
149 /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
150 /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
151 /*the beacon cannot be sent by HW.*/
152 /*@2010.06.23. Added by tynli.*/
153 if (is_send_beacon)
154 odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422);
155
156 /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
157 /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
158 u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
159 odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0))));
160
161 p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
162 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
163 *dm->is_fw_dw_rsvd_page_in_progress = false;
164 #endif
165 }
166
hal_txbf_jaguar_fw_txbf_cmd(void * dm_void)167 void hal_txbf_jaguar_fw_txbf_cmd(
168 void *dm_void)
169 {
170 struct dm_struct *dm = (struct dm_struct *)dm_void;
171 u8 idx, period0 = 0, period1 = 0;
172 u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
173 u8 u1_tx_bf_parm[3] = {0};
174 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
175
176 for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
177 /*@Modified by David*/
178 if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
179 if (idx == 0) {
180 if (beam_info->beamformee_entry[idx].is_sound)
181 PageNum0 = 0xFE;
182 else
183 PageNum0 = 0xFF; /*stop sounding*/
184 period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
185 } else if (idx == 1) {
186 if (beam_info->beamformee_entry[idx].is_sound)
187 PageNum1 = 0xFE;
188 else
189 PageNum1 = 0xFF; /*stop sounding*/
190 period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
191 }
192 }
193 }
194
195 u1_tx_bf_parm[0] = PageNum0;
196 u1_tx_bf_parm[1] = PageNum1;
197 u1_tx_bf_parm[2] = (period1 << 4) | period0;
198 odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
199
200 PHYDM_DBG(dm, DBG_TXBF,
201 "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
202 __func__, PageNum0, period0, PageNum1, period1);
203 }
204
hal_txbf_jaguar_enter(void * dm_void,u8 bfer_bfee_idx)205 void hal_txbf_jaguar_enter(
206 void *dm_void,
207 u8 bfer_bfee_idx)
208 {
209 struct dm_struct *dm = (struct dm_struct *)dm_void;
210 u8 i = 0;
211 u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
212 u8 bfee_idx = (bfer_bfee_idx & 0xF);
213 u32 csi_param;
214 struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
215 struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
216 struct _RT_BEAMFORMER_ENTRY beamformer_entry;
217 u16 sta_id = 0;
218
219 PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__);
220
221 hal_txbf_jaguar_rf_mode(dm, beamforming_info);
222
223 if (dm->rf_type == RF_2T2R)
224 odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/
225 else
226 odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/
227
228 if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
229 beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
230
231 /*Sounding protocol control*/
232 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
233
234 /*@MAC address/Partial AID of Beamformer*/
235 if (bfer_idx == 0) {
236 for (i = 0; i < 6; i++)
237 odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]);
238 /*@CSI report use legacy ofdm so don't need to fill P_AID. */
239 /*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */
240 } else {
241 for (i = 0; i < 6; i++)
242 odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]);
243 /*@CSI report use legacy ofdm so don't need to fill P_AID.*/
244 /*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/
245 }
246
247 /*@CSI report parameters of Beamformee*/
248 if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) {
249 if (dm->rf_type == RF_2T2R)
250 csi_param = 0x01090109;
251 else
252 csi_param = 0x01080108;
253 } else {
254 if (dm->rf_type == RF_2T2R)
255 csi_param = 0x03090309;
256 else
257 csi_param = 0x03080308;
258 }
259
260 odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param);
261 odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param);
262 odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param);
263
264 /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
265 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
266 }
267
268 if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
269 beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
270
271 if (phydm_acting_determine(dm, phydm_acting_as_ibss))
272 sta_id = beamformee_entry.mac_id;
273 else
274 sta_id = beamformee_entry.p_aid;
275
276 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
277 if (bfee_idx == 0) {
278 odm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id);
279 odm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7));
280 } else
281 odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
282
283 /*@CSI report parameters of Beamformee*/
284 if (bfee_idx == 0) {
285 /*@Get BIT24 & BIT25*/
286 u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3;
287
288 odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
289 odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9));
290 } else {
291 /*Set BIT25*/
292 odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200);
293 }
294 phydm_beamforming_notify(dm);
295 }
296 }
297
hal_txbf_jaguar_leave(void * dm_void,u8 idx)298 void hal_txbf_jaguar_leave(
299 void *dm_void,
300 u8 idx)
301 {
302 struct dm_struct *dm = (struct dm_struct *)dm_void;
303 struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
304 struct _RT_BEAMFORMER_ENTRY beamformer_entry;
305 struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
306
307 if (idx < BEAMFORMER_ENTRY_NUM) {
308 beamformer_entry = beamforming_info->beamformer_entry[idx];
309 beamformee_entry = beamforming_info->beamformee_entry[idx];
310 } else
311 return;
312
313 PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx);
314
315 /*@Clear P_AID of Beamformee*/
316 /*@Clear MAC address of Beamformer*/
317 /*@Clear Associated Bfmee Sel*/
318
319 if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
320 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
321 if (idx == 0) {
322 odm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0);
323 odm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0);
324 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
325 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
326 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
327 } else {
328 odm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0);
329 odm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0);
330 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
331 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
332 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
333 }
334 }
335
336 if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
337 hal_txbf_jaguar_rf_mode(dm, beamforming_info);
338 if (idx == 0) {
339 odm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0);
340 odm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0);
341 } else {
342 odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000);
343 odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60);
344 }
345 }
346 }
347
hal_txbf_jaguar_status(void * dm_void,u8 idx)348 void hal_txbf_jaguar_status(
349 void *dm_void,
350 u8 idx)
351 {
352 struct dm_struct *dm = (struct dm_struct *)dm_void;
353 u16 beam_ctrl_val;
354 u32 beam_ctrl_reg;
355 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
356 struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
357
358 if (phydm_acting_determine(dm, phydm_acting_as_ibss))
359 beam_ctrl_val = beamform_entry.mac_id;
360 else
361 beam_ctrl_val = beamform_entry.p_aid;
362
363 if (idx == 0)
364 beam_ctrl_reg = REG_TXBF_CTRL_8812A;
365 else {
366 beam_ctrl_reg = REG_TXBF_CTRL_8812A + 2;
367 beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
368 }
369
370 if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
371 if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
372 beam_ctrl_val |= BIT(9);
373 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
374 beam_ctrl_val |= (BIT(9) | BIT(10));
375 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
376 beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
377 } else
378 beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
379
380 PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__,
381 beam_ctrl_val);
382
383 odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
384 }
385
hal_txbf_jaguar_fw_txbf(void * dm_void,u8 idx)386 void hal_txbf_jaguar_fw_txbf(
387 void *dm_void,
388 u8 idx)
389 {
390 struct dm_struct *dm = (struct dm_struct *)dm_void;
391 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
392 struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
393
394 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
395
396 if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
397 hal_txbf_jaguar_download_ndpa(dm, idx);
398
399 hal_txbf_jaguar_fw_txbf_cmd(dm);
400 }
401
hal_txbf_jaguar_patch(void * dm_void,u8 operation)402 void hal_txbf_jaguar_patch(
403 void *dm_void,
404 u8 operation)
405 {
406 struct dm_struct *dm = (struct dm_struct *)dm_void;
407 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
408
409 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
410
411 if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
412 return;
413 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
414 if (operation == SCAN_OPT_BACKUP_BAND0)
415 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
416 else if (operation == SCAN_OPT_RESTORE)
417 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
418 #endif
419 }
420
hal_txbf_jaguar_clk_8812a(void * dm_void)421 void hal_txbf_jaguar_clk_8812a(
422 void *dm_void)
423 {
424 struct dm_struct *dm = (struct dm_struct *)dm_void;
425 u16 u2btmp;
426 u8 count = 0, u1btmp;
427 void *adapter = dm->adapter;
428
429 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
430
431 if (*dm->is_scan_in_process) {
432 PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__);
433 return;
434 }
435 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
436 /*Stop PCIe TxDMA*/
437 if (dm->support_interface == ODM_ITRF_PCIE)
438 odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
439 #endif
440
441 /*Stop Usb TxDMA*/
442 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
443 RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
444 PlatformReturnAllPendingTxPackets(adapter);
445 #else
446 rtw_write_port_cancel(adapter);
447 #endif
448
449 /*Wait TXFF empty*/
450 for (count = 0; count < 100; count++) {
451 u2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A);
452 u2btmp = u2btmp & 0xfff;
453 if (u2btmp != 0xfff) {
454 ODM_delay_ms(10);
455 continue;
456 } else
457 break;
458 }
459
460 /*TX pause*/
461 odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF);
462
463 /*Wait TX state Machine OK*/
464 for (count = 0; count < 100; count++) {
465 if (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0)
466 continue;
467 else
468 break;
469 }
470
471 /*Stop RX DMA path*/
472 u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
473 odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2));
474
475 for (count = 0; count < 100; count++) {
476 u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
477 if (u1btmp & BIT(1))
478 break;
479 else
480 ODM_delay_ms(10);
481 }
482
483 /*@Disable clock*/
484 odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0);
485 /*@Disable 320M*/
486 odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
487 /*@Enable 320M*/
488 odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
489 /*@Enable clock*/
490 odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc);
491
492 /*Release Tx pause*/
493 odm_write_1byte(dm, REG_TXPAUSE_8812A, 0);
494
495 /*@Enable RX DMA path*/
496 u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
497 odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2)));
498 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
499 /*@Enable PCIe TxDMA*/
500 if (dm->support_interface == ODM_ITRF_PCIE)
501 odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0);
502 #endif
503 /*Start Usb TxDMA*/
504 RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
505 }
506
507 #endif
508
509 #endif
510