1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_COMPILE_MU
phydm_get_gid(struct dm_struct * dm,u8 * phy_status_inf)34 u8 phydm_get_gid(struct dm_struct *dm, u8 *phy_status_inf)
35 {
36 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
37 struct phy_sts_rpt_jgr2_type1 *rpt_jgr2 = NULL;
38 #endif
39 #ifdef PHYSTS_3RD_TYPE_SUPPORT
40 struct phy_sts_rpt_jgr3_type1 *rpt_jgr3 = NULL;
41 #endif
42 u8 gid = 0;
43
44 if (dm->ic_phy_sts_type == PHYDM_PHYSTS_TYPE_1)
45 return 0;
46
47 if ((*phy_status_inf & 0xf) != 1)
48 return 0;
49
50 switch (dm->ic_phy_sts_type) {
51 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
52 case PHYDM_PHYSTS_TYPE_2:
53 rpt_jgr2 = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
54 gid = rpt_jgr2->gid;
55 break;
56 #endif
57 #ifdef PHYSTS_3RD_TYPE_SUPPORT
58 case PHYDM_PHYSTS_TYPE_3:
59 rpt_jgr3 = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
60 gid = rpt_jgr3->gid;
61 break;
62 #endif
63 default:
64 break;
65 }
66
67 return gid;
68 }
69 #endif
70
phydm_rx_statistic_cal(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo)71 void phydm_rx_statistic_cal(struct dm_struct *dm,
72 struct phydm_phyinfo_struct *phy_info,
73 u8 *phy_status_inf,
74 struct phydm_perpkt_info_struct *pktinfo)
75 {
76 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
77
78 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
79 struct phydm_bf_rate_info_jgr3 *bfrateinfo = &dm->bf_rate_info_jgr3;
80 #endif
81
82 u8 rate = (pktinfo->data_rate & 0x7f);
83 u8 bw_idx = phy_info->band_width;
84 u8 offset = 0;
85 u8 gid = 0;
86 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
87 u8 val = 0;
88 #endif
89 #ifdef PHYDM_COMPILE_MU
90 u8 is_mu_pkt = 0;
91 #endif
92
93 if (rate <= ODM_RATE54M) {
94 dbg_i->num_qry_legacy_pkt[rate]++;
95 } else if (rate <= ODM_RATEMCS31) {
96 dbg_i->ht_pkt_not_zero = true;
97 offset = rate - ODM_RATEMCS0;
98
99 if (offset > (HT_RATE_NUM - 1))
100 offset = HT_RATE_NUM - 1;
101
102 if (dm->support_ic_type &
103 (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
104 if (bw_idx == *dm->band_width) {
105 dbg_i->num_qry_ht_pkt[offset]++;
106
107 } else if (bw_idx == CHANNEL_WIDTH_20) {
108 dbg_i->num_qry_pkt_sc_20m[offset]++;
109 dbg_i->low_bw_20_occur = true;
110 }
111 } else {
112 dbg_i->num_qry_ht_pkt[offset]++;
113 }
114 }
115 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
116 else if (rate <= ODM_RATEVHTSS4MCS9) {
117 offset = rate - ODM_RATEVHTSS1MCS0;
118
119 if (offset > (VHT_RATE_NUM - 1))
120 offset = VHT_RATE_NUM - 1;
121
122 #ifdef PHYDM_COMPILE_MU
123 gid = phydm_get_gid(dm, phy_status_inf);
124
125 if (gid != 0 && gid != 63)
126 is_mu_pkt = true;
127
128 if (is_mu_pkt) {
129 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
130 (defined(PHYSTS_3RD_TYPE_SUPPORT)))
131 dbg_i->num_mu_vht_pkt[offset]++;
132 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
133 bfrateinfo->num_mu_vht_pkt[offset]++;
134 #endif
135 #else
136 dbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/
137 #endif
138 } else
139 #endif
140 {
141 dbg_i->vht_pkt_not_zero = true;
142
143 if (dm->support_ic_type &
144 (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
145 if (bw_idx == *dm->band_width) {
146 dbg_i->num_qry_vht_pkt[offset]++;
147 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
148 bfrateinfo->num_qry_vht_pkt[offset]++;
149 #endif
150
151 } else if (bw_idx == CHANNEL_WIDTH_20) {
152 dbg_i->num_qry_pkt_sc_20m[offset]++;
153 dbg_i->low_bw_20_occur = true;
154 } else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/
155 dbg_i->num_qry_pkt_sc_40m[offset]++;
156 dbg_i->low_bw_40_occur = true;
157 }
158 } else {
159 dbg_i->num_qry_vht_pkt[offset]++;
160 }
161 }
162
163 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
164 (defined(PHYSTS_3RD_TYPE_SUPPORT)))
165 if (pktinfo->ppdu_cnt < 4) {
166 val = rate;
167
168 #ifdef PHYDM_COMPILE_MU
169 if (is_mu_pkt)
170 val |= BIT(7);
171 #endif
172
173 dbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val;
174 dbg_i->gid_num[pktinfo->ppdu_cnt] = gid;
175 }
176 #endif
177 }
178 #endif
179 }
180
phydm_reset_phystatus_avg(struct dm_struct * dm)181 void phydm_reset_phystatus_avg(struct dm_struct *dm)
182 {
183 struct phydm_phystatus_avg *dbg_avg = NULL;
184
185 dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg;
186 odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0,
187 sizeof(struct phydm_phystatus_avg));
188 }
189
phydm_reset_phystatus_statistic(struct dm_struct * dm)190 void phydm_reset_phystatus_statistic(struct dm_struct *dm)
191 {
192 struct phydm_phystatus_statistic *dbg_s = NULL;
193
194 dbg_s = &dm->phy_dbg_info.physts_statistic_info;
195
196 odm_memory_set(dm, &dbg_s->rssi_cck_sum, 0,
197 sizeof(struct phydm_phystatus_statistic));
198 }
199
phydm_reset_phy_info(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info)200 void phydm_reset_phy_info(struct dm_struct *dm,
201 struct phydm_phyinfo_struct *phy_info)
202 {
203 u8 i = 0;
204
205 odm_memory_set(dm, &phy_info->physts_rpt_valid, 0,
206 sizeof(struct phydm_phyinfo_struct));
207
208 phy_info->rx_power = -110;
209 phy_info->recv_signal_power = -110;
210
211 for (i = 0; i < dm->num_rf_path; i++)
212 phy_info->rx_pwr[i] = -110;
213 }
214
phydm_avg_rssi_evm_snr(void * dm_void,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)215 void phydm_avg_rssi_evm_snr(void *dm_void,
216 struct phydm_phyinfo_struct *phy_info,
217 struct phydm_perpkt_info_struct *pktinfo)
218 {
219 struct dm_struct *dm = (struct dm_struct *)dm_void;
220 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
221 struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
222 u8 *rssi = phy_info->rx_mimo_signal_strength;
223 u8 *evm = phy_info->rx_mimo_evm_dbm;
224 s8 *snr = phy_info->rx_snr;
225 u32 size = PHYSTS_PATH_NUM; /*size of path=4*/
226 u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
227 u16 val = 0, intvl = 0;
228 u8 i = 0;
229
230 if (pktinfo->is_packet_beacon) {
231 for (i = 0; i < dm->num_rf_path; i++)
232 dbg_s->rssi_beacon_sum[i] += rssi[i];
233
234 dbg_s->rssi_beacon_cnt++;
235 }
236
237 if (pktinfo->data_rate <= ODM_RATE11M) {
238 /*RSSI*/
239 dbg_s->rssi_cck_sum += rssi[0];
240 #ifdef PHYSTS_3RD_TYPE_SUPPORT
241 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
242 for (i = 1; i < dm->num_rf_path; i++)
243 dbg_s->rssi_cck_sum_abv_2ss[i - 1] += rssi[i];
244 }
245 #endif
246 dbg_s->rssi_cck_cnt++;
247 } else if (pktinfo->data_rate <= ODM_RATE54M) {
248 for (i = 0; i < dm->num_rf_path; i++) {
249 /*SNR & RSSI*/
250 dbg_s->snr_ofdm_sum[i] += snr[i];
251 dbg_s->rssi_ofdm_sum[i] += rssi[i];
252 }
253 /*@evm*/
254 dbg_s->evm_ofdm_sum += evm[0];
255 dbg_s->rssi_ofdm_cnt++;
256
257 val = (u16)evm[0];
258 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
259 dbg_s->evm_ofdm_hist[intvl]++;
260
261 val = (u16)snr[0];
262 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
263 dbg_s->snr_ofdm_hist[intvl]++;
264
265 } else if (pktinfo->rate_ss == 1) {
266 /*@===[1-SS]==================================================================*/
267 for (i = 0; i < dm->num_rf_path; i++) {
268 /*SNR & RSSI*/
269 dbg_s->snr_1ss_sum[i] += snr[i];
270 dbg_s->rssi_1ss_sum[i] += rssi[i];
271 }
272
273 /*@evm*/
274 dbg_s->evm_1ss_sum += evm[0];
275 /*@EVM Histogram*/
276 val = (u16)evm[0];
277 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
278 dbg_s->evm_1ss_hist[intvl]++;
279
280 /*SNR Histogram*/
281 val = (u16)snr[0];
282 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
283 dbg_s->snr_1ss_hist[intvl]++;
284
285 dbg_s->rssi_1ss_cnt++;
286 } else if (pktinfo->rate_ss == 2) {
287 /*@===[2-SS]==================================================================*/
288 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
289 for (i = 0; i < dm->num_rf_path; i++) {
290 /*SNR & RSSI*/
291 dbg_s->snr_2ss_sum[i] += snr[i];
292 dbg_s->rssi_2ss_sum[i] += rssi[i];
293 }
294
295 for (i = 0; i < pktinfo->rate_ss; i++) {
296 /*@evm*/
297 dbg_s->evm_2ss_sum[i] += evm[i];
298 /*@EVM Histogram*/
299 val = (u16)evm[i];
300 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
301 size_th);
302 dbg_s->evm_2ss_hist[i][intvl]++;
303
304 /*SNR Histogram*/
305 val = (u16)snr[i];
306 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
307 size_th);
308 dbg_s->snr_2ss_hist[i][intvl]++;
309 }
310 dbg_s->rssi_2ss_cnt++;
311 #endif
312 } else if (pktinfo->rate_ss == 3) {
313 /*@===[3-SS]==================================================================*/
314 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
315 for (i = 0; i < dm->num_rf_path; i++) {
316 /*SNR & RSSI*/
317 dbg_s->snr_3ss_sum[i] += snr[i];
318 dbg_s->rssi_3ss_sum[i] += rssi[i];
319 }
320
321 for (i = 0; i < pktinfo->rate_ss; i++) {
322 /*@evm*/
323 dbg_s->evm_3ss_sum[i] += evm[i];
324 /*@EVM Histogram*/
325 val = (u16)evm[i];
326 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
327 size_th);
328 dbg_s->evm_3ss_hist[i][intvl]++;
329
330 /*SNR Histogram*/
331 val = (u16)snr[i];
332 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
333 size_th);
334 dbg_s->snr_3ss_hist[i][intvl]++;
335 }
336 dbg_s->rssi_3ss_cnt++;
337 #endif
338 } else if (pktinfo->rate_ss == 4) {
339 /*@===[4-SS]==================================================================*/
340 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
341 for (i = 0; i < dm->num_rf_path; i++) {
342 /*SNR & RSSI*/
343 dbg_s->snr_4ss_sum[i] += snr[i];
344 dbg_s->rssi_4ss_sum[i] += rssi[i];
345 }
346
347 for (i = 0; i < pktinfo->rate_ss; i++) {
348 /*@evm*/
349 dbg_s->evm_4ss_sum[i] += evm[i];
350
351 /*@EVM Histogram*/
352 val = (u16)evm[i];
353 intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
354 size_th);
355 dbg_s->evm_4ss_hist[i][intvl]++;
356
357 /*SNR Histogram*/
358 val = (u16)snr[i];
359 intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
360 size_th);
361 dbg_s->snr_4ss_hist[i][intvl]++;
362 }
363 dbg_s->rssi_4ss_cnt++;
364 #endif
365 }
366 }
367
phydm_avg_phystatus_init(void * dm_void)368 void phydm_avg_phystatus_init(void *dm_void)
369 {
370 struct dm_struct *dm = (struct dm_struct *)dm_void;
371 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
372 u16 snr_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
373 29, 32, 35};
374 u16 evm_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
375 29, 32, 35};
376 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
377 u16 cn_hist_th[PHY_HIST_TH_SIZE] = {2, 3, 4, 5, 6, 8, 10,
378 12, 14, 16, 18};
379 #endif
380 u32 size = PHY_HIST_TH_SIZE * 2;
381 u8 i = 0;
382
383 odm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size);
384 odm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size);
385 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
386 dm->pkt_proc_struct.physts_auto_swch_en = false;
387 for (i = 0; i < PHY_HIST_TH_SIZE; i++)
388 dbg_i->cn_hist_th[i] = cn_hist_th[i] << 1;
389 #endif
390 }
391
phydm_get_signal_quality(struct phydm_phyinfo_struct * phy_info,struct dm_struct * dm,struct phy_status_rpt_8192cd * phy_sts)392 u8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info,
393 struct dm_struct *dm,
394 struct phy_status_rpt_8192cd *phy_sts)
395 {
396 u8 sq_rpt;
397 u8 result = 0;
398
399 if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) {
400 result = 100;
401 } else {
402 sq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all;
403
404 if (sq_rpt > 64)
405 result = 0;
406 else if (sq_rpt < 20)
407 result = 100;
408 else
409 result = ((64 - sq_rpt) * 100) / 44;
410 }
411
412 return result;
413 }
414
phydm_pw_2_percent(s8 ant_power)415 u8 phydm_pw_2_percent(s8 ant_power)
416 {
417 if ((ant_power <= -100) || ant_power >= 20)
418 return 0;
419 else if (ant_power >= 0)
420 return 100;
421 else
422 return 100 + ant_power;
423 }
424
425 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
phydm_process_signal_strength(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)426 void phydm_process_signal_strength(struct dm_struct *dm,
427 struct phydm_phyinfo_struct *phy_info,
428 struct phydm_perpkt_info_struct *pktinfo)
429 {
430 boolean is_cck_rate = 0;
431 u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0;
432 u8 ss = 0; /*signal strenth after scale mapping*/
433 u8 pwdb = phy_info->rx_pwdb_all;
434 u8 i;
435
436 is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
437
438 /*use the best two RSSI only*/
439 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
440 tmp_rssi = phy_info->rx_mimo_signal_strength[i];
441
442 /*@Get the best two RSSI*/
443 if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) {
444 second_rssi = best_rssi;
445 best_rssi = tmp_rssi;
446 } else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) {
447 second_rssi = tmp_rssi;
448 }
449 }
450
451 if (best_rssi == 0)
452 return;
453
454 if (pktinfo->rate_ss == 1)
455 avg_rssi = best_rssi;
456 else
457 avg_rssi = (best_rssi + second_rssi) >> 1;
458
459 /* Update signal strength to UI,
460 * and phy_info->rx_pwdb_all is the maximum RSSI of all path
461 */
462 if (dm->support_ic_type & (PHYSTS_3RD_TYPE_IC | PHYSTS_2ND_TYPE_IC))
463 ss = SignalScaleProc(dm->adapter, pwdb, false, false);
464 else
465 ss = SignalScaleProc(dm->adapter, pwdb, true, is_cck_rate);
466
467 phy_info->signal_strength = ss;
468 }
469
phydm_sq_patch_lenovo(struct dm_struct * dm,u8 is_cck_rate,u8 pwdb_all,u8 path,u8 RSSI)470 static u8 phydm_sq_patch_lenovo(
471 struct dm_struct *dm,
472 u8 is_cck_rate,
473 u8 pwdb_all,
474 u8 path,
475 u8 RSSI)
476 {
477 u8 sq = 0;
478
479 if (is_cck_rate) {
480 if (dm->support_ic_type & ODM_RTL8192E) {
481 /*@
482 * <Roger_Notes>
483 * Expected signal strength and bars indication at Lenovo lab. 2013.04.11
484 * 802.11n, 802.11b, 802.11g only at channel 6
485 *
486 * Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm)
487 * 50 5 -49
488 * 55 5 -49
489 * 60 5 -50
490 * 65 5 -51
491 * 70 5 -52
492 * 75 5 -54
493 * 80 5 -55
494 * 85 4 -60
495 * 90 3 -63
496 * 95 3 -65
497 * 100 2 -67
498 * 102 2 -67
499 * 104 1 -70
500 */
501 if (pwdb_all >= 50)
502 sq = 100;
503 else if (pwdb_all >= 35 && pwdb_all < 50)
504 sq = 80;
505 else if (pwdb_all >= 31 && pwdb_all < 35)
506 sq = 60;
507 else if (pwdb_all >= 22 && pwdb_all < 31)
508 sq = 40;
509 else if (pwdb_all >= 18 && pwdb_all < 22)
510 sq = 20;
511 else
512 sq = 10;
513 } else {
514 if (pwdb_all >= 50)
515 sq = 100;
516 else if (pwdb_all >= 35 && pwdb_all < 50)
517 sq = 80;
518 else if (pwdb_all >= 22 && pwdb_all < 35)
519 sq = 60;
520 else if (pwdb_all >= 18 && pwdb_all < 22)
521 sq = 40;
522 else
523 sq = 10;
524 }
525
526 } else {
527 /* OFDM rate */
528
529 if (dm->support_ic_type & ODM_RTL8192E) {
530 if (RSSI >= 45)
531 sq = 100;
532 else if (RSSI >= 22 && RSSI < 45)
533 sq = 80;
534 else if (RSSI >= 18 && RSSI < 22)
535 sq = 40;
536 else
537 sq = 20;
538 } else {
539 if (RSSI >= 45)
540 sq = 100;
541 else if (RSSI >= 22 && RSSI < 45)
542 sq = 80;
543 else if (RSSI >= 18 && RSSI < 22)
544 sq = 40;
545 else
546 sq = 20;
547 }
548 }
549 return sq;
550 }
551
phydm_sq_patch_rt_cid_819x_acer(struct dm_struct * dm,u8 is_cck_rate,u8 pwdb_all,u8 path,u8 RSSI)552 static u8 phydm_sq_patch_rt_cid_819x_acer(
553 struct dm_struct *dm,
554 u8 is_cck_rate,
555 u8 pwdb_all,
556 u8 path,
557 u8 RSSI)
558 {
559 u8 sq = 0;
560
561 if (is_cck_rate) {
562 #if OS_WIN_FROM_WIN8(OS_VERSION)
563 if (pwdb_all >= 50)
564 sq = 100;
565 else if (pwdb_all >= 35 && pwdb_all < 50)
566 sq = 80;
567 else if (pwdb_all >= 30 && pwdb_all < 35)
568 sq = 60;
569 else if (pwdb_all >= 25 && pwdb_all < 30)
570 sq = 40;
571 else if (pwdb_all >= 20 && pwdb_all < 25)
572 sq = 20;
573 else
574 sq = 10;
575 #else
576 if (pwdb_all >= 50)
577 sq = 100;
578 else if (pwdb_all >= 35 && pwdb_all < 50)
579 sq = 80;
580 else if (pwdb_all >= 30 && pwdb_all < 35)
581 sq = 60;
582 else if (pwdb_all >= 25 && pwdb_all < 30)
583 sq = 40;
584 else if (pwdb_all >= 20 && pwdb_all < 25)
585 sq = 20;
586 else
587 sq = 10;
588
589 /* @Abnormal case, do not indicate the value above 20 on Win7 */
590 if (pwdb_all == 0)
591 sq = 20;
592 #endif
593
594 } else {
595 /* OFDM rate */
596 if (dm->support_ic_type & ODM_RTL8192E) {
597 if (RSSI >= 45)
598 sq = 100;
599 else if (RSSI >= 22 && RSSI < 45)
600 sq = 80;
601 else if (RSSI >= 18 && RSSI < 22)
602 sq = 40;
603 else
604 sq = 20;
605 } else {
606 if (RSSI >= 35)
607 sq = 100;
608 else if (RSSI >= 30 && RSSI < 35)
609 sq = 80;
610 else if (RSSI >= 25 && RSSI < 30)
611 sq = 40;
612 else
613 sq = 20;
614 }
615 }
616 return sq;
617 }
618 #endif
619
620 static u8
phydm_evm_2_percent(s8 value)621 phydm_evm_2_percent(s8 value)
622 {
623 /* @-33dB~0dB to 0%~99% */
624 s8 ret_val;
625
626 ret_val = value;
627 ret_val /= 2;
628
629 /*@dbg_print("value=%d\n", value);*/
630 #ifdef ODM_EVM_ENHANCE_ANTDIV
631 if (ret_val >= 0)
632 ret_val = 0;
633
634 if (ret_val <= -40)
635 ret_val = -40;
636
637 ret_val = 0 - ret_val;
638 ret_val *= 3;
639 #else
640 if (ret_val >= 0)
641 ret_val = 0;
642
643 if (ret_val <= -33)
644 ret_val = -33;
645
646 ret_val = 0 - ret_val;
647 ret_val *= 3;
648
649 if (ret_val == 99)
650 ret_val = 100;
651 #endif
652
653 return (u8)ret_val;
654 }
655
phydm_cck_rssi_convert(struct dm_struct * dm,u16 lna_idx,u8 vga_idx)656 s8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
657 {
658 /*@phydm_get_cck_rssi_table_from_reg*/
659 return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1));
660 }
661
phydm_get_cck_rssi_table_from_reg(struct dm_struct * dm)662 void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm)
663 {
664 u8 used_lna_idx_tmp;
665 u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd;
666 u32 val = 0;
667 u8 i;
668
669 /*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/
670 /*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/
671
672 PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n");
673
674 if (!(dm->support_ic_type & ODM_RTL8197F))
675 return;
676
677 reg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF);
678 reg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD);
679
680 PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80);
681 PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc);
682
683 for (i = 0; i <= 3; i++) {
684 used_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7);
685 val = (reg_0xabc >> (8 * i)) & 0xff;
686 dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val;
687 }
688
689 PHYDM_DBG(dm, ODM_COMP_INIT,
690 "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n",
691 dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1],
692 dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3],
693 dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5],
694 dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]);
695 }
696
phydm_get_cck_rssi(void * dm_void,u8 lna_idx,u8 vga_idx)697 s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx)
698 {
699 struct dm_struct *dm = (struct dm_struct *)dm_void;
700 s8 rx_pow = 0;
701
702 switch (dm->support_ic_type) {
703 #if (RTL8197F_SUPPORT)
704 case ODM_RTL8197F:
705 rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx);
706 break;
707 #endif
708
709 #if (RTL8723D_SUPPORT)
710 case ODM_RTL8723D:
711 rx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx);
712 break;
713 #endif
714
715 #if (RTL8710B_SUPPORT)
716 case ODM_RTL8710B:
717 rx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx);
718 break;
719 #endif
720
721 #if (RTL8721D_SUPPORT)
722 case ODM_RTL8721D:
723 rx_pow = phydm_cckrssi_8721d(dm, lna_idx, vga_idx);
724 break;
725 #endif
726
727 #if (RTL8710C_SUPPORT)
728 case ODM_RTL8710C:
729 rx_pow = phydm_cckrssi_8710c(dm, lna_idx, vga_idx);
730 break;
731 #endif
732
733 #if (RTL8192F_SUPPORT)
734 case ODM_RTL8192F:
735 rx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx);
736 break;
737 #endif
738
739 #if (RTL8821C_SUPPORT)
740 case ODM_RTL8821C:
741 rx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx);
742 break;
743 #endif
744
745 #if (RTL8195B_SUPPORT)
746 case ODM_RTL8195B:
747 rx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx);
748 break;
749 #endif
750
751 #if (RTL8188E_SUPPORT)
752 case ODM_RTL8188E:
753 rx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx);
754 break;
755 #endif
756
757 #if (RTL8192E_SUPPORT)
758 case ODM_RTL8192E:
759 rx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx);
760 break;
761 #endif
762
763 #if (RTL8723B_SUPPORT)
764 case ODM_RTL8723B:
765 rx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx);
766 break;
767 #endif
768
769 #if (RTL8703B_SUPPORT)
770 case ODM_RTL8703B:
771 rx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx);
772 break;
773 #endif
774
775 #if (RTL8188F_SUPPORT)
776 case ODM_RTL8188F:
777 rx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx);
778 break;
779 #endif
780
781 #if (RTL8195A_SUPPORT)
782 case ODM_RTL8195A:
783 rx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx);
784 break;
785 #endif
786
787 #if (RTL8812A_SUPPORT)
788 case ODM_RTL8812:
789 rx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx);
790 break;
791 #endif
792
793 #if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
794 case ODM_RTL8821:
795 case ODM_RTL8881A:
796 rx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx);
797 break;
798 #endif
799
800 #if (RTL8814A_SUPPORT)
801 case ODM_RTL8814A:
802 rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx);
803 break;
804 #endif
805
806 default:
807 break;
808 }
809
810 return rx_pow;
811 }
812
813 #if (ODM_IC_11N_SERIES_SUPPORT)
phydm_phy_sts_n_parsing(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo)814 void phydm_phy_sts_n_parsing(struct dm_struct *dm,
815 struct phydm_phyinfo_struct *phy_info,
816 u8 *phy_status_inf,
817 struct phydm_perpkt_info_struct *pktinfo)
818 {
819 u8 i = 0;
820 s8 rx_pwr[4], rx_pwr_all = 0;
821 u8 EVM, pwdb_all = 0, pwdb_all_bt = 0;
822 u8 RSSI, total_rssi = 0;
823 u8 rf_rx_num = 0;
824 u8 lna_idx = 0;
825 u8 vga_idx = 0;
826 u8 cck_agc_rpt;
827 s8 evm_tmp = 0;
828 u8 sq = 0;
829 u8 val_tmp = 0;
830 s8 val_s8 = 0;
831 struct phy_status_rpt_8192cd *phy_sts = NULL;
832
833 phy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf;
834
835 if (pktinfo->is_cck_rate) {
836 cck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a;
837
838 /*@3 bit LNA*/
839 lna_idx = ((cck_agc_rpt & 0xE0) >> 5);
840 vga_idx = (cck_agc_rpt & 0x1F);
841
842 #if (RTL8703B_SUPPORT)
843 if (dm->support_ic_type & (ODM_RTL8703B) &&
844 dm->cck_agc_report_type == 1) {
845 /*@4 bit LNA*/
846 if (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7))
847 val_tmp = 1;
848 else
849 val_tmp = 0;
850 lna_idx = (val_tmp << 3) | lna_idx;
851 }
852 #endif
853
854 rx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
855
856 PHYDM_DBG(dm, DBG_RSSI_MNTR,
857 "ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
858 dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all);
859
860 if (dm->board_type & ODM_BOARD_EXT_LNA)
861 rx_pwr_all -= dm->ext_lna_gain;
862
863 pwdb_all = phydm_pw_2_percent(rx_pwr_all);
864
865 if (pktinfo->is_to_self) {
866 dm->cck_lna_idx = lna_idx;
867 dm->cck_vga_idx = vga_idx;
868 }
869
870 phy_info->rx_pwdb_all = pwdb_all;
871 phy_info->bt_rx_rssi_percentage = pwdb_all;
872 phy_info->recv_signal_power = rx_pwr_all;
873
874 /* @(3) Get Signal Quality (EVM) */
875 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
876 if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)
877 sq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
878 else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
879 sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
880 else
881 #endif
882 sq = phydm_get_signal_quality(phy_info, dm, phy_sts);
883
884 /* @dbg_print("cck sq = %d\n", sq); */
885
886 phy_info->signal_quality = sq;
887 phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq;
888 phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
889
890 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
891 if (i == 0)
892 phy_info->rx_mimo_signal_strength[0] = pwdb_all;
893 else
894 phy_info->rx_mimo_signal_strength[i] = 0;
895 }
896 } else { /* @2 is OFDM rate */
897
898 /* @(1)Get RSSI for HT rate */
899
900 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
901 if (dm->rf_path_rx_enable & BIT(i))
902 rf_rx_num++;
903
904 val_s8 = phy_sts->path_agc[i].gain & 0x3F;
905 rx_pwr[i] = (val_s8 * 2) - 110;
906
907 if (pktinfo->is_to_self)
908 dm->ofdm_agc_idx[i] = val_s8;
909
910 phy_info->rx_pwr[i] = rx_pwr[i];
911 RSSI = phydm_pw_2_percent(rx_pwr[i]);
912 total_rssi += RSSI;
913
914 phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
915
916 /* @Get Rx snr value in DB */
917 val_s8 = (s8)(phy_sts->path_rxsnr[i] / 2);
918 phy_info->rx_snr[i] = val_s8;
919
920 /* Record Signal Strength for next packet */
921
922 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
923 if (i == RF_PATH_A) {
924 if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
925 phy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI);
926 } else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
927 phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI);
928 }
929 #endif
930 }
931
932 /* @(2)PWDB, Average PWDB calculated by hardware (for RA) */
933 val_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1;
934 rx_pwr_all = (val_s8 & 0x7f) - 110;
935
936 pwdb_all = phydm_pw_2_percent(rx_pwr_all);
937 pwdb_all_bt = pwdb_all;
938
939 phy_info->rx_pwdb_all = pwdb_all;
940 phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
941 phy_info->rx_power = rx_pwr_all;
942 phy_info->recv_signal_power = rx_pwr_all;
943
944 /* @(3)EVM of HT rate */
945 for (i = 0; i < pktinfo->rate_ss; i++) {
946 /* @Do not use shift operation like "rx_evmX >>= 1"
947 * because the compilor of free build environment
948 * fill most significant bit to "zero" when doing shifting
949 * operation which may change a negative
950 * value to positive one, then the dbm value
951 * (which is supposed to be negative) is not correct anymore.
952 */
953 EVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]);
954
955 /*@Fill value in RFD, Get the 1st spatial stream only*/
956 if (i == RF_PATH_A)
957 phy_info->signal_quality = (u8)(EVM & 0xff);
958
959 phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);
960
961 if (phy_sts->stream_rxevm[i] < 0)
962 evm_tmp = 0 - phy_sts->stream_rxevm[i];
963
964 if (evm_tmp == 64)
965 evm_tmp = 0;
966
967 phy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp;
968 }
969 phydm_parsing_cfo(dm, pktinfo,
970 phy_sts->path_cfotail, pktinfo->rate_ss);
971 }
972
973 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
974 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel;
975 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b;
976 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2;
977 #endif
978 }
979 #endif
980
981 #if ODM_IC_11AC_SERIES_SUPPORT
982 static s16
phydm_cfo(s8 value)983 phydm_cfo(s8 value)
984 {
985 s16 ret_val;
986
987 if (value < 0) {
988 ret_val = 0 - value;
989 ret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */
990 ret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/
991 } else {
992 ret_val = value;
993 ret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/
994 }
995 return ret_val;
996 }
997
998 static u8
phydm_evm_dbm(s8 value)999 phydm_evm_dbm(s8 value)
1000 {
1001 s8 ret_val = value;
1002
1003 /* @-33dB~0dB to 33dB ~ 0dB */
1004 if (ret_val == -128)
1005 ret_val = 127;
1006 else if (ret_val < 0)
1007 ret_val = 0 - ret_val;
1008
1009 ret_val = ret_val >> 1;
1010 return (u8)ret_val;
1011 }
1012
phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo,struct phy_status_rpt_8812 * phy_sts)1013 void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info,
1014 struct phydm_perpkt_info_struct *
1015 pktinfo,
1016 struct phy_status_rpt_8812 *
1017 phy_sts)
1018 {
1019 if (pktinfo->data_rate > ODM_RATE54M) {
1020 switch (phy_sts->r_RFMOD) {
1021 case 1:
1022 if (phy_sts->sub_chnl == 0)
1023 phy_info->band_width = 1;
1024 else
1025 phy_info->band_width = 0;
1026 break;
1027
1028 case 2:
1029 if (phy_sts->sub_chnl == 0)
1030 phy_info->band_width = 2;
1031 else if (phy_sts->sub_chnl == 9 ||
1032 phy_sts->sub_chnl == 10)
1033 phy_info->band_width = 1;
1034 else
1035 phy_info->band_width = 0;
1036 break;
1037
1038 default:
1039 case 0:
1040 phy_info->band_width = 0;
1041 break;
1042 }
1043 }
1044 }
1045
phydm_get_sq(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 is_cck_rate)1046 void phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info,
1047 u8 is_cck_rate)
1048 {
1049 u8 sq = 0;
1050 u8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/
1051 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1052 u8 rssi = phy_info->rx_mimo_signal_strength[0];
1053 #endif
1054
1055 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1056 if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
1057 if (is_cck_rate)
1058 sq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0);
1059 else
1060 sq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi);
1061 } else
1062 #endif
1063 {
1064 if (is_cck_rate) {
1065 if (pwdb_all > 40 && !dm->is_in_hct_test) {
1066 sq = 100;
1067 } else {
1068 if (pwdb_all > 64)
1069 sq = 0;
1070 else if (pwdb_all < 20)
1071 sq = 100;
1072 else
1073 sq = ((64 - pwdb_all) * 100) / 44;
1074 }
1075 } else {
1076 sq = phy_info->rx_mimo_signal_quality[0];
1077 }
1078 }
1079
1080 #if 0
1081 /* @dbg_print("cck sq = %d\n", sq); */
1082 #endif
1083 phy_info->signal_quality = sq;
1084 }
1085
phydm_rx_physts_1st_type(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo)1086 void phydm_rx_physts_1st_type(struct dm_struct *dm,
1087 struct phydm_phyinfo_struct *phy_info,
1088 u8 *phy_status_inf,
1089 struct phydm_perpkt_info_struct *pktinfo)
1090 {
1091 u8 i = 0;
1092 s8 rx_pwr_db = 0;
1093 u8 val = 0; /*tmp value*/
1094 s8 val_s8 = 0; /*tmp value*/
1095 u8 rssi = 0; /*pre path RSSI*/
1096 u8 rf_rx_num = 0;
1097 u8 lna_idx = 0, vga_idx = 0;
1098 u8 cck_agc_rpt = 0;
1099 struct phy_status_rpt_8812 *phy_sts = NULL;
1100 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1101 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1102 #endif
1103
1104 phy_sts = (struct phy_status_rpt_8812 *)phy_status_inf;
1105 phydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts);
1106
1107 /* @== [CCK rate] ====================================================*/
1108 if (pktinfo->is_cck_rate) {
1109 cck_agc_rpt = phy_sts->cfosho[0];
1110 lna_idx = (cck_agc_rpt & 0xE0) >> 5;
1111 vga_idx = cck_agc_rpt & 0x1F;
1112
1113 rx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
1114 rssi = phydm_pw_2_percent(rx_pwr_db);
1115
1116 if (dm->support_ic_type == ODM_RTL8812 &&
1117 !dm->is_cck_high_power) {
1118 if (rssi >= 80) {
1119 rssi = ((rssi - 80) << 1) +
1120 ((rssi - 80) >> 1) + 80;
1121 } else if ((rssi <= 78) && (rssi >= 20)) {
1122 rssi += 3;
1123 }
1124 }
1125 dm->cck_lna_idx = lna_idx;
1126 dm->cck_vga_idx = vga_idx;
1127
1128 phy_info->rx_pwdb_all = rssi;
1129 phy_info->rx_mimo_signal_strength[0] = rssi;
1130 } else {
1131 /* @== [OFDM rate] ===================================================*/
1132 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
1133 /*@[RSSI]*/
1134 if (dm->rf_path_rx_enable & BIT(i))
1135 rf_rx_num++;
1136
1137 if (i < RF_PATH_C)
1138 val = phy_sts->gain_trsw[i];
1139 else
1140 val = phy_sts->gain_trsw_cd[i - 2];
1141
1142 phy_info->rx_pwr[i] = (val & 0x7F) - 110;
1143 rssi = phydm_pw_2_percent(phy_info->rx_pwr[i]);
1144 phy_info->rx_mimo_signal_strength[i] = rssi;
1145
1146 /*@[SNR]*/
1147 if (i < RF_PATH_C)
1148 val_s8 = phy_sts->rxsnr[i];
1149 else if (dm->support_ic_type & (ODM_RTL8814A))
1150 val_s8 = (s8)phy_sts->csi_current[i - 2];
1151
1152 phy_info->rx_snr[i] = val_s8 >> 1;
1153
1154 /*@[CFO_short & CFO_tail]*/
1155 if (i < RF_PATH_C) {
1156 val_s8 = phy_sts->cfosho[i];
1157 phy_info->cfo_short[i] = phydm_cfo(val_s8);
1158 val_s8 = phy_sts->cfotail[i];
1159 phy_info->cfo_tail[i] = phydm_cfo(val_s8);
1160 }
1161
1162 if (i < RF_PATH_C && pktinfo->is_to_self)
1163 dm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i];
1164 }
1165
1166 /* @== [PWDB] ========================================================*/
1167
1168 /*@(Avg PWDB calculated by hardware*/
1169 if (!dm->is_mp_chip) /*@8812, 8821*/
1170 val = phy_sts->pwdb_all;
1171 else
1172 val = phy_sts->pwdb_all >> 1; /*old fomula*/
1173
1174 rx_pwr_db = (val & 0x7f) - 110;
1175 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db);
1176
1177 /*@(4)EVM of OFDM rate*/
1178 for (i = 0; i < pktinfo->rate_ss; i++) {
1179 if (!pktinfo->is_cck_rate &&
1180 pktinfo->data_rate <= ODM_RATE54M) {
1181 val_s8 = phy_sts->sigevm;
1182 } else if (i < RF_PATH_C) {
1183 if (phy_sts->rxevm[i] == -128)
1184 phy_sts->rxevm[i] = -25;
1185
1186 val_s8 = phy_sts->rxevm[i];
1187 } else {
1188 if (phy_sts->rxevm_cd[i - 2] == -128)
1189 phy_sts->rxevm_cd[i - 2] = -25;
1190
1191 val_s8 = phy_sts->rxevm_cd[i - 2];
1192 }
1193 /*@[EVM to 0~100%]*/
1194 val = phydm_evm_2_percent(val_s8);
1195 phy_info->rx_mimo_signal_quality[i] = val;
1196 /*@[EVM dBm]*/
1197 phy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8);
1198 }
1199 phydm_parsing_cfo(dm, pktinfo,
1200 phy_sts->cfotail, pktinfo->rate_ss);
1201 }
1202
1203 /* @== [General Info] ================================================*/
1204
1205 phy_info->rx_power = rx_pwr_db;
1206 phy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all;
1207 phy_info->recv_signal_power = phy_info->rx_power;
1208 phydm_get_sq(dm, phy_info, pktinfo->is_cck_rate);
1209
1210 dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;
1211
1212 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1213 fat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur;
1214 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta;
1215 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb;
1216 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc;
1217 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd;
1218 #endif
1219 }
1220
1221 #endif
1222
phydm_reset_rssi_for_dm(struct dm_struct * dm,u8 station_id)1223 void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id)
1224 {
1225 struct cmn_sta_info *sta;
1226
1227 sta = dm->phydm_sta_info[station_id];
1228
1229 if (!is_sta_active(sta))
1230 return;
1231 PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n",
1232 station_id);
1233
1234 sta->rssi_stat.rssi_cck = -1;
1235 sta->rssi_stat.rssi_ofdm = -1;
1236 sta->rssi_stat.rssi = -1;
1237 sta->rssi_stat.ofdm_pkt_cnt = 0;
1238 sta->rssi_stat.cck_pkt_cnt = 0;
1239 sta->rssi_stat.cck_sum_power = 0;
1240 sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
1241 sta->rssi_stat.packet_map = 0;
1242 sta->rssi_stat.valid_bit = 0;
1243 }
1244
1245 #if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
1246
phydm_get_rssi_8814_ofdm(struct dm_struct * dm,u8 * rssi_in)1247 s32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in)
1248 {
1249 s32 rssi_avg;
1250 u8 rx_count = 0;
1251 u64 rssi_linear = 0;
1252
1253 if (dm->rx_ant_status & BB_PATH_A) {
1254 rx_count++;
1255 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]);
1256 }
1257
1258 if (dm->rx_ant_status & BB_PATH_B) {
1259 rx_count++;
1260 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]);
1261 }
1262
1263 if (dm->rx_ant_status & BB_PATH_C) {
1264 rx_count++;
1265 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]);
1266 }
1267
1268 if (dm->rx_ant_status & BB_PATH_D) {
1269 rx_count++;
1270 rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]);
1271 }
1272
1273 /* @Rounding and removing fractional bits */
1274 rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
1275
1276 /* @Calculate average RSSI */
1277 switch (rx_count) {
1278 case 2:
1279 rssi_linear = DIVIDED_2(rssi_linear);
1280 break;
1281 case 3:
1282 rssi_linear = DIVIDED_3(rssi_linear);
1283 break;
1284 case 4:
1285 rssi_linear = DIVIDED_4(rssi_linear);
1286 break;
1287 }
1288 rssi_avg = odm_convert_to_db(rssi_linear);
1289
1290 return rssi_avg;
1291 }
1292
phydm_process_rssi_for_dm(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)1293 void phydm_process_rssi_for_dm(struct dm_struct *dm,
1294 struct phydm_phyinfo_struct *phy_info,
1295 struct phydm_perpkt_info_struct *pktinfo)
1296 {
1297 s32 rssi_ave = 0; /*@average among all paths*/
1298 s8 rssi_all = 0; /*@average value of CCK & OFDM*/
1299 s8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0;
1300 u8 i = 0;
1301 u8 rssi_max = 0, rssi_min = 0;
1302 u32 w1 = 0, w2 = 0; /*weighting*/
1303 u8 send_rssi_2_fw = 0;
1304 u8 *rssi_tmp = NULL;
1305 struct cmn_sta_info *sta = NULL;
1306 struct rssi_info *rssi_t = NULL;
1307 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1308 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1309 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1310 #endif
1311 #endif
1312
1313 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
1314 return;
1315
1316 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
1317 odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo);
1318 #endif
1319
1320 sta = dm->phydm_sta_info[pktinfo->station_id];
1321
1322 if (!is_sta_active(sta))
1323 return;
1324
1325 rssi_t = &sta->rssi_stat;
1326
1327 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1328 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1329 if ((dm->support_ability & ODM_BB_ANT_DIV) &&
1330 fat_tab->enable_ctrl_frame_antdiv) {
1331 if (pktinfo->is_packet_match_bssid)
1332 dm->data_frame_num++;
1333
1334 if (fat_tab->use_ctrl_frame_antdiv) {
1335 if (!pktinfo->is_to_self) /*@data frame + CTRL frame*/
1336 return;
1337 } else {
1338 /*@data frame only*/
1339 if (!pktinfo->is_packet_match_bssid)
1340 return;
1341 }
1342 } else
1343 #endif
1344 #endif
1345 {
1346 if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
1347 return;
1348 }
1349
1350 if (pktinfo->is_packet_beacon) {
1351 dm->phy_dbg_info.num_qry_beacon_pkt++;
1352 dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
1353 }
1354
1355 /* @--------------Statistic for antenna/path diversity--------------- */
1356 #ifdef ODM_EVM_ENHANCE_ANTDIV
1357 if (dm->antdiv_evm_en)
1358 phydm_rx_rate_for_antdiv(dm, pktinfo);
1359 #endif
1360
1361 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
1362 if (dm->support_ability & ODM_BB_ANT_DIV)
1363 odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
1364 #endif
1365
1366 #if (defined(CONFIG_PATH_DIVERSITY))
1367 if (dm->support_ability & ODM_BB_PATH_DIV)
1368 phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
1369 #endif
1370 /* @----------------------------------------------------------------- */
1371
1372 rssi_cck_tmp = rssi_t->rssi_cck;
1373 rssi_ofdm_tmp = rssi_t->rssi_ofdm;
1374 rssi_all = rssi_t->rssi;
1375
1376 if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon))
1377 return;
1378
1379 if (!pktinfo->is_cck_rate) {
1380 /* @=== [ofdm RSSI] ======================================================== */
1381 rssi_tmp = phy_info->rx_mimo_signal_strength;
1382
1383 #if (RTL8814A_SUPPORT == 1)
1384 if (dm->support_ic_type & (ODM_RTL8814A)) {
1385 rssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp);
1386 } else
1387 #endif
1388 {
1389 if (rssi_tmp[RF_PATH_B] == 0) {
1390 rssi_ave = rssi_tmp[RF_PATH_A];
1391 } else {
1392 if (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) {
1393 rssi_max = rssi_tmp[RF_PATH_A];
1394 rssi_min = rssi_tmp[RF_PATH_B];
1395 } else {
1396 rssi_max = rssi_tmp[RF_PATH_B];
1397 rssi_min = rssi_tmp[RF_PATH_A];
1398 }
1399 if ((rssi_max - rssi_min) < 3)
1400 rssi_ave = rssi_max;
1401 else if ((rssi_max - rssi_min) < 6)
1402 rssi_ave = rssi_max - 1;
1403 else if ((rssi_max - rssi_min) < 10)
1404 rssi_ave = rssi_max - 2;
1405 else
1406 rssi_ave = rssi_max - 3;
1407 }
1408 }
1409
1410 /* OFDM MA RSSI */
1411 if (rssi_ofdm_tmp <= 0) { /* @initialize */
1412 rssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all;
1413 } else {
1414 rssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp,
1415 (1 << RSSI_MA) - 1,
1416 rssi_ave, 1);
1417 if (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp)
1418 rssi_ofdm_tmp++;
1419 }
1420
1421 PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_ofdm=%d\n", rssi_ofdm_tmp);
1422 } else {
1423 /* @=== [cck RSSI] ========================================================= */
1424 rssi_ave = phy_info->rx_pwdb_all;
1425
1426 if (rssi_t->cck_pkt_cnt <= 63)
1427 rssi_t->cck_pkt_cnt++;
1428
1429 /* @1 Process CCK RSSI */
1430 if (rssi_cck_tmp <= 0) { /* @initialize */
1431 rssi_cck_tmp = (s8)phy_info->rx_pwdb_all;
1432 rssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all;
1433 rssi_t->cck_pkt_cnt = 1; /*reset*/
1434 PHYDM_DBG(dm, DBG_RSSI_MNTR, "[1]CCK_INIT\n");
1435 } else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) {
1436 rssi_t->cck_sum_power = rssi_t->cck_sum_power +
1437 (u16)phy_info->rx_pwdb_all;
1438
1439 rssi_cck_tmp = rssi_t->cck_sum_power /
1440 rssi_t->cck_pkt_cnt;
1441
1442 PHYDM_DBG(dm, DBG_RSSI_MNTR,
1443 "[2]SumPow=%d, cck_pkt=%d\n",
1444 rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt);
1445 } else {
1446 rssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp,
1447 (1 << RSSI_MA) - 1,
1448 phy_info->rx_pwdb_all,
1449 1);
1450 if (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp)
1451 rssi_cck_tmp++;
1452 }
1453 PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_cck=%d\n", rssi_cck_tmp);
1454 }
1455
1456 /* @=== [ofdm + cck weighting RSSI] ========================================= */
1457 if (!pktinfo->is_cck_rate) {
1458 if (rssi_t->ofdm_pkt_cnt < 8 && !(rssi_t->packet_map & BIT(7)))
1459 rssi_t->ofdm_pkt_cnt++; /*OFDM packet cnt in bitmap*/
1460
1461 rssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0);
1462 } else {
1463 if (rssi_t->ofdm_pkt_cnt > 0 && rssi_t->packet_map & BIT(7))
1464 rssi_t->ofdm_pkt_cnt--;
1465
1466 rssi_t->packet_map = rssi_t->packet_map << 1;
1467 }
1468
1469 if (rssi_t->ofdm_pkt_cnt == 8) {
1470 rssi_all = rssi_ofdm_tmp;
1471 } else {
1472 if (rssi_t->valid_bit < 8)
1473 rssi_t->valid_bit++;
1474
1475 if (rssi_t->valid_bit == 8) {
1476 if (rssi_t->ofdm_pkt_cnt > 4)
1477 w1 = 64;
1478 else
1479 w1 = (u32)(rssi_t->ofdm_pkt_cnt << 4);
1480
1481 w2 = 64 - w1;
1482
1483 rssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp +
1484 w2 * (u32)rssi_cck_tmp) >> 6);
1485 } else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 8)*/
1486 w1 = (u32)rssi_t->ofdm_pkt_cnt;
1487 w2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt);
1488 rssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1,
1489 (u32)rssi_cck_tmp, w2);
1490 } else {
1491 rssi_all = 0;
1492 }
1493 }
1494 PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi=%d,w1=%d,w2=%d\n", rssi_all, w1, w2);
1495
1496 if ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) &&
1497 rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) {
1498 send_rssi_2_fw = 1;
1499 rssi_t->is_send_rssi = RA_RSSI_STATE_SEND;
1500 }
1501
1502 rssi_t->rssi_cck = rssi_cck_tmp;
1503 rssi_t->rssi_ofdm = rssi_ofdm_tmp;
1504 rssi_t->rssi = rssi_all;
1505
1506 if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
1507 if (rssi_t->ofdm_pkt_cnt != 0)
1508 rssi_t->rssi = rssi_ofdm_tmp;
1509
1510 PHYDM_DBG(dm, DBG_RSSI_MNTR,
1511 "[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\n",
1512 rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt);
1513 }
1514
1515 #if 0
1516 /* @dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting);*/
1517 /* @dbg_print("rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\n", */
1518 /* rssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */
1519 #endif
1520 }
1521 #endif
1522
1523 #ifdef PHYSTS_3RD_TYPE_SUPPORT
1524 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
phydm_physts_auto_switch_jgr3_reset(void * dm_void)1525 void phydm_physts_auto_switch_jgr3_reset(void *dm_void)
1526 {
1527 struct dm_struct *dm = (struct dm_struct *)dm_void;
1528 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
1529
1530 pkt_proc->phy_ppdu_cnt = 0xff;
1531 pkt_proc->mac_ppdu_cnt = 0xff;
1532 pkt_proc->page_bitmap_record = 0;
1533 }
1534
phydm_physts_auto_switch_jgr3(void * dm_void,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo)1535 boolean phydm_physts_auto_switch_jgr3(void *dm_void, u8 *phy_sts,
1536 struct phydm_perpkt_info_struct *pktinfo)
1537 {
1538 struct dm_struct *dm = (struct dm_struct *)dm_void;
1539 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
1540 boolean is_skip_physts_parsing = false;
1541 u8 phy_sts_byte0 = (*phy_sts & 0xff);
1542 u8 phy_ppdu_cnt_pre = 0, mac_ppdu_cnt_pre = 0;
1543 u8 ppdu_phy_rate_pre = 0, ppdu_macid_pre = 0;
1544 u8 page = phy_sts_byte0 & 0xf;
1545
1546 if (!pkt_proc->physts_auto_swch_en)
1547 return is_skip_physts_parsing;
1548
1549 phy_ppdu_cnt_pre = pkt_proc->phy_ppdu_cnt;
1550 mac_ppdu_cnt_pre = pkt_proc->mac_ppdu_cnt;
1551 ppdu_phy_rate_pre = pkt_proc->ppdu_phy_rate;
1552 ppdu_macid_pre = pkt_proc->ppdu_macid;
1553
1554 pkt_proc->phy_ppdu_cnt = (phy_sts_byte0 & 0x30) >> 4;
1555 pkt_proc->mac_ppdu_cnt = pktinfo->ppdu_cnt;
1556 pkt_proc->ppdu_phy_rate = pktinfo->data_rate;
1557 pkt_proc->ppdu_macid = pktinfo->station_id;
1558
1559 PHYDM_DBG(dm, DBG_PHY_STATUS,
1560 "[rate:0x%x] PPDU mac{pre, curr}= {%d, %d}, phy{pre, curr}= {%d, %d}\n",
1561 pktinfo->data_rate, mac_ppdu_cnt_pre, pkt_proc->mac_ppdu_cnt,
1562 phy_ppdu_cnt_pre, pkt_proc->phy_ppdu_cnt);
1563
1564 if (pktinfo->data_rate < ODM_RATEMCS0) {
1565 pkt_proc->page_bitmap_record = 0;
1566 return is_skip_physts_parsing;
1567 }
1568
1569 if (ppdu_macid_pre == pkt_proc->ppdu_macid &&
1570 ppdu_phy_rate_pre == pkt_proc->ppdu_phy_rate &&
1571 phy_ppdu_cnt_pre == pkt_proc->phy_ppdu_cnt &&
1572 mac_ppdu_cnt_pre == pkt_proc->mac_ppdu_cnt) {
1573 if (pkt_proc->page_bitmap_record & BIT(page)) {
1574 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect page-%d enough\n", page);*/
1575 is_skip_physts_parsing = true;
1576 } else if (pkt_proc->page_bitmap_record ==
1577 pkt_proc->page_bitmap_target) {
1578 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect all enough\n");*/
1579 is_skip_physts_parsing = true;
1580 } else {
1581 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "update page-%d\n", page);*/
1582 pkt_proc->page_bitmap_record |= BIT(page);
1583 }
1584 pkt_proc->is_1st_mpdu = false;
1585 } else {
1586 /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "[New Pkt] update page-%d\n", page);*/
1587 pkt_proc->page_bitmap_record = BIT(page);
1588 pkt_proc->is_1st_mpdu = true;
1589 }
1590
1591 PHYDM_DBG(dm, DBG_PHY_STATUS,
1592 "bitmap{record, target}= {0x%x, 0x%x}\n",
1593 pkt_proc->page_bitmap_record,
1594 pkt_proc->page_bitmap_target);
1595
1596 return is_skip_physts_parsing;
1597 }
1598
phydm_physts_auto_switch_jgr3_set(void * dm_void,boolean enable,u8 bitmap_en)1599 void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable,
1600 u8 bitmap_en)
1601 {
1602 struct dm_struct *dm = (struct dm_struct *)dm_void;
1603 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
1604 u16 en_page_num = 1;
1605
1606 if (!(dm->support_ic_type & PHYSTS_AUTO_SWITCH_IC))
1607 return;
1608 #if 0
1609 if (!(dm->support_ic_type & PHYSTS_3RD_TYPE_IC))
1610 return;
1611 #endif
1612 pkt_proc->physts_auto_swch_en = enable;
1613 pkt_proc->page_bitmap_target = bitmap_en;
1614 phydm_physts_auto_switch_jgr3_reset(dm);
1615 en_page_num = phydm_ones_num_in_bitmap((u64)bitmap_en, 8);
1616
1617 PHYDM_DBG(dm, DBG_CMN, "[%s]en=%d, bitmap_en=%d, en_page_num=%d\n",
1618 __func__, enable, bitmap_en, en_page_num);
1619
1620 if (enable) {
1621 /*@per MPDU latch & update phy-staatus*/
1622 odm_set_mac_reg(dm, R_0x60c, BIT(31), 1);
1623 /*@Update Period (OFDM Symbol)*/
1624 odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 3);
1625 /*@switchin bitmap*/
1626 odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, bitmap_en);
1627 /*@mode 3*/
1628 odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 3);
1629 } else {
1630 odm_set_mac_reg(dm, R_0x60c, BIT(31), 0);
1631 odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x1);
1632 odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, 0x2);
1633 odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 0);
1634 }
1635 }
1636
phydm_avg_condi_num(void * dm_void,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)1637 void phydm_avg_condi_num(void *dm_void,
1638 struct phydm_phyinfo_struct *phy_info,
1639 struct phydm_perpkt_info_struct *pktinfo)
1640 {
1641 struct dm_struct *dm = (struct dm_struct *)dm_void;
1642 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
1643 struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
1644 u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
1645 u16 val = 0, intvl = 0;
1646 u8 arry_idx = 0;
1647
1648 if (pktinfo->rate_ss == 1)
1649 return;
1650
1651 arry_idx = pktinfo->rate_ss - 1;
1652
1653 dbg_s->p4_cnt[arry_idx]++;
1654 dbg_s->cn_sum[arry_idx] += dbg_i->condition_num_seg0;
1655
1656 /*CN Histogram*/
1657 val = (u16)dbg_i->condition_num_seg0;
1658 intvl = phydm_find_intrvl(dm, val, dbg_i->cn_hist_th, size_th);
1659 dbg_s->cn_hist[arry_idx][intvl]++;
1660
1661 dbg_i->condi_num = (u32)dbg_i->condition_num_seg0; /*will remove*/
1662 }
1663 #endif
1664
phydm_print_phystat_jgr3(struct dm_struct * dm,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)1665 void phydm_print_phystat_jgr3(struct dm_struct *dm, u8 *phy_sts,
1666 struct phydm_perpkt_info_struct *pktinfo,
1667 struct phydm_phyinfo_struct *phy_info)
1668 {
1669 struct phy_sts_rpt_jgr3_type0 *rpt0 = NULL;
1670 struct phy_sts_rpt_jgr3_type1 *rpt1 = NULL;
1671 struct phy_sts_rpt_jgr3_type2_3 *rpt2 = NULL;
1672 struct phy_sts_rpt_jgr3_type4 *rpt3 = NULL;
1673 struct phy_sts_rpt_jgr3_type5 *rpt4 = NULL;
1674 struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
1675 u8 phy_status_page_num = (*phy_sts & 0xf);
1676 u32 *phy_status_tmp = NULL;
1677 u8 i = 0;
1678 /*u32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2;*/
1679
1680 if (!(dm->debug_components & DBG_PHY_STATUS))
1681 return;
1682
1683 rpt0 = (struct phy_sts_rpt_jgr3_type0 *)phy_sts;
1684 rpt1 = (struct phy_sts_rpt_jgr3_type1 *)phy_sts;
1685 rpt2 = (struct phy_sts_rpt_jgr3_type2_3 *)phy_sts;
1686 rpt3 = (struct phy_sts_rpt_jgr3_type4 *)phy_sts;
1687 rpt4 = (struct phy_sts_rpt_jgr3_type5 *)phy_sts;
1688
1689 phy_status_tmp = (u32 *)phy_sts;
1690
1691 if (dbg->show_phy_sts_all_pkt == 0) {
1692 if (!pktinfo->is_packet_match_bssid)
1693 return;
1694 }
1695
1696 dbg->show_phy_sts_cnt++;
1697
1698 if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
1699 if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
1700 return;
1701 }
1702
1703 if (phy_status_page_num == 0)
1704 pr_debug("Phy Status Rpt: CCK\n");
1705 else
1706 pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
1707
1708 pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d, ppdu_cnt=%d\n",
1709 pktinfo->station_id, pktinfo->data_rate,
1710 pktinfo->is_packet_match_bssid, pktinfo->ppdu_cnt);
1711
1712 for (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++)
1713 pr_debug("Offset[%d:%d] = 0x%x\n",
1714 ((4 * i) + 3), (4 * i), phy_status_tmp[i]);
1715
1716 if (phy_status_page_num == 0) { /* @CCK(default) */
1717 pr_debug("[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\n",
1718 rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a,
1719 rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b,
1720 rpt0->agc_table_c);
1721 pr_debug("[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\n",
1722 rpt0->path_sel_o, rpt0->gnt_bt_keep_cck,
1723 rpt0->hw_antsw_occur_keep_cck, rpt0->band,
1724 rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc,
1725 rpt0->agc_table_d);
1726 pr_debug("[8] AntIdx={%d, %d, %d, %d}, Length=%d\n",
1727 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
1728 rpt0->antidx_a, rpt0->length);
1729 pr_debug("[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\n",
1730 rpt0->mf_off, rpt0->sqloss, rpt0->lockbit,
1731 rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a,
1732 rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a,
1733 rpt0->signal_quality);
1734 pr_debug("[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\n",
1735 rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b,
1736 rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b);
1737 pr_debug("[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\n",
1738 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
1739 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
1740 pr_debug("[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\n",
1741 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
1742 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
1743 } else if (phy_status_page_num == 1) {
1744 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\n",
1745 rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a,
1746 rpt1->channel_pri_msb, rpt1->pkt_cnt);
1747 pr_debug("[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\n",
1748 rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt,
1749 rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc,
1750 rpt1->l_rxsc, rpt1->pwdb_d);
1751 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Channel_sec[msb,lsb]={%d, %d}\n",
1752 rpt1->antidx_d, rpt1->antidx_c,
1753 rpt1->antidx_b, rpt1->antidx_a,
1754 rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c,
1755 rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a,
1756 rpt1->channel_sec_msb, rpt1->channel_sec_lsb);
1757 pr_debug("[12] GID=%d, PAID[msb,lsb]={%d,%d}\n",
1758 rpt1->gid, rpt1->paid_msb, rpt1->paid);
1759 pr_debug("[16] RX_EVM[D:A]={%d, %d, %d, %d}\n",
1760 rpt1->rxevm[3], rpt1->rxevm[2],
1761 rpt1->rxevm[1], rpt1->rxevm[0]);
1762 pr_debug("[20] CFO_tail[D:A]={%d, %d, %d, %d}\n",
1763 rpt1->cfo_tail[3], rpt1->cfo_tail[2],
1764 rpt1->cfo_tail[1], rpt1->cfo_tail[0]);
1765 pr_debug("[24] RX_SNR[D:A]={%d, %d, %d, %d}\n\n",
1766 rpt1->rxsnr[3], rpt1->rxsnr[2],
1767 rpt1->rxsnr[1], rpt1->rxsnr[0]);
1768 } else if (phy_status_page_num == 2 || phy_status_page_num == 3) {
1769 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
1770 rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0],
1771 rpt2->channel_msb, rpt2->pkt_cnt);
1772 pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
1773 rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt,
1774 rpt2->band, rpt2->channel_lsb,
1775 rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]);
1776 pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\n",
1777 rpt2->agc_table_d, rpt2->agc_table_c,
1778 rpt2->agc_table_b, rpt2->agc_table_a,
1779 rpt2->pwed_th, rpt2->shift_l_map);
1780 pr_debug("[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\n",
1781 rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb,
1782 rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb,
1783 rpt2->mp_gain_b_lsb, rpt2->mp_gain_a,
1784 rpt2->cnt_cca2agc_rdy);
1785 pr_debug("[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\n",
1786 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0],
1787 rpt2->aagc_step_d, rpt2->aagc_step_c,
1788 rpt2->aagc_step_b, rpt2->aagc_step_a,
1789 rpt2->is_freq_select_fading, rpt2->mp_gain_d);
1790 pr_debug("[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\n",
1791 rpt2->dagc_gain[1], rpt2->dagc_gain[0],
1792 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]);
1793 pr_debug("[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\n",
1794 rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb,
1795 rpt2->syn_count_lsb, rpt2->counter,
1796 rpt2->dagc_gain[3], rpt2->dagc_gain[2]);
1797 } else if (phy_status_page_num == 4) { /*type 4*/
1798 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
1799 rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0],
1800 rpt3->channel_msb, rpt3->pkt_cnt);
1801 pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
1802 rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt,
1803 rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc,
1804 rpt3->l_rxsc, rpt3->pwdb[3]);
1805 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\n BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\n",
1806 rpt3->antidx_d, rpt3->antidx_c,
1807 rpt3->antidx_b, rpt3->antidx_a,
1808 rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c,
1809 rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a,
1810 rpt3->training_done_d, rpt3->training_done_c,
1811 rpt3->training_done_b, rpt3->training_done_a,
1812 rpt3->bad_tone_cnt_cn_excess_0,
1813 rpt3->bad_tone_cnt_min_eign_0);
1814 pr_debug("[12] avg_cond_num_1=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d,\n bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\n",
1815 ((rpt3->avg_cond_num_1_msb << 1) |
1816 rpt3->avg_cond_num_1_lsb),
1817 rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1,
1818 rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt);
1819 pr_debug("[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\n",
1820 rpt3->rxevm[3], rpt3->rxevm[2],
1821 rpt3->rxevm[1], rpt3->rxevm[0]);
1822 pr_debug("[20] Eigenvalue[D:A]={%d, %d, %d, %d}\n",
1823 rpt3->eigenvalue[3], rpt3->eigenvalue[2],
1824 rpt3->eigenvalue[1], rpt3->eigenvalue[0]);
1825 pr_debug("[24] RX SNR[D:A]={%d, %d, %d, %d}\n",
1826 rpt3->rxsnr[3], rpt3->rxsnr[2],
1827 rpt3->rxsnr[1], rpt3->rxsnr[0]);
1828 } else if (phy_status_page_num == 5) { /*type 5*/
1829 pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
1830 rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0],
1831 rpt4->channel_msb, rpt4->pkt_cnt);
1832 pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
1833 rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt,
1834 rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc,
1835 rpt4->l_rxsc, rpt4->pwdb[3]);
1836 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\n",
1837 rpt4->antidx_d, rpt4->antidx_c,
1838 rpt4->antidx_b, rpt4->antidx_a,
1839 rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c,
1840 rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a);
1841 pr_debug("[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\n",
1842 rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg,
1843 rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg,
1844 rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg,
1845 rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg,
1846 rpt4->tx_pkt_cnt);
1847 pr_debug("[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\n",
1848 rpt4->inf_pos_1_b, rpt4->inf_pos_0_b,
1849 rpt4->inf_pos_1_a, rpt4->inf_pos_0_a);
1850 pr_debug("[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\n",
1851 rpt4->inf_pos_1_d, rpt4->inf_pos_0_d,
1852 rpt4->inf_pos_1_c, rpt4->inf_pos_0_c);
1853 }
1854 }
1855
phydm_reset_phy_info_jgr3(struct dm_struct * phydm,struct phydm_phyinfo_struct * phy_info)1856 void phydm_reset_phy_info_jgr3(struct dm_struct *phydm,
1857 struct phydm_phyinfo_struct *phy_info)
1858 {
1859 u8 i;
1860
1861 phy_info->rx_pwdb_all = 0;
1862 phy_info->signal_quality = 0;
1863 phy_info->band_width = 0;
1864 phy_info->rx_count = 0;
1865 phy_info->rx_power = -110;
1866 phy_info->recv_signal_power = -110;
1867 phy_info->bt_rx_rssi_percentage = 0;
1868 phy_info->signal_strength = 0;
1869 phy_info->channel = 0;
1870 phy_info->is_mu_packet = 0;
1871 phy_info->is_beamformed = 0;
1872 phy_info->rxsc = 0;
1873
1874 for (i = 0; i < 4; i++) {
1875 phy_info->rx_mimo_signal_strength[i] = 0;
1876 phy_info->rx_mimo_signal_quality[i] = 0;
1877 phy_info->rx_mimo_evm_dbm[i] = 0;
1878 phy_info->cfo_short[i] = 0;
1879 phy_info->cfo_tail[i] = 0;
1880 phy_info->rx_pwr[i] = -110;
1881 phy_info->rx_snr[i] = 0;
1882 }
1883 }
1884
1885 #if 0
1886 void phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
1887 s8 rx_snr, struct phydm_phyinfo_struct *phy_info)
1888 {
1889 u8 evm_dbm = 0;
1890 u8 evm_percentage = 0;
1891
1892 /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
1893
1894 evm_dbm = (rx_evm == -128) ? 0 : ((u8)(0 - rx_evm) >> 1);
1895 evm_percentage = (evm_dbm >= 34) ? 100 : evm_dbm * 3;
1896
1897 phy_info->rx_pwr[rx_path] = pwr;
1898
1899 /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
1900 phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
1901 phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
1902 phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
1903 phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
1904 phy_info->rx_snr[rx_path] = rx_snr >> 1;
1905 }
1906
1907 void phydm_common_phy_info_jgr3(s8 rx_power, u8 channel, boolean is_beamformed,
1908 boolean is_mu_packet, u8 bandwidth,
1909 u8 signal_quality, u8 rxsc,
1910 struct phydm_phyinfo_struct *phy_info)
1911 {
1912 phy_info->rx_power = rx_power; /* RSSI in dB */
1913 phy_info->recv_signal_power = rx_power; /* RSSI in dB */
1914 phy_info->channel = channel; /* @channel number */
1915 phy_info->is_beamformed = is_beamformed; /* @apply BF */
1916 phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
1917 phy_info->rxsc = rxsc;
1918
1919 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power); /*percentage */
1920 phy_info->signal_quality = signal_quality; /* signal quality */
1921 phy_info->band_width = bandwidth; /* @bandwidth */
1922 }
1923 #endif
1924
phydm_get_physts_0_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)1925 void phydm_get_physts_0_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
1926 struct phydm_perpkt_info_struct *pktinfo,
1927 struct phydm_phyinfo_struct *phy_info)
1928 {
1929 /* type 0 is used for cck packet */
1930 struct phy_sts_rpt_jgr3_type0 *phy_sts = NULL;
1931 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
1932 u8 sq = 0, i, rx_cnt = 0;
1933 s8 rx_power[4], pwdb;
1934 s8 rx_pwr_db_max = -120;
1935
1936 phy_sts = (struct phy_sts_rpt_jgr3_type0 *)phy_status_inf;
1937
1938 #if (RTL8197G_SUPPORT)
1939 if (dm->support_ic_type & ODM_RTL8197G) {
1940 if (dm->rx_ant_status == BB_PATH_B) {
1941 phy_sts->pwdb_b = phy_sts->pwdb_a;
1942 phy_sts->gain_b = phy_sts->gain_a;
1943 phy_sts->pwdb_a = 0;
1944 phy_sts->gain_a = 0;
1945 }
1946 }
1947 #endif
1948
1949 rx_power[0] = phy_sts->pwdb_a;
1950 rx_power[1] = phy_sts->pwdb_b;
1951 rx_power[2] = phy_sts->pwdb_c;
1952 rx_power[3] = phy_sts->pwdb_d;
1953
1954 #if (RTL8822C_SUPPORT || RTL8197G_SUPPORT)
1955 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8197G)) {
1956 struct phydm_physts *physts_table = &dm->dm_physts_table;
1957 if (phy_sts->gain_a < physts_table->cck_gi_l_bnd)
1958 rx_power[0] += ((physts_table->cck_gi_l_bnd -
1959 phy_sts->gain_a) << 1);
1960 else if (phy_sts->gain_a > physts_table->cck_gi_u_bnd)
1961 rx_power[0] -= ((phy_sts->gain_a -
1962 physts_table->cck_gi_u_bnd) << 1);
1963
1964 if (phy_sts->gain_b < physts_table->cck_gi_l_bnd)
1965 rx_power[1] += ((physts_table->cck_gi_l_bnd -
1966 phy_sts->gain_b) << 1);
1967 else if (phy_sts->gain_b > physts_table->cck_gi_u_bnd)
1968 rx_power[1] -= ((phy_sts->gain_b -
1969 physts_table->cck_gi_u_bnd) << 1);
1970 }
1971 #endif
1972
1973 /* @Update per-path information */
1974 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
1975 if ((dm->rx_ant_status & BIT(i)) == 0)
1976 continue;
1977
1978 rx_cnt++; /* @check the number of the ant */
1979
1980 if (rx_cnt > dm->num_rf_path)
1981 break;
1982
1983 if (pktinfo->is_to_self)
1984 dm->ofdm_agc_idx[i] = rx_power[i];
1985
1986 /* @Setting the RX power: agc_idx -110 dBm*/
1987 pwdb = rx_power[i] - 110;
1988
1989 phy_info->rx_pwr[i] = pwdb;
1990 phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
1991
1992 /* search maximum pwdb */
1993 if (pwdb > rx_pwr_db_max)
1994 rx_pwr_db_max = pwdb;
1995 }
1996
1997 /* @Calculate Signal Quality*/
1998 if (phy_sts->signal_quality >= 64) {
1999 sq = 0;
2000 } else if (phy_sts->signal_quality <= 20) {
2001 sq = 100;
2002 } else {
2003 /* @mapping to 2~99% */
2004 sq = 64 - phy_sts->signal_quality;
2005 sq = ((sq << 3) + sq) >> 2;
2006 }
2007
2008 /* @Modify CCK PWDB if old AGC */
2009 if (!dm->cck_new_agc) {
2010 u8 lna_idx[4], vga_idx[4];
2011
2012 lna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a);
2013 vga_idx[0] = phy_sts->vga_a;
2014 lna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b);
2015 vga_idx[1] = phy_sts->vga_b;
2016 lna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c);
2017 vga_idx[2] = phy_sts->vga_c;
2018 lna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d);
2019 vga_idx[3] = phy_sts->vga_d;
2020 }
2021
2022 /*@CCK no STBC and LDPC*/
2023 dbg_i->is_ldpc_pkt = false;
2024 dbg_i->is_stbc_pkt = false;
2025
2026 /*cck channel has hw bug, [WLANBB-1429]*/
2027 phy_info->channel = 0;
2028 phy_info->rx_power = rx_pwr_db_max;
2029 phy_info->recv_signal_power = rx_pwr_db_max;
2030 phy_info->is_beamformed = false;
2031 phy_info->is_mu_packet = false;
2032 phy_info->rxsc = phy_sts->l_rxsc;
2033 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
2034 phy_info->signal_quality = sq;
2035 phy_info->band_width = CHANNEL_WIDTH_20;
2036
2037 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2038 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2039 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2040 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2041 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2042 #endif
2043 }
2044
phydm_get_physts_1_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2045 void phydm_get_physts_1_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2046 struct phydm_perpkt_info_struct *pktinfo,
2047 struct phydm_phyinfo_struct *phy_info)
2048 {
2049 struct phy_sts_rpt_jgr3_type1 *phy_sts = NULL;
2050 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2051 s8 evm = 0;
2052 u8 i;
2053 s8 sq = 0;
2054
2055 phy_sts = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
2056
2057 /* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
2058
2059 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2060 if ((dm->rx_ant_status & BIT(i)) == 0)
2061 continue;
2062
2063 evm = phy_sts->rxevm[i];
2064 evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
2065 sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
2066
2067 phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
2068 phy_info->rx_mimo_signal_quality[i] = sq;
2069 phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
2070 /*@CFO(kHz) = CFO_tail*312.5(kHz)/2^7 ~= CFO tail * 5/2 (kHz)*/
2071 phy_info->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
2072 dbg_i->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
2073 }
2074 phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
2075
2076 if (phy_sts->gid != 0 && phy_sts->gid != 63) {
2077 phy_info->is_mu_packet = true;
2078 dbg_i->num_qry_mu_pkt++;
2079 } else {
2080 phy_info->is_mu_packet = false;
2081 }
2082
2083 phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
2084
2085 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2086 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2087 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2088 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2089 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2090 #endif
2091 }
2092
phydm_get_physts_2_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2093 void phydm_get_physts_2_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2094 struct phydm_perpkt_info_struct *pktinfo,
2095 struct phydm_phyinfo_struct *phy_info)
2096 {
2097 /* type 2 & 3 is used for ofdm packet */
2098 struct phy_sts_rpt_jgr3_type2_3 *phy_sts = NULL;
2099 }
2100
phydm_get_physts_4_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2101 void phydm_get_physts_4_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2102 struct phydm_perpkt_info_struct *pktinfo,
2103 struct phydm_phyinfo_struct *phy_info)
2104 {
2105 struct phy_sts_rpt_jgr3_type4 *phy_sts = NULL;
2106 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2107 s8 evm = 0;
2108 u8 i;
2109 s8 sq = 0;
2110
2111 phy_sts = (struct phy_sts_rpt_jgr3_type4 *)phy_status_inf;
2112
2113 /* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
2114
2115 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2116 if ((dm->rx_ant_status & BIT(i)) == 0)
2117 continue;
2118
2119 evm = phy_sts->rxevm[i];
2120 evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
2121 sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
2122
2123 phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
2124 phy_info->rx_mimo_signal_quality[i] = sq;
2125 phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
2126 }
2127 phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
2128 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2129 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2130 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2131 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2132 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2133 #endif
2134 odm_move_memory(dm, dbg_i->eigen_val, phy_sts->eigenvalue, 4);
2135 dbg_i->condition_num_seg0 = phy_sts->avg_cond_num_0;
2136 }
2137
phydm_get_physts_5_others_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2138 void phydm_get_physts_5_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2139 struct phydm_perpkt_info_struct *pktinfo,
2140 struct phydm_phyinfo_struct *phy_info)
2141 {
2142 struct phy_sts_rpt_jgr3_type5 *phy_sts = NULL;
2143
2144 }
2145
phydm_get_physts_ofdm_cmn_jgr3(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2146 void phydm_get_physts_ofdm_cmn_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
2147 struct phydm_perpkt_info_struct *pktinfo,
2148 struct phydm_phyinfo_struct *phy_info)
2149 {
2150 struct phy_sts_rpt_jgr3_ofdm_cmn *phy_sts = NULL;
2151 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2152 s8 rx_pwr_db_max = -120;
2153 s8 pwdb = 0;
2154 u8 i, rx_cnt = 0;
2155
2156 phy_sts = (struct phy_sts_rpt_jgr3_ofdm_cmn *)phy_status_inf;
2157
2158 /* Parsing Offset0 & 4*/
2159 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2160 if ((dm->rx_ant_status & BIT(i)) == 0)
2161 continue;
2162
2163 rx_cnt++; /* @check the number of the ant */
2164
2165 pwdb = (s8)phy_sts->pwdb[i] - 110; /*@dB*/
2166
2167 if (pktinfo->is_to_self)
2168 dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
2169
2170 /* search maximum pwdb */
2171 if (pwdb > rx_pwr_db_max)
2172 rx_pwr_db_max = pwdb;
2173
2174 phy_info->rx_pwr[i] = pwdb;
2175 phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
2176 }
2177
2178 phy_info->rx_count = (rx_cnt > 0) ? rx_cnt - 1 : 0; /*from 1~4 to 0~3 */
2179 phy_info->rx_power = rx_pwr_db_max;
2180 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
2181 phy_info->recv_signal_power = rx_pwr_db_max;
2182 phy_info->channel = phy_sts->channel_lsb;
2183 phy_info->is_beamformed = (boolean)phy_sts->beamformed;
2184 phy_info->rxsc = (PHYDM_IS_LEGACY_RATE(pktinfo->data_rate)) ?
2185 phy_sts->l_rxsc : phy_sts->ht_rxsc;
2186 phy_info->band_width = phydm_rxsc_2_bw(dm, phy_info->rxsc);
2187
2188 dbg_i->is_ldpc_pkt = phy_sts->ldpc;
2189 dbg_i->is_stbc_pkt = phy_sts->stbc;
2190 dbg_i->num_qry_bf_pkt += phy_sts->beamformed;
2191 }
2192
phydm_process_dm_rssi_jgr3(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)2193 void phydm_process_dm_rssi_jgr3(struct dm_struct *dm,
2194 struct phydm_phyinfo_struct *phy_info,
2195 struct phydm_perpkt_info_struct *pktinfo)
2196 {
2197 struct cmn_sta_info *sta = NULL;
2198 struct rssi_info *rssi_t = NULL;
2199 u8 rssi_tmp = 0;
2200 u64 rssi_linear = 0;
2201 s16 rssi_db = 0;
2202 u8 i = 0;
2203 u8 rx_count = 0;
2204
2205 #if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
2206 struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
2207 #endif
2208
2209 /*@[Step4]*/
2210 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
2211 return;
2212
2213 sta = dm->phydm_sta_info[pktinfo->station_id];
2214
2215 if (!is_sta_active(sta))
2216 return;
2217
2218 if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
2219 return;
2220
2221 if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
2222 return;
2223
2224 if (pktinfo->is_packet_beacon) {
2225 dm->phy_dbg_info.num_qry_beacon_pkt++;
2226 dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
2227 }
2228
2229 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2230 if (dm->support_ability & ODM_BB_ANT_DIV)
2231 odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
2232 #endif
2233
2234 #ifdef ODM_EVM_ENHANCE_ANTDIV
2235 phydm_rx_rate_for_antdiv(dm, pktinfo);
2236 #endif
2237
2238 #if (defined(CONFIG_PATH_DIVERSITY))
2239 if (dm->support_ability & ODM_BB_PATH_DIV)
2240 phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
2241 #endif
2242
2243 #if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
2244 if (cckrx_t->en_cck_rx_pathdiv)
2245 phydm_process_rssi_for_cck_rx_pathdiv(dm, phy_info, pktinfo);
2246 #endif
2247
2248 rssi_t = &sta->rssi_stat;
2249
2250 for (i = 0; i < dm->num_rf_path; i++) {
2251 rssi_tmp = phy_info->rx_mimo_signal_strength[i];
2252 if (rssi_tmp != 0) {
2253 rx_count++;
2254 rssi_linear += phydm_db_2_linear(rssi_tmp);
2255 }
2256 }
2257 /* @Rounding and removing fractional bits */
2258 rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
2259
2260 switch (rx_count) {
2261 case 2:
2262 rssi_linear = DIVIDED_2(rssi_linear);
2263 break;
2264 case 3:
2265 rssi_linear = DIVIDED_3(rssi_linear);
2266 break;
2267 case 4:
2268 rssi_linear = DIVIDED_4(rssi_linear);
2269 break;
2270 }
2271
2272 rssi_db = (s16)odm_convert_to_db(rssi_linear);
2273
2274 if (rssi_t->rssi_acc == 0) {
2275 rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
2276 rssi_t->rssi = (s8)(rssi_db);
2277 } else {
2278 rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
2279 rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
2280 }
2281
2282 if (pktinfo->is_cck_rate)
2283 rssi_t->rssi_cck = (s8)rssi_db;
2284 else
2285 rssi_t->rssi_ofdm = (s8)rssi_db;
2286 }
2287
phydm_rx_physts_jgr3(void * dm_void,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2288 void phydm_rx_physts_jgr3(void *dm_void, u8 *phy_sts,
2289 struct phydm_perpkt_info_struct *pktinfo,
2290 struct phydm_phyinfo_struct *phy_info)
2291 {
2292 struct dm_struct *dm = (struct dm_struct *)dm_void;
2293 u8 phy_status_type = (*phy_sts & 0xf);
2294
2295 /*@[Step 2]*/
2296 /*phydm_reset_phy_info_jgr3(dm, phy_info);*/ /* @Memory reset */
2297
2298 /* Phy status parsing */
2299 switch (phy_status_type) {
2300 case 0: /*@CCK*/
2301 phydm_get_physts_0_jgr3(dm, phy_sts, pktinfo, phy_info);
2302 break;
2303 case 1:
2304 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2305 phydm_get_physts_1_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2306 break;
2307 case 2:
2308 case 3:
2309 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2310 phydm_get_physts_2_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2311 break;
2312 case 4:
2313 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2314 phydm_get_physts_4_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2315 case 5:
2316 phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
2317 phydm_get_physts_5_others_jgr3(dm, phy_sts, pktinfo, phy_info);
2318 break;
2319 default:
2320 break;
2321 }
2322
2323 #if 0
2324 PHYDM_DBG(dm, DBG_PHY_STATUS, "RSSI: {%d, %d}\n",
2325 phy_info->rx_mimo_signal_strength[0],
2326 phy_info->rx_mimo_signal_strength[1]);
2327 PHYDM_DBG(dm, DBG_PHY_STATUS, "rxdb: {%d, %d}\n",
2328 phy_info->rx_pwr[0], phy_info->rx_pwr[1]);
2329 PHYDM_DBG(dm, DBG_PHY_STATUS, "EVM: {%d, %d}\n",
2330 phy_info->rx_mimo_evm_dbm[0], phy_info->rx_mimo_evm_dbm[1]);
2331 PHYDM_DBG(dm, DBG_PHY_STATUS, "SQ: {%d, %d}\n",
2332 phy_info->rx_mimo_signal_quality[0],
2333 phy_info->rx_mimo_signal_quality[1]);
2334 PHYDM_DBG(dm, DBG_PHY_STATUS, "SNR: {%d, %d}\n",
2335 phy_info->rx_snr[0], phy_info->rx_snr[1]);
2336 PHYDM_DBG(dm, DBG_PHY_STATUS, "CFO: {%d, %d}\n",
2337 phy_info->cfo_tail[0], phy_info->cfo_tail[1]);
2338 PHYDM_DBG(dm, DBG_PHY_STATUS,
2339 "rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
2340 phy_info->rx_pwdb_all, phy_info->rx_power,
2341 phy_info->recv_signal_power);
2342 PHYDM_DBG(dm, DBG_PHY_STATUS, "signal_quality = %d\n",
2343 phy_info->signal_quality);
2344 PHYDM_DBG(dm, DBG_PHY_STATUS,
2345 "is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
2346 phy_info->is_beamformed, phy_info->is_mu_packet,
2347 phy_info->rx_count);
2348 PHYDM_DBG(dm, DBG_PHY_STATUS,
2349 "channel = %d, rxsc = %d, band_width = %d\n",
2350 phy_info->channel, phy_info->rxsc, phy_info->band_width);
2351 #endif
2352
2353 /*@[Step 1]*/
2354 phydm_print_phystat_jgr3(dm, phy_sts, pktinfo, phy_info);
2355 }
2356
2357 #endif
2358
2359 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
2360 /* @For 8822B only!! need to move to FW finally */
2361 /*@==============================================*/
2362
2363 boolean
phydm_query_is_mu_api(struct dm_struct * phydm,u8 ppdu_idx,u8 * p_data_rate,u8 * p_gid)2364 phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
2365 u8 *p_gid)
2366 {
2367 u8 data_rate = 0, gid = 0;
2368 boolean is_mu = false;
2369
2370 data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
2371 gid = phydm->phy_dbg_info.gid_num[ppdu_idx];
2372
2373 if (data_rate & BIT(7)) {
2374 is_mu = true;
2375 data_rate = data_rate & ~(BIT(7));
2376 } else {
2377 is_mu = false;
2378 }
2379
2380 *p_data_rate = data_rate;
2381 *p_gid = gid;
2382
2383 return is_mu;
2384 }
2385
phydm_print_phy_sts_jgr2(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2386 void phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf,
2387 struct phydm_perpkt_info_struct *pktinfo,
2388 struct phydm_phyinfo_struct *phy_info)
2389 {
2390 struct phy_sts_rpt_jgr2_type0 *rpt0 = NULL;
2391 struct phy_sts_rpt_jgr2_type1 *rpt = NULL;
2392 struct phy_sts_rpt_jgr2_type2 *rpt2 = NULL;
2393 struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
2394 u8 phy_status_page_num = (*phy_status_inf & 0xf);
2395 u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0};
2396 u8 i;
2397 u32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2;
2398
2399 rpt0 = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
2400 rpt = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
2401 rpt2 = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
2402
2403 odm_move_memory(dm, phy_status, phy_status_inf, size);
2404
2405 if (!(dm->debug_components & DBG_PHY_STATUS))
2406 return;
2407
2408 if (dbg->show_phy_sts_all_pkt == 0) {
2409 if (!pktinfo->is_packet_match_bssid)
2410 return;
2411 }
2412
2413 dbg->show_phy_sts_cnt++;
2414 #if 0
2415 dbg_print("cnt=%d, max=%d\n",
2416 dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt);
2417 #endif
2418
2419 if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
2420 if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
2421 return;
2422 }
2423
2424 pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
2425 pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n",
2426 pktinfo->station_id, pktinfo->data_rate,
2427 pktinfo->is_packet_match_bssid);
2428
2429 for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++)
2430 pr_debug("Offset[%d:%d] = 0x%x\n",
2431 ((4 * i) + 3), (4 * i), phy_status[i]);
2432
2433 if (phy_status_page_num == 0) {
2434 pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n",
2435 rpt0->trsw, rpt0->gain, rpt0->pwdb);
2436 pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n",
2437 rpt0->band, rpt0->channel,
2438 rpt0->agc_table, rpt0->rxsc);
2439 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
2440 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
2441 rpt0->antidx_a, rpt0->length);
2442 pr_debug("[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\n",
2443 rpt0->lna_h, rpt0->bb_power, rpt0->lna_l,
2444 rpt0->vga, rpt0->signal_quality);
2445
2446 } else if (phy_status_page_num == 1) {
2447 pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
2448 rpt->pwdb[3], rpt->pwdb[2],
2449 rpt->pwdb[1], rpt->pwdb[0]);
2450 pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n",
2451 rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt,
2452 rpt->hw_antsw_occu, rpt->band, rpt->channel,
2453 rpt->ht_rxsc, rpt->l_rxsc);
2454 pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
2455 rpt->antidx_d, rpt->antidx_c, rpt->antidx_b,
2456 rpt->antidx_a, rpt->lsig_length);
2457 pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n",
2458 rpt->rf_mode, rpt->nb_intf_flag,
2459 (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid,
2460 (rpt->paid + (rpt->paid_msb << 8)));
2461 pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n",
2462 rpt->rxevm[3], rpt->rxevm[2],
2463 rpt->rxevm[1], rpt->rxevm[0]);
2464 pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n",
2465 rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1],
2466 rpt->cfo_tail[0]);
2467 pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n",
2468 rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1],
2469 rpt->rxsnr[0]);
2470
2471 } else if (phy_status_page_num == 2) {
2472 pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
2473 rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1],
2474 rpt2->pwdb[0]);
2475 pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\n",
2476 rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt,
2477 rpt2->hw_antsw_occu, rpt2->band, rpt2->channel,
2478 rpt2->ht_rxsc, rpt2->l_rxsc);
2479 pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n",
2480 rpt2->agc_table_d, rpt2->agc_table_c,
2481 rpt2->agc_table_b, rpt2->agc_table_a,
2482 rpt2->cnt_pw2cca, rpt2->shift_l_map);
2483 pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n",
2484 rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c,
2485 rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a,
2486 rpt2->gain_a, rpt2->cnt_cca2agc_rdy);
2487 pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n",
2488 rpt2->aagc_step_d, rpt2->aagc_step_c,
2489 rpt2->aagc_step_b, rpt2->aagc_step_a,
2490 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2],
2491 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]);
2492 pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n",
2493 rpt2->dagc_gain[3],
2494 rpt2->dagc_gain[2], rpt2->dagc_gain[1],
2495 rpt2->dagc_gain[0]);
2496 pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n",
2497 rpt2->syn_count, rpt2->counter);
2498 }
2499 }
2500
phydm_set_per_path_phy_info(u8 rx_path,s8 pwr,s8 rx_evm,s8 cfo_tail,s8 rx_snr,u8 ant_idx,struct phydm_phyinfo_struct * phy_info)2501 void phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
2502 s8 rx_snr, u8 ant_idx,
2503 struct phydm_phyinfo_struct *phy_info)
2504 {
2505 u8 evm_dbm = 0;
2506 u8 evm_percentage = 0;
2507
2508 /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
2509
2510 if (rx_evm < 0) {
2511 /* @Calculate EVM in dBm */
2512 evm_dbm = ((u8)(0 - rx_evm) >> 1);
2513
2514 if (evm_dbm == 64)
2515 evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/
2516
2517 if (evm_dbm != 0) {
2518 /* @Convert EVM to 0%~100% percentage */
2519 if (evm_dbm >= 34)
2520 evm_percentage = 100;
2521 else
2522 evm_percentage = (evm_dbm << 1) + (evm_dbm);
2523 }
2524 }
2525
2526 phy_info->rx_pwr[rx_path] = pwr;
2527
2528 /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
2529 phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
2530 phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
2531 phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
2532 phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
2533 phy_info->rx_snr[rx_path] = rx_snr >> 1;
2534 phy_info->ant_idx[rx_path] = ant_idx;
2535
2536 #if 0
2537 if (!pktinfo->is_packet_match_bssid)
2538 return;
2539
2540 dbg_print("path (%d)--------\n", rx_path);
2541 dbg_print("rx_pwr = %d, Signal strength = %d\n",
2542 phy_info->rx_pwr[rx_path],
2543 phy_info->rx_mimo_signal_strength[rx_path]);
2544 dbg_print("evm_dbm = %d, Signal quality = %d\n",
2545 phy_info->rx_mimo_evm_dbm[rx_path],
2546 phy_info->rx_mimo_signal_quality[rx_path]);
2547 dbg_print("CFO = %d, SNR = %d\n",
2548 phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]);
2549
2550 #endif
2551 }
2552
phydm_set_common_phy_info(s8 rx_power,u8 channel,boolean is_beamformed,boolean is_mu_packet,u8 bandwidth,u8 signal_quality,u8 rxsc,struct phydm_phyinfo_struct * phy_info)2553 void phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed,
2554 boolean is_mu_packet, u8 bandwidth,
2555 u8 signal_quality, u8 rxsc,
2556 struct phydm_phyinfo_struct *phy_info)
2557 {
2558 phy_info->rx_power = rx_power; /* RSSI in dB */
2559 phy_info->recv_signal_power = rx_power; /* RSSI in dB */
2560 phy_info->channel = channel; /* @channel number */
2561 phy_info->is_beamformed = is_beamformed; /* @apply BF */
2562 phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
2563 phy_info->rxsc = rxsc;
2564
2565 /* RSSI in percentage */
2566 phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power);
2567 phy_info->signal_quality = signal_quality; /* signal quality */
2568 phy_info->band_width = bandwidth; /* @bandwidth */
2569
2570 #if 0
2571 if (!pktinfo->is_packet_match_bssid)
2572 return;
2573
2574 dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
2575 phy_info->rx_pwdb_all, phy_info->rx_power,
2576 phy_info->recv_signal_power);
2577 dbg_print("signal_quality = %d\n", phy_info->signal_quality);
2578 dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
2579 phy_info->is_beamformed, phy_info->is_mu_packet,
2580 phy_info->rx_count + 1);
2581 dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel,
2582 rxsc, bandwidth);
2583
2584 #endif
2585 }
2586
phydm_get_phy_sts_type0(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2587 void phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf,
2588 struct phydm_perpkt_info_struct *pktinfo,
2589 struct phydm_phyinfo_struct *phy_info)
2590 {
2591 /* type 0 is used for cck packet */
2592 struct phy_sts_rpt_jgr2_type0 *phy_sts = NULL;
2593 u8 sq = 0;
2594 s8 rx_pow = 0;
2595 u8 lna_idx = 0, vga_idx = 0;
2596 u8 ant_idx;
2597
2598 phy_sts = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
2599 rx_pow = phy_sts->pwdb - 110;
2600
2601 /* Fill in per-path antenna index */
2602 ant_idx = phy_sts->antidx_a;
2603
2604 if (dm->support_ic_type & ODM_RTL8723D) {
2605 #if (RTL8723D_SUPPORT)
2606 rx_pow = phy_sts->pwdb - 97;
2607 #endif
2608 }
2609 #if (RTL8821C_SUPPORT)
2610 else if (dm->support_ic_type & ODM_RTL8821C) {
2611 if (phy_sts->pwdb >= -57)
2612 rx_pow = phy_sts->pwdb - 100;
2613 else
2614 rx_pow = phy_sts->pwdb - 102;
2615 }
2616 #endif
2617
2618 if (pktinfo->is_to_self) {
2619 dm->ofdm_agc_idx[0] = phy_sts->pwdb;
2620 dm->ofdm_agc_idx[1] = 0;
2621 dm->ofdm_agc_idx[2] = 0;
2622 dm->ofdm_agc_idx[3] = 0;
2623 }
2624
2625 /* @Calculate Signal Quality*/
2626 if (phy_sts->signal_quality >= 64) {
2627 sq = 0;
2628 } else if (phy_sts->signal_quality <= 20) {
2629 sq = 100;
2630 } else {
2631 /* @mapping to 2~99% */
2632 sq = 64 - phy_sts->signal_quality;
2633 sq = ((sq << 3) + sq) >> 2;
2634 }
2635
2636 /* @Get RSSI for old CCK AGC */
2637 if (!dm->cck_new_agc) {
2638 vga_idx = phy_sts->vga;
2639
2640 if (dm->support_ic_type & ODM_RTL8197F) {
2641 /*@3bit LNA*/
2642 lna_idx = phy_sts->lna_l;
2643 } else {
2644 /*@4bit LNA*/
2645 lna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l;
2646 }
2647 rx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
2648 }
2649
2650 /* @Confirm CCK RSSI */
2651 #if (RTL8197F_SUPPORT)
2652 if (dm->support_ic_type & ODM_RTL8197F) {
2653 u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */
2654 u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */
2655
2656 if (phy_sts->bb_power < bb_pwr_th_l ||
2657 phy_sts->bb_power > bb_pwr_th_h)
2658 rx_pow = 0; /* @Error RSSI for CCK ; set 100*/
2659 }
2660 #endif
2661
2662 /*@CCK no STBC and LDPC*/
2663 dm->phy_dbg_info.is_ldpc_pkt = false;
2664 dm->phy_dbg_info.is_stbc_pkt = false;
2665
2666 /* Update Common information */
2667 phydm_set_common_phy_info(rx_pow, phy_sts->channel, false,
2668 false, CHANNEL_WIDTH_20, sq,
2669 phy_sts->rxsc, phy_info);
2670 /* Update CCK pwdb */
2671 phydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, ant_idx,
2672 phy_info);
2673
2674 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2675 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2676 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2677 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2678 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2679 #endif
2680 }
2681
phydm_get_phy_sts_type1(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2682 void phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf,
2683 struct phydm_perpkt_info_struct *pktinfo,
2684 struct phydm_phyinfo_struct *phy_info)
2685 {
2686 /* type 1 is used for ofdm packet */
2687 struct phy_sts_rpt_jgr2_type1 *phy_sts = NULL;
2688 struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
2689 s8 rx_pwr_db = -120;
2690 s8 rx_pwr = 0;
2691 u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
2692 boolean is_mu;
2693 u8 ant_idx[4];
2694
2695 phy_sts = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
2696
2697 /* Fill in per-path antenna index */
2698 ant_idx[0] = phy_sts->antidx_a;
2699 ant_idx[1] = phy_sts->antidx_b;
2700 ant_idx[2] = phy_sts->antidx_c;
2701 ant_idx[3] = phy_sts->antidx_d;
2702
2703 /* Update per-path information */
2704 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
2705 if (!(dm->rx_ant_status & BIT(i)))
2706 continue;
2707 rx_count++;
2708
2709 if (rx_count > dm->num_rf_path)
2710 break;
2711
2712 /* Update per-path information
2713 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
2714 */
2715 /* @EVM report is reported by stream, not path */
2716 rx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/
2717
2718 if (pktinfo->is_to_self)
2719 dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
2720
2721 phydm_set_per_path_phy_info(i, rx_pwr,
2722 phy_sts->rxevm[rx_count - 1],
2723 phy_sts->cfo_tail[i],
2724 phy_sts->rxsnr[i],
2725 ant_idx[i], phy_info);
2726 /* search maximum pwdb */
2727 if (rx_pwr > rx_pwr_db)
2728 rx_pwr_db = rx_pwr;
2729 }
2730
2731 /* @mapping RX counter from 1~4 to 0~3 */
2732 if (rx_count > 0)
2733 phy_info->rx_count = rx_count - 1;
2734
2735 /* @Check if MU packet or not */
2736 if (phy_sts->gid != 0 && phy_sts->gid != 63) {
2737 is_mu = true;
2738 dbg_i->num_qry_mu_pkt++;
2739 } else {
2740 is_mu = false;
2741 }
2742
2743 /* @count BF packet */
2744 dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;
2745
2746 /*STBC or LDPC pkt*/
2747 dbg_i->is_ldpc_pkt = phy_sts->ldpc;
2748 dbg_i->is_stbc_pkt = phy_sts->stbc;
2749
2750 /* @Check sub-channel */
2751 if (pktinfo->data_rate > ODM_RATE11M &&
2752 pktinfo->data_rate < ODM_RATEMCS0)
2753 rxsc = phy_sts->l_rxsc;
2754 else
2755 rxsc = phy_sts->ht_rxsc;
2756
2757 /* @Check RX bandwidth */
2758 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2759 if (rxsc >= 1 && rxsc <= 8)
2760 bw = CHANNEL_WIDTH_20;
2761 else if ((rxsc >= 9) && (rxsc <= 12))
2762 bw = CHANNEL_WIDTH_40;
2763 else if (rxsc >= 13)
2764 bw = CHANNEL_WIDTH_80;
2765 else
2766 bw = phy_sts->rf_mode;
2767
2768 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
2769 if (phy_sts->rf_mode == 0)
2770 bw = CHANNEL_WIDTH_20;
2771 else if ((rxsc == 1) || (rxsc == 2))
2772 bw = CHANNEL_WIDTH_20;
2773 else
2774 bw = CHANNEL_WIDTH_40;
2775 }
2776
2777 /* Update packet information */
2778 phydm_set_common_phy_info(rx_pwr_db, phy_sts->channel,
2779 (boolean)phy_sts->beamformed, is_mu, bw,
2780 phy_info->rx_mimo_signal_quality[0],
2781 rxsc, phy_info);
2782
2783 phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
2784 #ifdef PHYDM_LNA_SAT_CHK_TYPE2
2785 phydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr);
2786 #endif
2787
2788 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2789 dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
2790 dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
2791 dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
2792 dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
2793 #endif
2794 }
2795
phydm_get_phy_sts_type2(struct dm_struct * dm,u8 * phy_status_inf,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2796 void phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf,
2797 struct phydm_perpkt_info_struct *pktinfo,
2798 struct phydm_phyinfo_struct *phy_info)
2799 {
2800 struct phy_sts_rpt_jgr2_type2 *phy_sts = NULL;
2801 s8 rx_pwr_db_max = -120;
2802 s8 rx_pwr = 0;
2803 u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
2804
2805 phy_sts = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
2806
2807 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
2808 if (!(dm->rx_ant_status & BIT(i)))
2809 continue;
2810 rx_count++;
2811
2812 if (rx_count > dm->num_rf_path)
2813 break;
2814
2815 /* Update per-path information*/
2816 /* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */
2817 #if (RTL8197F_SUPPORT)
2818 if ((dm->support_ic_type & ODM_RTL8197F) &&
2819 phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/
2820
2821 if (i == RF_PATH_A) {
2822 rx_pwr = (phy_sts->gain_a) << 1;
2823 rx_pwr = rx_pwr - 110;
2824 } else if (i == RF_PATH_B) {
2825 rx_pwr = (phy_sts->gain_b) << 1;
2826 rx_pwr = rx_pwr - 110;
2827 } else {
2828 rx_pwr = 0;
2829 }
2830 } else
2831 #endif
2832 rx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/
2833
2834 phydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, 0, phy_info);
2835
2836 if (rx_pwr > rx_pwr_db_max) /* search max pwdb */
2837 rx_pwr_db_max = rx_pwr;
2838 }
2839
2840 /* @mapping RX counter from 1~4 to 0~3 */
2841 if (rx_count > 0)
2842 phy_info->rx_count = rx_count - 1;
2843
2844 /* @Check RX sub-channel */
2845 if (pktinfo->data_rate > ODM_RATE11M &&
2846 pktinfo->data_rate < ODM_RATEMCS0)
2847 rxsc = phy_sts->l_rxsc;
2848 else
2849 rxsc = phy_sts->ht_rxsc;
2850
2851 /*STBC or LDPC pkt*/
2852 dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
2853 dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
2854
2855 /* @Check RX bandwidth */
2856 /* @BW information of sc=0 is useless,
2857 *because there is no information of RF mode
2858 */
2859 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2860 if (rxsc >= 1 && rxsc <= 8)
2861 bw = CHANNEL_WIDTH_20;
2862 else if ((rxsc >= 9) && (rxsc <= 12))
2863 bw = CHANNEL_WIDTH_40;
2864 else if (rxsc >= 13)
2865 bw = CHANNEL_WIDTH_80;
2866
2867 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
2868 if (rxsc == 3)
2869 bw = CHANNEL_WIDTH_40;
2870 else if ((rxsc == 1) || (rxsc == 2))
2871 bw = CHANNEL_WIDTH_20;
2872 }
2873
2874 /* Update packet information */
2875 phydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel,
2876 (boolean)phy_sts->beamformed,
2877 false, bw, 0, rxsc, phy_info);
2878 }
2879
phydm_process_rssi_for_dm_2nd_type(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,struct phydm_perpkt_info_struct * pktinfo)2880 void phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm,
2881 struct phydm_phyinfo_struct *phy_info,
2882 struct phydm_perpkt_info_struct *pktinfo
2883 )
2884 {
2885 struct cmn_sta_info *sta = NULL;
2886 struct rssi_info *rssi_t = NULL;
2887 u8 rssi_tmp = 0;
2888 u64 rssi_linear = 0;
2889 s16 rssi_db = 0;
2890 u8 i = 0;
2891
2892 if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
2893 return;
2894
2895 sta = dm->phydm_sta_info[pktinfo->station_id];
2896
2897 if (!is_sta_active(sta))
2898 return;
2899
2900 if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
2901 return;
2902
2903 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2904 if (dm->support_ability & ODM_BB_ANT_DIV)
2905 odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
2906 #endif
2907
2908 #if (defined(CONFIG_PATH_DIVERSITY))
2909 if (dm->support_ability & ODM_BB_PATH_DIV)
2910 phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
2911 #endif
2912
2913 #ifdef CONFIG_ADAPTIVE_SOML
2914 phydm_rx_qam_for_soml(dm, pktinfo);
2915 phydm_rx_rate_for_soml(dm, pktinfo);
2916 #endif
2917
2918 if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
2919 return;
2920
2921 if (pktinfo->is_packet_beacon) {
2922 dm->phy_dbg_info.num_qry_beacon_pkt++;
2923 dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
2924 }
2925
2926 rssi_t = &sta->rssi_stat;
2927
2928 for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
2929 rssi_tmp = phy_info->rx_mimo_signal_strength[i];
2930 if (rssi_tmp != 0)
2931 rssi_linear += phydm_db_2_linear(rssi_tmp);
2932 }
2933 /* @Rounding and removing fractional bits */
2934 rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
2935
2936 switch (phy_info->rx_count + 1) {
2937 case 2:
2938 rssi_linear = DIVIDED_2(rssi_linear);
2939 break;
2940 case 3:
2941 rssi_linear = DIVIDED_3(rssi_linear);
2942 break;
2943 case 4:
2944 rssi_linear = DIVIDED_4(rssi_linear);
2945 break;
2946 }
2947
2948 rssi_db = (s16)odm_convert_to_db(rssi_linear);
2949
2950 if (rssi_t->rssi_acc == 0) {
2951 rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
2952 rssi_t->rssi = (s8)(rssi_db);
2953 } else {
2954 rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
2955 rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
2956 }
2957
2958 if (pktinfo->is_cck_rate)
2959 rssi_t->rssi_cck = (s8)rssi_db;
2960 else
2961 rssi_t->rssi_ofdm = (s8)rssi_db;
2962 }
2963
phydm_rx_physts_2nd_type(void * dm_void,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo,struct phydm_phyinfo_struct * phy_info)2964 void phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts,
2965 struct phydm_perpkt_info_struct *pktinfo,
2966 struct phydm_phyinfo_struct *phy_info)
2967 {
2968 struct dm_struct *dm = (struct dm_struct *)dm_void;
2969 u8 page = (*phy_sts & 0xf);
2970
2971 /* Phy status parsing */
2972 switch (page) {
2973 case 0: /*@CCK*/
2974 phydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info);
2975 break;
2976 case 1:
2977 phydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info);
2978 break;
2979 case 2:
2980 phydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info);
2981 break;
2982 default:
2983 break;
2984 }
2985
2986 #if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
2987 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B))
2988 phydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info);
2989 #endif
2990 }
2991
2992 /*@==============================================*/
2993 #endif
2994
odm_phy_status_query(struct dm_struct * dm,struct phydm_phyinfo_struct * phy_info,u8 * phy_sts,struct phydm_perpkt_info_struct * pktinfo)2995 boolean odm_phy_status_query(struct dm_struct *dm,
2996 struct phydm_phyinfo_struct *phy_info,
2997 u8 *phy_sts,
2998 struct phydm_perpkt_info_struct *pktinfo)
2999 {
3000 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3001 struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
3002 boolean auto_swch_en = dm->pkt_proc_struct.physts_auto_swch_en;
3003 #endif
3004 u8 rate = pktinfo->data_rate;
3005 u8 page = (*phy_sts & 0xf);
3006
3007 pktinfo->is_cck_rate = PHYDM_IS_CCK_RATE(rate);
3008 pktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate);
3009 dm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/
3010
3011 if (pktinfo->is_cck_rate)
3012 dm->phy_dbg_info.num_qry_phy_status_cck++;
3013 else
3014 dm->phy_dbg_info.num_qry_phy_status_ofdm++;
3015
3016 /*Reset phy_info*/
3017 phydm_reset_phy_info(dm, phy_info);
3018
3019 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
3020 #ifdef PHYSTS_3RD_TYPE_SUPPORT
3021 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3022 if (phydm_physts_auto_switch_jgr3(dm, phy_sts, pktinfo)) {
3023 PHYDM_DBG(dm, DBG_PHY_STATUS, "SKIP parsing\n");
3024 phy_info->physts_rpt_valid = false;
3025 return false;
3026 }
3027 #endif
3028 phydm_rx_physts_jgr3(dm, phy_sts, pktinfo, phy_info);
3029 phydm_process_dm_rssi_jgr3(dm, phy_info, pktinfo);
3030 #endif
3031 } else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
3032 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
3033 phydm_rx_physts_2nd_type(dm, phy_sts, pktinfo, phy_info);
3034 phydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo);
3035 #endif
3036 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
3037 #if ODM_IC_11AC_SERIES_SUPPORT
3038 phydm_rx_physts_1st_type(dm, phy_info, phy_sts, pktinfo);
3039 phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
3040 #endif
3041 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
3042 #if ODM_IC_11N_SERIES_SUPPORT
3043 phydm_phy_sts_n_parsing(dm, phy_info, phy_sts, pktinfo);
3044 phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
3045 #endif
3046 }
3047 phy_info->signal_strength = phy_info->rx_pwdb_all;
3048 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3049 phydm_process_signal_strength(dm, phy_info, pktinfo);
3050 #endif
3051
3052 /*For basic debug message*/
3053 if (pktinfo->is_packet_match_bssid || *dm->mp_mode) {
3054 dm->curr_station_id = pktinfo->station_id;
3055 dm->rx_rate = rate;
3056 dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A];
3057 dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B];
3058 dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C];
3059 dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D];
3060
3061 if (rate >= ODM_RATE6M && rate <= ODM_RATE54M)
3062 dm->rxsc_l = (s8)phy_info->rxsc;
3063 else if (phy_info->band_width == CHANNEL_WIDTH_20)
3064 dm->rxsc_20 = (s8)phy_info->rxsc;
3065 else if (phy_info->band_width == CHANNEL_WIDTH_40)
3066 dm->rxsc_40 = (s8)phy_info->rxsc;
3067 else if (phy_info->band_width == CHANNEL_WIDTH_80)
3068 dm->rxsc_80 = (s8)phy_info->rxsc;
3069
3070 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3071 if (auto_swch_en && page == 4 && pktinfo->rate_ss > 1)
3072 phydm_avg_condi_num(dm, phy_info, pktinfo);
3073
3074 if (!auto_swch_en ||
3075 (pkt_proc->is_1st_mpdu || PHYDM_IS_LEGACY_RATE(rate)))
3076 #endif
3077 {
3078 phydm_avg_rssi_evm_snr(dm, phy_info, pktinfo);
3079 phydm_rx_statistic_cal(dm, phy_info, phy_sts, pktinfo);
3080 }
3081 }
3082
3083 phy_info->physts_rpt_valid = true;
3084 return true;
3085 }
3086
phydm_rx_phy_status_init(void * dm_void)3087 void phydm_rx_phy_status_init(void *dm_void)
3088 {
3089 struct dm_struct *dm = (struct dm_struct *)dm_void;
3090 struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
3091
3092 dbg->show_phy_sts_all_pkt = 0;
3093 dbg->show_phy_sts_max_cnt = 1;
3094 dbg->show_phy_sts_cnt = 0;
3095
3096 phydm_avg_phystatus_init(dm);
3097
3098 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3099 dm->pkt_proc_struct.physts_auto_swch_en = false;
3100 #endif
3101 }
3102
phydm_physts_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3103 void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used,
3104 char *output, u32 *_out_len)
3105 {
3106 struct dm_struct *dm = (struct dm_struct *)dm_void;
3107 char help[] = "-h";
3108 boolean enable;
3109 u32 var[10] = {0};
3110 u32 used = *_used;
3111 u32 out_len = *_out_len;
3112 u8 i = 0;
3113
3114 for (i = 0; i < 3; i++) {
3115 if (input[i + 1])
3116 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
3117 }
3118
3119 if ((strcmp(input[1], help) == 0)) {
3120 PDM_SNPF(out_len, used, output + used, out_len - used,
3121 "Page Auto Switching: swh {en} {bitmap(hex)}\n");
3122 } else if ((strcmp(input[1], "swh") == 0)) {
3123 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
3124 PHYDM_SSCANF(input[3], DCMD_HEX, &var[2]);
3125 enable = (boolean)var[1];
3126 phydm_physts_auto_switch_jgr3_set(dm, enable, (u8)var[2]);
3127
3128 PDM_SNPF(out_len, used, output + used, out_len - used,
3129 "Page Auto Switching: en=%d, bitmap=0x%x\n",
3130 enable, var[2]);
3131 #endif
3132 }
3133 *_used = used;
3134 *_out_len = out_len;
3135 }
3136