1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The full GNU General Public License is included in this distribution in the 15*4882a593Smuzhiyun * file called LICENSE. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Contact Information: 18*4882a593Smuzhiyun * wlanfae <wlanfae@realtek.com> 19*4882a593Smuzhiyun * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20*4882a593Smuzhiyun * Hsinchu 300, Taiwan. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Larry Finger <Larry.Finger@lwfinger.net> 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun *****************************************************************************/ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifndef __PHYDMDYNAMICTXPOWER_H__ 27*4882a593Smuzhiyun #define __PHYDMDYNAMICTXPOWER_H__ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #ifdef CONFIG_DYNAMIC_TX_TWR 30*4882a593Smuzhiyun /* @============================================================ 31*4882a593Smuzhiyun * Definition 32*4882a593Smuzhiyun * ============================================================ 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 2019.6.14, Modify per sta API to fix the AP problem of early return*/ 36*4882a593Smuzhiyun #define DYNAMIC_TXPWR_VERSION "2.1" 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define DTP_POWER_LEVEL_SIZE 3 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 41*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 42*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 43*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 44*4882a593Smuzhiyun #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 45*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 46*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 47*4882a593Smuzhiyun #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 48*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 49*4882a593Smuzhiyun #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 53*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 80 54*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 63 55*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 55 56*4882a593Smuzhiyun #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 57*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90 58*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85 59*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80 60*4882a593Smuzhiyun #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 61*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90 62*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85 63*4882a593Smuzhiyun #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define tx_high_pwr_level_normal 0 67*4882a593Smuzhiyun #define tx_high_pwr_level_level1 1 68*4882a593Smuzhiyun #define tx_high_pwr_level_level2 2 69*4882a593Smuzhiyun #define tx_high_pwr_level_level3 3 70*4882a593Smuzhiyun #define tx_high_pwr_level_unchange 4 71*4882a593Smuzhiyun #define DTP_FLOOR_UP_GAP 3 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* @============================================================ 74*4882a593Smuzhiyun * enumrate 75*4882a593Smuzhiyun * ============================================================ 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun enum phydm_dtp_power_offset { 78*4882a593Smuzhiyun PHYDM_OFFSET_ZERO = 0, 79*4882a593Smuzhiyun PHYDM_OFFSET_MINUS_3DB = 1, 80*4882a593Smuzhiyun PHYDM_OFFSET_MINUS_7DB = 2, 81*4882a593Smuzhiyun PHYDM_OFFSET_MINUS_11DB = 3, 82*4882a593Smuzhiyun PHYDM_OFFSET_ADD_3DB = 4, 83*4882a593Smuzhiyun PHYDM_OFFSET_ADD_6DB = 5 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun enum phydm_dtp_power_offset_2nd { 87*4882a593Smuzhiyun PHYDM_2ND_OFFSET_ZERO = 0, 88*4882a593Smuzhiyun PHYDM_2ND_OFFSET_MINUS_3DB = 1, 89*4882a593Smuzhiyun PHYDM_2ND_OFFSET_MINUS_7DB = 2, 90*4882a593Smuzhiyun PHYDM_2ND_OFFSET_MINUS_11DB = 3 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun enum phydm_dtp_power_offset_bbram { 94*4882a593Smuzhiyun /*@ HW min use 1dB*/ 95*4882a593Smuzhiyun PHYDM_BBRAM_OFFSET_ZERO = 0, 96*4882a593Smuzhiyun PHYDM_BBRAM_OFFSET_MINUS_3DB = -3, 97*4882a593Smuzhiyun PHYDM_BBRAM_OFFSET_MINUS_7DB = -7, 98*4882a593Smuzhiyun PHYDM_BBRAM_OFFSET_MINUS_11DB = -11 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun enum phydm_dtp_power_pkt_type { 102*4882a593Smuzhiyun RAM_PWR_OFST0 = 0, 103*4882a593Smuzhiyun RAM_PWR_OFST1 = 1, 104*4882a593Smuzhiyun REG_PWR_OFST0 = 2, 105*4882a593Smuzhiyun REG_PWR_OFST1 = 3 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* @============================================================ 109*4882a593Smuzhiyun * structure 110*4882a593Smuzhiyun * ============================================================ 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* @============================================================ 114*4882a593Smuzhiyun * Function Prototype 115*4882a593Smuzhiyun * ============================================================ 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun extern void 119*4882a593Smuzhiyun odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id); 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun void phydm_dynamic_tx_power(void *dm_void); 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun void phydm_dynamic_tx_power_init(void *dm_void); 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output, 126*4882a593Smuzhiyun u32 *_out_len); 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len); 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en, 131*4882a593Smuzhiyun s8 pwr_ofst); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1, 134*4882a593Smuzhiyun boolean pwr_ofst_en, s8 pwr_ofst); 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 138*4882a593Smuzhiyun void odm_dynamic_tx_power_win(void *dm_void); 139*4882a593Smuzhiyun #endif 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif 142*4882a593Smuzhiyun #endif 143