1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
phydm_rxsc_2_bw(void * dm_void,u8 rxsc)34 enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 enum channel_width bw = 0;
38
39 /* @Check RX bandwidth */
40 if (rxsc == 0)
41 bw = *dm->band_width; /*@full bw*/
42 else if (rxsc >= 1 && rxsc <= 8)
43 bw = CHANNEL_WIDTH_20;
44 else if (rxsc >= 9 && rxsc <= 12)
45 bw = CHANNEL_WIDTH_40;
46 else /*if (rxsc >= 13)*/
47 bw = CHANNEL_WIDTH_80;
48
49 return bw;
50 }
51
phydm_reset_bb_hw_cnt(void * dm_void)52 void phydm_reset_bb_hw_cnt(void *dm_void)
53 {
54 struct dm_struct *dm = (struct dm_struct *)dm_void;
55
56 /*@ Reset all counter when 1 */
57 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
58 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
59 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
60 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
61 /*@ Reset all counter when 1 (including PMAC and PHY)*/
62 /* Reset Page F counter*/
63 odm_set_bb_reg(dm, R_0xb58, BIT(0), 1);
64 odm_set_bb_reg(dm, R_0xb58, BIT(0), 0);
65 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
66 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1);
67 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0);
68 }
69 }
70
phydm_dynamic_ant_weighting(void * dm_void)71 void phydm_dynamic_ant_weighting(void *dm_void)
72 {
73 struct dm_struct *dm = (struct dm_struct *)dm_void;
74
75 #ifdef DYN_ANT_WEIGHTING_SUPPORT
76 #if (RTL8197F_SUPPORT)
77 if (dm->support_ic_type & (ODM_RTL8197F))
78 phydm_dynamic_ant_weighting_8197f(dm);
79 #endif
80
81 #if (RTL8812A_SUPPORT)
82 if (dm->support_ic_type & (ODM_RTL8812)) {
83 phydm_dynamic_ant_weighting_8812a(dm);
84 }
85 #endif
86
87 #if (RTL8822B_SUPPORT)
88 if (dm->support_ic_type & (ODM_RTL8822B))
89 phydm_dynamic_ant_weighting_8822b(dm);
90 #endif
91 #endif
92 }
93
94 #ifdef DYN_ANT_WEIGHTING_SUPPORT
phydm_ant_weight_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)95 void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
96 char *output, u32 *_out_len)
97 {
98 struct dm_struct *dm = (struct dm_struct *)dm_void;
99 char help[] = "-h";
100 u32 var1[10] = {0};
101 u32 used = *_used;
102 u32 out_len = *_out_len;
103
104 if (!(dm->support_ic_type &
105 (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8812 | ODM_RTL8197F))) {
106 return;
107 }
108
109 if ((strcmp(input[1], help) == 0)) {
110 PDM_SNPF(out_len, used, output + used, out_len - used,
111 "echo dis_dym_ant_weighting {0/1}\n");
112
113 } else {
114 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
115
116 if (var1[0] == 1) {
117 dm->is_disable_dym_ant_weighting = 1;
118 PDM_SNPF(out_len, used, output + used, out_len - used,
119 "Disable dyn-ant-weighting\n");
120 } else {
121 dm->is_disable_dym_ant_weighting = 0;
122 PDM_SNPF(out_len, used, output + used, out_len - used,
123 "Enable dyn-ant-weighting\n");
124 }
125 }
126 *_used = used;
127 *_out_len = out_len;
128 }
129 #endif
130
phydm_trx_antenna_setting_init(void * dm_void,u8 num_rf_path)131 void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)
132 {
133 struct dm_struct *dm = (struct dm_struct *)dm_void;
134 u8 rx_ant = 0, tx_ant = 0;
135 u8 path_bitmap = 1;
136
137 path_bitmap = (u8)phydm_gen_bitmask(num_rf_path);
138
139 /*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/
140
141 dm->tx_ant_status = path_bitmap;
142 dm->rx_ant_status = path_bitmap;
143
144 if (num_rf_path == PDM_1SS)
145 return;
146
147 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
148 if (dm->support_ic_type &
149 (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) {
150 dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3);
151 dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3);
152 } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) {
153 dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf);
154 dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf);
155 }
156 #endif
157 /* @trx_ant_status are already updated in trx mode API in JGR3 ICs */
158
159 PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n",
160 __func__, dm->tx_ant_status, dm->rx_ant_status);
161 }
162
phydm_config_ofdm_tx_path(void * dm_void,enum bb_path path)163 void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path)
164 {
165 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT || RTL8812A_SUPPORT)
166 struct dm_struct *dm = (struct dm_struct *)dm_void;
167 u8 ofdm_tx_path = 0x33;
168
169 if (dm->num_rf_path == PDM_1SS)
170 return;
171
172 switch (dm->support_ic_type) {
173 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
174 case ODM_RTL8192E:
175 case ODM_RTL8192F:
176 if (path == BB_PATH_A)
177 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
178 else if (path == BB_PATH_B)
179 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221323);
180 else if (path == BB_PATH_AB)
181 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
182
183 break;
184 #endif
185
186 #if (RTL8812A_SUPPORT)
187 case ODM_RTL8812:
188 if (path == BB_PATH_A)
189 ofdm_tx_path = 0x11;
190 else if (path == BB_PATH_B)
191 ofdm_tx_path = 0x22;
192 else if (path == BB_PATH_AB)
193 ofdm_tx_path = 0x33;
194
195 odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path);
196
197 break;
198 #endif
199
200 default:
201 break;
202 }
203 #endif
204 }
205
phydm_config_ofdm_rx_path(void * dm_void,enum bb_path path)206 void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path)
207 {
208 struct dm_struct *dm = (struct dm_struct *)dm_void;
209 u8 val = 0;
210
211 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8192F)) {
212 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
213 if (path == BB_PATH_A)
214 val = 1;
215 else if (path == BB_PATH_B)
216 val = 2;
217 else if (path == BB_PATH_AB)
218 val = 3;
219
220 odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val));
221 odm_set_bb_reg(dm, R_0xd04, 0xf, val);
222 #endif
223 }
224 #if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
225 else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
226 if (path == BB_PATH_A)
227 val = 1;
228 else if (path == BB_PATH_B)
229 val = 2;
230 else if (path == BB_PATH_AB)
231 val = 3;
232
233 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val));
234 }
235 #endif
236 }
237
phydm_config_cck_rx_antenna_init(void * dm_void)238 void phydm_config_cck_rx_antenna_init(void *dm_void)
239 {
240 struct dm_struct *dm = (struct dm_struct *)dm_void;
241
242 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
243 if (dm->support_ic_type & ODM_IC_1SS)
244 return;
245
246 /*@CCK 2R CCA parameters*/
247 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/
248 odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/
249 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/
250 odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/
251 odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/
252
253 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F))
254 odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/
255 else if (dm->support_ic_type & ODM_RTL8814A)
256 odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/
257 #endif
258 }
259
phydm_config_cck_rx_path(void * dm_void,enum bb_path path)260 void phydm_config_cck_rx_path(void *dm_void, enum bb_path path)
261 {
262 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
263 struct dm_struct *dm = (struct dm_struct *)dm_void;
264 u8 path_div_select = 0;
265 u8 cck_path[2] = {0};
266 u8 en_2R_path = 0;
267 u8 en_2R_mrc = 0;
268 u8 i = 0, j = 0;
269 u8 num_enable_path = 0;
270 u8 cck_mrc_max_path = 2;
271
272 if (dm->support_ic_type & ODM_IC_1SS)
273 return;
274
275 for (i = 0; i < 4; i++) {
276 if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/
277 num_enable_path++;
278 cck_path[j] = i;
279 j++;
280 }
281 if (num_enable_path >= cck_mrc_max_path)
282 break;
283 }
284
285 if (num_enable_path > 1) {
286 path_div_select = 1;
287 en_2R_path = 1;
288 en_2R_mrc = 1;
289 } else {
290 path_div_select = 0;
291 en_2R_path = 0;
292 en_2R_mrc = 0;
293 }
294 /*@CCK_1 input signal path*/
295 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]);
296 /*@CCK_2 input signal path*/
297 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]);
298 /*@enable Rx path diversity*/
299 odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select);
300 /*@enable 2R Rx path*/
301 odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path);
302 /*@enable 2R MRC*/
303 odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc);
304 if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
305 if (path == BB_PATH_A) {
306 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
307 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
308 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
309 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
310 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
311 } else if (path == BB_PATH_B) {/*@for DC cancellation*/
312 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
313 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
314 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
315 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
316 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
317 } else if (path == BB_PATH_AB) {
318 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
319 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
320 odm_set_bb_reg(dm, R_0xa74, BIT(8), 1);
321 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1);
322 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1);
323 }
324 } else if (dm->support_ic_type & ODM_RTL8822B) {
325 if (path == BB_PATH_A) {
326 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
327 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
328 } else {
329 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
330 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
331 }
332 }
333
334 #endif
335 }
336
phydm_config_cck_tx_path(void * dm_void,enum bb_path path)337 void phydm_config_cck_tx_path(void *dm_void, enum bb_path path)
338 {
339 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
340 struct dm_struct *dm = (struct dm_struct *)dm_void;
341
342 if (path == BB_PATH_A)
343 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
344 else if (path == BB_PATH_B)
345 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
346 else /*if (path == BB_PATH_AB)*/
347 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
348 #endif
349 }
350
phydm_config_trx_path_v2(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)351 void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,
352 char *output, u32 *_out_len)
353 {
354 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
355 RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT ||\
356 RTL8812F_SUPPORT || RTL8198F_SUPPORT)
357 struct dm_struct *dm = (struct dm_struct *)dm_void;
358 u32 used = *_used;
359 u32 out_len = *_out_len;
360 u32 val[10] = {0};
361 char help[] = "-h";
362 u8 i = 0, input_idx = 0;
363 enum bb_path tx_path, rx_path, tx_path_ctrl;
364 boolean dbg_mode_en;
365
366 if (!(dm->support_ic_type &
367 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C |
368 ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8198F)))
369 return;
370
371 for (i = 0; i < 5; i++) {
372 if (input[i + 1]) {
373 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
374 input_idx++;
375 }
376 }
377
378 if (input_idx == 0)
379 return;
380
381 dbg_mode_en = (boolean)val[0];
382 tx_path = (enum bb_path)val[1];
383 rx_path = (enum bb_path)val[2];
384 tx_path_ctrl = (enum bb_path)val[3];
385
386 if ((strcmp(input[1], help) == 0)) {
387 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8822B |
388 ODM_RTL8192F)) {
389 PDM_SNPF(out_len, used, output + used, out_len - used,
390 "{en} {tx_path} {rx_path} {ff:auto, else:1ss_tx_path}\n"
391 );
392 } else {
393 PDM_SNPF(out_len, used, output + used, out_len - used,
394 "{en} {tx_path} {rx_path} {is_tx_2_path}\n");
395 }
396
397 } else if (dbg_mode_en) {
398 dm->is_disable_phy_api = false;
399 phydm_api_trx_mode(dm, tx_path, rx_path, tx_path_ctrl);
400 dm->is_disable_phy_api = true;
401 PDM_SNPF(out_len, used, output + used, out_len - used,
402 "T/RX path = 0x%x/0x%x, tx_path_ctrl=%d\n",
403 tx_path, rx_path, tx_path_ctrl);
404 PDM_SNPF(out_len, used, output + used, out_len - used,
405 "T/RX path_en={0x%x, 0x%x}, tx_1ss=%d\n",
406 dm->tx_ant_status, dm->rx_ant_status,
407 dm->tx_1ss_status);
408 } else {
409 dm->is_disable_phy_api = false;
410 PDM_SNPF(out_len, used, output + used, out_len - used,
411 "Disable API debug mode\n");
412 }
413 #endif
414 }
415
phydm_config_trx_path_v1(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)416 void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used,
417 char *output, u32 *_out_len)
418 {
419 #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
420 struct dm_struct *dm = (struct dm_struct *)dm_void;
421 u32 used = *_used;
422 u32 out_len = *_out_len;
423 u32 val[10] = {0};
424 char help[] = "-h";
425 u8 i = 0, input_idx = 0;
426
427 if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)))
428 return;
429
430 for (i = 0; i < 5; i++) {
431 if (input[i + 1]) {
432 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
433 input_idx++;
434 }
435 }
436
437 if (input_idx == 0)
438 return;
439
440 if ((strcmp(input[1], help) == 0)) {
441 PDM_SNPF(out_len, used, output + used, out_len - used,
442 "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n");
443
444 *_used = used;
445 *_out_len = out_len;
446 return;
447
448 } else if (val[0] == 0) {
449 /* @CCK */
450 if (val[1] == 1) { /*TX*/
451 if (val[2] == 1)
452 phydm_config_cck_tx_path(dm, BB_PATH_A);
453 else if (val[2] == 2)
454 phydm_config_cck_tx_path(dm, BB_PATH_B);
455 else if (val[2] == 3)
456 phydm_config_cck_tx_path(dm, BB_PATH_AB);
457 } else if (val[1] == 2) { /*RX*/
458
459 phydm_config_cck_rx_antenna_init(dm);
460
461 if (val[2] == 1)
462 phydm_config_cck_rx_path(dm, BB_PATH_A);
463 else if (val[2] == 2)
464 phydm_config_cck_rx_path(dm, BB_PATH_B);
465 else if (val[2] == 3)
466 phydm_config_cck_rx_path(dm, BB_PATH_AB);
467 }
468 }
469 /* OFDM */
470 else if (val[0] == 1) {
471 if (val[1] == 1) /*TX*/
472 phydm_config_ofdm_tx_path(dm, val[2]);
473 else if (val[1] == 2) /*RX*/
474 phydm_config_ofdm_rx_path(dm, val[2]);
475 }
476
477 PDM_SNPF(out_len, used, output + used, out_len - used,
478 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
479 (val[0] == 1) ? "OFDM" : "CCK",
480 (val[1] == 1) ? "TX" : "RX",
481 (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "",
482 (val[2] & 0x4) ? "C" : "",
483 (val[2] & 0x8) ? "D" : "");
484
485 *_used = used;
486 *_out_len = out_len;
487 #endif
488 }
489
phydm_config_trx_path(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)490 void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
491 char *output, u32 *_out_len)
492 {
493 struct dm_struct *dm = (struct dm_struct *)dm_void;
494
495 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
496 #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
497 phydm_config_trx_path_v1(dm, input, _used, output, _out_len);
498 #endif
499 } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F |
500 ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |
501 ODM_RTL8197G | ODM_RTL8814B | ODM_RTL8198F)) {
502 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\
503 RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
504 RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
505 RTL8197G_SUPPORT || RTL8198F_SUPPORT)
506 phydm_config_trx_path_v2(dm, input, _used, output, _out_len);
507 #endif
508 }
509 }
510
phydm_tx_2path(void * dm_void)511 void phydm_tx_2path(void *dm_void)
512 {
513 #if (defined(PHYDM_COMPILE_IC_2SS))
514 struct dm_struct *dm = (struct dm_struct *)dm_void;
515 enum bb_path rx_path = (enum bb_path)dm->rx_ant_status;
516
517 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
518
519
520 if (!(dm->support_ic_type & ODM_IC_2SS))
521 return;
522
523 #if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT ||\
524 RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
525 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |
526 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
527 phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, BB_PATH_AB);
528 #endif
529
530 #if (RTL8812A_SUPPORT || RTL8192E_SUPPORT)
531 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
532 phydm_config_cck_tx_path(dm, BB_PATH_AB);
533 phydm_config_ofdm_tx_path(dm, BB_PATH_AB);
534 }
535 #endif
536 #endif
537 }
538
phydm_stop_3_wire(void * dm_void,u8 set_type)539 void phydm_stop_3_wire(void *dm_void, u8 set_type)
540 {
541 struct dm_struct *dm = (struct dm_struct *)dm_void;
542
543 if (set_type == PHYDM_SET) {
544 /*@[Stop 3-wires]*/
545 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
546 odm_set_bb_reg(dm, R_0x180c, 0x3, 0x0);
547 odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
548
549 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
550 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
551 odm_set_bb_reg(dm, R_0x410c, 0x3, 0x0);
552 odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
553 }
554 #endif
555
556 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
557 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
558 odm_set_bb_reg(dm, R_0x520c, 0x3, 0x0);
559 odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
560 odm_set_bb_reg(dm, R_0x530c, 0x3, 0x0);
561 odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
562 }
563 #endif
564 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
565 odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4);
566 odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4);
567 } else {
568 odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf);
569 }
570
571 } else { /*@if (set_type == PHYDM_REVERT)*/
572
573 /*@[Start 3-wires]*/
574 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
575 odm_set_bb_reg(dm, R_0x180c, 0x3, 0x3);
576 odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
577
578 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
579 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
580 odm_set_bb_reg(dm, R_0x410c, 0x3, 0x3);
581 odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
582 }
583 #endif
584
585 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
586 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
587 odm_set_bb_reg(dm, R_0x520c, 0x3, 0x3);
588 odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
589 odm_set_bb_reg(dm, R_0x530c, 0x3, 0x3);
590 odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
591 }
592 #endif
593 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
594 odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7);
595 odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7);
596 } else {
597 odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0);
598 }
599 }
600 }
601
phydm_stop_ic_trx(void * dm_void,u8 set_type)602 u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
603 {
604 struct dm_struct *dm = (struct dm_struct *)dm_void;
605 struct phydm_api_stuc *api = &dm->api_table;
606 u8 i = 0;
607 boolean trx_idle_success = false;
608 u32 dbg_port_value = 0;
609
610 if (set_type == PHYDM_SET) {
611 /*[Stop TRX]---------------------------------------------------------*/
612 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
613 for (i = 0; i < 100; i++) {
614 dbg_port_value = odm_get_bb_reg(dm, R_0x2db4,
615 MASKDWORD);
616 /* BB idle */
617 if ((dbg_port_value & 0x1FFEFF3F) == 0 &&
618 (dbg_port_value & 0xC0010000) ==
619 0xC0010000) {
620 PHYDM_DBG(dm, ODM_COMP_API,
621 "Stop trx wait for (%d) times\n",
622 i);
623
624 trx_idle_success = true;
625 break;
626 }
627 }
628 } else {
629 /*set debug port to 0x0*/
630 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
631 return PHYDM_SET_FAIL;
632 for (i = 0; i < 100; i++) {
633 dbg_port_value = phydm_get_bb_dbg_port_val(dm);
634 /* PHYTXON && CCA_all */
635 if (dm->support_ic_type & (ODM_RTL8721D |
636 ODM_RTL8710B | ODM_RTL8710C |
637 ODM_RTL8188F | ODM_RTL8723D)) {
638 if ((dbg_port_value &
639 (BIT(20) | BIT(15))) == 0) {
640 PHYDM_DBG(dm, ODM_COMP_API,
641 "Stop trx wait for (%d) times\n",
642 i);
643
644 trx_idle_success = true;
645 break;
646 }
647 } else {
648 if ((dbg_port_value &
649 (BIT(17) | BIT(3))) == 0) {
650 PHYDM_DBG(dm, ODM_COMP_API,
651 "Stop trx wait for (%d) times\n",
652 i);
653
654 trx_idle_success = true;
655 break;
656 }
657 }
658 ODM_delay_ms(1);
659 }
660 phydm_release_bb_dbg_port(dm);
661 }
662
663 if (trx_idle_success) {
664 api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);
665
666 /*pause all TX queue*/
667 odm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff);
668
669 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
670 /*disable OFDM RX CCA*/
671 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
672 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
673 /*disable OFDM RX CCA*/
674 odm_set_bb_reg(dm, R_0x838, BIT(1), 1);
675 } else {
676 api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);
677 api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);
678 /* [ Set IQK Matrix = 0 ]
679 * equivalent to [ Turn off CCA]
680 */
681 odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);
682 odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0);
683 }
684 phydm_dis_cck_trx(dm, PHYDM_SET);
685 } else {
686 return PHYDM_SET_FAIL;
687 }
688
689 return PHYDM_SET_SUCCESS;
690
691 } else { /*@if (set_type == PHYDM_REVERT)*/
692 /*Release all TX queue*/
693 odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap);
694
695 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
696 /*@enable OFDM RX CCA*/
697 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
698 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
699 /*@enable OFDM RX CCA*/
700 odm_set_bb_reg(dm, R_0x838, BIT(1), 0);
701 } else {
702 /* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/
703 odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1);
704 odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2);
705 }
706 phydm_dis_cck_trx(dm, PHYDM_REVERT);
707 return PHYDM_SET_SUCCESS;
708 }
709 }
710
phydm_dis_cck_trx(void * dm_void,u8 set_type)711 void phydm_dis_cck_trx(void *dm_void, u8 set_type)
712 {
713 struct dm_struct *dm = (struct dm_struct *)dm_void;
714 struct phydm_api_stuc *api = &dm->api_table;
715
716 if (set_type == PHYDM_SET) {
717 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
718 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,
719 0xf0000000);
720 /* @CCK RxIQ weighting = [0,0] */
721 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
722 /* @disable CCK Tx */
723 odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);
724 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
725 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
726 0xf0000000);
727 /* @disable CCK block */
728 odm_set_bb_reg(dm, R_0x808, BIT(28), 0);
729 /* @disable CCK Tx */
730 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
731 } else {
732 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
733 0xf0000000);
734 /* @disable whole CCK block */
735 odm_set_bb_reg(dm, R_0x800, BIT(24), 0);
736 /* @disable CCK Tx */
737 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
738 }
739 } else if (set_type == PHYDM_REVERT) {
740 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
741 /* @CCK RxIQ weighting = [1,1] */
742 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
743 /* @enable CCK Tx */
744 odm_set_bb_reg(dm, R_0x1a04, 0xf0000000,
745 api->ccktx_path);
746 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
747 /* @enable CCK block */
748 odm_set_bb_reg(dm, R_0x808, BIT(28), 1);
749 /* @enable CCK Tx */
750 odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
751 api->ccktx_path);
752 } else {
753 /* @enable whole CCK block */
754 odm_set_bb_reg(dm, R_0x800, BIT(24), 1);
755 /* @enable CCK Tx */
756 odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
757 api->ccktx_path);
758 }
759 }
760 }
761
phydm_bw_fixed_enable(void * dm_void,u8 enable)762 void phydm_bw_fixed_enable(void *dm_void, u8 enable)
763 {
764 #ifdef CONFIG_BW_INDICATION
765 struct dm_struct *dm = (struct dm_struct *)dm_void;
766 boolean val = (enable == FUNC_ENABLE) ? 1 : 0;
767
768 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B))
769 odm_set_bb_reg(dm, R_0x840, BIT(4), val);
770 else if (dm->support_ic_type & ODM_RTL8822C)
771 odm_set_bb_reg(dm, R_0x878, BIT(28), val);
772 #endif
773 }
774
phydm_bw_fixed_setting(void * dm_void)775 void phydm_bw_fixed_setting(void *dm_void)
776 {
777 #ifdef CONFIG_BW_INDICATION
778 struct dm_struct *dm = (struct dm_struct *)dm_void;
779 struct phydm_api_stuc *api = &dm->api_table;
780 u8 bw = *dm->band_width;
781 u32 reg = 0, reg_mask = 0, reg_value = 0;
782
783 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
784 return;
785
786 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
787 ODM_RTL8195B)) {
788 reg = R_0x840;
789 reg_mask = 0xf;
790 reg_value = api->pri_ch_idx;
791 } else if (dm->support_ic_type & ODM_RTL8822C) {
792 reg = R_0x878;
793 reg_mask = 0xc0000000;
794 reg_value = 0x0;
795 }
796
797 switch (bw) {
798 case CHANNEL_WIDTH_80:
799 odm_set_bb_reg(dm, reg, reg_mask, reg_value);
800 break;
801 case CHANNEL_WIDTH_40:
802 odm_set_bb_reg(dm, reg, reg_mask, reg_value);
803 break;
804 default:
805 odm_set_bb_reg(dm, reg, reg_mask, 0x0);
806 }
807
808 phydm_bw_fixed_enable(dm, FUNC_ENABLE);
809 #endif
810 }
811
phydm_set_ext_switch(void * dm_void,u32 ext_ant_switch)812 void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)
813 {
814 #if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
815 struct dm_struct *dm = (struct dm_struct *)dm_void;
816
817 if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)))
818 return;
819
820 /*Output Pin Settings*/
821
822 /*select DPDT_P and DPDT_N as output pin*/
823 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
824
825 /*@by WLAN control*/
826 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
827
828 /*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/
829 odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77);
830
831 if (ext_ant_switch == 1) { /*@2b'01*/
832 odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1);
833 PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n");
834 } else if (ext_ant_switch == 2) { /*@2b'10*/
835 odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2);
836 PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n");
837 }
838 #endif
839 }
840
phydm_csi_mask_enable(void * dm_void,u32 enable)841 void phydm_csi_mask_enable(void *dm_void, u32 enable)
842 {
843 struct dm_struct *dm = (struct dm_struct *)dm_void;
844 boolean en = false;
845
846 en = (enable == FUNC_ENABLE) ? true : false;
847
848 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
849 odm_set_bb_reg(dm, R_0xd2c, BIT(28), en);
850 PHYDM_DBG(dm, ODM_COMP_API,
851 "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", en);
852 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
853 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
854 odm_set_bb_reg(dm, R_0xc0c, BIT(3), en);
855 PHYDM_DBG(dm, ODM_COMP_API,
856 "Enable CSI Mask: Reg 0xc0c[3] = ((0x%x))\n", en);
857 #endif
858 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
859 odm_set_bb_reg(dm, R_0x874, BIT(0), en);
860 PHYDM_DBG(dm, ODM_COMP_API,
861 "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", en);
862 }
863 }
864
phydm_clean_all_csi_mask(void * dm_void)865 void phydm_clean_all_csi_mask(void *dm_void)
866 {
867 struct dm_struct *dm = (struct dm_struct *)dm_void;
868
869 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
870 odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0);
871 odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0);
872 odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0);
873 odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0);
874 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
875 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
876 u8 i = 0, idx_lmt = 0;
877
878 if (dm->support_ic_type &
879 (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
880 idx_lmt = 127;
881 else /*@for IC supporting 80 + 80*/
882 idx_lmt = 255;
883
884 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
885 odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
886 for (i = 0; i < idx_lmt; i++) {
887 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i);
888 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0);
889 }
890 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
891 #endif
892 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
893 odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);
894 odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);
895 odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);
896 odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);
897 odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);
898 odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);
899 odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);
900 odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);
901 }
902 }
903
phydm_set_csi_mask(void * dm_void,u32 tone_idx_tmp,u8 tone_direction)904 void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction)
905 {
906 struct dm_struct *dm = (struct dm_struct *)dm_void;
907 u8 byte_offset = 0, bit_offset = 0;
908 u32 target_reg = 0;
909 u8 reg_tmp_value = 0;
910 u32 tone_num = 64;
911 u32 tone_num_shift = 0;
912 u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
913
914 /* @calculate real tone idx*/
915 if ((tone_idx_tmp % 10) >= 5)
916 tone_idx_tmp += 10;
917
918 tone_idx_tmp = (tone_idx_tmp / 10);
919
920 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
921 tone_num = 64;
922 csi_mask_reg_p = 0xD40;
923 csi_mask_reg_n = 0xD48;
924
925 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
926 tone_num = 128;
927 csi_mask_reg_p = 0x880;
928 csi_mask_reg_n = 0x890;
929 }
930
931 if (tone_direction == FREQ_POSITIVE) {
932 if (tone_idx_tmp >= (tone_num - 1))
933 tone_idx_tmp = (tone_num - 1);
934
935 byte_offset = (u8)(tone_idx_tmp >> 3);
936 bit_offset = (u8)(tone_idx_tmp & 0x7);
937 target_reg = csi_mask_reg_p + byte_offset;
938
939 } else {
940 tone_num_shift = tone_num;
941
942 if (tone_idx_tmp >= tone_num)
943 tone_idx_tmp = tone_num;
944
945 tone_idx_tmp = tone_num - tone_idx_tmp;
946
947 byte_offset = (u8)(tone_idx_tmp >> 3);
948 bit_offset = (u8)(tone_idx_tmp & 0x7);
949 target_reg = csi_mask_reg_n + byte_offset;
950 }
951
952 reg_tmp_value = odm_read_1byte(dm, target_reg);
953 PHYDM_DBG(dm, ODM_COMP_API,
954 "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
955 (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
956 reg_tmp_value |= BIT(bit_offset);
957 odm_write_1byte(dm, target_reg, reg_tmp_value);
958 PHYDM_DBG(dm, ODM_COMP_API,
959 "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
960 (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
961 }
962
phydm_set_nbi_reg(void * dm_void,u32 tone_idx_tmp,u32 bw)963 void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
964 {
965 struct dm_struct *dm = (struct dm_struct *)dm_void;
966 /*tone_idx X 10*/
967 u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135,
968 155, 185, 205, 225, 245,
969 265, 285, 305, 335, 355,
970 375, 395, 415, 435, 455,
971 485, 505, 525, 555, 585, 615, 635};
972 /*tone_idx X 10*/
973 u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135,
974 155, 175, 195, 225, 245,
975 265, 285, 305, 325, 345,
976 365, 385, 405, 425, 445,
977 465, 485, 505, 525, 545,
978 565, 585, 605, 625, 645,
979 665, 695, 715, 735, 755,
980 775, 795, 815, 835, 855,
981 875, 895, 915, 935, 955,
982 975, 995, 1015, 1035, 1055,
983 1085, 1105, 1125, 1145, 1175,
984 1195, 1225, 1255, 1275};
985 u32 reg_idx = 0;
986 u32 i;
987 u8 nbi_table_idx = FFT_128_TYPE;
988
989 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
990 nbi_table_idx = FFT_128_TYPE;
991 } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
992 nbi_table_idx = FFT_256_TYPE;
993 } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
994 if (bw == 80)
995 nbi_table_idx = FFT_256_TYPE;
996 else /*@20M, 40M*/
997 nbi_table_idx = FFT_128_TYPE;
998 }
999
1000 if (nbi_table_idx == FFT_128_TYPE) {
1001 for (i = 0; i < NBI_128TONE; i++) {
1002 if (tone_idx_tmp < nbi_128[i]) {
1003 reg_idx = i + 1;
1004 break;
1005 }
1006 }
1007
1008 } else if (nbi_table_idx == FFT_256_TYPE) {
1009 for (i = 0; i < NBI_256TONE; i++) {
1010 if (tone_idx_tmp < nbi_256[i]) {
1011 reg_idx = i + 1;
1012 break;
1013 }
1014 }
1015 }
1016
1017 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1018 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx);
1019 PHYDM_DBG(dm, ODM_COMP_API,
1020 "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n",
1021 reg_idx);
1022 } else {
1023 odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx);
1024 PHYDM_DBG(dm, ODM_COMP_API,
1025 "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
1026 reg_idx);
1027 }
1028 }
1029
phydm_nbi_enable(void * dm_void,u32 enable)1030 void phydm_nbi_enable(void *dm_void, u32 enable)
1031 {
1032 struct dm_struct *dm = (struct dm_struct *)dm_void;
1033 u32 val = 0;
1034
1035 val = (enable == FUNC_ENABLE) ? 1 : 0;
1036
1037 PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
1038
1039 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1040 if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
1041 val = (enable == FUNC_ENABLE) ? 0xf : 0;
1042 odm_set_bb_reg(dm, R_0xc50, 0xf000000, val);
1043 } else {
1044 odm_set_bb_reg(dm, R_0xc40, BIT(9), val);
1045 }
1046 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1047 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
1048 ODM_RTL8195B)) {
1049 odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
1050 odm_set_bb_reg(dm, R_0xc20, BIT(28), val);
1051 if (dm->rf_type > RF_1T1R)
1052 odm_set_bb_reg(dm, R_0xe20, BIT(28), val);
1053 } else {
1054 odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
1055 }
1056 }
1057 }
1058
phydm_find_fc(void * dm_void,u32 channel,u32 bw,u32 second_ch,u32 * fc_in)1059 u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in)
1060 {
1061 struct dm_struct *dm = (struct dm_struct *)dm_void;
1062 u32 fc = *fc_in;
1063 u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100,
1064 108, 116, 124, 132, 140,
1065 149, 157, 165, 173};
1066 u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132,
1067 149, 165};
1068 u32 *start_ch = &start_ch_per_40m[0];
1069 u32 num_start_channel = NUM_START_CH_40M;
1070 u32 channel_offset = 0;
1071 u32 i;
1072
1073 /*@2.4G*/
1074 if (channel <= 14 && channel > 0) {
1075 if (bw == 80)
1076 return PHYDM_SET_FAIL;
1077
1078 fc = 2412 + (channel - 1) * 5;
1079
1080 if (bw == 40 && second_ch == PHYDM_ABOVE) {
1081 if (channel >= 10) {
1082 PHYDM_DBG(dm, ODM_COMP_API,
1083 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1084 channel, second_ch);
1085 return PHYDM_SET_FAIL;
1086 }
1087 fc += 10;
1088 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
1089 if (channel <= 2) {
1090 PHYDM_DBG(dm, ODM_COMP_API,
1091 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1092 channel, second_ch);
1093 return PHYDM_SET_FAIL;
1094 }
1095 fc -= 10;
1096 }
1097 }
1098 /*@5G*/
1099 else if (channel >= 36 && channel <= 177) {
1100 if (bw != 20) {
1101 if (bw == 40) {
1102 num_start_channel = NUM_START_CH_40M;
1103 start_ch = &start_ch_per_40m[0];
1104 channel_offset = CH_OFFSET_40M;
1105 } else if (bw == 80) {
1106 num_start_channel = NUM_START_CH_80M;
1107 start_ch = &start_ch_per_80m[0];
1108 channel_offset = CH_OFFSET_80M;
1109 }
1110
1111 for (i = 0; i < (num_start_channel - 1); i++) {
1112 if (channel < start_ch[i + 1]) {
1113 channel = start_ch[i] + channel_offset;
1114 break;
1115 }
1116 }
1117 PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n",
1118 channel);
1119 }
1120
1121 fc = 5180 + (channel - 36) * 5;
1122
1123 } else {
1124 PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
1125 channel);
1126 return PHYDM_SET_FAIL;
1127 }
1128
1129 *fc_in = fc;
1130
1131 return PHYDM_SET_SUCCESS;
1132 }
1133
phydm_find_intf_distance(void * dm_void,u32 bw,u32 fc,u32 f_interference,u32 * tone_idx_tmp_in)1134 u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference,
1135 u32 *tone_idx_tmp_in)
1136 {
1137 struct dm_struct *dm = (struct dm_struct *)dm_void;
1138 u32 bw_up = 0, bw_low = 0;
1139 u32 int_distance = 0;
1140 u32 tone_idx_tmp = 0;
1141 u8 set_result = PHYDM_SET_NO_NEED;
1142
1143 bw_up = fc + bw / 2;
1144 bw_low = fc - bw / 2;
1145
1146 PHYDM_DBG(dm, ODM_COMP_API,
1147 "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1148 fc, bw_up, f_interference);
1149
1150 if (f_interference >= bw_low && f_interference <= bw_up) {
1151 int_distance = DIFF_2(fc, f_interference);
1152 /*@10*(int_distance /0.3125)*/
1153 tone_idx_tmp = (int_distance << 5);
1154 PHYDM_DBG(dm, ODM_COMP_API,
1155 "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
1156 int_distance, tone_idx_tmp / 10,
1157 tone_idx_tmp % 10);
1158 *tone_idx_tmp_in = tone_idx_tmp;
1159 set_result = PHYDM_SET_SUCCESS;
1160 }
1161
1162 return set_result;
1163 }
1164
phydm_csi_mask_setting(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch)1165 u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,
1166 u32 f_intf, u32 sec_ch)
1167 {
1168 struct dm_struct *dm = (struct dm_struct *)dm_void;
1169 u32 fc = 2412;
1170 u8 direction = FREQ_POSITIVE;
1171 u32 tone_idx = 0;
1172 u8 set_result = PHYDM_SET_SUCCESS;
1173 u8 rpt = 0;
1174
1175 if (enable == FUNC_DISABLE) {
1176 set_result = PHYDM_SET_SUCCESS;
1177 phydm_clean_all_csi_mask(dm);
1178
1179 } else {
1180 PHYDM_DBG(dm, ODM_COMP_API,
1181 "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1182 ch, bw, f_intf,
1183 (((bw == 20) || (ch > 14)) ? "Don't care" :
1184 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
1185
1186 /*@calculate fc*/
1187 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1188 set_result = PHYDM_SET_FAIL;
1189 } else {
1190 /*@calculate interference distance*/
1191 rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
1192 &tone_idx);
1193 if (rpt == PHYDM_SET_SUCCESS) {
1194 if (f_intf >= fc)
1195 direction = FREQ_POSITIVE;
1196 else
1197 direction = FREQ_NEGATIVE;
1198
1199 phydm_set_csi_mask(dm, tone_idx, direction);
1200 set_result = PHYDM_SET_SUCCESS;
1201 } else {
1202 set_result = PHYDM_SET_NO_NEED;
1203 }
1204 }
1205 }
1206
1207 if (set_result == PHYDM_SET_SUCCESS)
1208 phydm_csi_mask_enable(dm, enable);
1209 else
1210 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1211
1212 return set_result;
1213 }
1214
phydm_spur_case_mapping(void * dm_void)1215 boolean phydm_spur_case_mapping(void *dm_void)
1216 {
1217 struct dm_struct *dm = (struct dm_struct *)dm_void;
1218 u8 channel = *dm->channel, bw = *dm->band_width;
1219 boolean mapping_result = false;
1220 #if (RTL8814B_SUPPORT == 1)
1221 if (channel == 153 && bw == CHANNEL_WIDTH_20) {
1222 odm_set_bb_reg(dm, R_0x804, BIT(31), 0);
1223 odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 0);
1224 mapping_result = true;
1225 } else if (channel == 151 && bw == CHANNEL_WIDTH_40) {
1226 odm_set_bb_reg(dm, R_0x804, BIT(31), 0);
1227 odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 0);
1228 mapping_result = true;
1229 } else if (channel == 155 && bw == CHANNEL_WIDTH_80) {
1230 odm_set_bb_reg(dm, R_0x804, BIT(31), 0);
1231 odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 0);
1232 mapping_result = true;
1233 } else {
1234 odm_set_bb_reg(dm, R_0x804, BIT(31), 1);
1235 odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 1);
1236 }
1237 #endif
1238 return mapping_result;
1239 }
1240
1241 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_rf_psd_jgr3(void * dm_void,u8 path,u32 tone_idx)1242 u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx)
1243 {
1244 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
1245 struct dm_struct *dm = (struct dm_struct *)dm_void;
1246 u32 reg_1b04 = 0, reg_1b08 = 0, reg_1b0c_11_10 = 0;
1247 u32 reg_1b14 = 0, reg_1b18 = 0, reg_1b1c = 0;
1248 u32 reg_1b28 = 0;
1249 u32 reg_1bcc_5_0 = 0;
1250 u32 reg_1b2c_27_16 = 0, reg_1b34 = 0, reg_1bd4 = 0;
1251 u32 reg_180c = 0, reg_410c = 0, reg_520c = 0, reg_530c = 0;
1252 u32 igi = 0;
1253 u32 i = 0;
1254 u32 psd_val = 0, psd_val_msb = 0, psd_val_lsb = 0, psd_max = 0;
1255 u32 psd_status_temp = 0;
1256 u16 poll_cnt = 0;
1257
1258 /*read and record the ori. value*/
1259 reg_1b04 = odm_get_bb_reg(dm, R_0x1b04, MASKDWORD);
1260 reg_1b08 = odm_get_bb_reg(dm, R_0x1b08, MASKDWORD);
1261 reg_1b0c_11_10 = odm_get_bb_reg(dm, R_0x1b0c, 0xc00);
1262 reg_1b14 = odm_get_bb_reg(dm, R_0x1b14, MASKDWORD);
1263 reg_1b18 = odm_get_bb_reg(dm, R_0x1b18, MASKDWORD);
1264 reg_1b1c = odm_get_bb_reg(dm, R_0x1b1c, MASKDWORD);
1265 reg_1b28 = odm_get_bb_reg(dm, R_0x1b28, MASKDWORD);
1266 reg_1bcc_5_0 = odm_get_bb_reg(dm, R_0x1bcc, 0x3f);
1267 reg_1b2c_27_16 = odm_get_bb_reg(dm, R_0x1b2c, 0xfff0000);
1268 reg_1b34 = odm_get_bb_reg(dm, R_0x1b34, MASKDWORD);
1269 reg_1bd4 = odm_get_bb_reg(dm, R_0x1bd4, MASKDWORD);
1270 igi = odm_get_bb_reg(dm, R_0x1d70, MASKDWORD);
1271 reg_180c = odm_get_bb_reg(dm, R_0x180c, 0x3);
1272 reg_410c = odm_get_bb_reg(dm, R_0x410c, 0x3);
1273 reg_520c = odm_get_bb_reg(dm, R_0x520c, 0x3);
1274 reg_530c = odm_get_bb_reg(dm, R_0x530c, 0x3);
1275
1276 /*rf psd reg setting*/
1277 odm_set_bb_reg(dm, R_0x1b00, 0x6, path); /*path is RF_path*/
1278 odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x0);
1279 odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x80);
1280 odm_set_bb_reg(dm, R_0x1b0c, 0xc00, 0x3);
1281 odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, 0x0);
1282 odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, 0x1);
1283 /*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
1284 odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x82103D21);
1285 /*#else*/
1286 /*odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x821A3D21);*/
1287 /*#endif*/
1288 odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, 0x0);
1289 odm_set_bb_reg(dm, R_0x1bcc, 0x3f, 0x3f);
1290 odm_set_bb_reg(dm, R_0x8a0, 0xf, 0x0); /* AGC off */
1291 odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, 0x20202020);
1292
1293 for (i = tone_idx - 1; i <= tone_idx + 1; i++) {
1294 /*set psd tone_idx for detection*/
1295 odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, i);
1296 /*one shot for RXIQK psd*/
1297 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
1298 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
1299
1300 if (dm->support_ic_type & ODM_RTL8814B)
1301 for (poll_cnt = 0; poll_cnt < 20; poll_cnt++) {
1302 odm_set_bb_reg(dm, R_0x1bd4, 0x3f0000, 0x2b);
1303 psd_status_temp = odm_get_bb_reg(dm, R_0x1bfc,
1304 BIT(1));
1305 if (!psd_status_temp)
1306 ODM_delay_us(10);
1307 else
1308 break;
1309 }
1310 else
1311 ODM_delay_us(250);
1312
1313 /*read RxIQK power*/
1314 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
1315 if (dm->support_ic_type & ODM_RTL8814B)
1316 psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x7ff0000);
1317 else if (dm->support_ic_type & ODM_RTL8198F)
1318 psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x1f0000);
1319
1320 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
1321 psd_val_lsb = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
1322 if (dm->support_ic_type & ODM_RTL8814B)
1323 psd_val = (psd_val_msb << 21) + (psd_val_lsb >> 11);
1324 else if (dm->support_ic_type & ODM_RTL8198F)
1325 psd_val = (psd_val_msb << 27) + (psd_val_lsb >> 5);
1326
1327 if (psd_val > psd_max)
1328 psd_max = psd_val;
1329 }
1330
1331 /*refill the ori. value*/
1332 odm_set_bb_reg(dm, R_0x1b00, 0x6, path);
1333 odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, reg_1b04);
1334 odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, reg_1b08);
1335 odm_set_bb_reg(dm, R_0x1b0c, 0xc00, reg_1b0c_11_10);
1336 odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, reg_1b14);
1337 odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, reg_1b18);
1338 odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, reg_1b1c);
1339 odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, reg_1b28);
1340 odm_set_bb_reg(dm, R_0x1bcc, 0x3f, reg_1bcc_5_0);
1341 odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, reg_1b2c_27_16);
1342 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, reg_1b34);
1343 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, reg_1bd4);
1344 odm_set_bb_reg(dm, R_0x8a0, 0xf, 0xf); /* AGC on */
1345 odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, igi);
1346 PHYDM_DBG(dm, ODM_COMP_API, "psd_max %d\n", psd_max);
1347
1348 return psd_max;
1349 #else
1350 return 0;
1351 #endif
1352 }
1353
phydm_find_intf_distance_jgr3(void * dm_void,u32 bw,u32 fc,u32 f_interference,u32 * tone_idx_tmp_in)1354 u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
1355 u32 f_interference, u32 *tone_idx_tmp_in)
1356 {
1357 struct dm_struct *dm = (struct dm_struct *)dm_void;
1358 u32 bw_up = 0, bw_low = 0;
1359 u32 int_distance = 0;
1360 u32 tone_idx_tmp = 0;
1361 u8 set_result = PHYDM_SET_NO_NEED;
1362 u8 channel = *dm->channel;
1363
1364 bw_up = 1000 * (fc + bw / 2);
1365 bw_low = 1000 * (fc - bw / 2);
1366 fc = 1000 * fc;
1367
1368 PHYDM_DBG(dm, ODM_COMP_API,
1369 "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1370 fc, bw_up, f_interference);
1371
1372 if (f_interference >= bw_low && f_interference <= bw_up) {
1373 int_distance = DIFF_2(fc, f_interference);
1374 /*@10*(int_distance /0.3125)*/
1375 if (channel < 15 &&
1376 (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F)))
1377 tone_idx_tmp = int_distance / 312;
1378 else
1379 tone_idx_tmp = ((int_distance + 156) / 312);
1380 PHYDM_DBG(dm, ODM_COMP_API,
1381 "int_distance = ((%d)) , tone_idx_tmp = ((%d))\n",
1382 int_distance, tone_idx_tmp);
1383 *tone_idx_tmp_in = tone_idx_tmp;
1384 set_result = PHYDM_SET_SUCCESS;
1385 }
1386
1387 return set_result;
1388 }
1389
phydm_csi_mask_setting_jgr3(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch,u8 wgt)1390 u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
1391 u32 f_intf, u32 sec_ch, u8 wgt)
1392 {
1393 struct dm_struct *dm = (struct dm_struct *)dm_void;
1394 u32 fc = 2412;
1395 u8 direction = FREQ_POSITIVE;
1396 u32 tone_idx = 0;
1397 u8 set_result = PHYDM_SET_SUCCESS;
1398 u8 rpt = 0;
1399
1400 if (enable == FUNC_DISABLE) {
1401 phydm_csi_mask_enable(dm, FUNC_ENABLE);
1402 phydm_clean_all_csi_mask(dm);
1403 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1404 set_result = PHYDM_SET_SUCCESS;
1405 } else {
1406 PHYDM_DBG(dm, ODM_COMP_API,
1407 "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n",
1408 ch, bw, f_intf,
1409 (((bw == 20) || (ch > 14)) ? "Don't care" :
1410 (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt);
1411
1412 /*@calculate fc*/
1413 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1414 set_result = PHYDM_SET_FAIL;
1415 } else {
1416 /*@calculate interference distance*/
1417 rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
1418 &tone_idx);
1419 if (rpt == PHYDM_SET_SUCCESS) {
1420 if (f_intf >= 1000 * fc)
1421 direction = FREQ_POSITIVE;
1422 else
1423 direction = FREQ_NEGATIVE;
1424
1425 phydm_csi_mask_enable(dm, FUNC_ENABLE);
1426 phydm_set_csi_mask_jgr3(dm, tone_idx, direction,
1427 wgt);
1428 set_result = PHYDM_SET_SUCCESS;
1429 } else {
1430 set_result = PHYDM_SET_NO_NEED;
1431 }
1432 }
1433 if (!(set_result == PHYDM_SET_SUCCESS))
1434 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1435 }
1436
1437 return set_result;
1438 }
1439
phydm_set_csi_mask_jgr3(void * dm_void,u32 tone_idx_tmp,u8 tone_direction,u8 wgt)1440 void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
1441 u8 wgt)
1442 {
1443 struct dm_struct *dm = (struct dm_struct *)dm_void;
1444 u32 multi_tone_idx_tmp = 0;
1445 u32 reg_tmp = 0;
1446 u32 tone_num = 64;
1447 u32 table_addr = 0;
1448 u32 addr = 0;
1449 u8 rf_bw = 0;
1450 u8 value = 0;
1451 u8 channel = *dm->channel;
1452
1453 rf_bw = odm_read_1byte(dm, R_0x9b0);
1454 if (((rf_bw & 0xc) >> 2) == 0x2)
1455 tone_num = 128; /* @RF80 : tone(-1) at tone_idx=255 */
1456 else
1457 tone_num = 64; /* @RF20/40 : tone(-1) at tone_idx=127 */
1458
1459 if (tone_direction == FREQ_POSITIVE) {
1460 if (tone_idx_tmp >= (tone_num - 1))
1461 tone_idx_tmp = (tone_num - 1);
1462 } else {
1463 if (tone_idx_tmp >= tone_num)
1464 tone_idx_tmp = tone_num;
1465
1466 tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
1467 }
1468 table_addr = tone_idx_tmp >> 1;
1469
1470 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1471 PHYDM_DBG(dm, ODM_COMP_API,
1472 "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1473 tone_idx_tmp, reg_tmp);
1474 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
1475 odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
1476
1477 if (channel < 15 &&
1478 (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F))) {
1479 if (tone_idx_tmp % 2 == 1) {
1480 if (tone_direction == FREQ_POSITIVE) {
1481 /*===Tone 1===*/
1482 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1483 (table_addr & 0xff));
1484 value = (BIT(3) | (wgt & 0x7)) << 4;
1485 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1486 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1487 PHYDM_DBG(dm, ODM_COMP_API,
1488 "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1489 tone_idx_tmp, reg_tmp);
1490 /*===Tone 2===*/
1491 value = 0;
1492 multi_tone_idx_tmp = tone_idx_tmp + 1;
1493 table_addr = multi_tone_idx_tmp >> 1;
1494 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1495 (table_addr & 0xff));
1496 value = (BIT(3) | (wgt & 0x7));
1497 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1498 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1499 PHYDM_DBG(dm, ODM_COMP_API,
1500 "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1501 tone_idx_tmp, reg_tmp);
1502 } else {
1503 /*===Tone 1 & 2===*/
1504 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1505 (table_addr & 0xff));
1506 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1507 (BIT(3) | (wgt & 0x7));
1508 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1509 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1510 PHYDM_DBG(dm, ODM_COMP_API,
1511 "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1512 tone_idx_tmp, reg_tmp);
1513 }
1514 } else {
1515 if (tone_direction == FREQ_POSITIVE) {
1516 /*===Tone 1 & 2===*/
1517 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1518 (table_addr & 0xff));
1519 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1520 (BIT(3) | (wgt & 0x7));
1521 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1522 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1523 PHYDM_DBG(dm, ODM_COMP_API,
1524 "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1525 tone_idx_tmp, reg_tmp);
1526 } else {
1527 /*===Tone 1===*/
1528 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1529 (table_addr & 0xff));
1530 value = (BIT(3) | (wgt & 0x7));
1531 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1532 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1533 PHYDM_DBG(dm, ODM_COMP_API,
1534 "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1535 tone_idx_tmp, reg_tmp);
1536
1537 /*===Tone 2===*/
1538 value = 0;
1539 multi_tone_idx_tmp = tone_idx_tmp - 1;
1540 table_addr = multi_tone_idx_tmp >> 1;
1541 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1542 (table_addr & 0xff));
1543 value = (BIT(3) | (wgt & 0x7)) << 4;
1544 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1545 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1546 PHYDM_DBG(dm, ODM_COMP_API,
1547 "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1548 tone_idx_tmp, reg_tmp);
1549 }
1550 }
1551 } else {
1552 if ((dm->support_ic_type & (ODM_RTL8814B)) &&
1553 phydm_spur_case_mapping(dm)) {
1554 if (!(tone_idx_tmp % 2)) {
1555 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1556 (table_addr & 0xff));
1557 value = ((BIT(3) | (((wgt + 4) <= 7 ? (wgt +
1558 4) : 7) & 0x7)) << 4) | (BIT(3) |
1559 (wgt & 0x7));
1560 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1561 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1562 PHYDM_DBG(dm, ODM_COMP_API,
1563 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1564 tone_idx_tmp, reg_tmp);
1565 if (tone_idx_tmp == 0)
1566 table_addr = tone_num - 1;
1567 else
1568 table_addr = table_addr - 1;
1569 if (tone_idx_tmp != tone_num) {
1570 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1571 (table_addr & 0xff));
1572 value = (BIT(3) | (((wgt + 4) <= 7 ?
1573 (wgt + 4) : 7) & 0x7)) << 4;
1574 odm_set_bb_reg(dm, R_0x1d94, 0xff,
1575 value);
1576 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1577 PHYDM_DBG(dm, ODM_COMP_API,
1578 "New Mask Reg0x1d94 = ((0x%x))\n",
1579 reg_tmp);
1580 }
1581 } else {
1582 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1583 (table_addr & 0xff));
1584 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1585 (BIT(3) | (((wgt + 4) <= 7 ? (wgt +
1586 4) : 7) & 0x7));
1587 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1588 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1589 PHYDM_DBG(dm, ODM_COMP_API,
1590 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1591 tone_idx_tmp, reg_tmp);
1592 if (tone_idx_tmp == (tone_num << 1) - 1)
1593 table_addr = 0;
1594 else
1595 table_addr = table_addr + 1;
1596 if (tone_idx_tmp != tone_num - 1) {
1597 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1598 (table_addr & 0xff));
1599 value = (BIT(3) | (((wgt + 4) <= 7 ?
1600 (wgt + 4) : 7) & 0x7));
1601 odm_set_bb_reg(dm, R_0x1d94, 0xff,
1602 value);
1603 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1604 PHYDM_DBG(dm, ODM_COMP_API,
1605 "New Mask Reg0x1d94 = ((0x%x))\n",
1606 reg_tmp);
1607 }
1608 }
1609 } else {
1610 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr &
1611 0xff));
1612 if (tone_idx_tmp % 2)
1613 value = (BIT(3) | (wgt & 0x7)) << 4;
1614 else
1615 value = BIT(3) | (wgt & 0x7);
1616
1617 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1618 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1619 PHYDM_DBG(dm, ODM_COMP_API,
1620 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1621 tone_idx_tmp, reg_tmp);
1622 }
1623 }
1624 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
1625 }
1626
phydm_nbi_reset_jgr3(void * dm_void)1627 void phydm_nbi_reset_jgr3(void *dm_void)
1628 {
1629 struct dm_struct *dm = (struct dm_struct *)dm_void;
1630
1631 odm_set_bb_reg(dm, R_0x818, BIT(3), 1);
1632 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0);
1633 odm_set_bb_reg(dm, R_0x818, BIT(3), 0);
1634 odm_set_bb_reg(dm, R_0x818, BIT(11), 0);
1635 #if RTL8814B_SUPPORT
1636 if (dm->support_ic_type & ODM_RTL8814B) {
1637 odm_set_bb_reg(dm, R_0x1944, 0x300, 0x3);
1638 odm_set_bb_reg(dm, R_0x4044, 0x300, 0x3);
1639 odm_set_bb_reg(dm, R_0x5044, 0x300, 0x3);
1640 odm_set_bb_reg(dm, R_0x5144, 0x300, 0x3);
1641 odm_set_bb_reg(dm, R_0x810, 0xf, 0x0);
1642 odm_set_bb_reg(dm, R_0x810, 0xf0000, 0x0);
1643 odm_set_bb_reg(dm, R_0xc24, MASKDWORD, 0x406000ff);
1644 }
1645 #endif
1646 }
1647
phydm_nbi_setting_jgr3(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch,u8 path)1648 u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
1649 u32 sec_ch, u8 path)
1650 {
1651 struct dm_struct *dm = (struct dm_struct *)dm_void;
1652 u32 fc = 2412;
1653 u8 direction = FREQ_POSITIVE;
1654 u32 tone_idx = 0;
1655 u8 set_result = PHYDM_SET_SUCCESS;
1656 u8 rpt = 0;
1657
1658 if (enable == FUNC_DISABLE) {
1659 phydm_nbi_reset_jgr3(dm);
1660 set_result = PHYDM_SET_SUCCESS;
1661 } else {
1662 PHYDM_DBG(dm, ODM_COMP_API,
1663 "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1664 ch, bw, f_intf,
1665 (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
1666 (ch > 14)) ? "Don't care" :
1667 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
1668
1669 /*@calculate fc*/
1670 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1671 set_result = PHYDM_SET_FAIL;
1672 } else {
1673 /*@calculate interference distance*/
1674 rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
1675 &tone_idx);
1676 if (rpt == PHYDM_SET_SUCCESS) {
1677 if (f_intf >= 1000 * fc)
1678 direction = FREQ_POSITIVE;
1679 else
1680 direction = FREQ_NEGATIVE;
1681
1682 phydm_set_nbi_reg_jgr3(dm, tone_idx, direction,
1683 path);
1684 set_result = PHYDM_SET_SUCCESS;
1685 } else {
1686 set_result = PHYDM_SET_NO_NEED;
1687 }
1688 }
1689 }
1690
1691 if (set_result == PHYDM_SET_SUCCESS)
1692 phydm_nbi_enable_jgr3(dm, enable, path);
1693 else
1694 phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);
1695
1696 if (dm->support_ic_type & ODM_RTL8814B)
1697 odm_set_bb_reg(dm, R_0x1d3c, BIT(19), 0);
1698
1699 return set_result;
1700 }
1701
phydm_set_nbi_reg_jgr3(void * dm_void,u32 tone_idx_tmp,u8 tone_direction,u8 path)1702 void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
1703 u8 path)
1704 {
1705 struct dm_struct *dm = (struct dm_struct *)dm_void;
1706 u32 reg_tmp_value = 0;
1707 u32 tone_num = 64;
1708 u32 addr = 0;
1709 u8 rf_bw = 0;
1710
1711 rf_bw = odm_read_1byte(dm, R_0x9b0);
1712 if (((rf_bw & 0xc) >> 2) == 0x2)
1713 tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */
1714 else
1715 tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */
1716
1717 if (tone_direction == FREQ_POSITIVE) {
1718 if (tone_idx_tmp >= (tone_num - 1))
1719 tone_idx_tmp = (tone_num - 1);
1720 } else {
1721 if (tone_idx_tmp >= tone_num)
1722 tone_idx_tmp = tone_num;
1723
1724 tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
1725 }
1726 /*Mark the tone idx for Packet detection*/
1727 #if RTL8814B_SUPPORT
1728 if (dm->support_ic_type & ODM_RTL8814B) {
1729 odm_set_bb_reg(dm, R_0xc24, 0xff, 0xff);
1730 if ((*dm->channel == 5) &&
1731 (*dm->band_width == CHANNEL_WIDTH_40))
1732 odm_set_bb_reg(dm, R_0xc24, 0xff00, 0x1a);
1733 else
1734 odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp);
1735 }
1736 #endif
1737 switch (path) {
1738 case RF_PATH_A:
1739 odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp);
1740 PHYDM_DBG(dm, ODM_COMP_API,
1741 "Set tone idx[%d]:PATH-A = ((0x%x))\n",
1742 tone_idx_tmp, tone_idx_tmp);
1743 break;
1744 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1745 case RF_PATH_B:
1746 odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp);
1747 PHYDM_DBG(dm, ODM_COMP_API,
1748 "Set tone idx[%d]:PATH-B = ((0x%x))\n",
1749 tone_idx_tmp, tone_idx_tmp);
1750 break;
1751 #endif
1752 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1753 case RF_PATH_C:
1754 odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp);
1755 PHYDM_DBG(dm, ODM_COMP_API,
1756 "Set tone idx[%d]:PATH-C = ((0x%x))\n",
1757 tone_idx_tmp, tone_idx_tmp);
1758 break;
1759 #endif
1760 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1761 case RF_PATH_D:
1762 odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp);
1763 PHYDM_DBG(dm, ODM_COMP_API,
1764 "Set tone idx[%d]:PATH-D = ((0x%x))\n",
1765 tone_idx_tmp, tone_idx_tmp);
1766 break;
1767 #endif
1768 default:
1769 break;
1770 }
1771 }
1772
phydm_nbi_enable_jgr3(void * dm_void,u32 enable,u8 path)1773 void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)
1774 {
1775 struct dm_struct *dm = (struct dm_struct *)dm_void;
1776 boolean val = false;
1777
1778 val = (enable == FUNC_ENABLE) ? true : false;
1779
1780 PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
1781
1782 if (dm->support_ic_type & ODM_RTL8814B) {
1783 odm_set_bb_reg(dm, R_0x1d3c, BIT(19), val);
1784 odm_set_bb_reg(dm, R_0x818, BIT(3), val);
1785 } else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
1786 odm_set_bb_reg(dm, R_0x818, BIT(3), !val);
1787 }
1788 odm_set_bb_reg(dm, R_0x818, BIT(11), val);
1789 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0xf);
1790
1791 if (enable == FUNC_ENABLE) {
1792 switch (path) {
1793 case RF_PATH_A:
1794 odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
1795 break;
1796 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1797 case RF_PATH_B:
1798 odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
1799 break;
1800 #endif
1801 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1802 case RF_PATH_C:
1803 odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
1804 break;
1805 #endif
1806 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1807 case RF_PATH_D:
1808 odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
1809 break;
1810 #endif
1811 default:
1812 break;
1813 }
1814 } else {
1815 odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
1816 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1817 odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
1818 #endif
1819 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1820 odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
1821 #endif
1822 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1823 odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
1824 #endif
1825 #if RTL8812F_SUPPORT
1826 if (dm->support_ic_type & ODM_RTL8812F) {
1827 odm_set_bb_reg(dm, R_0x818, BIT(3), val);
1828 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0x0);
1829 }
1830 #endif
1831 }
1832 }
1833
phydm_phystat_rpt_jgr3(void * dm_void,enum phystat_rpt info,enum rf_path ant_path)1834 u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
1835 enum rf_path ant_path)
1836 {
1837 struct dm_struct *dm = (struct dm_struct *)dm_void;
1838 s8 evm_org, cfo_org, rxsnr_org;
1839 u8 i, return_info = 0, tmp_lsb = 0, tmp_msb = 0, tmp_info = 0;
1840
1841 /* Update the status for each pkt */
1842 odm_set_bb_reg(dm, R_0x8c4, 0xfff000, 0x448);
1843 odm_set_bb_reg(dm, R_0x8c0, MASKLWORD, 0x4001);
1844 /* PHY status Page1 */
1845 odm_set_bb_reg(dm, R_0x8c0, 0x3C00000, 0x1);
1846 /*choose debug port for phystatus */
1847 odm_set_bb_reg(dm, R_0x1c3c, 0xFFF00, 0x380);
1848
1849 if (info == PHY_PWDB) {
1850 /* Choose the report of the diff path */
1851 if (ant_path == RF_PATH_A)
1852 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1);
1853 else if (ant_path == RF_PATH_B)
1854 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x2);
1855 else if (ant_path == RF_PATH_C)
1856 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x3);
1857 else if (ant_path == RF_PATH_D)
1858 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x4);
1859 } else if (info == PHY_EVM) {
1860 /* Choose the report of the diff path */
1861 if (ant_path == RF_PATH_A)
1862 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
1863 else if (ant_path == RF_PATH_B)
1864 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x11);
1865 else if (ant_path == RF_PATH_C)
1866 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
1867 else if (ant_path == RF_PATH_D)
1868 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
1869 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1870 } else if (info == PHY_CFO) {
1871 /* Choose the report of the diff path */
1872 if (ant_path == RF_PATH_A)
1873 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
1874 else if (ant_path == RF_PATH_B)
1875 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
1876 else if (ant_path == RF_PATH_C)
1877 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x16);
1878 else if (ant_path == RF_PATH_D)
1879 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x17);
1880 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1881 } else if (info == PHY_RXSNR) {
1882 /* Choose the report of the diff path */
1883 if (ant_path == RF_PATH_A)
1884 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x18);
1885 else if (ant_path == RF_PATH_B)
1886 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x19);
1887 else if (ant_path == RF_PATH_C)
1888 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1a);
1889 else if (ant_path == RF_PATH_D)
1890 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1b);
1891 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1892 } else if (info == PHY_LGAIN) {
1893 /* choose page */
1894 odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
1895 /* Choose the report of the diff path */
1896 if (ant_path == RF_PATH_A) {
1897 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
1898 tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
1899 return_info = tmp_info;
1900 } else if (ant_path == RF_PATH_B) {
1901 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
1902 tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xc0);
1903 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
1904 tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf);
1905 tmp_info |= (tmp_msb << 2) | tmp_lsb;
1906 return_info = tmp_info;
1907 } else if (ant_path == RF_PATH_C) {
1908 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
1909 tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf0);
1910 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xf);
1911 tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3);
1912 tmp_info |= (tmp_msb << 4) | tmp_lsb;
1913 return_info = tmp_info;
1914 } else if (ant_path == RF_PATH_D) {
1915 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
1916 tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
1917 return_info = tmp_info;
1918 }
1919 } else if (info == PHY_HT_AAGC_GAIN) {
1920 /* choose page */
1921 odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
1922 /* Choose the report of the diff path */
1923 if (ant_path == RF_PATH_A)
1924 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
1925 else if (ant_path == RF_PATH_B)
1926 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
1927 else if (ant_path == RF_PATH_C)
1928 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
1929 else if (ant_path == RF_PATH_D)
1930 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
1931 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1932 }
1933 return return_info;
1934 }
1935
phydm_ex_hal8814b_wifi_only_hw_config(void * dm_void)1936 void phydm_ex_hal8814b_wifi_only_hw_config(void *dm_void)
1937 {
1938 /*BB control*/
1939 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);*/
1940 /*SW control*/
1941 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);*/
1942 /*antenna mux switch */
1943 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);*/
1944
1945 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);*/
1946
1947 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);*/
1948 /*switch to WL side controller and gnt_wl gnt_bt debug signal */
1949 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);*/
1950 /*gnt_wl=1 , gnt_bt=0*/
1951 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff,
1952 * 0x7700);
1953 */
1954 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff,
1955 * 0xc00f0038);
1956 */
1957 }
1958
phydm_user_position_for_sniffer(void * dm_void,u8 user_position)1959 void phydm_user_position_for_sniffer(void *dm_void, u8 user_position)
1960 {
1961 struct dm_struct *dm = (struct dm_struct *)dm_void;
1962
1963 /* user position valid */
1964 odm_set_bb_reg(dm, R_0xa68, BIT(17), 1);
1965 /* Select user seat from pmac */
1966 odm_set_bb_reg(dm, R_0xa68, BIT(16), 1);
1967 /*user seat*/
1968 odm_set_bb_reg(dm, R_0xa68, (BIT(19) | BIT(18)), user_position);
1969 }
1970
1971 boolean
phydm_bb_ctrl_txagc_ofst_jgr3(void * dm_void,s8 pw_offset,u8 add_half_db)1972 phydm_bb_ctrl_txagc_ofst_jgr3(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
1973 u8 add_half_db /*@(+0.5 dB)*/)
1974 {
1975 struct dm_struct *dm = (struct dm_struct *)dm_void;
1976 s8 pw_idx = pw_offset * 4; /*@ 7Bit, 0.25dB unit*/
1977
1978 if (pw_offset < -16 || pw_offset > 15) {
1979 pr_debug("[Warning][%s]Ofst error=%d", __func__, pw_offset);
1980 return false;
1981 }
1982
1983 if (add_half_db)
1984 pw_idx += 2;
1985
1986 PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
1987
1988 odm_set_bb_reg(dm, R_0x18a0, 0x3f, pw_idx);
1989
1990 if (dm->num_rf_path >= 2)
1991 odm_set_bb_reg(dm, R_0x41a0, 0x3f, pw_idx);
1992
1993 if (dm->num_rf_path >= 3)
1994 odm_set_bb_reg(dm, R_0x52a0, 0x3f, pw_idx);
1995
1996 if (dm->num_rf_path >= 4)
1997 odm_set_bb_reg(dm, R_0x53a0, 0x3f, pw_idx);
1998
1999 return true;
2000 }
2001
2002 #endif
phydm_nbi_setting(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch)2003 u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
2004 u32 sec_ch)
2005 {
2006 struct dm_struct *dm = (struct dm_struct *)dm_void;
2007 u32 fc = 2412;
2008 u8 direction = FREQ_POSITIVE;
2009 u32 tone_idx = 0;
2010 u8 set_result = PHYDM_SET_SUCCESS;
2011 u8 rpt = 0;
2012
2013 if (enable == FUNC_DISABLE) {
2014 set_result = PHYDM_SET_SUCCESS;
2015 } else {
2016 PHYDM_DBG(dm, ODM_COMP_API,
2017 "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2018 ch, bw, f_intf,
2019 (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
2020 (ch > 14)) ? "Don't care" :
2021 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
2022
2023 /*@calculate fc*/
2024 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
2025 set_result = PHYDM_SET_FAIL;
2026 } else {
2027 /*@calculate interference distance*/
2028 rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
2029 &tone_idx);
2030 if (rpt == PHYDM_SET_SUCCESS) {
2031 if (f_intf >= fc)
2032 direction = FREQ_POSITIVE;
2033 else
2034 direction = FREQ_NEGATIVE;
2035
2036 phydm_set_nbi_reg(dm, tone_idx, bw);
2037
2038 set_result = PHYDM_SET_SUCCESS;
2039 } else {
2040 set_result = PHYDM_SET_NO_NEED;
2041 }
2042 }
2043 }
2044
2045 if (set_result == PHYDM_SET_SUCCESS)
2046 phydm_nbi_enable(dm, enable);
2047 else
2048 phydm_nbi_enable(dm, FUNC_DISABLE);
2049
2050 return set_result;
2051 }
2052
phydm_nbi_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2053 void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
2054 u32 *_out_len)
2055 {
2056 struct dm_struct *dm = (struct dm_struct *)dm_void;
2057 u32 used = *_used;
2058 u32 out_len = *_out_len;
2059 u32 val[10] = {0};
2060 char help[] = "-h";
2061 u8 i = 0, input_idx = 0, idx_lmt = 0;
2062 u32 enable = 0; /*@function enable*/
2063 u32 ch = 0;
2064 u32 bw = 0;
2065 u32 f_int = 0; /*@interference frequency*/
2066 u32 sec_ch = 0; /*secondary channel*/
2067 u8 rpt = 0;
2068 u8 path = 0;
2069
2070 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2071 idx_lmt = 6;
2072 else
2073 idx_lmt = 5;
2074 for (i = 0; i < idx_lmt; i++) {
2075 if (input[i + 1]) {
2076 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
2077 input_idx++;
2078 }
2079 }
2080
2081 if (input_idx == 0)
2082 return;
2083
2084 enable = val[0];
2085 ch = val[1];
2086 bw = val[2];
2087 f_int = val[3];
2088 sec_ch = val[4];
2089 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2090 path = (u8)val[5];
2091 #endif
2092
2093 if ((strcmp(input[1], help) == 0)) {
2094 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2095 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2096 PDM_SNPF(out_len, used, output + used, out_len - used,
2097 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n");
2098 else
2099 #endif
2100 PDM_SNPF(out_len, used, output + used, out_len - used,
2101 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)}\n");
2102 *_used = used;
2103 *_out_len = out_len;
2104 return;
2105 } else if (val[0] == FUNC_ENABLE) {
2106 PDM_SNPF(out_len, used, output + used, out_len - used,
2107 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2108 ch, bw, f_int,
2109 ((sec_ch == PHYDM_DONT_CARE) ||
2110 (bw == 20) || (ch > 14)) ? "Don't care" :
2111 ((sec_ch == PHYDM_ABOVE) ? "H" : "L"));
2112 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2113 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2114 rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
2115 sec_ch, path);
2116 else
2117 #endif
2118 rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
2119 sec_ch);
2120 } else if (val[0] == FUNC_DISABLE) {
2121 PDM_SNPF(out_len, used, output + used, out_len - used,
2122 "[Disable NBI]\n");
2123 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2124 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2125 rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
2126 sec_ch, path);
2127 else
2128 #endif
2129 rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
2130 sec_ch);
2131 } else {
2132 rpt = PHYDM_SET_FAIL;
2133 }
2134
2135 PDM_SNPF(out_len, used, output + used, out_len - used,
2136 "[NBI set result: %s]\n",
2137 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
2138 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
2139
2140 *_used = used;
2141 *_out_len = out_len;
2142 }
2143
phydm_csi_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2144 void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
2145 u32 *_out_len)
2146 {
2147 struct dm_struct *dm = (struct dm_struct *)dm_void;
2148 u32 used = *_used;
2149 u32 out_len = *_out_len;
2150 u32 val[10] = {0};
2151 char help[] = "-h";
2152 u8 i = 0, input_idx = 0, idx_lmt = 0;
2153 u32 enable = 0; /*@function enable*/
2154 u32 ch = 0;
2155 u32 bw = 0;
2156 u32 f_int = 0; /*@interference frequency*/
2157 u32 sec_ch = 0; /*secondary channel*/
2158 u8 rpt = 0;
2159 u8 wgt = 0;
2160
2161 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2162 idx_lmt = 6;
2163 else
2164 idx_lmt = 5;
2165
2166 for (i = 0; i < idx_lmt; i++) {
2167 if (input[i + 1]) {
2168 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
2169 input_idx++;
2170 }
2171 }
2172
2173 if (input_idx == 0)
2174 return;
2175
2176 enable = val[0];
2177 ch = val[1];
2178 bw = val[2];
2179 f_int = val[3];
2180 sec_ch = val[4];
2181 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2182 wgt = (u8)val[5];
2183 #endif
2184
2185 if ((strcmp(input[1], help) == 0)) {
2186 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2187 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2188 PDM_SNPF(out_len, used, output + used, out_len - used,
2189 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(KHz)} {Scnd_CH(L=1, H=2)}\n{wgt:(7:3/4),(6~1: 1/2 ~ 1/64),(0:0)}\n");
2190 else
2191 #endif
2192 PDM_SNPF(out_len, used, output + used, out_len - used,
2193 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n");
2194
2195 *_used = used;
2196 *_out_len = out_len;
2197 return;
2198
2199 } else if (val[0] == FUNC_ENABLE) {
2200 PDM_SNPF(out_len, used, output + used, out_len - used,
2201 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2202 ch, bw, f_int,
2203 (ch > 14) ? "Don't care" :
2204 (((sec_ch == PHYDM_DONT_CARE) ||
2205 (bw == 20) || (ch > 14)) ? "H" : "L"));
2206 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2207 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2208 rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
2209 f_int, sec_ch, wgt);
2210 else
2211 #endif
2212 rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
2213 sec_ch);
2214 } else if (val[0] == FUNC_DISABLE) {
2215 PDM_SNPF(out_len, used, output + used, out_len - used,
2216 "[Disable CSI MASK]\n");
2217 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2218 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2219 rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
2220 f_int, sec_ch, wgt);
2221 else
2222 #endif
2223 rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
2224 sec_ch);
2225 } else {
2226 rpt = PHYDM_SET_FAIL;
2227 }
2228 PDM_SNPF(out_len, used, output + used, out_len - used,
2229 "[CSI MASK set result: %s]\n",
2230 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
2231 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
2232
2233 *_used = used;
2234 *_out_len = out_len;
2235 }
2236
phydm_stop_ck320(void * dm_void,u8 enable)2237 void phydm_stop_ck320(void *dm_void, u8 enable)
2238 {
2239 struct dm_struct *dm = (struct dm_struct *)dm_void;
2240 u32 val = enable ? 1 : 0;
2241
2242 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2243 odm_set_bb_reg(dm, R_0x8b4, BIT(6), val);
2244 } else {
2245 if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/
2246 odm_set_bb_reg(dm, R_0x87c, BIT(29), val);
2247 else /*N-1SS*/
2248 odm_set_bb_reg(dm, R_0x87c, BIT(31), val);
2249 }
2250 }
2251
2252 boolean
phydm_bb_ctrl_txagc_ofst(void * dm_void,s8 pw_offset,u8 add_half_db)2253 phydm_bb_ctrl_txagc_ofst(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2254 u8 add_half_db /*@(+0.5 dB)*/)
2255 {
2256 struct dm_struct *dm = (struct dm_struct *)dm_void;
2257 s8 pw_idx;
2258 u8 offset_bit_num = 0;
2259
2260 if (dm->support_ic_type & N_IC_TX_OFFEST_5_BIT) {
2261 /*@ 5Bit, 0.5dB unit*/
2262 if (pw_offset < -8 || pw_offset > 7) {
2263 pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
2264 return false;
2265 }
2266 offset_bit_num = 5;
2267 } else {
2268 if (pw_offset < -16 || pw_offset > 15) {
2269 pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
2270 return false;
2271 }
2272 if (dm->support_ic_type & N_IC_TX_OFFEST_7_BIT) {
2273 /*@ 7Bit, 0.25dB unit*/
2274 offset_bit_num = 7;
2275 } else {
2276 /*@ 6Bit, 0.5dB unit*/
2277 offset_bit_num = 6;
2278 }
2279 }
2280
2281 pw_idx = (offset_bit_num == 7) ? pw_offset * 4 : pw_offset * 2;
2282
2283 if (add_half_db)
2284 pw_idx = (offset_bit_num == 7) ? pw_idx + 2 : pw_idx + 1;
2285
2286 PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
2287
2288 switch (dm->ic_ip_series) {
2289 case PHYDM_IC_AC:
2290 odm_set_bb_reg(dm, R_0x8b4, 0x3f, pw_idx); /*6Bit*/
2291 break;
2292 case PHYDM_IC_N:
2293 if (offset_bit_num == 5) {
2294 odm_set_bb_reg(dm, R_0x80c, 0x1f00, pw_idx);
2295 if (dm->num_rf_path >= 2)
2296 odm_set_bb_reg(dm, R_0x80c, 0x3e000, pw_idx);
2297 } else if (offset_bit_num == 6) {
2298 odm_set_bb_reg(dm, R_0x80c, 0x3f00, pw_idx);
2299 if (dm->num_rf_path >= 2)
2300 odm_set_bb_reg(dm, R_0x80c, 0xfc000, pw_idx);
2301 } else { /*7Bit*/
2302 odm_set_bb_reg(dm, R_0x80c, 0x7f00, pw_idx);
2303 if (dm->num_rf_path >= 2)
2304 odm_set_bb_reg(dm, R_0x80c, 0x3f8000, pw_idx);
2305 }
2306 break;
2307 }
2308 return true;
2309 }
2310
2311 boolean
phydm_set_bb_txagc_offset(void * dm_void,s8 pw_offset,u8 add_half_db)2312 phydm_set_bb_txagc_offset(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2313 u8 add_half_db /*@(+0.5 dB)*/)
2314 {
2315 struct dm_struct *dm = (struct dm_struct *)dm_void;
2316 boolean rpt = false;
2317
2318 PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n",
2319 pw_offset, add_half_db);
2320
2321 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2322 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
2323 rpt = phydm_bb_ctrl_txagc_ofst_jgr3(dm, pw_offset, add_half_db);
2324 } else
2325 #endif
2326 {
2327 rpt = phydm_bb_ctrl_txagc_ofst(dm, pw_offset, add_half_db);
2328 }
2329
2330 PHYDM_DBG(dm, ODM_COMP_API, "TX AGC Offset set_success=%d", rpt);
2331
2332 return rpt;
2333 }
2334
2335 #ifdef PHYDM_COMMON_API_SUPPORT
phydm_reset_txagc(void * dm_void)2336 void phydm_reset_txagc(void *dm_void)
2337 {
2338 struct dm_struct *dm = (struct dm_struct *)dm_void;
2339 u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
2340 u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
2341 u32 r_txagc_diff = R_0x3a00;
2342 u8 i = 0;
2343
2344 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
2345 PHYDM_DBG(dm, ODM_COMP_API, "Only for JGR3 ICs!\n");
2346 return;
2347 }
2348
2349 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2350 odm_set_bb_reg(dm, r_txagc_cck[i], 0x7f0000, 0x0);
2351 odm_set_bb_reg(dm, r_txagc_ofdm[i], 0x1fc00, 0x0);
2352 }
2353
2354 for (i = 0; i <= ODM_RATEVHTSS4MCS6; i = i + 4)
2355 odm_set_bb_reg(dm, r_txagc_diff + i, MASKDWORD, 0x0);
2356 }
2357 boolean
phydm_api_shift_txagc(void * dm_void,u32 pwr_offset,enum rf_path path,boolean is_positive)2358 phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
2359 boolean is_positive) {
2360 struct dm_struct *dm = (struct dm_struct *)dm_void;
2361 boolean ret = false;
2362 u32 txagc_cck = 0;
2363 u32 txagc_ofdm = 0;
2364 u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
2365 u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
2366
2367 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
2368 if (dm->support_ic_type &
2369 (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
2370 if (path > RF_PATH_B) {
2371 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2372 path);
2373 return false;
2374 }
2375 txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
2376 0x7F0000);
2377 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
2378 0x1FC00);
2379 if (is_positive) {
2380 if (((txagc_cck + pwr_offset) > 127) ||
2381 ((txagc_ofdm + pwr_offset) > 127))
2382 return false;
2383
2384 txagc_cck += pwr_offset;
2385 txagc_ofdm += pwr_offset;
2386 } else {
2387 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2388 return false;
2389
2390 txagc_cck -= pwr_offset;
2391 txagc_ofdm -= pwr_offset;
2392 }
2393 #if (RTL8822C_SUPPORT)
2394 ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck,
2395 path, PDM_CCK);
2396 ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm,
2397 path, PDM_OFDM);
2398 #endif
2399 #if (RTL8812F_SUPPORT)
2400 ret = config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_cck,
2401 path, PDM_CCK);
2402 ret &= config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_ofdm,
2403 path, PDM_OFDM);
2404 #endif
2405 #if (RTL8197G_SUPPORT)
2406 ret = config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_cck,
2407 path, PDM_CCK);
2408 ret &= config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_ofdm,
2409 path, PDM_OFDM);
2410 #endif
2411 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2412 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2413 __func__, path, txagc_cck, txagc_ofdm);
2414 }
2415 #endif
2416
2417 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
2418 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {
2419 if (path > RF_PATH_D) {
2420 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2421 path);
2422 return false;
2423 }
2424 txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
2425 0x7F0000);
2426 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
2427 0x1FC00);
2428 if (is_positive) {
2429 if (((txagc_cck + pwr_offset) > 127) ||
2430 ((txagc_ofdm + pwr_offset) > 127))
2431 return false;
2432
2433 txagc_cck += pwr_offset;
2434 txagc_ofdm += pwr_offset;
2435 } else {
2436 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2437 return false;
2438
2439 txagc_cck -= pwr_offset;
2440 txagc_ofdm -= pwr_offset;
2441 }
2442 #if (RTL8198F_SUPPORT)
2443 ret = config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_cck,
2444 path, PDM_CCK);
2445 ret &= config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_ofdm,
2446 path, PDM_OFDM);
2447 #endif
2448 #if (RTL8814B_SUPPORT)
2449 ret = config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_cck,
2450 path, PDM_CCK);
2451 ret &= config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_ofdm,
2452 path, PDM_OFDM);
2453 #endif
2454 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2455 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2456 __func__, path, txagc_cck, txagc_ofdm);
2457 }
2458 #endif
2459
2460 return ret;
2461 }
2462
2463 boolean
phydm_api_set_txagc(void * dm_void,u32 pwr_idx,enum rf_path path,u8 rate,boolean is_single_rate)2464 phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
2465 u8 rate, boolean is_single_rate)
2466 {
2467 struct dm_struct *dm = (struct dm_struct *)dm_void;
2468 boolean ret = false;
2469 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\
2470 RTL8814B_SUPPORT || RTL8197G_SUPPORT)
2471 u8 base = 0;
2472 u8 txagc_tmp = 0;
2473 s8 pw_by_rate_tmp = 0;
2474 s8 pw_by_rate_new = 0;
2475 #endif
2476 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2477 u8 i = 0;
2478 #endif
2479
2480 #if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
2481 if (dm->support_ic_type &
2482 (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
2483 if (is_single_rate) {
2484 #if (RTL8822B_SUPPORT)
2485 if (dm->support_ic_type == ODM_RTL8822B)
2486 ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx,
2487 path, rate);
2488 #endif
2489
2490 #if (RTL8821C_SUPPORT)
2491 if (dm->support_ic_type == ODM_RTL8821C)
2492 ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx,
2493 path, rate);
2494 #endif
2495
2496 #if (RTL8195B_SUPPORT)
2497 if (dm->support_ic_type == ODM_RTL8195B)
2498 ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx,
2499 path, rate);
2500 #endif
2501
2502 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2503 set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx);
2504 #endif
2505
2506 } else {
2507 #if (RTL8822B_SUPPORT)
2508 if (dm->support_ic_type == ODM_RTL8822B)
2509 ret = config_phydm_write_txagc_8822b(dm,
2510 pwr_idx,
2511 path,
2512 rate);
2513 #endif
2514
2515 #if (RTL8821C_SUPPORT)
2516 if (dm->support_ic_type == ODM_RTL8821C)
2517 ret = config_phydm_write_txagc_8821c(dm,
2518 pwr_idx,
2519 path,
2520 rate);
2521 #endif
2522
2523 #if (RTL8195B_SUPPORT)
2524 if (dm->support_ic_type == ODM_RTL8195B)
2525 ret = config_phydm_write_txagc_8195b(dm,
2526 pwr_idx,
2527 path,
2528 rate);
2529 #endif
2530
2531 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2532 for (i = 0; i < 4; i++)
2533 set_current_tx_agc(dm->priv, path, (rate + i),
2534 (u8)pwr_idx);
2535 #endif
2536 }
2537 }
2538 #endif
2539
2540 #if (RTL8198F_SUPPORT)
2541 if (dm->support_ic_type & ODM_RTL8198F) {
2542 if (rate < 0x4)
2543 txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
2544 rate,
2545 PDM_CCK);
2546 else
2547 txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
2548 rate,
2549 PDM_OFDM);
2550
2551 pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate);
2552 base = txagc_tmp - pw_by_rate_tmp;
2553 base = base & 0x7f;
2554 if (DIFF_2((pwr_idx & 0x7f), base) > 64 || pwr_idx > 127)
2555 return false;
2556
2557 pw_by_rate_new = (s8)(pwr_idx - base);
2558 ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate);
2559 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2560 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2561 __func__, path, rate, base, pw_by_rate_new);
2562 }
2563 #endif
2564
2565 #if (RTL8822C_SUPPORT)
2566 if (dm->support_ic_type & ODM_RTL8822C) {
2567 if (rate < 0x4)
2568 txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
2569 rate,
2570 PDM_CCK);
2571 else
2572 txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
2573 rate,
2574 PDM_OFDM);
2575
2576 pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate);
2577 base = txagc_tmp - pw_by_rate_tmp;
2578 base = base & 0x7f;
2579 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2580 return false;
2581
2582 pw_by_rate_new = (s8)(pwr_idx - base);
2583 ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate);
2584 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2585 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2586 __func__, path, rate, base, pw_by_rate_new);
2587 }
2588 #endif
2589
2590 #if (RTL8814B_SUPPORT)
2591 if (dm->support_ic_type & ODM_RTL8814B) {
2592 if (rate < 0x4)
2593 txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
2594 rate,
2595 PDM_CCK);
2596 else
2597 txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
2598 rate,
2599 PDM_OFDM);
2600
2601 pw_by_rate_tmp = config_phydm_read_txagc_diff_8814b(dm, rate);
2602 base = txagc_tmp - pw_by_rate_tmp;
2603 base = base & 0x7f;
2604 if (DIFF_2((pwr_idx & 0x7f), base) > 64)
2605 return false;
2606
2607 pw_by_rate_new = (s8)(pwr_idx - base);
2608 ret = phydm_write_txagc_1byte_8814b(dm, pw_by_rate_new, rate);
2609 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2610 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2611 __func__, path, rate, base, pw_by_rate_new);
2612 }
2613 #endif
2614
2615 #if (RTL8812F_SUPPORT)
2616 if (dm->support_ic_type & ODM_RTL8812F) {
2617 if (rate < 0x4)
2618 txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
2619 rate,
2620 PDM_CCK);
2621 else
2622 txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
2623 rate,
2624 PDM_OFDM);
2625
2626 pw_by_rate_tmp = config_phydm_read_txagc_diff_8812f(dm, rate);
2627 base = txagc_tmp - pw_by_rate_tmp;
2628 base = base & 0x7f;
2629 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2630 return false;
2631
2632 pw_by_rate_new = (s8)(pwr_idx - base);
2633 ret = phydm_write_txagc_1byte_8812f(dm, pw_by_rate_new, rate);
2634 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2635 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2636 __func__, path, rate, base, pw_by_rate_new);
2637 }
2638 #endif
2639
2640 #if (RTL8197G_SUPPORT)
2641 if (dm->support_ic_type & ODM_RTL8197G) {
2642 if (rate < 0x4)
2643 txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
2644 rate,
2645 PDM_CCK);
2646 else
2647 txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
2648 rate,
2649 PDM_OFDM);
2650
2651 pw_by_rate_tmp = config_phydm_read_txagc_diff_8197g(dm, rate);
2652 base = txagc_tmp - pw_by_rate_tmp;
2653 base = base & 0x7f;
2654 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2655 return false;
2656
2657 pw_by_rate_new = (s8)(pwr_idx - base);
2658 ret = phydm_write_txagc_1byte_8197g(dm, pw_by_rate_new, rate);
2659 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2660 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2661 __func__, path, rate, base, pw_by_rate_new);
2662 }
2663 #endif
2664
2665 #if (RTL8197F_SUPPORT)
2666 if (dm->support_ic_type & ODM_RTL8197F)
2667 ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate);
2668 #endif
2669
2670 #if (RTL8192F_SUPPORT)
2671 if (dm->support_ic_type & ODM_RTL8192F)
2672 ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate);
2673 #endif
2674
2675 #if (RTL8721D_SUPPORT)
2676 if (dm->support_ic_type & ODM_RTL8721D)
2677 ret = config_phydm_write_txagc_8721d(dm, pwr_idx, path, rate);
2678 #endif
2679 #if (RTL8710C_SUPPORT)
2680 if (dm->support_ic_type & ODM_RTL8710C)
2681 ret = config_phydm_write_txagc_8710c(dm, pwr_idx, path, rate);
2682 #endif
2683 return ret;
2684 }
2685
phydm_api_get_txagc(void * dm_void,enum rf_path path,u8 hw_rate)2686 u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
2687 {
2688 struct dm_struct *dm = (struct dm_struct *)dm_void;
2689 u8 ret = 0;
2690
2691 #if (RTL8822B_SUPPORT)
2692 if (dm->support_ic_type & ODM_RTL8822B)
2693 ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
2694 #endif
2695
2696 #if (RTL8197F_SUPPORT)
2697 if (dm->support_ic_type & ODM_RTL8197F)
2698 ret = config_phydm_read_txagc_8197f(dm, path, hw_rate);
2699 #endif
2700
2701 #if (RTL8821C_SUPPORT)
2702 if (dm->support_ic_type & ODM_RTL8821C)
2703 ret = config_phydm_read_txagc_8821c(dm, path, hw_rate);
2704 #endif
2705
2706 #if (RTL8195B_SUPPORT)
2707 if (dm->support_ic_type & ODM_RTL8195B)
2708 ret = config_phydm_read_txagc_8195b(dm, path, hw_rate);
2709 #endif
2710
2711 /*@jj add 20170822*/
2712 #if (RTL8192F_SUPPORT)
2713 if (dm->support_ic_type & ODM_RTL8192F)
2714 ret = config_phydm_read_txagc_8192f(dm, path, hw_rate);
2715 #endif
2716
2717 #if (RTL8198F_SUPPORT)
2718 if (dm->support_ic_type & ODM_RTL8198F) {
2719 if (hw_rate < 0x4) {
2720 ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
2721 PDM_CCK);
2722 } else {
2723 ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
2724 PDM_OFDM);
2725 }
2726 }
2727 #endif
2728
2729 #if (RTL8822C_SUPPORT)
2730 if (dm->support_ic_type & ODM_RTL8822C) {
2731 if (hw_rate < 0x4) {
2732 ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
2733 PDM_CCK);
2734 } else {
2735 ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
2736 PDM_OFDM);
2737 }
2738 }
2739 #endif
2740
2741 #if (RTL8814B_SUPPORT)
2742 if (dm->support_ic_type & ODM_RTL8814B) {
2743 if (hw_rate < 0x4) {
2744 ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
2745 PDM_CCK);
2746 } else {
2747 ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
2748 PDM_OFDM);
2749 }
2750 }
2751 #endif
2752
2753 #if (RTL8812F_SUPPORT)
2754 if (dm->support_ic_type & ODM_RTL8812F) {
2755 if (hw_rate < 0x4) {
2756 ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
2757 PDM_CCK);
2758 } else {
2759 ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
2760 PDM_OFDM);
2761 }
2762 }
2763 #endif
2764
2765 #if (RTL8197G_SUPPORT)
2766 if (dm->support_ic_type & ODM_RTL8197G) {
2767 if (hw_rate < 0x4) {
2768 ret = config_phydm_read_txagc_8197g(dm, path,
2769 hw_rate,
2770 PDM_CCK);
2771 } else {
2772 ret = config_phydm_read_txagc_8197g(dm, path,
2773 hw_rate,
2774 PDM_OFDM);
2775 }
2776 }
2777 #endif
2778
2779 #if (RTL8721D_SUPPORT)
2780 if (dm->support_ic_type & ODM_RTL8721D)
2781 ret = config_phydm_read_txagc_8721d(dm, path, hw_rate);
2782 #endif
2783 #if (RTL8710C_SUPPORT)
2784 if (dm->support_ic_type & ODM_RTL8710C)
2785 ret = config_phydm_read_txagc_8710c(dm, path, hw_rate);
2786 #endif
2787 return ret;
2788 }
2789
2790 #if (RTL8822C_SUPPORT)
phydm_shift_rxagc_table(void * dm_void,boolean is_pos_shift,u8 sft)2791 void phydm_shift_rxagc_table(void *dm_void, boolean is_pos_shift, u8 sft)
2792 {
2793 struct dm_struct *dm = (struct dm_struct *)dm_void;
2794 u8 i = 0;
2795 u8 j = 0;
2796 u32 reg = 0;
2797 u16 max_rf_gain = 0;
2798 u16 min_rf_gain = 0;
2799
2800 dm->is_agc_tab_pos_shift = is_pos_shift;
2801 dm->agc_table_shift = sft;
2802
2803 for (i = 0; i <= dm->agc_table_cnt; i++) {
2804 max_rf_gain = dm->agc_rf_gain_ori[i][0];
2805 min_rf_gain = dm->agc_rf_gain_ori[i][63];
2806
2807 if (dm->support_ic_type & ODM_RTL8822C)
2808 dm->l_bnd_detect[i] = false;
2809
2810 for (j = 0; j < 64; j++) {
2811 if (is_pos_shift) {
2812 if (j < sft)
2813 reg = (max_rf_gain & 0x3ff);
2814 else
2815 reg = (dm->agc_rf_gain_ori[i][j - sft] &
2816 0x3ff);
2817 } else {
2818 if (j > 63 - sft)
2819 reg = (min_rf_gain & 0x3ff);
2820
2821 else
2822 reg = (dm->agc_rf_gain_ori[i][j + sft] &
2823 0x3ff);
2824 }
2825 dm->agc_rf_gain[i][j] = (u16)(reg & 0x3ff);
2826
2827 reg |= (j & 0x3f) << 16;/*mp_gain_idx*/
2828 reg |= (i & 0xf) << 22;/*table*/
2829 reg |= BIT(29) | BIT(28);/*write en*/
2830 odm_set_bb_reg(dm, R_0x1d90, MASKDWORD, reg);
2831 }
2832 }
2833
2834 if (dm->support_ic_type & ODM_RTL8822C)
2835 odm_set_bb_reg(dm, R_0x828, 0xf8, L_BND_DEFAULT_8822C);
2836 }
2837 #endif
2838
2839 boolean
phydm_api_switch_bw_channel(void * dm_void,u8 ch,u8 pri_ch,enum channel_width bw)2840 phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
2841 enum channel_width bw)
2842 {
2843 struct dm_struct *dm = (struct dm_struct *)dm_void;
2844 boolean ret = false;
2845
2846 switch (dm->support_ic_type) {
2847 #if (RTL8822B_SUPPORT)
2848 case ODM_RTL8822B:
2849 ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw);
2850 break;
2851 #endif
2852
2853 #if (RTL8197F_SUPPORT)
2854 case ODM_RTL8197F:
2855 ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw);
2856 break;
2857 #endif
2858
2859 #if (RTL8821C_SUPPORT)
2860 case ODM_RTL8821C:
2861 ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw);
2862 break;
2863 #endif
2864
2865 #if (RTL8195B_SUPPORT)
2866 case ODM_RTL8195B:
2867 ret = config_phydm_switch_channel_bw_8195b(dm, ch, pri_ch, bw);
2868 break;
2869 #endif
2870
2871 #if (RTL8192F_SUPPORT)
2872 case ODM_RTL8192F:
2873 ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);
2874 break;
2875 #endif
2876
2877 #if (RTL8198F_SUPPORT)
2878 case ODM_RTL8198F:
2879 ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw);
2880 break;
2881 #endif
2882
2883 #if (RTL8822C_SUPPORT)
2884 case ODM_RTL8822C:
2885 ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw);
2886 break;
2887 #endif
2888
2889 #if (RTL8814B_SUPPORT)
2890 case ODM_RTL8814B:
2891 ret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw);
2892 break;
2893 #endif
2894
2895 #if (RTL8812F_SUPPORT)
2896 case ODM_RTL8812F:
2897 ret = config_phydm_switch_channel_bw_8812f(dm, ch, pri_ch, bw);
2898 break;
2899 #endif
2900
2901 #if (RTL8197G_SUPPORT)
2902 case ODM_RTL8197G:
2903 ret = config_phydm_switch_channel_bw_8197g(dm, ch, pri_ch, bw);
2904 break;
2905 #endif
2906
2907 #if (RTL8721D_SUPPORT)
2908 case ODM_RTL8721D:
2909 ret = config_phydm_switch_channel_bw_8721d(dm, ch, pri_ch, bw);
2910 break;
2911 #endif
2912 #if (RTL8710C_SUPPORT)
2913 case ODM_RTL8710C:
2914 ret = config_phydm_switch_channel_bw_8710c(dm, ch, pri_ch, bw);
2915 break;
2916 #endif
2917
2918 default:
2919 break;
2920 }
2921 return ret;
2922 }
2923
2924 boolean
phydm_api_trx_mode(void * dm_void,enum bb_path tx_path,enum bb_path rx_path,enum bb_path tx_path_ctrl)2925 phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
2926 enum bb_path tx_path_ctrl)
2927 {
2928 struct dm_struct *dm = (struct dm_struct *)dm_void;
2929 boolean ret = false;
2930 boolean is_2tx = false;
2931
2932 if (tx_path_ctrl == BB_PATH_AB)
2933 is_2tx = true;
2934
2935 switch (dm->support_ic_type) {
2936 #if (RTL8822B_SUPPORT)
2937 case ODM_RTL8822B:
2938 ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,
2939 tx_path_ctrl);
2940 break;
2941 #endif
2942
2943 #if (RTL8197F_SUPPORT)
2944 case ODM_RTL8197F:
2945 ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx);
2946 break;
2947 #endif
2948
2949 #if (RTL8192F_SUPPORT)
2950 case ODM_RTL8192F:
2951 ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path,
2952 tx_path_ctrl);
2953 break;
2954 #endif
2955
2956 #if (RTL8198F_SUPPORT)
2957 case ODM_RTL8198F:
2958 ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx);
2959 break;
2960 #endif
2961
2962 #if (RTL8814B_SUPPORT)
2963 case ODM_RTL8814B:
2964 ret = config_phydm_trx_mode_8814b(dm, tx_path, rx_path);
2965 break;
2966 #endif
2967
2968 #if (RTL8822C_SUPPORT)
2969 case ODM_RTL8822C:
2970 ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path,
2971 tx_path_ctrl);
2972 break;
2973 #endif
2974
2975 #if (RTL8812F_SUPPORT)
2976 case ODM_RTL8812F:
2977 ret = config_phydm_trx_mode_8812f(dm, tx_path, rx_path, is_2tx);
2978 break;
2979 #endif
2980
2981 #if (RTL8197G_SUPPORT)
2982 case ODM_RTL8197G:
2983 ret = config_phydm_trx_mode_8197g(dm, tx_path, rx_path, is_2tx);
2984 break;
2985 #endif
2986
2987 #if (RTL8721D_SUPPORT)
2988 case ODM_RTL8721D:
2989 ret = config_phydm_trx_mode_8721d(dm, tx_path, rx_path, is_2tx);
2990 break;
2991 #endif
2992
2993 #if (RTL8710C_SUPPORT)
2994 case ODM_RTL8710C:
2995 ret = config_phydm_trx_mode_8710c(dm, tx_path, rx_path, is_2tx);
2996 break;
2997 #endif
2998 }
2999 return ret;
3000 }
3001 #endif
3002
3003 #ifdef PHYDM_COMMON_API_NOT_SUPPORT
config_phydm_read_txagc_n(void * dm_void,enum rf_path path,u8 hw_rate)3004 u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
3005 {
3006 struct dm_struct *dm = (struct dm_struct *)dm_void;
3007 u8 read_back_data = INVALID_TXAGC_DATA;
3008 u32 reg_txagc;
3009 u32 reg_mask;
3010 /* This function is for 92E/88E etc... */
3011 /* @Input need to be HW rate index, not driver rate index!!!! */
3012
3013 /* @Error handling */
3014 if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) {
3015 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n",
3016 __func__, path);
3017 return INVALID_TXAGC_DATA;
3018 }
3019
3020 if (path == RF_PATH_A) {
3021 switch (hw_rate) {
3022 case ODM_RATE1M:
3023 reg_txagc = R_0xe08;
3024 reg_mask = 0x00007f00;
3025 break;
3026 case ODM_RATE2M:
3027 reg_txagc = R_0x86c;
3028 reg_mask = 0x00007f00;
3029 break;
3030 case ODM_RATE5_5M:
3031 reg_txagc = R_0x86c;
3032 reg_mask = 0x007f0000;
3033 break;
3034 case ODM_RATE11M:
3035 reg_txagc = R_0x86c;
3036 reg_mask = 0x7f000000;
3037 break;
3038
3039 case ODM_RATE6M:
3040 reg_txagc = R_0xe00;
3041 reg_mask = 0x0000007f;
3042 break;
3043 case ODM_RATE9M:
3044 reg_txagc = R_0xe00;
3045 reg_mask = 0x00007f00;
3046 break;
3047 case ODM_RATE12M:
3048 reg_txagc = R_0xe00;
3049 reg_mask = 0x007f0000;
3050 break;
3051 case ODM_RATE18M:
3052 reg_txagc = R_0xe00;
3053 reg_mask = 0x7f000000;
3054 break;
3055 case ODM_RATE24M:
3056 reg_txagc = R_0xe04;
3057 reg_mask = 0x0000007f;
3058 break;
3059 case ODM_RATE36M:
3060 reg_txagc = R_0xe04;
3061 reg_mask = 0x00007f00;
3062 break;
3063 case ODM_RATE48M:
3064 reg_txagc = R_0xe04;
3065 reg_mask = 0x007f0000;
3066 break;
3067 case ODM_RATE54M:
3068 reg_txagc = R_0xe04;
3069 reg_mask = 0x7f000000;
3070 break;
3071
3072 case ODM_RATEMCS0:
3073 reg_txagc = R_0xe10;
3074 reg_mask = 0x0000007f;
3075 break;
3076 case ODM_RATEMCS1:
3077 reg_txagc = R_0xe10;
3078 reg_mask = 0x00007f00;
3079 break;
3080 case ODM_RATEMCS2:
3081 reg_txagc = R_0xe10;
3082 reg_mask = 0x007f0000;
3083 break;
3084 case ODM_RATEMCS3:
3085 reg_txagc = R_0xe10;
3086 reg_mask = 0x7f000000;
3087 break;
3088 case ODM_RATEMCS4:
3089 reg_txagc = R_0xe14;
3090 reg_mask = 0x0000007f;
3091 break;
3092 case ODM_RATEMCS5:
3093 reg_txagc = R_0xe14;
3094 reg_mask = 0x00007f00;
3095 break;
3096 case ODM_RATEMCS6:
3097 reg_txagc = R_0xe14;
3098 reg_mask = 0x007f0000;
3099 break;
3100 case ODM_RATEMCS7:
3101 reg_txagc = R_0xe14;
3102 reg_mask = 0x7f000000;
3103 break;
3104 case ODM_RATEMCS8:
3105 reg_txagc = R_0xe18;
3106 reg_mask = 0x0000007f;
3107 break;
3108 case ODM_RATEMCS9:
3109 reg_txagc = R_0xe18;
3110 reg_mask = 0x00007f00;
3111 break;
3112 case ODM_RATEMCS10:
3113 reg_txagc = R_0xe18;
3114 reg_mask = 0x007f0000;
3115 break;
3116 case ODM_RATEMCS11:
3117 reg_txagc = R_0xe18;
3118 reg_mask = 0x7f000000;
3119 break;
3120 case ODM_RATEMCS12:
3121 reg_txagc = R_0xe1c;
3122 reg_mask = 0x0000007f;
3123 break;
3124 case ODM_RATEMCS13:
3125 reg_txagc = R_0xe1c;
3126 reg_mask = 0x00007f00;
3127 break;
3128 case ODM_RATEMCS14:
3129 reg_txagc = R_0xe1c;
3130 reg_mask = 0x007f0000;
3131 break;
3132 case ODM_RATEMCS15:
3133 reg_txagc = R_0xe1c;
3134 reg_mask = 0x7f000000;
3135 break;
3136
3137 default:
3138 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
3139 break;
3140 }
3141 } else if (path == RF_PATH_B) {
3142 switch (hw_rate) {
3143 case ODM_RATE1M:
3144 reg_txagc = R_0x838;
3145 reg_mask = 0x00007f00;
3146 break;
3147 case ODM_RATE2M:
3148 reg_txagc = R_0x838;
3149 reg_mask = 0x007f0000;
3150 break;
3151 case ODM_RATE5_5M:
3152 reg_txagc = R_0x838;
3153 reg_mask = 0x7f000000;
3154 break;
3155 case ODM_RATE11M:
3156 reg_txagc = R_0x86c;
3157 reg_mask = 0x0000007f;
3158 break;
3159
3160 case ODM_RATE6M:
3161 reg_txagc = R_0x830;
3162 reg_mask = 0x0000007f;
3163 break;
3164 case ODM_RATE9M:
3165 reg_txagc = R_0x830;
3166 reg_mask = 0x00007f00;
3167 break;
3168 case ODM_RATE12M:
3169 reg_txagc = R_0x830;
3170 reg_mask = 0x007f0000;
3171 break;
3172 case ODM_RATE18M:
3173 reg_txagc = R_0x830;
3174 reg_mask = 0x7f000000;
3175 break;
3176 case ODM_RATE24M:
3177 reg_txagc = R_0x834;
3178 reg_mask = 0x0000007f;
3179 break;
3180 case ODM_RATE36M:
3181 reg_txagc = R_0x834;
3182 reg_mask = 0x00007f00;
3183 break;
3184 case ODM_RATE48M:
3185 reg_txagc = R_0x834;
3186 reg_mask = 0x007f0000;
3187 break;
3188 case ODM_RATE54M:
3189 reg_txagc = R_0x834;
3190 reg_mask = 0x7f000000;
3191 break;
3192
3193 case ODM_RATEMCS0:
3194 reg_txagc = R_0x83c;
3195 reg_mask = 0x0000007f;
3196 break;
3197 case ODM_RATEMCS1:
3198 reg_txagc = R_0x83c;
3199 reg_mask = 0x00007f00;
3200 break;
3201 case ODM_RATEMCS2:
3202 reg_txagc = R_0x83c;
3203 reg_mask = 0x007f0000;
3204 break;
3205 case ODM_RATEMCS3:
3206 reg_txagc = R_0x83c;
3207 reg_mask = 0x7f000000;
3208 break;
3209 case ODM_RATEMCS4:
3210 reg_txagc = R_0x848;
3211 reg_mask = 0x0000007f;
3212 break;
3213 case ODM_RATEMCS5:
3214 reg_txagc = R_0x848;
3215 reg_mask = 0x00007f00;
3216 break;
3217 case ODM_RATEMCS6:
3218 reg_txagc = R_0x848;
3219 reg_mask = 0x007f0000;
3220 break;
3221 case ODM_RATEMCS7:
3222 reg_txagc = R_0x848;
3223 reg_mask = 0x7f000000;
3224 break;
3225
3226 case ODM_RATEMCS8:
3227 reg_txagc = R_0x84c;
3228 reg_mask = 0x0000007f;
3229 break;
3230 case ODM_RATEMCS9:
3231 reg_txagc = R_0x84c;
3232 reg_mask = 0x00007f00;
3233 break;
3234 case ODM_RATEMCS10:
3235 reg_txagc = R_0x84c;
3236 reg_mask = 0x007f0000;
3237 break;
3238 case ODM_RATEMCS11:
3239 reg_txagc = R_0x84c;
3240 reg_mask = 0x7f000000;
3241 break;
3242 case ODM_RATEMCS12:
3243 reg_txagc = R_0x868;
3244 reg_mask = 0x0000007f;
3245 break;
3246 case ODM_RATEMCS13:
3247 reg_txagc = R_0x868;
3248 reg_mask = 0x00007f00;
3249 break;
3250 case ODM_RATEMCS14:
3251 reg_txagc = R_0x868;
3252 reg_mask = 0x007f0000;
3253 break;
3254 case ODM_RATEMCS15:
3255 reg_txagc = R_0x868;
3256 reg_mask = 0x7f000000;
3257 break;
3258
3259 default:
3260 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
3261 break;
3262 }
3263 } else {
3264 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n");
3265 }
3266 read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask);
3267 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n",
3268 __func__, path, hw_rate, read_back_data);
3269 return read_back_data;
3270 }
3271 #endif
3272
3273 #ifdef CONFIG_MCC_DM
3274 #ifdef DYN_ANT_WEIGHTING_SUPPORT
phydm_set_weighting_cmn(struct dm_struct * dm)3275 void phydm_set_weighting_cmn(struct dm_struct *dm)
3276 {
3277 PHYDM_DBG(dm, DBG_COMP_MCC, "%s\n", __func__);
3278 odm_set_bb_reg(dm, 0xc04, (BIT(18) | BIT(21)), 0x0);
3279 odm_set_bb_reg(dm, 0xe04, (BIT(18) | BIT(21)), 0x0);
3280 }
3281
phydm_set_weighting_mcc(u8 b_equal_weighting,void * dm_void,u8 port)3282 void phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port)
3283 {
3284 /*u8 reg_8;*/
3285 struct dm_struct *dm = (struct dm_struct *)dm_void;
3286 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3287 u8 val_0x98e, val_0x98f, val_0x81b;
3288 u32 temp_reg;
3289
3290 PHYDM_DBG(dm, DBG_COMP_MCC, "ant_weighting_mcc, port = %d\n", port);
3291 if (b_equal_weighting) {
3292 temp_reg = odm_get_bb_reg(dm, 0x98c, 0x00ff0000);
3293 val_0x98e = (u8)(temp_reg >> 16) & 0xc0;
3294 temp_reg = odm_get_bb_reg(dm, 0x98c, 0xff000000);
3295 val_0x98f = (u8)(temp_reg >> 24) & 0x7f;
3296 temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
3297 val_0x81b = (u8)(temp_reg >> 24) & 0xfd;
3298 PHYDM_DBG(dm, DBG_COMP_MCC, "Equal weighting ,rssi_min = %d\n",
3299 dm->rssi_min);
3300 /*equal weighting*/
3301 } else {
3302 val_0x98e = 0x44;
3303 val_0x98f = 0x43;
3304 temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
3305 val_0x81b = (u8)(temp_reg >> 24) | BIT(2);
3306 PHYDM_DBG(dm, DBG_COMP_MCC, "AGC weighting ,rssi_min = %d\n",
3307 dm->rssi_min);
3308 /*fix sec_min_wgt = 1/2*/
3309 }
3310 mcc_dm->mcc_reg_id[2] = 0x2;
3311 mcc_dm->mcc_dm_reg[2] = 0x98e;
3312 mcc_dm->mcc_dm_val[2][port] = val_0x98e;
3313
3314 mcc_dm->mcc_reg_id[3] = 0x3;
3315 mcc_dm->mcc_dm_reg[3] = 0x98f;
3316 mcc_dm->mcc_dm_val[3][port] = val_0x98f;
3317
3318 mcc_dm->mcc_reg_id[4] = 0x4;
3319 mcc_dm->mcc_dm_reg[4] = 0x81b;
3320 mcc_dm->mcc_dm_val[4][port] = val_0x81b;
3321 }
3322
phydm_dyn_ant_dec_mcc(u8 port,u8 rssi_in,void * dm_void)3323 void phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void)
3324 {
3325 struct dm_struct *dm = (struct dm_struct *)dm_void;
3326 u8 rssi_l2h = 43, rssi_h2l = 37;
3327
3328 if (rssi_in == 0xff)
3329 phydm_set_weighting_mcc(FALSE, dm, port);
3330 else if (rssi_in >= rssi_l2h)
3331 phydm_set_weighting_mcc(TRUE, dm, port);
3332 else if (rssi_in <= rssi_h2l)
3333 phydm_set_weighting_mcc(FALSE, dm, port);
3334 }
3335
phydm_dynamic_ant_weighting_mcc_8822b(void * dm_void)3336 void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void)
3337 {
3338 struct dm_struct *dm = (struct dm_struct *)dm_void;
3339 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3340 u8 i;
3341
3342 phydm_set_weighting_cmn(dm);
3343 for (i = 0; i <= 1; i++)
3344 phydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm);
3345 }
3346 #endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
3347
phydm_mcc_init(void * dm_void)3348 void phydm_mcc_init(void *dm_void)
3349 {
3350 struct dm_struct *dm = (struct dm_struct *)dm_void;
3351 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3352 u8 i;
3353
3354 /*PHYDM_DBG(dm, DBG_COMP_MCC, ("MCC init\n"));*/
3355 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC init\n");
3356 for (i = 0; i < MCC_DM_REG_NUM; i++) {
3357 mcc_dm->mcc_reg_id[i] = 0xff;
3358 mcc_dm->mcc_dm_reg[i] = 0;
3359 mcc_dm->mcc_dm_val[i][0] = 0;
3360 mcc_dm->mcc_dm_val[i][1] = 0;
3361 }
3362 for (i = 0; i < NUM_STA; i++) {
3363 mcc_dm->sta_macid[0][i] = 0xff;
3364 mcc_dm->sta_macid[1][i] = 0xff;
3365 }
3366 /* Function init */
3367 dm->is_stop_dym_ant_weighting = 0;
3368 }
3369
phydm_check(void * dm_void)3370 u8 phydm_check(void *dm_void)
3371 {
3372 struct dm_struct *dm = (struct dm_struct *)dm_void;
3373 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3374 struct cmn_sta_info *p_entry = NULL;
3375 u8 shift = 0;
3376 u8 i = 0;
3377 u8 j = 0;
3378 u8 rssi_min[2] = {0xff, 0xff};
3379 u8 sta_num = 8;
3380 u8 mcc_macid = 0;
3381
3382 for (i = 0; i <= 1; i++) {
3383 for (j = 0; j < sta_num; j++) {
3384 if (mcc_dm->sta_macid[i][j] != 0xff) {
3385 mcc_macid = mcc_dm->sta_macid[i][j];
3386 p_entry = dm->phydm_sta_info[mcc_macid];
3387 if (!p_entry) {
3388 PHYDM_DBG(dm, DBG_COMP_MCC,
3389 "PEntry NULL(mac=%d)\n",
3390 mcc_dm->sta_macid[i][j]);
3391 return _FAIL;
3392 }
3393 PHYDM_DBG(dm, DBG_COMP_MCC,
3394 "undec_smoothed_pwdb=%d\n",
3395 p_entry->rssi_stat.rssi);
3396 if (p_entry->rssi_stat.rssi < rssi_min[i])
3397 rssi_min[i] = p_entry->rssi_stat.rssi;
3398 }
3399 }
3400 }
3401 mcc_dm->mcc_rssi[0] = (u8)rssi_min[0];
3402 mcc_dm->mcc_rssi[1] = (u8)rssi_min[1];
3403 return _SUCCESS;
3404 }
3405
phydm_mcc_h2ccmd_rst(void * dm_void)3406 void phydm_mcc_h2ccmd_rst(void *dm_void)
3407 {
3408 struct dm_struct *dm = (struct dm_struct *)dm_void;
3409 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3410 u8 i;
3411 u8 regid;
3412 u8 h2c_mcc[H2C_MAX_LENGTH];
3413
3414 /* RST MCC */
3415 for (i = 0; i < H2C_MAX_LENGTH; i++)
3416 h2c_mcc[i] = 0xff;
3417 h2c_mcc[0] = 0x00;
3418 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
3419 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C RST\n");
3420 }
3421
phydm_mcc_h2ccmd(void * dm_void)3422 void phydm_mcc_h2ccmd(void *dm_void)
3423 {
3424 struct dm_struct *dm = (struct dm_struct *)dm_void;
3425 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3426 u8 i;
3427 u8 regid;
3428 u8 h2c_mcc[H2C_MAX_LENGTH];
3429
3430 if (mcc_dm->mcc_rf_ch[0] == 0xff && mcc_dm->mcc_rf_ch[1] == 0xff) {
3431 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC channel Error\n");
3432 return;
3433 }
3434 /* Set Channel number */
3435 for (i = 0; i < H2C_MAX_LENGTH; i++)
3436 h2c_mcc[i] = 0xff;
3437 h2c_mcc[0] = 0xe0;
3438 h2c_mcc[1] = (u8)(mcc_dm->mcc_rf_ch[0]);
3439 h2c_mcc[2] = (u8)(mcc_dm->mcc_rf_ch[0] >> 8);
3440 h2c_mcc[3] = (u8)(mcc_dm->mcc_rf_ch[1]);
3441 h2c_mcc[4] = (u8)(mcc_dm->mcc_rf_ch[1] >> 8);
3442 h2c_mcc[5] = 0xff;
3443 h2c_mcc[6] = 0xff;
3444 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
3445 PHYDM_DBG(dm, DBG_COMP_MCC,
3446 "MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3447 h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3],
3448 h2c_mcc[4], h2c_mcc[5], h2c_mcc[6]);
3449
3450 /* Set Reg and value*/
3451 for (i = 0; i < H2C_MAX_LENGTH; i++)
3452 h2c_mcc[i] = 0xff;
3453
3454 for (i = 0; i < MCC_DM_REG_NUM; i++) {
3455 regid = mcc_dm->mcc_reg_id[i];
3456 if (regid != 0xff) {
3457 h2c_mcc[0] = 0xa0 | (regid & 0x1f);
3458 h2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]);
3459 h2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);
3460 h2c_mcc[3] = mcc_dm->mcc_dm_val[i][0];
3461 h2c_mcc[4] = mcc_dm->mcc_dm_val[i][1];
3462 h2c_mcc[5] = 0xff;
3463 h2c_mcc[6] = 0xff;
3464 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH,
3465 h2c_mcc);
3466 PHYDM_DBG(dm, DBG_COMP_MCC,
3467 "MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3468 h2c_mcc[0], h2c_mcc[1], h2c_mcc[2],
3469 h2c_mcc[3], h2c_mcc[4],
3470 h2c_mcc[5], h2c_mcc[6]);
3471 }
3472 }
3473 }
3474
phydm_mcc_ctrl(void * dm_void)3475 void phydm_mcc_ctrl(void *dm_void)
3476 {
3477 struct dm_struct *dm = (struct dm_struct *)dm_void;
3478 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3479 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3480
3481 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC status: %x\n", mcc_dm->mcc_status);
3482 /*MCC stage no change*/
3483 if (mcc_dm->mcc_status == mcc_dm->mcc_pre_status)
3484 return;
3485 /*Not in MCC stage*/
3486 if (mcc_dm->mcc_status == 0) {
3487 /* Enable normal Ant-weighting */
3488 dm->is_stop_dym_ant_weighting = 0;
3489 /* Enable normal DIG */
3490 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20);
3491 } else {
3492 /* Disable normal Ant-weighting */
3493 dm->is_stop_dym_ant_weighting = 1;
3494 /* Enable normal DIG */
3495 odm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1,
3496 0x20);
3497 }
3498 if (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0)
3499 phydm_mcc_init(dm);
3500 mcc_dm->mcc_pre_status = mcc_dm->mcc_status;
3501 }
3502
phydm_fill_mcccmd(void * dm_void,u8 regid,u16 reg_add,u8 val0,u8 val1)3503 void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
3504 u8 val0, u8 val1)
3505 {
3506 struct dm_struct *dm = (struct dm_struct *)dm_void;
3507 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3508
3509 mcc_dm->mcc_reg_id[regid] = regid;
3510 mcc_dm->mcc_dm_reg[regid] = reg_add;
3511 mcc_dm->mcc_dm_val[regid][0] = val0;
3512 mcc_dm->mcc_dm_val[regid][1] = val1;
3513 }
3514
phydm_mcc_switch(void * dm_void)3515 void phydm_mcc_switch(void *dm_void)
3516 {
3517 struct dm_struct *dm = (struct dm_struct *)dm_void;
3518 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3519 s8 ret;
3520
3521 phydm_mcc_ctrl(dm);
3522 if (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/
3523 phydm_mcc_h2ccmd_rst(dm);
3524 return;
3525 }
3526 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC switch\n");
3527 ret = phydm_check(dm);
3528 if (ret == _FAIL) {
3529 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC check fail\n");
3530 return;
3531 }
3532 /* Set IGI*/
3533 phydm_mcc_igi_cal(dm);
3534
3535 /* Set Antenna Gain*/
3536 #if (RTL8822B_SUPPORT == 1)
3537 phydm_dynamic_ant_weighting_mcc_8822b(dm);
3538 #endif
3539 /* Set H2C Cmd*/
3540 phydm_mcc_h2ccmd(dm);
3541 }
3542 #endif
3543
3544 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_normal_driver_rx_sniffer(struct dm_struct * dm,u8 * desc,PRT_RFD_STATUS rt_rfd_status,u8 * drv_info,u8 phy_status)3545 void phydm_normal_driver_rx_sniffer(
3546 struct dm_struct *dm,
3547 u8 *desc,
3548 PRT_RFD_STATUS rt_rfd_status,
3549 u8 *drv_info,
3550 u8 phy_status)
3551 {
3552 #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
3553 u32 *msg;
3554 u16 seq_num;
3555
3556 if (rt_rfd_status->packet_report_type != NORMAL_RX)
3557 return;
3558
3559 if (!dm->is_linked) {
3560 if (rt_rfd_status->is_hw_error)
3561 return;
3562 }
3563
3564 if (phy_status == true) {
3565 if (dm->rx_pkt_type == type_block_ack ||
3566 dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts)
3567 seq_num = 0;
3568 else
3569 seq_num = rt_rfd_status->seq_num;
3570
3571 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3572 "%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
3573 seq_num,
3574 /*rt_rfd_status->mac_id,*/
3575 (rt_rfd_status->is_crc ? "C" :
3576 rt_rfd_status->is_ampdu ? "A" : "_"),
3577 rt_rfd_status->data_rate,
3578 rt_rfd_status->length,
3579 ((rt_rfd_status->band_width == 0) ? "20M" :
3580 ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
3581 (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
3582
3583 if (dm->rx_pkt_type == type_asoc_req)
3584 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ");
3585 else if (dm->rx_pkt_type == type_asoc_rsp)
3586 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP");
3587 else if (dm->rx_pkt_type == type_probe_req)
3588 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ");
3589 else if (dm->rx_pkt_type == type_probe_rsp)
3590 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP");
3591 else if (dm->rx_pkt_type == type_deauth)
3592 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH");
3593 else if (dm->rx_pkt_type == type_beacon)
3594 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON");
3595 else if (dm->rx_pkt_type == type_block_ack_req)
3596 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ");
3597 else if (dm->rx_pkt_type == type_rts)
3598 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_");
3599 else if (dm->rx_pkt_type == type_cts)
3600 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_");
3601 else if (dm->rx_pkt_type == type_ack)
3602 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_");
3603 else if (dm->rx_pkt_type == type_block_ack)
3604 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__");
3605 else if (dm->rx_pkt_type == type_data)
3606 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_");
3607 else if (dm->rx_pkt_type == type_data_ack)
3608 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack");
3609 else if (dm->rx_pkt_type == type_qos_data)
3610 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data");
3611 else
3612 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]",
3613 dm->rx_pkt_type);
3614
3615 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]",
3616 dm->rssi_a,
3617 dm->rssi_b,
3618 dm->rssi_c,
3619 dm->rssi_d);
3620
3621 msg = (u32 *)drv_info;
3622
3623 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3624 " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
3625 msg[6], msg[5], msg[4], msg[3],
3626 msg[2], msg[1], msg[1]);
3627 } else {
3628 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3629 "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
3630 rt_rfd_status->seq_num,
3631 /*rt_rfd_status->mac_id,*/
3632 (rt_rfd_status->is_crc ? "C" :
3633 (rt_rfd_status->is_ampdu) ? "A" : "_"),
3634 rt_rfd_status->data_rate,
3635 rt_rfd_status->length,
3636 ((rt_rfd_status->band_width == 0) ? "20M" :
3637 ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
3638 (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
3639 }
3640
3641 #endif
3642 }
3643
3644 #endif
3645