1 /******************************************************************************
2 *
3 * Copyright(c) 2014 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include <drv_types.h>
17 #include <hal_data.h>
18
19 /* A mapping from HalData to ODM. */
boardType(u8 InterfaceSel)20 enum odm_board_type boardType(u8 InterfaceSel)
21 {
22 enum odm_board_type board = ODM_BOARD_DEFAULT;
23
24 #ifdef CONFIG_PCI_HCI
25 INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
26 switch (pcie) {
27 case INTF_SEL0_SOLO_MINICARD:
28 board |= ODM_BOARD_MINICARD;
29 break;
30 case INTF_SEL1_BT_COMBO_MINICARD:
31 board |= ODM_BOARD_BT;
32 board |= ODM_BOARD_MINICARD;
33 break;
34 default:
35 board = ODM_BOARD_DEFAULT;
36 break;
37 }
38
39 #elif defined(CONFIG_USB_HCI)
40 INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel;
41 switch (usb) {
42 case INTF_SEL1_USB_High_Power:
43 board |= ODM_BOARD_EXT_LNA;
44 board |= ODM_BOARD_EXT_PA;
45 break;
46 case INTF_SEL2_MINICARD:
47 board |= ODM_BOARD_MINICARD;
48 break;
49 case INTF_SEL4_USB_Combo:
50 board |= ODM_BOARD_BT;
51 break;
52 case INTF_SEL5_USB_Combo_MF:
53 board |= ODM_BOARD_BT;
54 break;
55 case INTF_SEL0_USB:
56 case INTF_SEL3_USB_Solo:
57 default:
58 board = ODM_BOARD_DEFAULT;
59 break;
60 }
61
62 #endif
63 /* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
64
65 return board;
66 }
67
rtw_hal_update_iqk_fw_offload_cap(_adapter * adapter)68 void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
69 {
70 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
71 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
72
73 if (hal->RegIQKFWOffload) {
74 rtw_sctx_init(&hal->iqk_sctx, 0);
75 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
76 } else
77 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
78
79 RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
80
81 if (rtw_mi_check_status(adapter, MI_LINKED)) {
82 #ifdef CONFIG_LPS
83 LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
84 #endif
85 halrf_iqk_trigger(p_dm_odm, _FALSE);
86 }
87 }
88
89 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
rtw_phydm_iqk_trigger(_adapter * adapter)90 void rtw_phydm_iqk_trigger(_adapter *adapter)
91 {
92 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
93 u8 clear = _TRUE;
94 u8 segment = _FALSE;
95 u8 rfk_forbidden = _FALSE;
96
97 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
98 #if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)
99 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
100 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
101 #else
102 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
103 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
104 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
105 #endif
106 }
107 #endif
108
rtw_phydm_iqk_trigger_all(_adapter * adapter)109 void rtw_phydm_iqk_trigger_all(_adapter *adapter)
110 {
111 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
112 u8 clear = _TRUE;
113 u8 segment = _FALSE;
114 u8 rfk_forbidden = _FALSE;
115
116 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
117 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
118 #if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)
119 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
120 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
121 #else
122 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
123 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
124 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
125 #endif /* (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) */
126 #else
127 halrf_iqk_trigger(p_dm_odm, _FALSE);
128 #endif /* ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1)) */
129 }
130
rtw_phydm_iqk_trigger_dbg(_adapter * adapter,bool recovery,bool clear,bool segment)131 void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
132 {
133 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
134
135 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
136 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
137 #else
138 halrf_iqk_trigger(p_dm_odm, recovery);
139 #endif
140 }
rtw_phydm_lck_trigger(_adapter * adapter)141 void rtw_phydm_lck_trigger(_adapter *adapter)
142 {
143 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
144
145 halrf_lck_trigger(p_dm_odm);
146 }
147
rtw_hal_phydm_cal_trigger(_adapter * adapter)148 void rtw_hal_phydm_cal_trigger(_adapter *adapter)
149 {
150 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
151
152 rtw_ps_deny(adapter, PS_DENY_IOCTL);
153 LeaveAllPowerSaveModeDirect(adapter);
154
155 rtw_phydm_iqk_trigger_all(adapter);
156
157 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
158 }
159
160 #ifdef CONFIG_DBG_RF_CAL
rtw_hal_iqk_test(_adapter * adapter,bool recovery,bool clear,bool segment)161 void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
162 {
163 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
164
165 rtw_ps_deny(adapter, PS_DENY_IOCTL);
166 LeaveAllPowerSaveModeDirect(adapter);
167
168 rtw_phydm_ability_backup(adapter);
169 rtw_phydm_func_disable_all(adapter);
170
171 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
172
173 rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
174 rtw_phydm_ability_restore(adapter);
175
176 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
177 }
178
rtw_hal_lck_test(_adapter * adapter)179 void rtw_hal_lck_test(_adapter *adapter)
180 {
181 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
182
183 rtw_ps_deny(adapter, PS_DENY_IOCTL);
184 LeaveAllPowerSaveModeDirect(adapter);
185
186 rtw_phydm_ability_backup(adapter);
187 rtw_phydm_func_disable_all(adapter);
188
189 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
190
191 rtw_phydm_lck_trigger(adapter);
192
193 rtw_phydm_ability_restore(adapter);
194 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
195 }
196 #endif
197
198 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
rtw_hal_update_param_init_fw_offload_cap(_adapter * adapter)199 void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
200 {
201 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
202
203 if (adapter->registrypriv.fw_param_init)
204 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
205 else
206 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
207
208 RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
209 }
210 #endif
211
record_ra_info(void * p_dm_void,u8 macid,struct cmn_sta_info * p_sta,u64 ra_mask)212 void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
213 {
214 struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
215 _adapter *adapter = p_dm->adapter;
216 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
217 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
218
219 if (p_sta) {
220 rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
221 rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
222 rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
223 rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
224
225 rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
226 }
227 }
228
229 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
rtw_phydm_fill_desc_dpt(void * dm,u8 * desc,u8 dpt_lv)230 void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
231 {
232 struct dm_struct *p_dm = (struct dm_struct *)dm;
233 _adapter *adapter = p_dm->adapter;
234
235 switch (rtw_get_chip_type(adapter)) {
236 /*
237 #ifdef CONFIG_RTL8188F
238 case RTL8188F:
239 break;
240 #endif
241
242 #ifdef CONFIG_RTL8723B
243 case RTL8723B :
244 break;
245 #endif
246
247 #ifdef CONFIG_RTL8703B
248 case RTL8703B :
249 break;
250 #endif
251
252 #ifdef CONFIG_RTL8812A
253 case RTL8812 :
254 break;
255 #endif
256
257 #ifdef CONFIG_RTL8821A
258 case RTL8821:
259 break;
260 #endif
261
262 #ifdef CONFIG_RTL8814A
263 case RTL8814A :
264 break;
265 #endif
266
267 #ifdef CONFIG_RTL8192F
268 case RTL8192F :
269 break;
270 #endif
271 */
272 /*
273 #ifdef CONFIG_RTL8192E
274 case RTL8192E :
275 SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
276 break;
277 #endif
278 */
279 #ifdef CONFIG_RTL8822B
280 case RTL8822B :
281 SET_TX_DESC_TXPWR_OFSET_8822B(desc, dpt_lv);
282 break;
283 #endif
284
285 #ifdef CONFIG_RTL8821C
286 case RTL8821C :
287 SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
288 break;
289 #endif
290
291 default :
292 RTW_ERR("%s IC not support dynamic tx power\n", __func__);
293 break;
294 }
295 }
rtw_phydm_set_dyntxpwr(_adapter * adapter,u8 * desc,u8 mac_id)296 void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
297 {
298 struct dm_struct *dm = adapter_to_phydm(adapter);
299
300 odm_set_dyntxpwr(dm, desc, mac_id);
301 }
302 #endif
303
304 #ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(_adapter * adapter,u8 state)305 void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
306 {
307 struct registry_priv *pregistrypriv = &adapter->registrypriv;
308 struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
309 struct dm_struct *dm = adapter_to_phydm(adapter);
310 u8 tdma_dig_en;
311
312 switch (state) {
313 case TDMADIG_INIT:
314 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
315 phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
316 break;
317 case TDMADIG_NON_INIT:
318 if(pregistrypriv->tdmadig_dynamic) {
319 if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
320 tdma_dig_en = 0;
321 else
322 tdma_dig_en = pregistrypriv->tdmadig_en;
323 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
324 }
325 break;
326 default:
327 break;
328
329 }
330 }
331 #endif/*CONFIG_TDMADIG*/
rtw_phydm_ops_func_init(struct dm_struct * p_phydm)332 void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
333 {
334 struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
335
336 p_ra_t->record_ra_info = record_ra_info;
337 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
338 p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
339 #endif
340 }
rtw_phydm_priv_init(_adapter * adapter)341 void rtw_phydm_priv_init(_adapter *adapter)
342 {
343 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
344 struct dm_struct *phydm = &(hal->odmpriv);
345
346 phydm->adapter = adapter;
347 odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
348 }
349
Init_ODM_ComInfo(_adapter * adapter)350 void Init_ODM_ComInfo(_adapter *adapter)
351 {
352 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
353 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
354 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
355 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
356 int i;
357
358 /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
359 pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
360 rtw_odm_init_ic_type(adapter);
361
362 if (rtw_get_intf_type(adapter) == RTW_GSPI)
363 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
364 else
365 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
366
367 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
368
369 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
370
371 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
372
373 #ifdef CONFIG_ADVANCE_OTA
374 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
375 #endif
376 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
377
378 {
379 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
380 u8 odm_board_type = ODM_BOARD_DEFAULT;
381
382 if (pHalData->ExternalLNA_2G != 0) {
383 odm_board_type |= ODM_BOARD_EXT_LNA;
384 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
385 }
386 if (pHalData->external_lna_5g != 0) {
387 odm_board_type |= ODM_BOARD_EXT_LNA_5G;
388 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
389 }
390 if (pHalData->ExternalPA_2G != 0) {
391 odm_board_type |= ODM_BOARD_EXT_PA;
392 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
393 }
394 if (pHalData->external_pa_5g != 0) {
395 odm_board_type |= ODM_BOARD_EXT_PA_5G;
396 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
397 }
398 if (pHalData->EEPROMBluetoothCoexist)
399 odm_board_type |= ODM_BOARD_BT;
400
401 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
402 /* 1 ============== End of BoardType ============== */
403 }
404
405 rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
406
407 #ifdef CONFIG_DFS_MASTER
408 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter_to_rfctl(adapter)->dfs_region_domain);
409 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
410 #endif
411
412 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
413 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
414 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
415 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
416
417 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
418 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
419
420 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
421
422 /*Add by YuChen for kfree init*/
423 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
424 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
425
426 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
427 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
428 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
429
430 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
431 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
432 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
433
434 /* waiting for PhyDMV034 support*/
435 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability));
436 /*Add by YuChen for adaptivity init*/
437 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
438 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
439 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
440 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
441
442 /*halrf info init*/
443 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
444 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
445 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_MP_POWER_TRACKING_TYPE, pHalData->txpwr_pg_mode);
446
447 if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
448 rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
449
450 #ifdef CONFIG_IQK_PA_OFF
451 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
452 #endif
453 rtw_hal_update_iqk_fw_offload_cap(adapter);
454 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
455 rtw_hal_update_param_init_fw_offload_cap(adapter);
456 #endif
457
458 /* Pointer reference */
459 /*Antenna diversity relative parameters*/
460 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
461 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
462
463 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
464 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
465 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
466
467 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
468 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
469
470 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
471 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
472 #ifdef CONFIG_NARROWBAND_SUPPORTING
473 if ((adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
474 || (adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
475 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(adapter->registrypriv.rtw_nb_config));
476 }
477 else
478 #endif
479 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
480 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
481 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
482
483 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
484 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
485 /*Add by Yuchen for phydm beamforming*/
486 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
487 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
488 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
489 #ifdef CONFIG_RTL8723B
490 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
491 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
492 #endif /*CONFIG_RTL8723B*/
493 #ifdef CONFIG_USB_HCI
494 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
495 #endif
496
497 #ifdef CONFIG_DYNAMIC_SOML
498 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
499 #endif
500 #ifdef CONFIG_RTW_PATH_DIV
501 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_PATH_DIV, &(adapter->registrypriv.path_div));
502 #endif
503 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
504
505 /*halrf info hook*/
506 /* waiting for PhyDMV034 support*/
507 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
508 #ifdef CONFIG_MP_INCLUDED
509 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
510 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
511 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
512 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
513 #endif/*CONFIG_MP_INCLUDED*/
514 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
515 phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
516
517 rtw_phydm_ops_func_init(pDM_Odm);
518 phydm_dm_early_init(pDM_Odm);
519 /* TODO */
520 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
521 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
522 }
523
524
525 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
526 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
527 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
528 { 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
529
530 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
531 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
532 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
533 { 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
534
535 static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
536 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
537 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
538 { 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
539
540
541 struct turbo_edca_setting{
542 u32 edca_ul; /* uplink, tx */
543 u32 edca_dl; /* downlink, rx */
544 };
545
546 #define TURBO_EDCA_ENT(UL, DL) {UL, DL}
547
548 #if 0
549 #define TURBO_EDCA_MODE_NUM 18
550 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
551 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
552 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
553 TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */
554
555 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
556 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
557 TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */
558
559 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
560 TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
561 TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
562
563 TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
564 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
565 TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
566
567 TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
568 TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
569 TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
570
571 TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
572
573 TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
574
575 TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
576 };
577 #else
578 #define TURBO_EDCA_MODE_NUM 8
579 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
580 /* { UL, DL } */
581 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
582
583 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
584
585 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
586
587 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
588
589 TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
590
591 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
592
593 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
594
595 TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
596 };
597 #endif
598
rtw_hal_turbo_edca(_adapter * adapter)599 void rtw_hal_turbo_edca(_adapter *adapter)
600 {
601 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
602 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
603 struct recv_priv *precvpriv = &(adapter->recvpriv);
604 struct registry_priv *pregpriv = &adapter->registrypriv;
605 struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
606 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
607
608 /* Parameter suggested by Scott */
609 #if 0
610 u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
611 u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
612 #endif
613 u32 EDCA_BE_UL = 0x5ea42b;
614 u32 EDCA_BE_DL = 0x00a42b;
615 u8 ic_type = rtw_get_chip_type(adapter);
616
617 u8 iot_peer = 0;
618 u8 wireless_mode = 0xFF; /* invalid value */
619 u8 traffic_index;
620 u32 edca_param;
621 u64 cur_tx_bytes = 0;
622 u64 cur_rx_bytes = 0;
623 u8 bbtchange = _TRUE;
624 u8 is_bias_on_rx = _FALSE;
625 u8 is_linked = _FALSE;
626 u8 interface_type;
627
628 if (hal_data->dis_turboedca == 1)
629 return;
630
631 if (rtw_mi_check_status(adapter, MI_ASSOC))
632 is_linked = _TRUE;
633
634 if (is_linked != _TRUE) {
635 precvpriv->is_any_non_be_pkts = _FALSE;
636 return;
637 }
638
639 if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
640 precvpriv->is_any_non_be_pkts = _FALSE;
641 return;
642 }
643
644 interface_type = rtw_get_intf_type(adapter);
645 wireless_mode = pmlmeext->cur_wireless_mode;
646
647 iot_peer = pmlmeinfo->assoc_AP_vendor;
648
649 if (iot_peer >= HT_IOT_PEER_MAX) {
650 precvpriv->is_any_non_be_pkts = _FALSE;
651 return;
652 }
653
654 if (ic_type == RTL8188E) {
655 if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
656 is_bias_on_rx = _TRUE;
657 }
658
659 /* Check if the status needs to be changed. */
660 if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
661 cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
662 cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
663
664 /* traffic, TX or RX */
665 if (is_bias_on_rx) {
666 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
667 /* Uplink TP is present. */
668 traffic_index = UP_LINK;
669 } else {
670 /* Balance TP is present. */
671 traffic_index = DOWN_LINK;
672 }
673 } else {
674 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
675 /* Downlink TP is present. */
676 traffic_index = DOWN_LINK;
677 } else {
678 /* Balance TP is present. */
679 traffic_index = UP_LINK;
680 }
681 }
682 #if 0
683 if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
684 || (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
685 #endif
686 {
687 if (interface_type == RTW_PCIE) {
688 EDCA_BE_UL = 0x6ea42b;
689 EDCA_BE_DL = 0x6ea42b;
690 }
691
692 /* 92D txop can't be set to 0x3e for cisco1250 */
693 if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
694 EDCA_BE_DL = edca_setting_DL[iot_peer];
695 EDCA_BE_UL = edca_setting_UL[iot_peer];
696 }
697 /* merge from 92s_92c_merge temp*/
698 else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
699 EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
700 else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
701 EDCA_BE_DL = 0xa630;
702 else if (iot_peer == HT_IOT_PEER_MARVELL) {
703 EDCA_BE_DL = edca_setting_DL[iot_peer];
704 EDCA_BE_UL = edca_setting_UL[iot_peer];
705 } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
706 /* Set DL EDCA for Atheros peer to 0x3ea42b.*/
707 /* Suggested by SD3 Wilson for ASUS TP issue.*/
708 EDCA_BE_DL = edca_setting_DL[iot_peer];
709 }
710
711 if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
712 EDCA_BE_UL = 0x5ea42b;
713 EDCA_BE_DL = 0x5ea42b;
714
715 RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
716 }
717
718 if (interface_type == RTW_PCIE &&
719 ((ic_type == RTL8822B)
720 || (ic_type == RTL8822C)
721 || (ic_type == RTL8814A) || (ic_type == RTL8814B))) {
722 EDCA_BE_UL = 0x6ea42b;
723 EDCA_BE_DL = 0x6ea42b;
724 }
725
726 if ((ic_type == RTL8822B)
727 && (interface_type == RTW_SDIO))
728 EDCA_BE_DL = 0x00431c;
729
730 #ifdef CONFIG_RTW_TPT_MODE
731 if ( dvobj->tpt_mode > 0 ) {
732 EDCA_BE_UL = dvobj->edca_be_ul;
733 EDCA_BE_DL = dvobj->edca_be_dl;
734 }
735 #endif /* CONFIG_RTW_TPT_MODE */
736
737 /* keep this condition at last check */
738 if (hal_data->dis_turboedca == 2) {
739
740 if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
741
742 struct turbo_edca_setting param;
743
744 param = rtw_turbo_edca[hal_data->edca_param_mode];
745
746 EDCA_BE_UL = param.edca_ul;
747 EDCA_BE_DL = param.edca_dl;
748
749 } else {
750
751 EDCA_BE_UL = hal_data->edca_param_mode;
752 EDCA_BE_DL = hal_data->edca_param_mode;
753 }
754 }
755
756 if (traffic_index == DOWN_LINK)
757 edca_param = EDCA_BE_DL;
758 else
759 edca_param = EDCA_BE_UL;
760
761 #ifdef CONFIG_EXTEND_LOWRATE_TXOP
762 #define TXOP_CCK1M 0x01A6
763 #define TXOP_CCK2M 0x00E6
764 #define TXOP_CCK5M 0x006B
765 #define TXOP_OFD6M 0x0066
766 #define TXOP_MCS6M 0x0061
767 {
768 struct sta_info *psta;
769 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
770 u8 mac_id, role, current_rate_id;
771
772 /* search all used & connect2AP macid */
773 for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
774 if (rtw_macid_is_used(macid_ctl, mac_id)) {
775 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
776 if (role != H2C_MSR_ROLE_AP)
777 continue;
778
779 psta = macid_ctl->sta[mac_id];
780 current_rate_id = rtw_get_current_tx_rate(adapter, psta);
781 /* Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is */
782 switch (current_rate_id) {
783 case DESC_RATE1M:
784 edca_param &= 0x0000FFFF;
785 edca_param |= (TXOP_CCK1M<<16);
786 break;
787 case DESC_RATE2M:
788 edca_param &= 0x0000FFFF;
789 edca_param |= (TXOP_CCK2M<<16);
790 break;
791 case DESC_RATE5_5M:
792 edca_param &= 0x0000FFFF;
793 edca_param |= (TXOP_CCK5M<<16);
794 break;
795 case DESC_RATE6M:
796 edca_param &= 0x0000FFFF;
797 edca_param |= (TXOP_OFD6M<<16);
798 break;
799 case DESC_RATEMCS0:
800 edca_param &= 0x0000FFFF;
801 edca_param |= (TXOP_MCS6M<<16);
802 break;
803 default:
804 break;
805 }
806 }
807 }
808 }
809 #endif /* CONFIG_EXTEND_LOWRATE_TXOP */
810
811 #ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
812 edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
813 #endif
814
815 if ( edca_param != hal_data->ac_param_be) {
816
817 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
818
819 RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
820 }
821
822 hal_data->prv_traffic_idx = traffic_index;
823 }
824
825 hal_data->is_turbo_edca = _TRUE;
826 } else {
827 /* */
828 /* Turn Off EDCA turbo here. */
829 /* Restore original EDCA according to the declaration of AP. */
830 /* */
831 if (hal_data->is_turbo_edca) {
832 edca_param = hal_data->ac_param_be;
833 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
834 hal_data->is_turbo_edca = _FALSE;
835 }
836 }
837
838 }
839
rtw_dm_get_min_rssi(_adapter * adapter)840 s8 rtw_dm_get_min_rssi(_adapter *adapter)
841 {
842 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
843 struct sta_info *sta;
844 s8 min_rssi = 127, rssi;
845 int i;
846
847 for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
848 sta = macid_ctl->sta[i];
849 if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
850 || is_broadcast_mac_addr(sta->cmn.mac_addr))
851 continue;
852 rssi = sta->cmn.rssi_stat.rssi;
853 if (rssi >= 0 && min_rssi > rssi)
854 min_rssi = rssi;
855 }
856
857 return min_rssi == 127 ? 0 : min_rssi;
858 }
859
rtw_phydm_get_min_rssi(_adapter * adapter)860 s8 rtw_phydm_get_min_rssi(_adapter *adapter)
861 {
862 struct dm_struct *phydm = adapter_to_phydm(adapter);
863 s8 rssi_min = 0;
864
865 rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
866 return rssi_min;
867 }
868
rtw_phydm_get_cur_igi(_adapter * adapter)869 u8 rtw_phydm_get_cur_igi(_adapter *adapter)
870 {
871 struct dm_struct *phydm = adapter_to_phydm(adapter);
872 u8 cur_igi = 0;
873
874 cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
875 return cur_igi;
876 }
877
rtw_phydm_get_edcca_flag(_adapter * adapter)878 bool rtw_phydm_get_edcca_flag(_adapter *adapter)
879 {
880 struct dm_struct *phydm = adapter_to_phydm(adapter);
881 bool cur_edcca_flag = 0;
882
883 cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
884 return cur_edcca_flag;
885 }
886
rtw_phydm_get_phy_cnt(_adapter * adapter,enum phy_cnt cnt)887 u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
888 {
889 struct dm_struct *phydm = adapter_to_phydm(adapter);
890
891 if (cnt == FA_OFDM)
892 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
893 else if (cnt == FA_CCK)
894 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
895 else if (cnt == FA_TOTAL)
896 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
897 else if (cnt == CCA_OFDM)
898 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
899 else if (cnt == CCA_CCK)
900 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
901 else if (cnt == CCA_ALL)
902 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
903 else if (cnt == CRC32_OK_VHT)
904 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
905 else if (cnt == CRC32_OK_HT)
906 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
907 else if (cnt == CRC32_OK_LEGACY)
908 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
909 else if (cnt == CRC32_OK_CCK)
910 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
911 else if (cnt == CRC32_ERROR_VHT)
912 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
913 else if (cnt == CRC32_ERROR_HT)
914 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
915 else if (cnt == CRC32_ERROR_LEGACY)
916 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
917 else if (cnt == CRC32_ERROR_CCK)
918 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
919 else
920 return 0;
921 }
922
rtw_phydm_is_iqk_in_progress(_adapter * adapter)923 u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
924 {
925 u8 rts = _FALSE;
926 struct dm_struct *podmpriv = adapter_to_phydm(adapter);
927
928 odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
929 if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
930 RTW_ERR("IQK InProgress\n");
931 rts = _TRUE;
932 }
933 odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
934
935 return rts;
936 }
937
SetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)938 void SetHalODMVar(
939 PADAPTER Adapter,
940 HAL_ODM_VARIABLE eVariable,
941 void *pValue1,
942 BOOLEAN bSet)
943 {
944 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
945 /* _irqL irqL; */
946 switch (eVariable) {
947 case HAL_ODM_STA_INFO: {
948 struct sta_info *psta = (struct sta_info *)pValue1;
949
950 if (bSet) {
951 RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
952 psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
953 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
954 } else {
955 RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
956 /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
957 psta->cmn.dm_ctrl = 0;
958 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
959
960 /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
961 }
962 }
963 break;
964 case HAL_ODM_P2P_STATE:
965 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
966 break;
967 case HAL_ODM_WIFI_DISPLAY_STATE:
968 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
969 break;
970 case HAL_ODM_REGULATION:
971 /* used to auto enable/disable adaptivity by SD7 */
972 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
973 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
974 break;
975 case HAL_ODM_INITIAL_GAIN: {
976 u8 rx_gain = *((u8 *)(pValue1));
977 /*printk("rx_gain:%x\n",rx_gain);*/
978 if (rx_gain == 0xff) {/*restore rx gain*/
979 /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
980 odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
981 } else {
982 /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
983 /*odm_write_dig(podmpriv,rx_gain);*/
984 odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
985 }
986 }
987 break;
988 case HAL_ODM_RX_INFO_DUMP: {
989 u8 cur_igi = 0;
990 s8 rssi_min;
991 void *sel;
992
993 sel = pValue1;
994 cur_igi = rtw_phydm_get_cur_igi(Adapter);
995 rssi_min = rtw_phydm_get_min_rssi(Adapter);
996
997 _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
998 _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
999 , podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
1000 _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
1001 rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
1002 rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
1003 rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
1004
1005 if (podmpriv->is_linked) {
1006 _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
1007 if (IS_HARDWARE_TYPE_8814A(Adapter))
1008 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
1009 podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
1010 else
1011 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
1012 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1013 rtw_dump_raw_rssi_info(Adapter, sel);
1014 #endif
1015 }
1016 }
1017 break;
1018 case HAL_ODM_RX_Dframe_INFO: {
1019 void *sel;
1020
1021 sel = pValue1;
1022
1023 /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
1024 #ifdef DBG_RX_DFRAME_RAW_DATA
1025 rtw_dump_rx_dframe_info(Adapter, sel);
1026 #endif
1027 }
1028 break;
1029
1030 #ifdef CONFIG_ANTENNA_DIVERSITY
1031 case HAL_ODM_ANTDIV_SELECT: {
1032 u8 antenna = (*(u8 *)pValue1);
1033 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1034 /*switch antenna*/
1035 odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
1036 /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
1037
1038 }
1039 break;
1040 #endif
1041
1042 default:
1043 break;
1044 }
1045 }
1046
GetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)1047 void GetHalODMVar(
1048 PADAPTER Adapter,
1049 HAL_ODM_VARIABLE eVariable,
1050 void *pValue1,
1051 void *pValue2)
1052 {
1053 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
1054
1055 switch (eVariable) {
1056 #ifdef CONFIG_ANTENNA_DIVERSITY
1057 case HAL_ODM_ANTDIV_SELECT: {
1058 struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table;
1059 *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
1060 }
1061 break;
1062 #endif
1063 case HAL_ODM_INITIAL_GAIN:
1064 *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
1065 break;
1066 default:
1067 break;
1068 }
1069 }
1070
1071 #ifdef RTW_HALMAC
1072 #include "../hal_halmac.h"
1073 #endif
rtw_phydm_rfe_ctrl_gpio(_adapter * adapter,u8 gpio_num)1074 bool rtw_phydm_rfe_ctrl_gpio(
1075 _adapter *adapter,
1076 u8 gpio_num
1077 )
1078 {
1079 #ifdef RTW_HALMAC
1080 if(rtw_halmac_rfe_ctrl_cfg(adapter_to_dvobj(adapter), gpio_num))
1081 return _TRUE;
1082 else
1083 #endif/*RTW_HALMAC*/
1084 return _FALSE;
1085 }
1086
1087 enum hal_status
rtw_phydm_fw_iqk(struct dm_struct * p_dm_odm,u8 clear,u8 segment)1088 rtw_phydm_fw_iqk(
1089 struct dm_struct *p_dm_odm,
1090 u8 clear,
1091 u8 segment
1092 )
1093 {
1094 #ifdef RTW_HALMAC
1095 struct _ADAPTER *adapter = p_dm_odm->adapter;
1096
1097 if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
1098 return HAL_STATUS_SUCCESS;
1099 #endif
1100 return HAL_STATUS_FAILURE;
1101 }
1102
1103 enum hal_status
rtw_phydm_cfg_phy_para(struct dm_struct * p_dm_odm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)1104 rtw_phydm_cfg_phy_para(
1105 struct dm_struct *p_dm_odm,
1106 enum phydm_halmac_param config_type,
1107 u32 offset,
1108 u32 data,
1109 u32 mask,
1110 enum rf_path e_rf_path,
1111 u32 delay_time)
1112 {
1113 #ifdef RTW_HALMAC
1114 struct _ADAPTER *adapter = p_dm_odm->adapter;
1115 struct rtw_phy_parameter para;
1116
1117 switch (config_type) {
1118 case PHYDM_HALMAC_CMD_MAC_W8:
1119 para.cmd = 0; /* MAC register */
1120 para.data.mac.offset = offset;
1121 para.data.mac.value = data;
1122 para.data.mac.msk = mask;
1123 para.data.mac.msk_en = (mask) ? 1 : 0;
1124 para.data.mac.size = 1;
1125 break;
1126 case PHYDM_HALMAC_CMD_MAC_W16:
1127 para.cmd = 0; /* MAC register */
1128 para.data.mac.offset = offset;
1129 para.data.mac.value = data;
1130 para.data.mac.msk = mask;
1131 para.data.mac.msk_en = (mask) ? 1 : 0;
1132 para.data.mac.size = 2;
1133 break;
1134 case PHYDM_HALMAC_CMD_MAC_W32:
1135 para.cmd = 0; /* MAC register */
1136 para.data.mac.offset = offset;
1137 para.data.mac.value = data;
1138 para.data.mac.msk = mask;
1139 para.data.mac.msk_en = (mask) ? 1 : 0;
1140 para.data.mac.size = 4;
1141 break;
1142 case PHYDM_HALMAC_CMD_BB_W8:
1143 para.cmd = 1; /* BB register */
1144 para.data.bb.offset = offset;
1145 para.data.bb.value = data;
1146 para.data.bb.msk = mask;
1147 para.data.bb.msk_en = (mask) ? 1 : 0;
1148 para.data.bb.size = 1;
1149 break;
1150 case PHYDM_HALMAC_CMD_BB_W16:
1151 para.cmd = 1; /* BB register */
1152 para.data.bb.offset = offset;
1153 para.data.bb.value = data;
1154 para.data.bb.msk = mask;
1155 para.data.bb.msk_en = (mask) ? 1 : 0;
1156 para.data.bb.size = 2;
1157 break;
1158 case PHYDM_HALMAC_CMD_BB_W32:
1159 para.cmd = 1; /* BB register */
1160 para.data.bb.offset = offset;
1161 para.data.bb.value = data;
1162 para.data.bb.msk = mask;
1163 para.data.bb.msk_en = (mask) ? 1 : 0;
1164 para.data.bb.size = 4;
1165 break;
1166 case PHYDM_HALMAC_CMD_RF_W:
1167 para.cmd = 2; /* RF register */
1168 para.data.rf.offset = offset;
1169 para.data.rf.value = data;
1170 para.data.rf.msk = mask;
1171 para.data.rf.msk_en = (mask) ? 1 : 0;
1172 if (e_rf_path == RF_PATH_A)
1173 para.data.rf.path = 0;
1174 else if (e_rf_path == RF_PATH_B)
1175 para.data.rf.path = 1;
1176 else if (e_rf_path == RF_PATH_C)
1177 para.data.rf.path = 2;
1178 else if (e_rf_path == RF_PATH_D)
1179 para.data.rf.path = 3;
1180 else
1181 para.data.rf.path = 0;
1182 break;
1183 case PHYDM_HALMAC_CMD_DELAY_US:
1184 para.cmd = 3; /* Delay */
1185 para.data.delay.unit = 0; /* microsecond */
1186 para.data.delay.value = delay_time;
1187 break;
1188 case PHYDM_HALMAC_CMD_DELAY_MS:
1189 para.cmd = 3; /* Delay */
1190 para.data.delay.unit = 1; /* millisecond */
1191 para.data.delay.value = delay_time;
1192 break;
1193 case PHYDM_HALMAC_CMD_END:
1194 para.cmd = 0xFF; /* End command */
1195 break;
1196 default:
1197 return HAL_STATUS_FAILURE;
1198 }
1199
1200 if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶))
1201 return HAL_STATUS_FAILURE;
1202 #endif /*RTW_HALMAC*/
1203 return HAL_STATUS_SUCCESS;
1204 }
1205
1206
1207 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_phydm_wd_lps_lclk_hdl(_adapter * adapter)1208 void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
1209 {
1210 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1211 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1212 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1213 struct sta_priv *pstapriv = &adapter->stapriv;
1214 struct sta_info *psta = NULL;
1215 bool is_linked = _FALSE;
1216
1217 if (!rtw_is_hw_init_completed(adapter))
1218 return;
1219
1220 if (rtw_mi_check_status(adapter, MI_ASSOC))
1221 is_linked = _TRUE;
1222
1223 if (is_linked == _FALSE)
1224 return;
1225
1226 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1227 if (psta == NULL)
1228 return;
1229
1230 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
1231
1232 phydm_watchdog_lps_32k(&pHalData->odmpriv);
1233
1234 #ifdef CONFIG_LPS_PG
1235 if (pwrpriv->lps_level == LPS_PG) {
1236 if (rtw_hal_set_lps_pg_info_cmd(adapter) == _FAIL)
1237 RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n",
1238 FUNC_ADPT_ARG(adapter));
1239 }
1240 #endif /* CONFIG_LPS_PG */
1241 }
1242
rtw_phydm_watchdog_in_lps_lclk(_adapter * adapter)1243 void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
1244 {
1245 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1246 struct sta_priv *pstapriv = &adapter->stapriv;
1247 u8 cur_igi = 0;
1248 s8 min_rssi = 0;
1249
1250 if (!rtw_is_hw_init_completed(adapter))
1251 return;
1252
1253 cur_igi = rtw_phydm_get_cur_igi(adapter);
1254 min_rssi = rtw_dm_get_min_rssi(adapter);
1255 /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
1256
1257 if (min_rssi <= 0)
1258 return;
1259
1260 if ((cur_igi > min_rssi + 5) ||
1261 (cur_igi < min_rssi - 5)) {
1262 #ifdef CONFIG_LPS
1263 rtw_dm_in_lps_wk_cmd(adapter);
1264 #endif
1265 }
1266 }
1267 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
1268
dump_sta_traffic(void * sel,_adapter * adapter,struct sta_info * psta)1269 void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
1270 {
1271 struct ra_sta_info *ra_info;
1272 u8 curr_sgi = _FALSE;
1273 u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
1274
1275 if (!psta)
1276 return;
1277 RTW_PRINT_SEL(sel, "\n");
1278 RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
1279 psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
1280
1281 if (is_client_associated_to_ap(psta->padapter))
1282 RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
1283 rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
1284
1285 ra_info = &psta->cmn.ra_info;
1286 curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
1287 RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
1288 , HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
1289 , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
1290 );
1291
1292 if (0) {
1293 RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
1294 , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
1295 , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
1296 );
1297 RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
1298 , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
1299 , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
1300 );
1301 RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
1302 , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
1303 , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
1304 );
1305 RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
1306 , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
1307 , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
1308 );
1309 }
1310
1311 _RTW_PRINT_SEL(sel, "RTW: [TP] ");
1312 tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
1313 rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
1314 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1315
1316 if (tx_tp_mbips)
1317 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1318 else
1319 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
1320
1321 if (rx_tp_mbips)
1322 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1323 else
1324 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
1325
1326 if (bi_tp_mbips)
1327 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1328 else
1329 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1330
1331
1332 _RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
1333 tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
1334 rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
1335 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1336 if (tx_tp_mbips)
1337 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1338 else
1339 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
1340
1341 if (rx_tp_mbips)
1342 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1343 else
1344 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
1345
1346 if (bi_tp_mbips)
1347 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1348 else
1349 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1350
1351 #if 0
1352 RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
1353 (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
1354 (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
1355 #endif
1356 }
1357
dump_sta_info(void * sel,struct sta_info * psta)1358 void dump_sta_info(void *sel, struct sta_info *psta)
1359 {
1360 struct ra_sta_info *ra_info;
1361 u8 curr_tx_sgi = _FALSE;
1362 u8 curr_tx_rate = 0;
1363
1364 if (!psta)
1365 return;
1366
1367 ra_info = &psta->cmn.ra_info;
1368
1369 RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n",
1370 MAC_ARG(psta->cmn.mac_addr));
1371 RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
1372 RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
1373 RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
1374 RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
1375 RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
1376 ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
1377 RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
1378 RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
1379 RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
1380 (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
1381 RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
1382 (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
1383 RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
1384 RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
1385
1386 curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
1387 curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
1388 RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
1389 HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
1390 RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
1391 RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
1392 RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
1393 }
1394
rtw_phydm_ra_registed(_adapter * adapter,struct sta_info * psta)1395 void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
1396 {
1397 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1398 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1399 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
1400
1401 if (psta == NULL) {
1402 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
1403 rtw_warn_on(1);
1404 return;
1405 }
1406
1407 if (psta->cmn.mac_id >= macid_ctl->num)
1408 return;
1409
1410 phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
1411 dump_sta_info(RTW_DBGDUMP, psta);
1412 }
1413
init_phydm_info(_adapter * adapter)1414 static void init_phydm_info(_adapter *adapter)
1415 {
1416 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1417 struct dm_struct *phydm = &(hal_data->odmpriv);
1418
1419 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
1420 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
1421 }
1422
1423 #ifdef CONFIG_CTRL_TXSS_BY_TP
rtw_phydm_trx_cfg(_adapter * adapter,bool tx_1ss)1424 void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
1425 {
1426 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1427 enum bb_path txpath = BB_PATH_AB;
1428 enum bb_path rxpath = BB_PATH_AB;
1429 /*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
1430 enum bb_path txpath_1ss = BB_PATH_A;
1431
1432 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1433 txpath = (tx_1ss) ? BB_PATH_A : txpath;
1434
1435 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
1436 RTW_ERR("%s failed\n", __func__);
1437 }
1438 #endif
1439
1440
1441 /*
1442 * trx_mode init - 8822B / 8822C / 8192F
1443 * 1ssNTx - 8192E / 8812A / 8822B / 8822C / 8192F
1444 * Path-diversity - 8822B / 8822C / 8192F
1445 * PHYDM API - phydm_api_trx_mode
1446 */
rtw_phydm_config_trx_path(_adapter * adapter)1447 static u8 rtw_phydm_config_trx_path(_adapter *adapter)
1448 {
1449 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1450 enum bb_path txpath;
1451 enum bb_path rxpath;
1452 int i;
1453 u8 rst = _FAIL;
1454
1455 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1456 if (!txpath) {
1457 RTW_ERR("%s tx_path_bmp is empty\n", __func__);
1458 rtw_warn_on(1);
1459 goto exit;
1460 }
1461 if (!rxpath) {
1462 RTW_ERR("%s rx_path_bmp is empty\n", __func__);
1463 rtw_warn_on(1);
1464 goto exit;
1465 }
1466
1467 tx_path_nss_set_default(hal_data->txpath_nss, hal_data->txpath_num_nss
1468 , GET_HAL_TX_PATH_BMP(adapter));
1469
1470 #if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
1471 {
1472 enum bb_path txpath_1ss;
1473
1474 if (txpath == BB_PATH_AB) {
1475 switch (hal_data->max_tx_cnt) {
1476 case 2:
1477 #ifdef CONFIG_RTW_TX_NPATH_EN
1478 if (adapter->registrypriv.tx_npath == 1)
1479 txpath_1ss = BB_PATH_AB;
1480 else
1481 #endif
1482 #ifdef CONFIG_RTW_PATH_DIV
1483 if (adapter->registrypriv.path_div == 1) /* path diversity, support 2sts TX */
1484 txpath_1ss = BB_PATH_AUTO;
1485 else
1486 #endif
1487 txpath_1ss = BB_PATH_A;
1488 break;
1489 case 1:
1490 #ifdef CONFIG_RTW_PATH_DIV
1491 if (adapter->registrypriv.path_div == 1) /* path diversity, no support 2sts TX */
1492 txpath = txpath_1ss = BB_PATH_AUTO;
1493 else
1494 #endif
1495 txpath = txpath_1ss = BB_PATH_A;
1496 break;
1497 default:
1498 RTW_ERR("%s invalid max_tx_cnt:%u\n", __func__
1499 , hal_data->max_tx_cnt);
1500 rtw_warn_on(1);
1501 goto exit;
1502 }
1503 } else
1504 txpath_1ss = txpath;
1505
1506 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE) {
1507 RTW_ERR("%s txpath=0x%x, rxpath=0x%x, txpath_1ss=0x%x fail\n", __func__
1508 , txpath, rxpath, txpath_1ss);
1509 rtw_warn_on(1);
1510 goto exit;
1511 }
1512
1513 if (hal_data->txpath_nss[0] != txpath_1ss) {
1514 hal_data->txpath_nss[0] = txpath_1ss;
1515 if (txpath_1ss == BB_PATH_AUTO)
1516 hal_data->txpath_num_nss[0] = 1;
1517 else {
1518 hal_data->txpath_num_nss[0] = 0;
1519 for (i = 0; i < RF_PATH_MAX; i++) {
1520 if (txpath_1ss & BIT(i))
1521 hal_data->txpath_num_nss[0]++;
1522 }
1523 }
1524 }
1525 }
1526 #elif defined(CONFIG_RTL8814B)
1527 {
1528 if (config_phydm_trx_mode_8814b(adapter_to_phydm(adapter), txpath, rxpath) == FALSE) {
1529 RTW_ERR("%s txpath=0x%x, rxpath=0x%x fail\n", __func__
1530 , txpath, rxpath);
1531 rtw_warn_on(1);
1532 goto exit;
1533 }
1534
1535 /* 8814B is always full-TX */
1536 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1537 }
1538 #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
1539 {
1540 #ifdef CONFIG_RTW_TX_NPATH_EN
1541 if (adapter->registrypriv.tx_npath == 1) {
1542 phydm_tx_2path(adapter_to_phydm(adapter));
1543 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1544 }
1545 #endif
1546 }
1547 #endif
1548
1549 hal_data->txpath = txpath;
1550 hal_data->rxpath = rxpath;
1551 dump_hal_runtime_trx_mode(RTW_DBGDUMP, adapter);
1552 rst = _SUCCESS;
1553
1554 exit:
1555 return rst;
1556 }
1557
rtw_phydm_init(_adapter * adapter)1558 void rtw_phydm_init(_adapter *adapter)
1559 {
1560 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1561 struct dm_struct *phydm = &(hal_data->odmpriv);
1562
1563 rtw_phydm_config_trx_path(adapter);
1564 init_phydm_info(adapter);
1565 hal_data->phydm_init_result = odm_dm_init(phydm);
1566
1567 #ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
1568 phydm_pathb_q_matrix_rotate_en(phydm);
1569 #endif
1570 }
1571
rtw_phydm_set_crystal_cap(_adapter * adapter,u8 crystal_cap)1572 bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
1573 {
1574 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1575 struct dm_struct *phydm = &(hal_data->odmpriv);
1576
1577 return phydm_set_crystal_cap_reg(phydm, crystal_cap);
1578 }
1579
1580 #ifdef CONFIG_LPS_PG
1581 /*
1582 static void _lps_pg_state_update(_adapter *adapter)
1583 {
1584 u8 is_in_lpspg = _FALSE;
1585 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1586 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1587 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1588 struct sta_priv *pstapriv = &adapter->stapriv;
1589 struct sta_info *psta = NULL;
1590
1591 if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
1592 is_in_lpspg = _TRUE;
1593 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1594
1595 if (psta)
1596 psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
1597 }
1598 */
rtw_phydm_lps_pg_hdl(_adapter * adapter,struct sta_info * sta,bool in_lpspg)1599 void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
1600 {
1601 struct dm_struct *phydm = adapter_to_phydm(adapter);
1602 /*u8 rate_id;*/
1603
1604 if(sta == NULL) {
1605 RTW_ERR("%s sta is null\n", __func__);
1606 rtw_warn_on(1);
1607 return;
1608 }
1609
1610 if (in_lpspg) {
1611 sta->cmn.ra_info.disable_ra = _TRUE;
1612 sta->cmn.ra_info.disable_pt = _TRUE;
1613 /*TODO : DRV fix tx rate*/
1614 /*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
1615 } else {
1616 sta->cmn.ra_info.disable_ra = _FALSE;
1617 sta->cmn.ra_info.disable_pt = _FALSE;
1618 }
1619
1620 rtw_phydm_ra_registed(adapter, sta);
1621 }
1622 #endif
1623
1624 /*#define DBG_PHYDM_STATE_CHK*/
1625
1626
_rtw_phydm_rfk_condition_check(_adapter * adapter,u8 is_scaning,u8 ifs_linked)1627 static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
1628 {
1629 u8 rfk_allowed = _TRUE;
1630
1631 #ifdef CONFIG_SKIP_RFK_IN_DM
1632 rfk_allowed = _FALSE;
1633 if (0)
1634 RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
1635 return rfk_allowed;
1636 #endif
1637
1638 #ifdef CONFIG_MCC_MODE
1639 /*not in MCC State*/
1640 if (MCC_EN(adapter) &&
1641 rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
1642 rfk_allowed = _FALSE;
1643 if (0)
1644 RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
1645 return rfk_allowed;
1646 }
1647 #endif
1648
1649 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1650
1651 #endif
1652
1653 if (ifs_linked) {
1654 if (is_scaning) {
1655 rfk_allowed = _FALSE;
1656 RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
1657 }
1658 else {
1659 rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
1660 if (rfk_allowed == _FALSE)
1661 RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
1662 }
1663 }
1664
1665 return rfk_allowed;
1666 }
1667
1668 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
_rtw_phydm_iqk_segment_chk(_adapter * adapter,u8 ifs_linked)1669 static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
1670 {
1671 u8 iqk_sgt = _FALSE;
1672
1673 #if 0
1674 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1675 if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
1676 rst = _TRUE;
1677 #else
1678 if (ifs_linked)
1679 iqk_sgt = _TRUE;
1680 #endif
1681 return iqk_sgt;
1682 }
1683 #endif
1684
1685 /*check the tx low rate while unlinked to any AP;for pwr tracking */
_rtw_phydm_pwr_tracking_rate_check(_adapter * adapter)1686 static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
1687 {
1688 int i;
1689 _adapter *iface;
1690 u8 if_tx_rate = 0xFF;
1691 u8 tx_rate = 0xFF;
1692 struct mlme_ext_priv *pmlmeext = NULL;
1693 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1694 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1695 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
1696
1697 for (i = 0; i < dvobj->iface_nums; i++) {
1698 iface = dvobj->padapters[i];
1699 pmlmeext = &(iface->mlmeextpriv);
1700 if ((iface) && rtw_is_adapter_up(iface)) {
1701 #ifdef CONFIG_P2P
1702 if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
1703 if_tx_rate = IEEE80211_OFDM_RATE_6MB;
1704 else
1705 #endif
1706 if_tx_rate = pmlmeext->tx_rate;
1707
1708 if (if_tx_rate < tx_rate) {
1709 /*5G limit ofdm rate*/
1710 if (pHalData->current_channel > 14) {
1711 if (!IS_CCK_RATE(if_tx_rate))
1712 tx_rate = if_tx_rate;
1713 } else {
1714 tx_rate = if_tx_rate;
1715 }
1716 }
1717 RTW_DBG("%s i=%d if_tx_rate =0x%x\n", __func__, i, if_tx_rate);
1718 }
1719 }
1720
1721 /*suggest by RF James,unlinked setting ofdm rate*/
1722 if (tx_rate == 0xFF)
1723 tx_rate = IEEE80211_OFDM_RATE_6MB;
1724
1725 RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
1726 return tx_rate;
1727 }
1728
1729 #ifdef CONFIG_DYNAMIC_SOML
rtw_dyn_soml_byte_update(_adapter * adapter,u8 data_rate,u32 size)1730 void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
1731 {
1732 struct dm_struct *phydm = adapter_to_phydm(adapter);
1733
1734 phydm_soml_bytes_acq(phydm, data_rate, size);
1735 }
1736
rtw_dyn_soml_para_set(_adapter * adapter,u8 train_num,u8 intvl,u8 period,u8 delay)1737 void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
1738 u8 period, u8 delay)
1739 {
1740 struct dm_struct *phydm = adapter_to_phydm(adapter);
1741
1742 phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
1743 RTW_INFO("%s.\n", __func__);
1744 }
1745
rtw_dyn_soml_config(_adapter * adapter)1746 void rtw_dyn_soml_config(_adapter *adapter)
1747 {
1748 RTW_INFO("%s.\n", __func__);
1749
1750 if (adapter->registrypriv.dyn_soml_en == 1) {
1751 /* Must after phydm_adaptive_soml_init() */
1752 rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
1753 RTW_INFO("dyn_soml_en = 1\n");
1754 } else {
1755 if (adapter->registrypriv.dyn_soml_en == 2) {
1756 rtw_dyn_soml_para_set(adapter,
1757 adapter->registrypriv.dyn_soml_train_num,
1758 adapter->registrypriv.dyn_soml_interval,
1759 adapter->registrypriv.dyn_soml_period,
1760 adapter->registrypriv.dyn_soml_delay);
1761 RTW_INFO("dyn_soml_en = 2\n");
1762 RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
1763 adapter->registrypriv.dyn_soml_train_num,
1764 adapter->registrypriv.dyn_soml_interval,
1765 adapter->registrypriv.dyn_soml_period,
1766 adapter->registrypriv.dyn_soml_delay);
1767 } else if (adapter->registrypriv.dyn_soml_en == 0) {
1768 RTW_INFO("dyn_soml_en = 0\n");
1769 } else
1770 RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
1771 adapter->registrypriv.dyn_soml_en);
1772 }
1773 }
1774 #endif
1775
rtw_phydm_set_rrsr(_adapter * adapter,u32 rrsr_value,bool write_rrsr)1776 void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
1777 {
1778 struct dm_struct *phydm = adapter_to_phydm(adapter);
1779 u32 temp_rrsr =0xFFFFFFFF;
1780
1781 if (adapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
1782 temp_rrsr = adapter->registrypriv.set_rrsr_value;
1783 else
1784 temp_rrsr = rrsr_value;
1785
1786 odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, temp_rrsr);
1787 if(write_rrsr)
1788 phydm_rrsr_set_register(phydm, temp_rrsr);
1789 }
rtw_phydm_dyn_rrsr_en(_adapter * adapter,bool en_rrsr)1790 void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr)
1791 {
1792 struct dm_struct *phydm = adapter_to_phydm(adapter);
1793
1794 phydm_rrsr_en(phydm, en_rrsr);
1795 }
rtw_phydm_read_efuse(_adapter * adapter)1796 void rtw_phydm_read_efuse(_adapter *adapter)
1797 {
1798 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1799 struct dm_struct *phydm = &(hal_data->odmpriv);
1800
1801 /*PHYDM API - thermal trim*/
1802 phydm_get_thermal_trim_offset(phydm);
1803 /*PHYDM API - power trim*/
1804 phydm_get_power_trim_offset(phydm);
1805 }
1806
1807 #ifdef CONFIG_LPS_PWR_TRACKING
rtw_phydm_pwr_tracking_directly(_adapter * adapter)1808 void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
1809 {
1810 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1811 u8 rfk_forbidden = _TRUE;
1812 u8 is_linked = _FALSE;
1813
1814 if (rtw_mi_check_status(adapter, MI_ASSOC))
1815 is_linked = _TRUE;
1816
1817 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
1818 halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1819
1820 odm_txpowertracking_direct_ce(&hal_data->odmpriv);
1821 }
1822 #endif
1823
rtw_phydm_watchdog(_adapter * adapter,bool in_lps)1824 void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
1825 {
1826 u8 bLinked = _FALSE;
1827 u8 bsta_state = _FALSE;
1828 u8 bBtDisabled = _TRUE;
1829 u8 rfk_forbidden = _FALSE;
1830 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1831 u8 segment_iqk = _FALSE;
1832 #endif
1833 u8 tx_unlinked_low_rate = 0xFF;
1834 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1835
1836 if (!rtw_is_hw_init_completed(adapter)) {
1837 RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
1838 return;
1839 }
1840 if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY))
1841 pHalData->bScanInProcess = _TRUE;
1842 else
1843 pHalData->bScanInProcess = _FALSE;
1844
1845 if (rtw_mi_check_status(adapter, MI_ASSOC)) {
1846 bLinked = _TRUE;
1847 if (rtw_mi_check_status(adapter, MI_STA_LINKED))
1848 bsta_state = _TRUE;
1849 }
1850
1851 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
1852 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
1853
1854 #ifdef CONFIG_BT_COEXIST
1855 bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
1856 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
1857 (bBtDisabled == _TRUE) ? _FALSE : _TRUE);
1858 #else
1859 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE);
1860 #endif /* CONFIG_BT_COEXIST */
1861
1862 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
1863 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1864
1865 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1866 segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
1867 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
1868 #endif
1869 #ifdef DBG_PHYDM_STATE_CHK
1870 RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
1871 __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
1872 #endif
1873
1874 if (bLinked == _FALSE) {
1875 tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
1876 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
1877 }
1878
1879 /*if (!rtw_mi_stayin_union_band_chk(adapter)) {
1880 #ifdef DBG_PHYDM_STATE_CHK
1881 RTW_ERR("Not stay in union band, skip phydm\n");
1882 #endif
1883 goto _exit;
1884 }*/
1885
1886 #ifdef CONFIG_TDMADIG
1887 rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
1888 #endif/*CONFIG_TDMADIG*/
1889
1890 if (in_lps)
1891 phydm_watchdog_lps(&pHalData->odmpriv);
1892 else
1893 phydm_watchdog(&pHalData->odmpriv);
1894
1895 #ifdef CONFIG_RTW_ACS
1896 rtw_acs_update_current_info(adapter);
1897 #endif
1898
1899 return;
1900 }
1901
1902
1903