1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2012 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8192E_SPEC_H__ 16*4882a593Smuzhiyun #define __RTL8192E_SPEC_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <drv_conf.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define HAL_NAV_UPPER_UNIT_8192E 128 /* micro-second */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* ************************************************************ 23*4882a593Smuzhiyun * 8192E Regsiter offset definition 24*4882a593Smuzhiyun * ************************************************************ */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* ************************************************************ 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * ************************************************************ */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* ----------------------------------------------------- 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * 0x0000h ~ 0x00FFh System Configuration 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * ----------------------------------------------------- */ 35*4882a593Smuzhiyun #define REG_SYS_SWR_CTRL1_8192E 0x0010 /* 1 Byte */ 36*4882a593Smuzhiyun #define REG_SYS_SWR_CTRL2_8192E 0x0014 /* 1 Byte */ 37*4882a593Smuzhiyun #define REG_AFE_CTRL1_8192E 0x0024 38*4882a593Smuzhiyun #define REG_AFE_CTRL2_8192E 0x0028 39*4882a593Smuzhiyun #define REG_AFE_CTRL3_8192E 0x002c 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define REG_PAD_CTRL1_8192E 0x0064 42*4882a593Smuzhiyun #define REG_SDIO_CTRL_8192E 0x0070 43*4882a593Smuzhiyun #define REG_OPT_CTRL_8192E 0x0074 44*4882a593Smuzhiyun #define REG_RF_B_CTRL_8192E 0x0076 45*4882a593Smuzhiyun #define REG_AFE_CTRL4_8192E 0x0078 46*4882a593Smuzhiyun #define REG_LDO_SWR_CTRL 0x007C 47*4882a593Smuzhiyun #define REG_FW_DRV_MSG_8192E 0x0088 48*4882a593Smuzhiyun #define REG_HMEBOX_E2_E3_8192E 0x008C 49*4882a593Smuzhiyun #define REG_HIMR0_8192E 0x00B0 50*4882a593Smuzhiyun #define REG_HISR0_8192E 0x00B4 51*4882a593Smuzhiyun #define REG_HIMR1_8192E 0x00B8 52*4882a593Smuzhiyun #define REG_HISR1_8192E 0x00BC 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define REG_SYS_CFG1_8192E 0x00F0 55*4882a593Smuzhiyun #define REG_SYS_CFG2_8192E 0x00FC 56*4882a593Smuzhiyun /* ----------------------------------------------------- 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * 0x0100h ~ 0x01FFh MACTOP General Configuration 59*4882a593Smuzhiyun * 60*4882a593Smuzhiyun * ----------------------------------------------------- */ 61*4882a593Smuzhiyun #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 62*4882a593Smuzhiyun #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 63*4882a593Smuzhiyun #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 64*4882a593Smuzhiyun #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define REG_RSVD3_8192E 0x0168 67*4882a593Smuzhiyun #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 68*4882a593Smuzhiyun #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 69*4882a593Smuzhiyun #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define REG_HMEBOX_EXT0_8192E 0x01F0 72*4882a593Smuzhiyun #define REG_HMEBOX_EXT1_8192E 0x01F4 73*4882a593Smuzhiyun #define REG_HMEBOX_EXT2_8192E 0x01F8 74*4882a593Smuzhiyun #define REG_HMEBOX_EXT3_8192E 0x01FC 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* ----------------------------------------------------- 77*4882a593Smuzhiyun * 78*4882a593Smuzhiyun * 0x0200h ~ 0x027Fh TXDMA Configuration 79*4882a593Smuzhiyun * 80*4882a593Smuzhiyun * ----------------------------------------------------- */ 81*4882a593Smuzhiyun #define REG_DWBCN0_CTRL 0x0208 82*4882a593Smuzhiyun #define REG_DWBCN1_CTRL 0x0228 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* ----------------------------------------------------- 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun * 0x0280h ~ 0x02FFh RXDMA Configuration 87*4882a593Smuzhiyun * 88*4882a593Smuzhiyun * ----------------------------------------------------- */ 89*4882a593Smuzhiyun #define REG_RXDMA_8192E 0x0290 90*4882a593Smuzhiyun #define REG_EARLY_MODE_CONTROL_8192E 0x02BC 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define REG_RSVD5_8192E 0x02F0 93*4882a593Smuzhiyun #define REG_RSVD6_8192E 0x02F4 94*4882a593Smuzhiyun #define REG_RSVD7_8192E 0x02F8 95*4882a593Smuzhiyun #define REG_RSVD8_8192E 0x02FC 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* ----------------------------------------------------- 98*4882a593Smuzhiyun * 99*4882a593Smuzhiyun * 0x0300h ~ 0x03FFh PCIe 100*4882a593Smuzhiyun * 101*4882a593Smuzhiyun * ----------------------------------------------------- */ 102*4882a593Smuzhiyun #define REG_PCIE_CTRL_REG_8192E 0x0300 103*4882a593Smuzhiyun #define REG_INT_MIG_8192E 0x0304 /* Interrupt Migration */ 104*4882a593Smuzhiyun #define REG_BCNQ_TXBD_DESA_8192E 0x0308 /* TX Beacon Descriptor Address */ 105*4882a593Smuzhiyun #define REG_MGQ_TXBD_DESA_8192E 0x0310 /* TX Manage Queue Descriptor Address */ 106*4882a593Smuzhiyun #define REG_VOQ_TXBD_DESA_8192E 0x0318 /* TX VO Queue Descriptor Address */ 107*4882a593Smuzhiyun #define REG_VIQ_TXBD_DESA_8192E 0x0320 /* TX VI Queue Descriptor Address */ 108*4882a593Smuzhiyun #define REG_BEQ_TXBD_DESA_8192E 0x0328 /* TX BE Queue Descriptor Address */ 109*4882a593Smuzhiyun #define REG_BKQ_TXBD_DESA_8192E 0x0330 /* TX BK Queue Descriptor Address */ 110*4882a593Smuzhiyun #define REG_RXQ_RXBD_DESA_8192E 0x0338 /* RX Queue Descriptor Address */ 111*4882a593Smuzhiyun #define REG_HI0Q_TXBD_DESA_8192E 0x0340 112*4882a593Smuzhiyun #define REG_HI1Q_TXBD_DESA_8192E 0x0348 113*4882a593Smuzhiyun #define REG_HI2Q_TXBD_DESA_8192E 0x0350 114*4882a593Smuzhiyun #define REG_HI3Q_TXBD_DESA_8192E 0x0358 115*4882a593Smuzhiyun #define REG_HI4Q_TXBD_DESA_8192E 0x0360 116*4882a593Smuzhiyun #define REG_HI5Q_TXBD_DESA_8192E 0x0368 117*4882a593Smuzhiyun #define REG_HI6Q_TXBD_DESA_8192E 0x0370 118*4882a593Smuzhiyun #define REG_HI7Q_TXBD_DESA_8192E 0x0378 119*4882a593Smuzhiyun #define REG_MGQ_TXBD_NUM_8192E 0x0380 120*4882a593Smuzhiyun #define REG_RX_RXBD_NUM_8192E 0x0382 121*4882a593Smuzhiyun #define REG_VOQ_TXBD_NUM_8192E 0x0384 122*4882a593Smuzhiyun #define REG_VIQ_TXBD_NUM_8192E 0x0386 123*4882a593Smuzhiyun #define REG_BEQ_TXBD_NUM_8192E 0x0388 124*4882a593Smuzhiyun #define REG_BKQ_TXBD_NUM_8192E 0x038A 125*4882a593Smuzhiyun #define REG_HI0Q_TXBD_NUM_8192E 0x038C 126*4882a593Smuzhiyun #define REG_HI1Q_TXBD_NUM_8192E 0x038E 127*4882a593Smuzhiyun #define REG_HI2Q_TXBD_NUM_8192E 0x0390 128*4882a593Smuzhiyun #define REG_HI3Q_TXBD_NUM_8192E 0x0392 129*4882a593Smuzhiyun #define REG_HI4Q_TXBD_NUM_8192E 0x0394 130*4882a593Smuzhiyun #define REG_HI5Q_TXBD_NUM_8192E 0x0396 131*4882a593Smuzhiyun #define REG_HI6Q_TXBD_NUM_8192E 0x0398 132*4882a593Smuzhiyun #define REG_HI7Q_TXBD_NUM_8192E 0x039A 133*4882a593Smuzhiyun #define REG_TSFTIMER_HCI_8192E 0x039C 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* Read Write Point */ 136*4882a593Smuzhiyun #define REG_VOQ_TXBD_IDX_8192E 0x03A0 137*4882a593Smuzhiyun #define REG_VIQ_TXBD_IDX_8192E 0x03A4 138*4882a593Smuzhiyun #define REG_BEQ_TXBD_IDX_8192E 0x03A8 139*4882a593Smuzhiyun #define REG_BKQ_TXBD_IDX_8192E 0x03AC 140*4882a593Smuzhiyun #define REG_MGQ_TXBD_IDX_8192E 0x03B0 141*4882a593Smuzhiyun #define REG_RXQ_TXBD_IDX_8192E 0x03B4 142*4882a593Smuzhiyun #define REG_HI0Q_TXBD_IDX_8192E 0x03B8 143*4882a593Smuzhiyun #define REG_HI1Q_TXBD_IDX_8192E 0x03BC 144*4882a593Smuzhiyun #define REG_HI2Q_TXBD_IDX_8192E 0x03C0 145*4882a593Smuzhiyun #define REG_HI3Q_TXBD_IDX_8192E 0x03C4 146*4882a593Smuzhiyun #define REG_HI4Q_TXBD_IDX_8192E 0x03C8 147*4882a593Smuzhiyun #define REG_HI5Q_TXBD_IDX_8192E 0x03CC 148*4882a593Smuzhiyun #define REG_HI6Q_TXBD_IDX_8192E 0x03D0 149*4882a593Smuzhiyun #define REG_HI7Q_TXBD_IDX_8192E 0x03D4 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define REG_PCIE_HCPWM_8192EE 0x03D8 /* ?????? */ 152*4882a593Smuzhiyun #define REG_PCIE_HRPWM_8192EE 0x03DC /* PCIe RPWM */ /* ?????? */ 153*4882a593Smuzhiyun #define REG_DBI_WDATA_V1_8192E 0x03E8 154*4882a593Smuzhiyun #define REG_DBI_RDATA_V1_8192E 0x03EC 155*4882a593Smuzhiyun #define REG_DBI_FLAG_V1_8192E 0x03F0 156*4882a593Smuzhiyun #define REG_MDIO_V1_8192E 0x3F4 157*4882a593Smuzhiyun #define REG_PCIE_MIX_CFG_8192E 0x3F8 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* ----------------------------------------------------- 160*4882a593Smuzhiyun * 161*4882a593Smuzhiyun * 0x0400h ~ 0x047Fh Protocol Configuration 162*4882a593Smuzhiyun * 163*4882a593Smuzhiyun * ----------------------------------------------------- */ 164*4882a593Smuzhiyun #define REG_TXBF_CTRL_8192E 0x042C 165*4882a593Smuzhiyun #define REG_ARFR0_8192E 0x0444 166*4882a593Smuzhiyun #define REG_ARFR1_8192E 0x044C 167*4882a593Smuzhiyun #define REG_CCK_CHECK_8192E 0x0454 168*4882a593Smuzhiyun #define REG_AMPDU_MAX_TIME_8192E 0x0456 169*4882a593Smuzhiyun #define REG_BCNQ1_BDNY_8192E 0x0457 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define REG_AMPDU_MAX_LENGTH_8192E 0x0458 172*4882a593Smuzhiyun #define REG_WMAC_LBK_BUF_HD_8192E 0x045D 173*4882a593Smuzhiyun #define REG_NDPA_OPT_CTRL_8192E 0x045F 174*4882a593Smuzhiyun #define REG_DATA_SC_8192E 0x0483 175*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 176*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_LOW 0x0484 177*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_HIGH 0x0488 178*4882a593Smuzhiyun #endif 179*4882a593Smuzhiyun #define REG_ARFR2_8192E 0x048C 180*4882a593Smuzhiyun #define REG_ARFR3_8192E 0x0494 181*4882a593Smuzhiyun #define REG_TXRPT_START_OFFSET 0x04AC 182*4882a593Smuzhiyun #define REG_AMPDU_BURST_MODE_8192E 0x04BC 183*4882a593Smuzhiyun #define REG_HT_SINGLE_AMPDU_8192E 0x04C7 184*4882a593Smuzhiyun #define REG_MACID_PKT_DROP0_8192E 0x04D0 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* ----------------------------------------------------- 187*4882a593Smuzhiyun * 188*4882a593Smuzhiyun * 0x0500h ~ 0x05FFh EDCA Configuration 189*4882a593Smuzhiyun * 190*4882a593Smuzhiyun * ----------------------------------------------------- */ 191*4882a593Smuzhiyun #define REG_CTWND_8192E 0x0572 192*4882a593Smuzhiyun #define REG_SECONDARY_CCA_CTRL_8192E 0x0577 193*4882a593Smuzhiyun #define REG_SCH_TXCMD_8192E 0x05F8 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* ----------------------------------------------------- 196*4882a593Smuzhiyun * 197*4882a593Smuzhiyun * 0x0600h ~ 0x07FFh WMAC Configuration 198*4882a593Smuzhiyun * 199*4882a593Smuzhiyun * ----------------------------------------------------- */ 200*4882a593Smuzhiyun #define REG_MAC_CR_8192E 0x0600 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define REG_MAC_TX_SM_STATE_8192E 0x06B4 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun /* Power */ 205*4882a593Smuzhiyun #define REG_BFMER0_INFO_8192E 0x06E4 206*4882a593Smuzhiyun #define REG_BFMER1_INFO_8192E 0x06EC 207*4882a593Smuzhiyun #define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4 208*4882a593Smuzhiyun #define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8 209*4882a593Smuzhiyun #define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* Hardware Port 2 */ 212*4882a593Smuzhiyun #define REG_BFMEE_SEL_8192E 0x0714 213*4882a593Smuzhiyun #define REG_SND_PTCL_CTRL_8192E 0x0718 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun /* ----------------------------------------------------- 217*4882a593Smuzhiyun * 218*4882a593Smuzhiyun * Redifine register definition for compatibility 219*4882a593Smuzhiyun * 220*4882a593Smuzhiyun * ----------------------------------------------------- */ 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* TODO: use these definition when using REG_xxx naming rule. 223*4882a593Smuzhiyun * NOTE: DO NOT Remove these definition. Use later. */ 224*4882a593Smuzhiyun #define ISR_8192E REG_HISR0_8192E 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 227*4882a593Smuzhiyun * 8192E IMR/ISR bits (offset 0xB0, 8bits) 228*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 229*4882a593Smuzhiyun #define IMR_DISABLED_8192E 0 230*4882a593Smuzhiyun /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 231*4882a593Smuzhiyun #define IMR_TIMER2_8192E BIT(31) /* Timeout interrupt 2 */ 232*4882a593Smuzhiyun #define IMR_TIMER1_8192E BIT(30) /* Timeout interrupt 1 */ 233*4882a593Smuzhiyun #define IMR_PSTIMEOUT_8192E BIT(29) /* Power Save Time Out Interrupt */ 234*4882a593Smuzhiyun #define IMR_GTINT4_8192E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 235*4882a593Smuzhiyun #define IMR_GTINT3_8192E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 236*4882a593Smuzhiyun #define IMR_TXBCN0ERR_8192E BIT(26) /* Transmit Beacon0 Error */ 237*4882a593Smuzhiyun #define IMR_TXBCN0OK_8192E BIT(25) /* Transmit Beacon0 OK */ 238*4882a593Smuzhiyun #define IMR_TSF_BIT32_TOGGLE_8192E BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ 239*4882a593Smuzhiyun #define IMR_BCNDMAINT0_8192E BIT(20) /* Beacon DMA Interrupt 0 */ 240*4882a593Smuzhiyun #define IMR_BCNDERR0_8192E BIT(16) /* Beacon Queue DMA OK0 */ 241*4882a593Smuzhiyun #define IMR_HSISR_IND_ON_INT_8192E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 242*4882a593Smuzhiyun #define IMR_BCNDMAINT_E_8192E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 243*4882a593Smuzhiyun #define IMR_ATIMEND_8192E BIT(12) /* CTWidnow End or ATIM Window End */ 244*4882a593Smuzhiyun #define IMR_C2HCMD_8192E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ 245*4882a593Smuzhiyun #define IMR_CPWM2_8192E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ 246*4882a593Smuzhiyun #define IMR_CPWM_8192E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ 247*4882a593Smuzhiyun #define IMR_HIGHDOK_8192E BIT(7) /* High Queue DMA OK */ 248*4882a593Smuzhiyun #define IMR_MGNTDOK_8192E BIT(6) /* Management Queue DMA OK */ 249*4882a593Smuzhiyun #define IMR_BKDOK_8192E BIT(5) /* AC_BK DMA OK */ 250*4882a593Smuzhiyun #define IMR_BEDOK_8192E BIT(4) /* AC_BE DMA OK */ 251*4882a593Smuzhiyun #define IMR_VIDOK_8192E BIT(3) /* AC_VI DMA OK */ 252*4882a593Smuzhiyun #define IMR_VODOK_8192E BIT(2) /* AC_VO DMA OK */ 253*4882a593Smuzhiyun #define IMR_RDU_8192E BIT(1) /* Rx Descriptor Unavailable */ 254*4882a593Smuzhiyun #define IMR_ROK_8192E BIT(0) /* Receive DMA OK */ 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 257*4882a593Smuzhiyun #define IMR_BCNDMAINT7_8192E BIT(27) /* Beacon DMA Interrupt 7 */ 258*4882a593Smuzhiyun #define IMR_BCNDMAINT6_8192E BIT(26) /* Beacon DMA Interrupt 6 */ 259*4882a593Smuzhiyun #define IMR_BCNDMAINT5_8192E BIT(25) /* Beacon DMA Interrupt 5 */ 260*4882a593Smuzhiyun #define IMR_BCNDMAINT4_8192E BIT(24) /* Beacon DMA Interrupt 4 */ 261*4882a593Smuzhiyun #define IMR_BCNDMAINT3_8192E BIT(23) /* Beacon DMA Interrupt 3 */ 262*4882a593Smuzhiyun #define IMR_BCNDMAINT2_8192E BIT(22) /* Beacon DMA Interrupt 2 */ 263*4882a593Smuzhiyun #define IMR_BCNDMAINT1_8192E BIT(21) /* Beacon DMA Interrupt 1 */ 264*4882a593Smuzhiyun #define IMR_BCNDOK7_8192E BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ 265*4882a593Smuzhiyun #define IMR_BCNDOK6_8192E BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ 266*4882a593Smuzhiyun #define IMR_BCNDOK5_8192E BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ 267*4882a593Smuzhiyun #define IMR_BCNDOK4_8192E BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ 268*4882a593Smuzhiyun #define IMR_BCNDOK3_8192E BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ 269*4882a593Smuzhiyun #define IMR_BCNDOK2_8192E BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ 270*4882a593Smuzhiyun #define IMR_BCNDOK1_8192E BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ 271*4882a593Smuzhiyun #define IMR_ATIMEND_E_8192E BIT(13) /* ATIM Window End Extension for Win7 */ 272*4882a593Smuzhiyun #define IMR_TXERR_8192E BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ 273*4882a593Smuzhiyun #define IMR_RXERR_8192E BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ 274*4882a593Smuzhiyun #define IMR_TXFOVW_8192E BIT(9) /* Transmit FIFO Overflow */ 275*4882a593Smuzhiyun #define IMR_RXFOVW_8192E BIT(8) /* Receive FIFO Overflow */ 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 278*4882a593Smuzhiyun * 8192E Auto LLT bits (offset 0x224, 8bits) 279*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 280*4882a593Smuzhiyun * 224 REG_AUTO_LLT 281*4882a593Smuzhiyun * move to hal_com_reg.h */ 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 284*4882a593Smuzhiyun * 8192E Auto LLT bits (offset 0x290, 32bits) 285*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 286*4882a593Smuzhiyun #define BIT_DMA_MODE BIT(1) 287*4882a593Smuzhiyun #define BIT_USB_RXDMA_AGG_EN BIT(31) 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 290*4882a593Smuzhiyun * 8192E REG_SYS_CFG1 (offset 0xF0, 32bits) 291*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 292*4882a593Smuzhiyun #define BIT_SPSLDO_SEL BIT(24) 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 296*4882a593Smuzhiyun * 8192E REG_CCK_CHECK (offset 0x454, 8bits) 297*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 298*4882a593Smuzhiyun #define BIT_BCN_PORT_SEL BIT(5) 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* **************************************************************************** 301*4882a593Smuzhiyun * Regsiter Bit and Content definition 302*4882a593Smuzhiyun * **************************************************************************** */ 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* 2 ACMHWCTRL 0x05C0 */ 305*4882a593Smuzhiyun #define AcmHw_HwEn_8192E BIT(0) 306*4882a593Smuzhiyun #define AcmHw_VoqEn_8192E BIT(1) 307*4882a593Smuzhiyun #define AcmHw_ViqEn_8192E BIT(2) 308*4882a593Smuzhiyun #define AcmHw_BeqEn_8192E BIT(3) 309*4882a593Smuzhiyun #define AcmHw_VoqStatus_8192E BIT(5) 310*4882a593Smuzhiyun #define AcmHw_ViqStatus_8192E BIT(6) 311*4882a593Smuzhiyun #define AcmHw_BeqStatus_8192E BIT(7) 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun #endif /* __RTL8192E_SPEC_H__ */ 314