1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __PCI_OSINTF_H 16*4882a593Smuzhiyun #define __PCI_OSINTF_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifdef CONFIG_PLATFORM_RTK129X 19*4882a593Smuzhiyun #define PCIE_SLOT1_MEM_START 0x9804F000 20*4882a593Smuzhiyun #define PCIE_SLOT1_MEM_LEN 0x1000 21*4882a593Smuzhiyun #define PCIE_SLOT1_CTRL_START 0x9804EC00 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define PCIE_SLOT2_MEM_START 0x9803C000 24*4882a593Smuzhiyun #define PCIE_SLOT2_MEM_LEN 0x1000 25*4882a593Smuzhiyun #define PCIE_SLOT2_CTRL_START 0x9803BC00 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PCIE_MASK_OFFSET 0x100 /* mask offset from CTRL_START */ 28*4882a593Smuzhiyun #define PCIE_TRANSLATE_OFFSET 0x104 /* translate offset from CTRL_START */ 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PCI_BC_CLK_REQ BIT0 32*4882a593Smuzhiyun #define PCI_BC_ASPM_L0s BIT1 33*4882a593Smuzhiyun #define PCI_BC_ASPM_L1 BIT2 34*4882a593Smuzhiyun #define PCI_BC_ASPM_L1Off BIT3 35*4882a593Smuzhiyun //#define PCI_BC_ASPM_LTR BIT4 36*4882a593Smuzhiyun //#define PCI_BC_ASPM_OBFF BIT5 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void PlatformClearPciPMEStatus(PADAPTER Adapter); 39*4882a593Smuzhiyun void rtw_pci_aspm_config(_adapter *padapter); 40*4882a593Smuzhiyun void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble); 41*4882a593Smuzhiyun #ifdef CONFIG_64BIT_DMA 42*4882a593Smuzhiyun u8 PlatformEnableDMA64(PADAPTER Adapter); 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun #ifdef CONFIG_PCI_DYNAMIC_ASPM 45*4882a593Smuzhiyun void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode); 46*4882a593Smuzhiyun void rtw_pci_set_l1_latency(_adapter *padapter, u8 mode); 47*4882a593Smuzhiyun rtw_pci_dynamic_aspm_set_mode(_adapter * padapter,u8 mode)48*4882a593Smuzhiyunstatic inline void rtw_pci_dynamic_aspm_set_mode(_adapter *padapter, u8 mode) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); 51*4882a593Smuzhiyun struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun if (mode == pcipriv->aspm_mode) 54*4882a593Smuzhiyun return; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun pcipriv->aspm_mode = mode; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL 59*4882a593Smuzhiyun rtw_pci_set_aspm_lnkctl(padapter, mode); 60*4882a593Smuzhiyun #endif 61*4882a593Smuzhiyun #ifdef CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY 62*4882a593Smuzhiyun rtw_pci_set_l1_latency(padapter, mode); 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun } 65*4882a593Smuzhiyun #else 66*4882a593Smuzhiyun #define rtw_pci_dynamic_aspm_set_mode(adapter, mode) 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70