xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/include/hal_intf.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __HAL_INTF_H__
16*4882a593Smuzhiyun #define __HAL_INTF_H__
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun enum RTL871X_HCI_TYPE {
20*4882a593Smuzhiyun 	RTW_PCIE	= BIT0,
21*4882a593Smuzhiyun 	RTW_USB	= BIT1,
22*4882a593Smuzhiyun 	RTW_SDIO	= BIT2,
23*4882a593Smuzhiyun 	RTW_GSPI	= BIT3,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun enum _CHIP_TYPE {
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	NULL_CHIP_TYPE,
29*4882a593Smuzhiyun 	RTL8188E,
30*4882a593Smuzhiyun 	RTL8192E,
31*4882a593Smuzhiyun 	RTL8812,
32*4882a593Smuzhiyun 	RTL8821, /* RTL8811 */
33*4882a593Smuzhiyun 	RTL8723B,
34*4882a593Smuzhiyun 	RTL8814A,
35*4882a593Smuzhiyun 	RTL8703B,
36*4882a593Smuzhiyun 	RTL8188F,
37*4882a593Smuzhiyun 	RTL8188GTV,
38*4882a593Smuzhiyun 	RTL8822B,
39*4882a593Smuzhiyun 	RTL8723D,
40*4882a593Smuzhiyun 	RTL8821C,
41*4882a593Smuzhiyun 	RTL8710B,
42*4882a593Smuzhiyun 	RTL8192F,
43*4882a593Smuzhiyun 	RTL8822C,
44*4882a593Smuzhiyun 	RTL8814B,
45*4882a593Smuzhiyun 	MAX_CHIP_TYPE
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #ifdef RTW_HALMAC
49*4882a593Smuzhiyun enum fw_mem {
50*4882a593Smuzhiyun 	FW_EMEM,
51*4882a593Smuzhiyun 	FW_IMEM,
52*4882a593Smuzhiyun 	FW_DMEM,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun extern const u32 _chip_type_to_odm_ic_type[];
57*4882a593Smuzhiyun #define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)])
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun typedef enum _HAL_HW_TIMER_TYPE {
60*4882a593Smuzhiyun 	HAL_TIMER_NONE = 0,
61*4882a593Smuzhiyun 	HAL_TIMER_TXBF = 1,
62*4882a593Smuzhiyun 	HAL_TIMER_EARLYMODE = 2,
63*4882a593Smuzhiyun } HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun typedef enum _HW_VARIABLES {
67*4882a593Smuzhiyun 	HW_VAR_MEDIA_STATUS,
68*4882a593Smuzhiyun 	HW_VAR_SET_OPMODE,
69*4882a593Smuzhiyun 	HW_VAR_MAC_ADDR,
70*4882a593Smuzhiyun 	HW_VAR_BSSID,
71*4882a593Smuzhiyun 	HW_VAR_INIT_RTS_RATE,
72*4882a593Smuzhiyun 	HW_VAR_BASIC_RATE,
73*4882a593Smuzhiyun 	HW_VAR_TXPAUSE,
74*4882a593Smuzhiyun 	HW_VAR_BCN_FUNC,
75*4882a593Smuzhiyun 	HW_VAR_BCN_CTRL_ADDR,
76*4882a593Smuzhiyun 	HW_VAR_CORRECT_TSF,
77*4882a593Smuzhiyun 	HW_VAR_RCR,
78*4882a593Smuzhiyun 	HW_VAR_MLME_DISCONNECT,
79*4882a593Smuzhiyun 	HW_VAR_MLME_SITESURVEY,
80*4882a593Smuzhiyun 	HW_VAR_MLME_JOIN,
81*4882a593Smuzhiyun 	HW_VAR_ON_RCR_AM,
82*4882a593Smuzhiyun 	HW_VAR_OFF_RCR_AM,
83*4882a593Smuzhiyun 	HW_VAR_BEACON_INTERVAL,
84*4882a593Smuzhiyun 	HW_VAR_SLOT_TIME,
85*4882a593Smuzhiyun 	HW_VAR_RESP_SIFS,
86*4882a593Smuzhiyun 	HW_VAR_ACK_PREAMBLE,
87*4882a593Smuzhiyun 	HW_VAR_SEC_CFG,
88*4882a593Smuzhiyun 	HW_VAR_SEC_DK_CFG,
89*4882a593Smuzhiyun 	HW_VAR_BCN_VALID,
90*4882a593Smuzhiyun 	HW_VAR_FREECNT,
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	/* PHYDM odm->SupportAbility */
93*4882a593Smuzhiyun 	HW_VAR_CAM_EMPTY_ENTRY,
94*4882a593Smuzhiyun 	HW_VAR_CAM_INVALID_ALL,
95*4882a593Smuzhiyun 	HW_VAR_AC_PARAM_VO,
96*4882a593Smuzhiyun 	HW_VAR_AC_PARAM_VI,
97*4882a593Smuzhiyun 	HW_VAR_AC_PARAM_BE,
98*4882a593Smuzhiyun 	HW_VAR_AC_PARAM_BK,
99*4882a593Smuzhiyun 	HW_VAR_ACM_CTRL,
100*4882a593Smuzhiyun #ifdef CONFIG_WMMPS_STA
101*4882a593Smuzhiyun 	HW_VAR_UAPSD_TID,
102*4882a593Smuzhiyun #endif /* CONFIG_WMMPS_STA */
103*4882a593Smuzhiyun 	HW_VAR_AMPDU_MIN_SPACE,
104*4882a593Smuzhiyun #ifdef CONFIG_80211N_HT
105*4882a593Smuzhiyun 	HW_VAR_AMPDU_FACTOR,
106*4882a593Smuzhiyun #endif /* CONFIG_80211N_HT */
107*4882a593Smuzhiyun 	HW_VAR_RXDMA_AGG_PG_TH,
108*4882a593Smuzhiyun 	HW_VAR_SET_RPWM,
109*4882a593Smuzhiyun 	HW_VAR_CPWM,
110*4882a593Smuzhiyun 	HW_VAR_H2C_FW_PWRMODE,
111*4882a593Smuzhiyun 	HW_VAR_H2C_FW_PWRMODE_RFON_CTRL,
112*4882a593Smuzhiyun 	HW_VAR_H2C_INACTIVE_IPS,
113*4882a593Smuzhiyun 	HW_VAR_H2C_PS_TUNE_PARAM,
114*4882a593Smuzhiyun 	HW_VAR_H2C_FW_JOINBSSRPT,
115*4882a593Smuzhiyun 	HW_VAR_FWLPS_RF_ON,
116*4882a593Smuzhiyun 	HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
117*4882a593Smuzhiyun #ifdef CONFIG_LPS_POFF
118*4882a593Smuzhiyun 	HW_VAR_LPS_POFF_INIT,
119*4882a593Smuzhiyun 	HW_VAR_LPS_POFF_DEINIT,
120*4882a593Smuzhiyun 	HW_VAR_LPS_POFF_SET_MODE,
121*4882a593Smuzhiyun 	HW_VAR_LPS_POFF_WOW_EN,
122*4882a593Smuzhiyun #endif
123*4882a593Smuzhiyun #ifdef CONFIG_LPS_PG
124*4882a593Smuzhiyun 	HW_VAR_LPS_PG_HANDLE,
125*4882a593Smuzhiyun #endif
126*4882a593Smuzhiyun 	HW_VAR_TRIGGER_GPIO_0,
127*4882a593Smuzhiyun 	HW_VAR_BT_SET_COEXIST,
128*4882a593Smuzhiyun 	HW_VAR_BT_ISSUE_DELBA,
129*4882a593Smuzhiyun 	HW_VAR_SWITCH_EPHY_WoWLAN,
130*4882a593Smuzhiyun 	HW_VAR_EFUSE_USAGE,
131*4882a593Smuzhiyun 	HW_VAR_EFUSE_BYTES,
132*4882a593Smuzhiyun 	HW_VAR_EFUSE_BT_USAGE,
133*4882a593Smuzhiyun 	HW_VAR_EFUSE_BT_BYTES,
134*4882a593Smuzhiyun 	HW_VAR_FIFO_CLEARN_UP,
135*4882a593Smuzhiyun 	HW_VAR_RESTORE_HW_SEQ,
136*4882a593Smuzhiyun 	HW_VAR_CHECK_TXBUF,
137*4882a593Smuzhiyun 	HW_VAR_PCIE_STOP_TX_DMA,
138*4882a593Smuzhiyun 	HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
139*4882a593Smuzhiyun 	HW_VAR_HCI_SUS_STATE,
140*4882a593Smuzhiyun 	/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
141*4882a593Smuzhiyun 	/* Unit in microsecond. 0 means disable this function. */
142*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
143*4882a593Smuzhiyun 	HW_VAR_WOWLAN,
144*4882a593Smuzhiyun 	HW_VAR_WAKEUP_REASON,
145*4882a593Smuzhiyun #endif
146*4882a593Smuzhiyun 	HW_VAR_RPWM_TOG,
147*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
148*4882a593Smuzhiyun 	HW_VAR_WOW_OUTPUT_GPIO,
149*4882a593Smuzhiyun 	HW_VAR_WOW_INPUT_GPIO,
150*4882a593Smuzhiyun 	HW_SET_GPIO_WL_CTRL,
151*4882a593Smuzhiyun #endif
152*4882a593Smuzhiyun 	HW_VAR_SYS_CLKR,
153*4882a593Smuzhiyun 	HW_VAR_NAV_UPPER,
154*4882a593Smuzhiyun 	HW_VAR_RPT_TIMER_SETTING,
155*4882a593Smuzhiyun 	HW_VAR_TX_RPT_MAX_MACID,
156*4882a593Smuzhiyun 	HW_VAR_CHK_HI_QUEUE_EMPTY,
157*4882a593Smuzhiyun 	HW_VAR_CHK_MGQ_CPU_EMPTY,
158*4882a593Smuzhiyun 	HW_VAR_DL_BCN_SEL,
159*4882a593Smuzhiyun 	HW_VAR_AMPDU_MAX_TIME,
160*4882a593Smuzhiyun 	HW_VAR_WIRELESS_MODE,
161*4882a593Smuzhiyun 	HW_VAR_USB_MODE,
162*4882a593Smuzhiyun 	HW_VAR_PORT_SWITCH,
163*4882a593Smuzhiyun 	HW_VAR_PORT_CFG,
164*4882a593Smuzhiyun 	HW_VAR_DO_IQK,
165*4882a593Smuzhiyun 	HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/
166*4882a593Smuzhiyun 	HW_VAR_SET_REQ_FW_PS,
167*4882a593Smuzhiyun 	HW_VAR_FW_PS_STATE,
168*4882a593Smuzhiyun 	HW_VAR_SOUNDING_ENTER,
169*4882a593Smuzhiyun 	HW_VAR_SOUNDING_LEAVE,
170*4882a593Smuzhiyun 	HW_VAR_SOUNDING_RATE,
171*4882a593Smuzhiyun 	HW_VAR_SOUNDING_STATUS,
172*4882a593Smuzhiyun 	HW_VAR_SOUNDING_FW_NDPA,
173*4882a593Smuzhiyun 	HW_VAR_SOUNDING_CLK,
174*4882a593Smuzhiyun 	HW_VAR_SOUNDING_SET_GID_TABLE,
175*4882a593Smuzhiyun 	HW_VAR_SOUNDING_CSI_REPORT,
176*4882a593Smuzhiyun 	/*Add by YuChen for TXBF HW timer*/
177*4882a593Smuzhiyun 	HW_VAR_HW_REG_TIMER_INIT,
178*4882a593Smuzhiyun 	HW_VAR_HW_REG_TIMER_RESTART,
179*4882a593Smuzhiyun 	HW_VAR_HW_REG_TIMER_START,
180*4882a593Smuzhiyun 	HW_VAR_HW_REG_TIMER_STOP,
181*4882a593Smuzhiyun 	/*Add by YuChen for TXBF HW timer*/
182*4882a593Smuzhiyun 	HW_VAR_DL_RSVD_PAGE,
183*4882a593Smuzhiyun 	HW_VAR_MACID_LINK,
184*4882a593Smuzhiyun 	HW_VAR_MACID_NOLINK,
185*4882a593Smuzhiyun 	HW_VAR_DUMP_MAC_QUEUE_INFO,
186*4882a593Smuzhiyun 	HW_VAR_ASIX_IOT,
187*4882a593Smuzhiyun #ifdef CONFIG_MBSSID_CAM
188*4882a593Smuzhiyun 	HW_VAR_MBSSID_CAM_WRITE,
189*4882a593Smuzhiyun 	HW_VAR_MBSSID_CAM_CLEAR,
190*4882a593Smuzhiyun 	HW_VAR_RCR_MBSSID_EN,
191*4882a593Smuzhiyun #endif
192*4882a593Smuzhiyun 	HW_VAR_EN_HW_UPDATE_TSF,
193*4882a593Smuzhiyun 	HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,
194*4882a593Smuzhiyun 	HW_VAR_CH_SW_IQK_INFO_BACKUP,
195*4882a593Smuzhiyun 	HW_VAR_CH_SW_IQK_INFO_RESTORE,
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	HW_VAR_DBI,
198*4882a593Smuzhiyun 	HW_VAR_MDIO,
199*4882a593Smuzhiyun 	HW_VAR_L1OFF_CAPABILITY,
200*4882a593Smuzhiyun 	HW_VAR_L1OFF_NIC_SUPPORT,
201*4882a593Smuzhiyun #ifdef CONFIG_TDLS
202*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW
203*4882a593Smuzhiyun 	HW_VAR_TDLS_BCN_EARLY_C2H_RPT,
204*4882a593Smuzhiyun #endif
205*4882a593Smuzhiyun #endif
206*4882a593Smuzhiyun 	HW_VAR_DUMP_MAC_TXFIFO,
207*4882a593Smuzhiyun 	HW_VAR_PWR_CMD,
208*4882a593Smuzhiyun #ifdef CONFIG_FW_HANDLE_TXBCN
209*4882a593Smuzhiyun 	HW_VAR_BCN_HEAD_SEL,
210*4882a593Smuzhiyun #endif
211*4882a593Smuzhiyun 	HW_VAR_SET_SOML_PARAM,
212*4882a593Smuzhiyun 	HW_VAR_ENABLE_RX_BAR,
213*4882a593Smuzhiyun 	HW_VAR_TSF_AUTO_SYNC,
214*4882a593Smuzhiyun 	HW_VAR_LPS_STATE_CHK,
215*4882a593Smuzhiyun 	HW_VAR_LPS_RFON_CHK,
216*4882a593Smuzhiyun 	#ifdef CONFIG_RTS_FULL_BW
217*4882a593Smuzhiyun 	HW_VAR_SET_RTS_BW,
218*4882a593Smuzhiyun 	#endif
219*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
220*4882a593Smuzhiyun 	HW_VAR_ENSWBCN,
221*4882a593Smuzhiyun #endif
222*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
223*4882a593Smuzhiyun 	HW_VAR_VENDOR_WOW_MODE,
224*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
225*4882a593Smuzhiyun } HW_VARIABLES;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun typedef enum _HAL_DEF_VARIABLE {
228*4882a593Smuzhiyun 	HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
229*4882a593Smuzhiyun 	HAL_DEF_IS_SUPPORT_ANT_DIV,
230*4882a593Smuzhiyun 	HAL_DEF_DRVINFO_SZ,
231*4882a593Smuzhiyun 	HAL_DEF_MAX_RECVBUF_SZ,
232*4882a593Smuzhiyun 	HAL_DEF_RX_PACKET_OFFSET,
233*4882a593Smuzhiyun 	HAL_DEF_RX_DMA_SZ_WOW,
234*4882a593Smuzhiyun 	HAL_DEF_RX_DMA_SZ,
235*4882a593Smuzhiyun 	HAL_DEF_RX_PAGE_SIZE,
236*4882a593Smuzhiyun 	HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
237*4882a593Smuzhiyun 	HAL_DEF_RA_DECISION_RATE,
238*4882a593Smuzhiyun 	HAL_DEF_RA_SGI,
239*4882a593Smuzhiyun 	HAL_DEF_PT_PWR_STATUS,
240*4882a593Smuzhiyun 	HAL_DEF_TX_LDPC,				/* LDPC support */
241*4882a593Smuzhiyun 	HAL_DEF_RX_LDPC,				/* LDPC support */
242*4882a593Smuzhiyun 	HAL_DEF_TX_STBC,				/* TX STBC support */
243*4882a593Smuzhiyun 	HAL_DEF_RX_STBC,				/* RX STBC support */
244*4882a593Smuzhiyun 	HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit  Compressed Steering Capable */
245*4882a593Smuzhiyun 	HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */
246*4882a593Smuzhiyun 	HAL_DEF_VHT_MU_BEAMFORMER,	/* VHT MU Beamformer support */
247*4882a593Smuzhiyun 	HAL_DEF_VHT_MU_BEAMFORMEE,	/* VHT MU Beamformee support */
248*4882a593Smuzhiyun 	HAL_DEF_BEAMFORMER_CAP,
249*4882a593Smuzhiyun 	HAL_DEF_BEAMFORMEE_CAP,
250*4882a593Smuzhiyun 	HW_VAR_MAX_RX_AMPDU_FACTOR,
251*4882a593Smuzhiyun 	HW_DEF_RA_INFO_DUMP,
252*4882a593Smuzhiyun 	HAL_DEF_DBG_DUMP_TXPKT,
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	HAL_DEF_TX_PAGE_SIZE,
255*4882a593Smuzhiyun 	HAL_DEF_TX_PAGE_BOUNDARY,
256*4882a593Smuzhiyun 	HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
257*4882a593Smuzhiyun 	HAL_DEF_TX_BUFFER_LAST_ENTRY,
258*4882a593Smuzhiyun 	HAL_DEF_ANT_DETECT,/* to do for 8723a */
259*4882a593Smuzhiyun 	HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */
260*4882a593Smuzhiyun 	HAL_DEF_EFUSE_USAGE,	/* Get current EFUSE utilization. 2008.12.19. Added by Roger. */
261*4882a593Smuzhiyun 	HAL_DEF_EFUSE_BYTES,
262*4882a593Smuzhiyun 	HW_VAR_BEST_AMPDU_DENSITY,
263*4882a593Smuzhiyun } HAL_DEF_VARIABLE;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun typedef enum _HAL_ODM_VARIABLE {
266*4882a593Smuzhiyun 	HAL_ODM_STA_INFO,
267*4882a593Smuzhiyun 	HAL_ODM_P2P_STATE,
268*4882a593Smuzhiyun 	HAL_ODM_WIFI_DISPLAY_STATE,
269*4882a593Smuzhiyun 	HAL_ODM_REGULATION,
270*4882a593Smuzhiyun 	HAL_ODM_INITIAL_GAIN,
271*4882a593Smuzhiyun 	HAL_ODM_RX_INFO_DUMP,
272*4882a593Smuzhiyun 	HAL_ODM_RX_Dframe_INFO,
273*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY
274*4882a593Smuzhiyun 	HAL_ODM_ANTDIV_SELECT
275*4882a593Smuzhiyun #endif
276*4882a593Smuzhiyun } HAL_ODM_VARIABLE;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun typedef enum _HAL_INTF_PS_FUNC {
279*4882a593Smuzhiyun 	HAL_USB_SELECT_SUSPEND,
280*4882a593Smuzhiyun 	HAL_MAX_ID,
281*4882a593Smuzhiyun } HAL_INTF_PS_FUNC;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun struct txpwr_idx_comp;
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun struct hal_ops {
288*4882a593Smuzhiyun 	/*** initialize section ***/
289*4882a593Smuzhiyun 	void	(*read_chip_version)(_adapter *padapter);
290*4882a593Smuzhiyun 	void	(*init_default_value)(_adapter *padapter);
291*4882a593Smuzhiyun 	void	(*intf_chip_configure)(_adapter *padapter);
292*4882a593Smuzhiyun 	u8	(*read_adapter_info)(_adapter *padapter);
293*4882a593Smuzhiyun 	u32(*hal_power_on)(_adapter *padapter);
294*4882a593Smuzhiyun 	void	(*hal_power_off)(_adapter *padapter);
295*4882a593Smuzhiyun 	u32(*hal_init)(_adapter *padapter);
296*4882a593Smuzhiyun 	u32(*hal_deinit)(_adapter *padapter);
297*4882a593Smuzhiyun 	void	(*dm_init)(_adapter *padapter);
298*4882a593Smuzhiyun 	void	(*dm_deinit)(_adapter *padapter);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	/*** xmit section ***/
301*4882a593Smuzhiyun 	s32(*init_xmit_priv)(_adapter *padapter);
302*4882a593Smuzhiyun 	void	(*free_xmit_priv)(_adapter *padapter);
303*4882a593Smuzhiyun 	s32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe);
304*4882a593Smuzhiyun 	/*
305*4882a593Smuzhiyun 	 * mgnt_xmit should be implemented to run in interrupt context
306*4882a593Smuzhiyun 	 */
307*4882a593Smuzhiyun 	s32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe);
308*4882a593Smuzhiyun 	s32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
309*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE
310*4882a593Smuzhiyun 	s32(*xmit_thread_handler)(_adapter *padapter);
311*4882a593Smuzhiyun #endif
312*4882a593Smuzhiyun 	void	(*run_thread)(_adapter *padapter);
313*4882a593Smuzhiyun 	void	(*cancel_thread)(_adapter *padapter);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	/*** recv section ***/
316*4882a593Smuzhiyun 	s32(*init_recv_priv)(_adapter *padapter);
317*4882a593Smuzhiyun 	void	(*free_recv_priv)(_adapter *padapter);
318*4882a593Smuzhiyun #ifdef CONFIG_RECV_THREAD_MODE
319*4882a593Smuzhiyun 	s32 (*recv_hdl)(_adapter *adapter);
320*4882a593Smuzhiyun #endif
321*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
322*4882a593Smuzhiyun 	u32(*inirp_init)(_adapter *padapter);
323*4882a593Smuzhiyun 	u32(*inirp_deinit)(_adapter *padapter);
324*4882a593Smuzhiyun #endif
325*4882a593Smuzhiyun 	/*** interrupt hdl section ***/
326*4882a593Smuzhiyun 	void	(*enable_interrupt)(_adapter *padapter);
327*4882a593Smuzhiyun 	void	(*disable_interrupt)(_adapter *padapter);
328*4882a593Smuzhiyun 	u8(*check_ips_status)(_adapter *padapter);
329*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
330*4882a593Smuzhiyun 	s32(*interrupt_handler)(_adapter *padapter);
331*4882a593Smuzhiyun 	void (*unmap_beacon_icf)(_adapter *padapter);
332*4882a593Smuzhiyun #endif
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
335*4882a593Smuzhiyun 	void	(*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf);
336*4882a593Smuzhiyun #endif
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
339*4882a593Smuzhiyun 	void	(*irp_reset)(_adapter *padapter);
340*4882a593Smuzhiyun #endif
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	/*** DM section ***/
343*4882a593Smuzhiyun #ifdef CONFIG_RTW_SW_LED
344*4882a593Smuzhiyun 	void	(*InitSwLeds)(_adapter *padapter);
345*4882a593Smuzhiyun 	void	(*DeInitSwLeds)(_adapter *padapter);
346*4882a593Smuzhiyun #endif
347*4882a593Smuzhiyun 	void	(*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	void (*set_tx_power_level_handler)(_adapter *adapter, u8 channel);
350*4882a593Smuzhiyun 	void (*set_txpwr_done)(_adapter *adapter);
351*4882a593Smuzhiyun 	void (*set_tx_power_index_handler)(_adapter *adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	u8 (*get_tx_power_index_handler)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
354*4882a593Smuzhiyun 		, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
355*4882a593Smuzhiyun 	s8 (*get_txpwr_target_extra_bias)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	void	(*hal_dm_watchdog)(_adapter *padapter);
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	u8	(*set_hw_reg_handler)(_adapter *padapter, u8	variable, u8 *val);
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	void	(*GetHwRegHandler)(_adapter *padapter, u8	variable, u8 *val);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	void	(*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
370*4882a593Smuzhiyun 	void	(*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	void	(*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
377*4882a593Smuzhiyun 	void	(*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
378*4882a593Smuzhiyun 	u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
379*4882a593Smuzhiyun 	void	(*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
380*4882a593Smuzhiyun #ifdef CONFIG_SYSON_INDIRECT_ACCESS
381*4882a593Smuzhiyun 	u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
382*4882a593Smuzhiyun 	void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
383*4882a593Smuzhiyun #endif
384*4882a593Smuzhiyun 	void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params);
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun #ifdef CONFIG_HOSTAPD_MLME
387*4882a593Smuzhiyun 	s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt);
388*4882a593Smuzhiyun #endif
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
391*4882a593Smuzhiyun 	void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
392*4882a593Smuzhiyun 	void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
393*4882a593Smuzhiyun 	void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
394*4882a593Smuzhiyun 	u16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
395*4882a593Smuzhiyun 	int	(*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
396*4882a593Smuzhiyun 	int	(*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
397*4882a593Smuzhiyun 	u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
398*4882a593Smuzhiyun 	BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
399*4882a593Smuzhiyun #if defined(CONFIG_RTL8710B)
400*4882a593Smuzhiyun 	BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value);
401*4882a593Smuzhiyun #endif
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT
404*4882a593Smuzhiyun 	void (*sreset_init_value)(_adapter *padapter);
405*4882a593Smuzhiyun 	void (*sreset_reset_value)(_adapter *padapter);
406*4882a593Smuzhiyun 	void (*silentreset)(_adapter *padapter);
407*4882a593Smuzhiyun 	void (*sreset_xmit_status_check)(_adapter *padapter);
408*4882a593Smuzhiyun 	void (*sreset_linked_status_check)(_adapter *padapter);
409*4882a593Smuzhiyun 	u8(*sreset_get_wifi_status)(_adapter *padapter);
410*4882a593Smuzhiyun 	bool (*sreset_inprogress)(_adapter *padapter);
411*4882a593Smuzhiyun #endif
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun #ifdef CONFIG_IOL
414*4882a593Smuzhiyun 	int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
415*4882a593Smuzhiyun #endif
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	void (*hal_notch_filter)(_adapter *adapter, bool enable);
418*4882a593Smuzhiyun #ifdef RTW_HALMAC
419*4882a593Smuzhiyun 	void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length);
420*4882a593Smuzhiyun #else
421*4882a593Smuzhiyun 	s32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
422*4882a593Smuzhiyun #endif
423*4882a593Smuzhiyun 	void (*reqtxrpt)(_adapter *padapter, u8 macid);
424*4882a593Smuzhiyun 	s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
425*4882a593Smuzhiyun 	void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen,
426*4882a593Smuzhiyun 				 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
427*4882a593Smuzhiyun 	s32(*fw_dl)(_adapter *adapter, u8 wowlan);
428*4882a593Smuzhiyun #ifdef RTW_HALMAC
429*4882a593Smuzhiyun 	s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem);
430*4882a593Smuzhiyun #endif
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)
433*4882a593Smuzhiyun 	void (*clear_interrupt)(_adapter *padapter);
434*4882a593Smuzhiyun #endif
435*4882a593Smuzhiyun 	u8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan);
436*4882a593Smuzhiyun #ifdef CONFIG_GPIO_API
437*4882a593Smuzhiyun 	void (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag);
438*4882a593Smuzhiyun 	int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num);
439*4882a593Smuzhiyun 	void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num);
440*4882a593Smuzhiyun #endif
441*4882a593Smuzhiyun #ifdef CONFIG_FW_CORRECT_BCN
442*4882a593Smuzhiyun 	void (*fw_correct_bcn)(PADAPTER padapter);
443*4882a593Smuzhiyun #endif
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun #ifdef RTW_HALMAC
446*4882a593Smuzhiyun 	u8(*init_mac_register)(PADAPTER);
447*4882a593Smuzhiyun 	u8(*init_phy)(PADAPTER);
448*4882a593Smuzhiyun #endif /* RTW_HALMAC */
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
451*4882a593Smuzhiyun 	void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable);
452*4882a593Smuzhiyun #endif
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun #ifdef CONFIG_RFKILL_POLL
455*4882a593Smuzhiyun 	bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid);
456*4882a593Smuzhiyun #endif
457*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING
458*4882a593Smuzhiyun 	void (*tx_poll_handler)(_adapter *adapter);
459*4882a593Smuzhiyun #endif
460*4882a593Smuzhiyun };
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun typedef	enum _RT_EEPROM_TYPE {
463*4882a593Smuzhiyun 	EEPROM_93C46,
464*4882a593Smuzhiyun 	EEPROM_93C56,
465*4882a593Smuzhiyun 	EEPROM_BOOT_EFUSE,
466*4882a593Smuzhiyun } RT_EEPROM_TYPE, *PRT_EEPROM_TYPE;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun #define RF_CHANGE_BY_INIT	0
471*4882a593Smuzhiyun #define RF_CHANGE_BY_IPS	BIT28
472*4882a593Smuzhiyun #define RF_CHANGE_BY_PS	BIT29
473*4882a593Smuzhiyun #define RF_CHANGE_BY_HW	BIT30
474*4882a593Smuzhiyun #define RF_CHANGE_BY_SW	BIT31
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun typedef enum _HARDWARE_TYPE {
477*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188EE,
478*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188EU,
479*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188ES,
480*4882a593Smuzhiyun 	/*	NEW_GENERATION_IC */
481*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8192EE,
482*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8192EU,
483*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8192ES,
484*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8812E,
485*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8812AU,
486*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8811AU,
487*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821E,
488*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821U,
489*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821S,
490*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8723BE,
491*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8723BU,
492*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8723BS,
493*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8814AE,
494*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8814AU,
495*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8814AS,
496*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821BE,
497*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821BU,
498*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821BS,
499*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8822BE,
500*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8822BU,
501*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8822BS,
502*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8703BE,
503*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8703BU,
504*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8703BS,
505*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188FE,
506*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188FU,
507*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188FS,
508*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188GTVU,
509*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8188GTVS,
510*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8723DE,
511*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8723DU,
512*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8723DS,
513*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821CE,
514*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821CU,
515*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8821CS,
516*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8710BU,
517*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8192FS,
518*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8192FU,
519*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8192FE,
520*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8822CE,
521*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8822CU,
522*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8822CS,
523*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8814BE,
524*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8814BU,
525*4882a593Smuzhiyun 	HARDWARE_TYPE_RTL8814BS,
526*4882a593Smuzhiyun 	HARDWARE_TYPE_MAX,
527*4882a593Smuzhiyun } HARDWARE_TYPE;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun #define IS_NEW_GENERATION_IC(_Adapter)	(rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE)
530*4882a593Smuzhiyun /*
531*4882a593Smuzhiyun  * RTL8188E Series
532*4882a593Smuzhiyun  *   */
533*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188EE(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE)
534*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188EU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU)
535*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188ES(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES)
536*4882a593Smuzhiyun #define	IS_HARDWARE_TYPE_8188E(_Adapter)	\
537*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun /* RTL8812 Series */
540*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8812E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E)
541*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8812AU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU)
542*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8812(_Adapter)			\
543*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun /* RTL8821 Series */
546*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E)
547*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8811AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
548*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821U(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \
549*4882a593Smuzhiyun 		rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
550*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821S(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S)
551*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821(_Adapter)			\
552*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter))
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR(_Adapter)		\
555*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun /* RTL8192E Series */
558*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192EE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE)
559*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192EU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU)
560*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192ES(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES)
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192E(_Adapter)		\
563*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter))
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE)
566*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU)
567*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS)
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723B(_Adapter) \
570*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter))
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun /* RTL8814A Series */
573*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814AE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE)
574*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU)
575*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814AS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS)
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814A(_Adapter)		\
578*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter))
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun /* RTL8703B Series */
581*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8703BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE)
582*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8703BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS)
583*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8703BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU)
584*4882a593Smuzhiyun #define	IS_HARDWARE_TYPE_8703B(_Adapter)			\
585*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter))
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun /* RTL8723D Series */
588*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723DE(_Adapter)\
589*4882a593Smuzhiyun 	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE)
590*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723DS(_Adapter)\
591*4882a593Smuzhiyun 	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS)
592*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723DU(_Adapter)\
593*4882a593Smuzhiyun 	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU)
594*4882a593Smuzhiyun #define	IS_HARDWARE_TYPE_8723D(_Adapter)\
595*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8723DE(_Adapter) || \
596*4882a593Smuzhiyun 	 IS_HARDWARE_TYPE_8723DU(_Adapter) || \
597*4882a593Smuzhiyun 	 IS_HARDWARE_TYPE_8723DS(_Adapter))
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun /* RTL8192F Series */
600*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192FS(_Adapter)\
601*4882a593Smuzhiyun 	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS)
602*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192FU(_Adapter)\
603*4882a593Smuzhiyun 	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU)
604*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192FE(_Adapter)\
605*4882a593Smuzhiyun 	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE)
606*4882a593Smuzhiyun #define	IS_HARDWARE_TYPE_8192F(_Adapter)\
607*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8192FS(_Adapter) ||\
608*4882a593Smuzhiyun 	 IS_HARDWARE_TYPE_8192FU(_Adapter) ||\
609*4882a593Smuzhiyun 	 IS_HARDWARE_TYPE_8192FE(_Adapter))
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun /* RTL8188F Series */
612*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188FE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)
613*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188FS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)
614*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188FU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU)
615*4882a593Smuzhiyun #define	IS_HARDWARE_TYPE_8188F(_Adapter)			\
616*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188GTVU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU)
619*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188GTVS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS)
620*4882a593Smuzhiyun #define	IS_HARDWARE_TYPE_8188GTV(_Adapter)			\
621*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter))
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun /* RTL8710B Series */
624*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU)
625*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter))
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)
628*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)
629*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821B(_Adapter)		\
632*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter))
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE)
635*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU)
636*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS)
637*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822B(_Adapter)		\
638*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter))
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821CE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE)
641*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821CU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU)
642*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821CS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS)
643*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821C(_Adapter)		\
644*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822CE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CE)
647*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822CU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CU)
648*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822CS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CS)
649*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822C(_Adapter)		\
650*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8822CE(_Adapter) || IS_HARDWARE_TYPE_8822CU(_Adapter) || IS_HARDWARE_TYPE_8822CS(_Adapter))
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BE)
653*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BU)
654*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BS)
655*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814B(_Adapter)		\
656*4882a593Smuzhiyun 		(IS_HARDWARE_TYPE_8814BE(_Adapter) || IS_HARDWARE_TYPE_8814BU(_Adapter) || IS_HARDWARE_TYPE_8814BS(_Adapter))
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR2(_Adapter)		\
659*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter)		\
662*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR3(_Adapter)		\
665*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_8814B(_Adapter) || IS_HARDWARE_TYPE_8822C(_Adapter))
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR_ALL(_Adapter)		\
668*4882a593Smuzhiyun 	(IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) || IS_HARDWARE_TYPE_JAGUAR3(_Adapter))
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun typedef enum _wowlan_subcode {
672*4882a593Smuzhiyun 	WOWLAN_ENABLE			= 0,
673*4882a593Smuzhiyun 	WOWLAN_DISABLE			= 1,
674*4882a593Smuzhiyun 	WOWLAN_AP_ENABLE		= 2,
675*4882a593Smuzhiyun 	WOWLAN_AP_DISABLE		= 3,
676*4882a593Smuzhiyun 	WOWLAN_PATTERN_CLEAN		= 4
677*4882a593Smuzhiyun } wowlan_subcode;
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun struct wowlan_ioctl_param {
680*4882a593Smuzhiyun 	unsigned int subcode;
681*4882a593Smuzhiyun 	unsigned int subcode_value;
682*4882a593Smuzhiyun 	unsigned int wakeup_reason;
683*4882a593Smuzhiyun };
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun u8 rtw_hal_data_init(_adapter *padapter);
686*4882a593Smuzhiyun void rtw_hal_data_deinit(_adapter *padapter);
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun void rtw_hal_def_value_init(_adapter *padapter);
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun void	rtw_hal_free_data(_adapter *padapter);
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun void rtw_hal_dm_init(_adapter *padapter);
693*4882a593Smuzhiyun void rtw_hal_dm_deinit(_adapter *padapter);
694*4882a593Smuzhiyun #ifdef CONFIG_RTW_SW_LED
695*4882a593Smuzhiyun void rtw_hal_sw_led_init(_adapter *padapter);
696*4882a593Smuzhiyun void rtw_hal_sw_led_deinit(_adapter *padapter);
697*4882a593Smuzhiyun #endif
698*4882a593Smuzhiyun u32 rtw_hal_power_on(_adapter *padapter);
699*4882a593Smuzhiyun void rtw_hal_power_off(_adapter *padapter);
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun uint rtw_hal_init(_adapter *padapter);
702*4882a593Smuzhiyun #ifdef CONFIG_NEW_NETDEV_HDL
703*4882a593Smuzhiyun uint rtw_hal_iface_init(_adapter *adapter);
704*4882a593Smuzhiyun #endif
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit);
707*4882a593Smuzhiyun void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter);
708*4882a593Smuzhiyun void dump_hal_trx_mode(void *sel, _adapter *adapter);
709*4882a593Smuzhiyun u8 rtw_hal_rfpath_init(_adapter *adapter);
710*4882a593Smuzhiyun u8 rtw_hal_trxnss_init(_adapter *adapter);
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun uint rtw_hal_deinit(_adapter *padapter);
713*4882a593Smuzhiyun void rtw_hal_stop(_adapter *padapter);
714*4882a593Smuzhiyun u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
715*4882a593Smuzhiyun void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun void rtw_hal_chip_configure(_adapter *padapter);
718*4882a593Smuzhiyun u8 rtw_hal_read_chip_info(_adapter *padapter);
719*4882a593Smuzhiyun void rtw_hal_read_chip_version(_adapter *padapter);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
722*4882a593Smuzhiyun u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
725*4882a593Smuzhiyun void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun void rtw_hal_enable_interrupt(_adapter *padapter);
728*4882a593Smuzhiyun void rtw_hal_disable_interrupt(_adapter *padapter);
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun u8 rtw_hal_check_ips_status(_adapter *padapter);
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
733*4882a593Smuzhiyun 	u32	rtw_hal_inirp_init(_adapter *padapter);
734*4882a593Smuzhiyun 	u32	rtw_hal_inirp_deinit(_adapter *padapter);
735*4882a593Smuzhiyun #endif
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
738*4882a593Smuzhiyun 	void	rtw_hal_irp_reset(_adapter *padapter);
739*4882a593Smuzhiyun void	rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data);
740*4882a593Smuzhiyun u8	rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr);
741*4882a593Smuzhiyun void	rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data);
742*4882a593Smuzhiyun u16	rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr);
743*4882a593Smuzhiyun u8	rtw_hal_pci_l1off_nic_support(_adapter *padapter);
744*4882a593Smuzhiyun u8	rtw_hal_pci_l1off_capability(_adapter *padapter);
745*4882a593Smuzhiyun #endif
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun u8	rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
750*4882a593Smuzhiyun s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
751*4882a593Smuzhiyun s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun s32	rtw_hal_init_xmit_priv(_adapter *padapter);
754*4882a593Smuzhiyun void	rtw_hal_free_xmit_priv(_adapter *padapter);
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun s32	rtw_hal_init_recv_priv(_adapter *padapter);
757*4882a593Smuzhiyun void	rtw_hal_free_recv_priv(_adapter *padapter);
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun void rtw_hal_update_ra_mask(struct sta_info *psta);
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun void	rtw_hal_start_thread(_adapter *padapter);
762*4882a593Smuzhiyun void	rtw_hal_stop_thread(_adapter *padapter);
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
767*4882a593Smuzhiyun void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
768*4882a593Smuzhiyun u32	rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
769*4882a593Smuzhiyun void	rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun #define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))
773*4882a593Smuzhiyun #define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))
774*4882a593Smuzhiyun #define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
775*4882a593Smuzhiyun #define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun #ifdef CONFIG_SYSON_INDIRECT_ACCESS
778*4882a593Smuzhiyun u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask);
779*4882a593Smuzhiyun void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
780*4882a593Smuzhiyun #define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask))
781*4882a593Smuzhiyun #define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data))
782*4882a593Smuzhiyun #endif
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun #define phy_set_mac_reg	phy_set_bb_reg
785*4882a593Smuzhiyun #define phy_query_mac_reg phy_query_bb_reg
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
788*4882a593Smuzhiyun 	s32	rtw_hal_interrupt_handler(_adapter *padapter);
789*4882a593Smuzhiyun 	void	rtw_hal_unmap_beacon_icf(_adapter *padapter);
790*4882a593Smuzhiyun #endif
791*4882a593Smuzhiyun #if  defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
792*4882a593Smuzhiyun 	void	rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
793*4882a593Smuzhiyun #endif
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
796*4882a593Smuzhiyun void	rtw_hal_dm_watchdog(_adapter *padapter);
797*4882a593Smuzhiyun void	rtw_hal_dm_watchdog_in_lps(_adapter *padapter);
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun #ifdef CONFIG_HOSTAPD_MLME
800*4882a593Smuzhiyun 	s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
801*4882a593Smuzhiyun #endif
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT
804*4882a593Smuzhiyun void rtw_hal_sreset_init(_adapter *padapter);
805*4882a593Smuzhiyun void rtw_hal_sreset_reset(_adapter *padapter);
806*4882a593Smuzhiyun void rtw_hal_sreset_reset_value(_adapter *padapter);
807*4882a593Smuzhiyun void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
808*4882a593Smuzhiyun void rtw_hal_sreset_linked_status_check(_adapter *padapter);
809*4882a593Smuzhiyun u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter);
810*4882a593Smuzhiyun bool rtw_hal_sreset_inprogress(_adapter *padapter);
811*4882a593Smuzhiyun #endif
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun #ifdef CONFIG_IOL
814*4882a593Smuzhiyun int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
815*4882a593Smuzhiyun #endif
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE
818*4882a593Smuzhiyun s32 rtw_hal_xmit_thread_handler(_adapter *padapter);
819*4882a593Smuzhiyun #endif
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun #ifdef CONFIG_RECV_THREAD_MODE
822*4882a593Smuzhiyun s32 rtw_hal_recv_hdl(_adapter *adapter);
823*4882a593Smuzhiyun #endif
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun void rtw_hal_notch_filter(_adapter *adapter, bool enable);
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_REG
828*4882a593Smuzhiyun bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload);
829*4882a593Smuzhiyun bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf);
830*4882a593Smuzhiyun s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf);
831*4882a593Smuzhiyun #endif
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_PKT
834*4882a593Smuzhiyun bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload);
835*4882a593Smuzhiyun #endif
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
838*4882a593Smuzhiyun #ifndef RTW_HALMAC
839*4882a593Smuzhiyun s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
840*4882a593Smuzhiyun s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
841*4882a593Smuzhiyun #endif
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter);
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid);
846*4882a593Smuzhiyun s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid);
847*4882a593Smuzhiyun s32 rtw_hal_macid_sleep_all_used(_adapter *adapter);
848*4882a593Smuzhiyun s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter);
849*4882a593Smuzhiyun 
850*4882a593Smuzhiyun s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid);
851*4882a593Smuzhiyun s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid);
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
854*4882a593Smuzhiyun void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
855*4882a593Smuzhiyun 			      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
856*4882a593Smuzhiyun u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan);
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun #ifdef CONFIG_GPIO_API
859*4882a593Smuzhiyun void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag);
860*4882a593Smuzhiyun int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num);
861*4882a593Smuzhiyun void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num);
862*4882a593Smuzhiyun #endif
863*4882a593Smuzhiyun #ifdef CONFIG_FW_CORRECT_BCN
864*4882a593Smuzhiyun void rtw_hal_fw_correct_bcn(_adapter *padapter);
865*4882a593Smuzhiyun #endif
866*4882a593Smuzhiyun s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
869*4882a593Smuzhiyun 	void rtw_hal_clear_interrupt(_adapter *padapter);
870*4882a593Smuzhiyun #endif
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel);
873*4882a593Smuzhiyun void rtw_hal_update_txpwr_level(_adapter *adapter);
874*4882a593Smuzhiyun void rtw_hal_set_txpwr_done(_adapter *adapter);
875*4882a593Smuzhiyun void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
876*4882a593Smuzhiyun 	, enum rf_path rfpath, u8 rate);
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
879*4882a593Smuzhiyun 	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
880*4882a593Smuzhiyun 	, struct txpwr_idx_comp *tic);
881*4882a593Smuzhiyun s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
882*4882a593Smuzhiyun 	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun u8 rtw_hal_ops_check(_adapter *padapter);
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun #ifdef RTW_HALMAC
887*4882a593Smuzhiyun 	u8 rtw_hal_init_mac_register(PADAPTER);
888*4882a593Smuzhiyun 	u8 rtw_hal_init_phy(PADAPTER);
889*4882a593Smuzhiyun s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem);
890*4882a593Smuzhiyun #endif /* RTW_HALMAC */
891*4882a593Smuzhiyun 
892*4882a593Smuzhiyun #ifdef CONFIG_RFKILL_POLL
893*4882a593Smuzhiyun bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid);
894*4882a593Smuzhiyun #endif
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun #endif /* __HAL_INTF_H__ */
897