1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2019 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __HAL_IC_CFG_H__ 16*4882a593Smuzhiyun #define __HAL_IC_CFG_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define RTL8188E_SUPPORT 0 19*4882a593Smuzhiyun #define RTL8812A_SUPPORT 0 20*4882a593Smuzhiyun #define RTL8821A_SUPPORT 0 21*4882a593Smuzhiyun #define RTL8723B_SUPPORT 0 22*4882a593Smuzhiyun #define RTL8723D_SUPPORT 0 23*4882a593Smuzhiyun #define RTL8192E_SUPPORT 0 24*4882a593Smuzhiyun #define RTL8192F_SUPPORT 0 25*4882a593Smuzhiyun #define RTL8814A_SUPPORT 0 26*4882a593Smuzhiyun #define RTL8195A_SUPPORT 0 27*4882a593Smuzhiyun #define RTL8197F_SUPPORT 0 28*4882a593Smuzhiyun #define RTL8703B_SUPPORT 0 29*4882a593Smuzhiyun #define RTL8188F_SUPPORT 0 30*4882a593Smuzhiyun #define RTL8822B_SUPPORT 0 31*4882a593Smuzhiyun #define RTL8821B_SUPPORT 0 32*4882a593Smuzhiyun #define RTL8821C_SUPPORT 0 33*4882a593Smuzhiyun #define RTL8710B_SUPPORT 0 34*4882a593Smuzhiyun #define RTL8814B_SUPPORT 0 35*4882a593Smuzhiyun #define RTL8824B_SUPPORT 0 36*4882a593Smuzhiyun #define RTL8198F_SUPPORT 0 37*4882a593Smuzhiyun #define RTL8195B_SUPPORT 0 38*4882a593Smuzhiyun #define RTL8822C_SUPPORT 0 39*4882a593Smuzhiyun #define RTL8721D_SUPPORT 0 40*4882a593Smuzhiyun #define RTL8812F_SUPPORT 0 41*4882a593Smuzhiyun #define RTL8197G_SUPPORT 0 42*4882a593Smuzhiyun #define RTL8710C_SUPPORT 0 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /*#if (RTL8188E_SUPPORT==1)*/ 46*4882a593Smuzhiyun #define RATE_ADAPTIVE_SUPPORT 0 47*4882a593Smuzhiyun #define POWER_TRAINING_ACTIVE 0 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #ifdef CONFIG_MULTIDRV 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifdef CONFIG_RTL8188E 53*4882a593Smuzhiyun #undef RTL8188E_SUPPORT 54*4882a593Smuzhiyun #undef RATE_ADAPTIVE_SUPPORT 55*4882a593Smuzhiyun #undef POWER_TRAINING_ACTIVE 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define RTL8188E_SUPPORT 1 58*4882a593Smuzhiyun #define RATE_ADAPTIVE_SUPPORT 1 59*4882a593Smuzhiyun #define POWER_TRAINING_ACTIVE 1 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 62*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #ifdef CONFIG_RTL8812A 67*4882a593Smuzhiyun #undef RTL8812A_SUPPORT 68*4882a593Smuzhiyun #define RTL8812A_SUPPORT 1 69*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 70*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 73*4882a593Smuzhiyun #define CONFIG_BEAMFORMER_FW_NDPA 74*4882a593Smuzhiyun #define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/ 75*4882a593Smuzhiyun #define SUPPORT_MU_BF 0 76*4882a593Smuzhiyun #endif /*CONFIG_BEAMFORMING*/ 77*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 80*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 81*4882a593Smuzhiyun #endif 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #ifdef CONFIG_RTL8821A 85*4882a593Smuzhiyun #undef RTL8821A_SUPPORT 86*4882a593Smuzhiyun #define RTL8821A_SUPPORT 1 87*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 88*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 91*4882a593Smuzhiyun #define CONFIG_BEAMFORMER_FW_NDPA 92*4882a593Smuzhiyun #define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/ 93*4882a593Smuzhiyun #define SUPPORT_MU_BF 0 94*4882a593Smuzhiyun #endif 95*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 98*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun #endif 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #ifdef CONFIG_RTL8192E 103*4882a593Smuzhiyun #undef RTL8192E_SUPPORT 104*4882a593Smuzhiyun #define RTL8192E_SUPPORT 1 105*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 106*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 107*4882a593Smuzhiyun #endif 108*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 111*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 112*4882a593Smuzhiyun #endif 113*4882a593Smuzhiyun #endif 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #ifdef CONFIG_RTL8192F 116*4882a593Smuzhiyun #undef RTL8192F_SUPPORT 117*4882a593Smuzhiyun #define RTL8192F_SUPPORT 1 118*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 119*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 120*4882a593Smuzhiyun #endif 121*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 122*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 123*4882a593Smuzhiyun #endif 124*4882a593Smuzhiyun /*#define CONFIG_AMPDU_PRETX_CD*/ 125*4882a593Smuzhiyun /*#define DBG_LA_MODE*/ 126*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 127*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 128*4882a593Smuzhiyun #endif 129*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 130*4882a593Smuzhiyun /* #define CONFIG_NARROWBAND_SUPPORTING */ 131*4882a593Smuzhiyun #ifdef CONFIG_NARROWBAND_SUPPORTING 132*4882a593Smuzhiyun #define CONFIG_NB_VALUE RTW_NB_CONFIG_NONE /*RTW_NB_CONFIG_WIDTH_10 or RTW_NB_CONFIG_WIDTH_5 */ 133*4882a593Smuzhiyun #endif 134*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 135*4882a593Smuzhiyun #define CONFIG_WOW_PATTERN_IN_TXFIFO 136*4882a593Smuzhiyun #endif 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 139*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 140*4882a593Smuzhiyun #endif 141*4882a593Smuzhiyun #endif 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #ifdef CONFIG_RTL8723B 144*4882a593Smuzhiyun #undef RTL8723B_SUPPORT 145*4882a593Smuzhiyun #define RTL8723B_SUPPORT 1 146*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 147*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 148*4882a593Smuzhiyun #endif 149*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 152*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 153*4882a593Smuzhiyun #endif 154*4882a593Smuzhiyun #endif 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #ifdef CONFIG_RTL8723D 157*4882a593Smuzhiyun #undef RTL8723D_SUPPORT 158*4882a593Smuzhiyun #define RTL8723D_SUPPORT 1 159*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 160*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 161*4882a593Smuzhiyun #endif 162*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 163*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 164*4882a593Smuzhiyun #endif 165*4882a593Smuzhiyun #ifndef CONFIG_RTW_CUSTOMER_STR 166*4882a593Smuzhiyun #define CONFIG_RTW_CUSTOMER_STR 167*4882a593Smuzhiyun #endif 168*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 171*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 172*4882a593Smuzhiyun #endif 173*4882a593Smuzhiyun #endif 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #ifdef CONFIG_RTL8814A 176*4882a593Smuzhiyun #undef RTL8814A_SUPPORT 177*4882a593Smuzhiyun #define RTL8814A_SUPPORT 1 178*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 179*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 180*4882a593Smuzhiyun #endif 181*4882a593Smuzhiyun #define CONFIG_FW_CORRECT_BCN 182*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 183*4882a593Smuzhiyun #define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/ 184*4882a593Smuzhiyun #define SUPPORT_MU_BF 0 185*4882a593Smuzhiyun #endif 186*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 189*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 190*4882a593Smuzhiyun #endif 191*4882a593Smuzhiyun #endif 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #ifdef CONFIG_RTL8703B 194*4882a593Smuzhiyun #undef RTL8703B_SUPPORT 195*4882a593Smuzhiyun #define RTL8703B_SUPPORT 1 196*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 197*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 198*4882a593Smuzhiyun #endif 199*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 200*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 201*4882a593Smuzhiyun #endif 202*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 205*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 206*4882a593Smuzhiyun #endif 207*4882a593Smuzhiyun #endif 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #ifdef CONFIG_RTL8188F 210*4882a593Smuzhiyun #undef RTL8188F_SUPPORT 211*4882a593Smuzhiyun #define RTL8188F_SUPPORT 1 212*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 213*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 214*4882a593Smuzhiyun #endif 215*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 216*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 217*4882a593Smuzhiyun #endif 218*4882a593Smuzhiyun #ifndef CONFIG_RTW_CUSTOMER_STR 219*4882a593Smuzhiyun #define CONFIG_RTW_CUSTOMER_STR 220*4882a593Smuzhiyun #endif 221*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 224*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 225*4882a593Smuzhiyun #endif 226*4882a593Smuzhiyun #endif 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #ifdef CONFIG_RTL8188GTV 229*4882a593Smuzhiyun #undef RTL8188F_SUPPORT 230*4882a593Smuzhiyun #define RTL8188F_SUPPORT 1 231*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 232*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 233*4882a593Smuzhiyun #endif 234*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 235*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 236*4882a593Smuzhiyun #endif 237*4882a593Smuzhiyun #ifndef CONFIG_RTW_CUSTOMER_STR 238*4882a593Smuzhiyun #define CONFIG_RTW_CUSTOMER_STR 239*4882a593Smuzhiyun #endif 240*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 243*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 244*4882a593Smuzhiyun #endif 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) && !defined(CONFIG_FW_OFFLOAD_SET_TXPWR_IDX) 247*4882a593Smuzhiyun #define CONFIG_FW_OFFLOAD_SET_TXPWR_IDX 248*4882a593Smuzhiyun #endif 249*4882a593Smuzhiyun #endif 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #ifdef CONFIG_RTL8822B 252*4882a593Smuzhiyun #undef RTL8822B_SUPPORT 253*4882a593Smuzhiyun #define RTL8822B_SUPPORT 1 254*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 255*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 256*4882a593Smuzhiyun #endif /* CONFIG_FW_C2H_PKT */ 257*4882a593Smuzhiyun #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ 258*4882a593Smuzhiyun #define RTW_AMPDU_AGG_RETRY_AND_NEW 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 261*4882a593Smuzhiyun #define CONFIG_GTK_OL 262*4882a593Smuzhiyun /*#define CONFIG_ARP_KEEP_ALIVE*/ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 265*4882a593Smuzhiyun #ifndef WAKEUP_GPIO_IDX 266*4882a593Smuzhiyun #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ 267*4882a593Smuzhiyun #endif /* !WAKEUP_GPIO_IDX */ 268*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */ 269*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 272*4882a593Smuzhiyun #define CONFIG_AP_PORT_SWAP 273*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 274*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */ 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun /* 277*4882a593Smuzhiyun * Beamforming related definition 278*4882a593Smuzhiyun */ 279*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 280*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 281*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 282*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 285*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 286*4882a593Smuzhiyun #endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #ifndef DBG_RX_DFRAME_RAW_DATA 289*4882a593Smuzhiyun #define DBG_RX_DFRAME_RAW_DATA 290*4882a593Smuzhiyun #endif /* DBG_RX_DFRAME_RAW_DATA */ 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 293*4882a593Smuzhiyun #define RTW_IQK_FW_OFFLOAD 294*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* Checksum offload feature */ 297*4882a593Smuzhiyun /*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ 298*4882a593Smuzhiyun #if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG) 299*4882a593Smuzhiyun #define CONFIG_RTW_NETIF_SG 300*4882a593Smuzhiyun #endif 301*4882a593Smuzhiyun #define CONFIG_TCP_CSUM_OFFLOAD_RX 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun #define CONFIG_ADVANCE_OTA 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE 306*4882a593Smuzhiyun #define CONFIG_MCC_MODE_V2 307*4882a593Smuzhiyun #define CONFIG_MCC_PHYDM_OFFLOAD 308*4882a593Smuzhiyun #endif /* CONFIG_MCC_MODE */ 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) 311*4882a593Smuzhiyun #define CONFIG_TDLS_CH_SW_V2 312*4882a593Smuzhiyun #endif 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun #ifndef RTW_CHANNEL_SWITCH_OFFLOAD 315*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW_V2 316*4882a593Smuzhiyun #define RTW_CHANNEL_SWITCH_OFFLOAD 317*4882a593Smuzhiyun #endif 318*4882a593Smuzhiyun #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) 321*4882a593Smuzhiyun /* Supported since fw v22.1 */ 322*4882a593Smuzhiyun #define RTW_PER_CMD_SUPPORT_FW 323*4882a593Smuzhiyun #endif /* RTW_PER_CMD_SUPPORT_FW */ 324*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 325*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 326*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 327*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 328*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 329*4882a593Smuzhiyun #endif 330*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun #ifdef CONFIG_LPS 333*4882a593Smuzhiyun #define CONFIG_LPS_ACK /* Supported after FW v30 & v27.9 */ 334*4882a593Smuzhiyun #endif 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 337*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 338*4882a593Smuzhiyun #endif 339*4882a593Smuzhiyun #endif /* CONFIG_RTL8822B */ 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C 342*4882a593Smuzhiyun #undef RTL8822C_SUPPORT 343*4882a593Smuzhiyun #define RTL8822C_SUPPORT 1 344*4882a593Smuzhiyun /*#define DBG_LA_MODE*/ 345*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 346*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 347*4882a593Smuzhiyun #endif /* CONFIG_FW_C2H_PKT */ 348*4882a593Smuzhiyun #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 351*4882a593Smuzhiyun #define CONFIG_GTK_OL 352*4882a593Smuzhiyun /*#define CONFIG_ARP_KEEP_ALIVE*/ 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 355*4882a593Smuzhiyun #ifndef WAKEUP_GPIO_IDX 356*4882a593Smuzhiyun #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ 357*4882a593Smuzhiyun #endif /* !WAKEUP_GPIO_IDX */ 358*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */ 359*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 362*4882a593Smuzhiyun #define CONFIG_AP_PORT_SWAP 363*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 364*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */ 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun /* 367*4882a593Smuzhiyun * Beamforming related definition 368*4882a593Smuzhiyun */ 369*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 370*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 371*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 372*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun #ifdef CONFIG_NO_FW 375*4882a593Smuzhiyun #ifdef CONFIG_RTW_MAC_HIDDEN_RPT 376*4882a593Smuzhiyun #undef CONFIG_RTW_MAC_HIDDEN_RPT 377*4882a593Smuzhiyun #endif 378*4882a593Smuzhiyun #else 379*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 380*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 381*4882a593Smuzhiyun #endif 382*4882a593Smuzhiyun #endif 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun #ifndef DBG_RX_DFRAME_RAW_DATA 385*4882a593Smuzhiyun #define DBG_RX_DFRAME_RAW_DATA 386*4882a593Smuzhiyun #endif /* DBG_RX_DFRAME_RAW_DATA */ 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 389*4882a593Smuzhiyun /* #define RTW_IQK_FW_OFFLOAD */ 390*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 391*4882a593Smuzhiyun #define CONFIG_ADVANCE_OTA 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE 394*4882a593Smuzhiyun #define CONFIG_MCC_MODE_V2 395*4882a593Smuzhiyun #define CONFIG_MCC_PHYDM_OFFLOAD 396*4882a593Smuzhiyun #endif /* CONFIG_MCC_MODE */ 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) 399*4882a593Smuzhiyun #define CONFIG_TDLS_CH_SW_V2 400*4882a593Smuzhiyun #endif 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun #ifndef RTW_CHANNEL_SWITCH_OFFLOAD 403*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW_V2 404*4882a593Smuzhiyun #define RTW_CHANNEL_SWITCH_OFFLOAD 405*4882a593Smuzhiyun #endif 406*4882a593Smuzhiyun #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) 409*4882a593Smuzhiyun /* Supported since fw v22.1 */ 410*4882a593Smuzhiyun #define RTW_PER_CMD_SUPPORT_FW 411*4882a593Smuzhiyun #endif /* RTW_PER_CMD_SUPPORT_FW */ 412*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 413*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 414*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun /*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ 417*4882a593Smuzhiyun #if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG) 418*4882a593Smuzhiyun #define CONFIG_RTW_NETIF_SG 419*4882a593Smuzhiyun #endif 420*4882a593Smuzhiyun #define CONFIG_TCP_CSUM_OFFLOAD_RX 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 423*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 424*4882a593Smuzhiyun #endif 425*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun #ifdef CONFIG_LPS 428*4882a593Smuzhiyun #define CONFIG_LPS_ACK /* Supported after FW v07 */ 429*4882a593Smuzhiyun #define CONFIG_LPS_1T1R /* Supported after FW v07 */ 430*4882a593Smuzhiyun #endif 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun #define CONFIG_BT_EFUSE_MASK 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 435*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 436*4882a593Smuzhiyun #endif 437*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 438*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 439*4882a593Smuzhiyun #endif 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun #define CONFIG_RTL8822C_XCAP_NEW_POLICY 442*4882a593Smuzhiyun #endif /* CONFIG_RTL8822C */ 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun #ifdef CONFIG_RTL8821C 445*4882a593Smuzhiyun #undef RTL8821C_SUPPORT 446*4882a593Smuzhiyun #define RTL8821C_SUPPORT 1 447*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 448*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 449*4882a593Smuzhiyun #endif 450*4882a593Smuzhiyun #ifdef CONFIG_NO_FW 451*4882a593Smuzhiyun #ifdef CONFIG_RTW_MAC_HIDDEN_RPT 452*4882a593Smuzhiyun #undef CONFIG_RTW_MAC_HIDDEN_RPT 453*4882a593Smuzhiyun #endif 454*4882a593Smuzhiyun #else 455*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 456*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 457*4882a593Smuzhiyun #endif 458*4882a593Smuzhiyun #endif 459*4882a593Smuzhiyun #define LOAD_FW_HEADER_FROM_DRIVER 460*4882a593Smuzhiyun #define CONFIG_PHY_CAPABILITY_QUERY 461*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 462*4882a593Smuzhiyun #define CONFIG_AP_PORT_SWAP 463*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 464*4882a593Smuzhiyun #endif 465*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 466*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 467*4882a593Smuzhiyun #define RTW_IQK_FW_OFFLOAD 468*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 469*4882a593Smuzhiyun /*#define CONFIG_AMPDU_PRETX_CD*/ 470*4882a593Smuzhiyun /*#define DBG_PRE_TX_HANG*/ 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun /* Beamforming related definition */ 473*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 474*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 475*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 476*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 477*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 478*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 479*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 480*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 481*4882a593Smuzhiyun #endif 482*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun #ifdef CONFIG_LPS 485*4882a593Smuzhiyun /* #define CONFIG_LPS_ACK */ /* Supported after FW v25 */ 486*4882a593Smuzhiyun #endif 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 489*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 490*4882a593Smuzhiyun #endif 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun #define CONFIG_BT_EFUSE_MASK 493*4882a593Smuzhiyun #endif /*CONFIG_RTL8821C*/ 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun #ifdef CONFIG_RTL8710B 496*4882a593Smuzhiyun #undef RTL8710B_SUPPORT 497*4882a593Smuzhiyun #define RTL8710B_SUPPORT 1 498*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 499*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 500*4882a593Smuzhiyun #endif 501*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 504*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 505*4882a593Smuzhiyun #endif 506*4882a593Smuzhiyun #endif 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun #ifdef CONFIG_RTL8814B 509*4882a593Smuzhiyun #undef RTL8814B_SUPPORT 510*4882a593Smuzhiyun #define RTL8814B_SUPPORT 1 511*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 512*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 513*4882a593Smuzhiyun #endif /* CONFIG_FW_C2H_PKT */ 514*4882a593Smuzhiyun #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ 515*4882a593Smuzhiyun #define RTW_AMPDU_AGG_RETRY_AND_NEW 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 518*4882a593Smuzhiyun #define CONFIG_GTK_OL 519*4882a593Smuzhiyun /*#define CONFIG_ARP_KEEP_ALIVE*/ 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 522*4882a593Smuzhiyun #ifndef WAKEUP_GPIO_IDX 523*4882a593Smuzhiyun #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ 524*4882a593Smuzhiyun #endif /* !WAKEUP_GPIO_IDX */ 525*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */ 526*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 529*4882a593Smuzhiyun /*#define CONFIG_AP_PORT_SWAP*/ 530*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 531*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */ 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun /* 534*4882a593Smuzhiyun * Beamforming related definition 535*4882a593Smuzhiyun */ 536*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 537*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 538*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 539*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun #ifndef DBG_RX_DFRAME_RAW_DATA 542*4882a593Smuzhiyun #define DBG_RX_DFRAME_RAW_DATA 543*4882a593Smuzhiyun #endif /* DBG_RX_DFRAME_RAW_DATA */ 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 546*4882a593Smuzhiyun #define RTW_IQK_FW_OFFLOAD 547*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun /* Checksum offload feature */ 550*4882a593Smuzhiyun /*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */ 551*4882a593Smuzhiyun #define CONFIG_TCP_CSUM_OFFLOAD_RX 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun #define CONFIG_ADVANCE_OTA 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE 556*4882a593Smuzhiyun #define CONFIG_MCC_MODE_V2 557*4882a593Smuzhiyun #define CONFIG_MCC_PHYDM_OFFLOAD 558*4882a593Smuzhiyun #endif /* CONFIG_MCC_MODE */ 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) 561*4882a593Smuzhiyun #define CONFIG_TDLS_CH_SW_V2 562*4882a593Smuzhiyun #endif 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun #ifndef RTW_CHANNEL_SWITCH_OFFLOAD 565*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW_V2 566*4882a593Smuzhiyun #define RTW_CHANNEL_SWITCH_OFFLOAD 567*4882a593Smuzhiyun #endif 568*4882a593Smuzhiyun #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) 571*4882a593Smuzhiyun /* Supported since fw v22.1 */ 572*4882a593Smuzhiyun #define RTW_PER_CMD_SUPPORT_FW 573*4882a593Smuzhiyun #endif /* RTW_PER_CMD_SUPPORT_FW */ 574*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 575*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 576*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 577*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 578*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 579*4882a593Smuzhiyun #endif 580*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun #define CONFIG_PROTSEL_PORT 583*4882a593Smuzhiyun #define CONFIG_PROTSEL_ATIMDTIM 584*4882a593Smuzhiyun #define CONFIG_PROTSEL_MACSLEEP 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR 587*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_BCN_FUNC 588*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_MLME_DISCONNECT 589*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_MLME_JOIN 590*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_CORRECT_TSF 591*4882a593Smuzhiyun #define CONFIG_HAS_TX_BEACON_PAUSE 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun #define CONFIG_RTW_TX_NPATH_EN /* 8814B is always 4TX */ 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun #ifdef CONFIG_LPS 596*4882a593Smuzhiyun #define CONFIG_LPS_ACK /* Supported after FW v04 */ 597*4882a593Smuzhiyun #endif 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 600*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 601*4882a593Smuzhiyun #endif 602*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 603*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 604*4882a593Smuzhiyun #endif 605*4882a593Smuzhiyun #endif /* CONFIG_RTL8814B */ 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun #endif /*__HAL_IC_CFG_H__*/ 608