1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __HAL_DATA_H__ 16 #define __HAL_DATA_H__ 17 18 #if 1/* def CONFIG_SINGLE_IMG */ 19 20 #include "../hal/phydm/phydm_precomp.h" 21 #ifdef CONFIG_BT_COEXIST 22 #include <hal_btcoex.h> 23 #endif 24 #include <hal_btcoex_wifionly.h> 25 26 #ifdef CONFIG_SDIO_HCI 27 #include <hal_sdio.h> 28 #endif 29 #ifdef CONFIG_GSPI_HCI 30 #include <hal_gspi.h> 31 #endif 32 33 #if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) 34 #include "../hal/hal_dm_acs.h" 35 #endif 36 37 /* 38 * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 39 * */ 40 typedef enum _RT_MULTI_FUNC { 41 RT_MULTI_FUNC_NONE = 0x00, 42 RT_MULTI_FUNC_WIFI = 0x01, 43 RT_MULTI_FUNC_BT = 0x02, 44 RT_MULTI_FUNC_GPS = 0x04, 45 } RT_MULTI_FUNC, *PRT_MULTI_FUNC; 46 /* 47 * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 48 * */ 49 typedef enum _RT_POLARITY_CTL { 50 RT_POLARITY_LOW_ACT = 0, 51 RT_POLARITY_HIGH_ACT = 1, 52 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 53 54 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 55 typedef enum _RT_REGULATOR_MODE { 56 RT_SWITCHING_REGULATOR = 0, 57 RT_LDO_REGULATOR = 1, 58 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 59 60 /* 61 * Interface type. 62 * */ 63 typedef enum _INTERFACE_SELECT_PCIE { 64 INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */ 65 INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */ 66 INTF_SEL2_PCIe = 2, /* PCIe Card */ 67 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 68 69 70 typedef enum _INTERFACE_SELECT_USB { 71 INTF_SEL0_USB = 0, /* USB */ 72 INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */ 73 INTF_SEL2_MINICARD = 2, /* Minicard */ 74 INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */ 75 INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */ 76 INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */ 77 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 78 79 typedef enum _RT_AMPDU_BRUST_MODE { 80 RT_AMPDU_BRUST_NONE = 0, 81 RT_AMPDU_BRUST_92D = 1, 82 RT_AMPDU_BRUST_88E = 2, 83 RT_AMPDU_BRUST_8812_4 = 3, 84 RT_AMPDU_BRUST_8812_8 = 4, 85 RT_AMPDU_BRUST_8812_12 = 5, 86 RT_AMPDU_BRUST_8812_15 = 6, 87 RT_AMPDU_BRUST_8723B = 7, 88 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; 89 90 /* Tx Power Limit Table Size */ 91 #define MAX_REGULATION_NUM 4 92 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 93 #define MAX_2_4G_BANDWIDTH_NUM 2 94 #define MAX_RATE_SECTION_NUM 10 95 #define MAX_5G_BANDWIDTH_NUM 4 96 97 #define NUM_OF_TARGET_TXPWR_2G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 98 #define NUM_OF_TARGET_TXPWR_5G 9 /* OFDM:1, HT:4, VHT:4 */ 99 100 #ifdef RTW_RX_AGGREGATION 101 typedef enum _RX_AGG_MODE { 102 RX_AGG_DISABLE, 103 RX_AGG_DMA, 104 RX_AGG_USB, 105 RX_AGG_MIX 106 } RX_AGG_MODE; 107 108 /* #define MAX_RX_DMA_BUFFER_SIZE 10240 */ /* 10K for 8192C RX DMA buffer */ 109 110 #endif /* RTW_RX_AGGREGATION */ 111 112 /* E-Fuse */ 113 #ifdef CONFIG_RTL8188E 114 #define EFUSE_MAP_SIZE 512 115 #endif 116 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) 117 #define EFUSE_MAP_SIZE 512 118 #endif 119 #ifdef CONFIG_RTL8192E 120 #define EFUSE_MAP_SIZE 512 121 #endif 122 #ifdef CONFIG_RTL8723B 123 #define EFUSE_MAP_SIZE 512 124 #endif 125 #ifdef CONFIG_RTL8814A 126 #define EFUSE_MAP_SIZE 512 127 #endif 128 #ifdef CONFIG_RTL8703B 129 #define EFUSE_MAP_SIZE 512 130 #endif 131 #ifdef CONFIG_RTL8723D 132 #define EFUSE_MAP_SIZE 512 133 #endif 134 #ifdef CONFIG_RTL8188F 135 #define EFUSE_MAP_SIZE 512 136 #endif 137 #ifdef CONFIG_RTL8188GTV 138 #define EFUSE_MAP_SIZE 512 139 #endif 140 #ifdef CONFIG_RTL8710B 141 #define EFUSE_MAP_SIZE 512 142 #endif 143 #ifdef CONFIG_RTL8192F 144 #define EFUSE_MAP_SIZE 512 145 #endif 146 147 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814B) 148 #define EFUSE_MAX_SIZE 1024 149 #elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B) 150 #define EFUSE_MAX_SIZE 256 151 #else 152 #define EFUSE_MAX_SIZE 512 153 #endif 154 /* end of E-Fuse */ 155 156 #define Mac_OFDM_OK 0x00000000 157 #define Mac_OFDM_Fail 0x10000000 158 #define Mac_OFDM_FasleAlarm 0x20000000 159 #define Mac_CCK_OK 0x30000000 160 #define Mac_CCK_Fail 0x40000000 161 #define Mac_CCK_FasleAlarm 0x50000000 162 #define Mac_HT_OK 0x60000000 163 #define Mac_HT_Fail 0x70000000 164 #define Mac_HT_FasleAlarm 0x90000000 165 #define Mac_DropPacket 0xA0000000 166 167 #ifdef CONFIG_RF_POWER_TRIM 168 #if defined(CONFIG_RTL8723B) 169 #define REG_RF_BB_GAIN_OFFSET 0x7f 170 #define RF_GAIN_OFFSET_MASK 0xfffff 171 #elif defined(CONFIG_RTL8188E) 172 #define REG_RF_BB_GAIN_OFFSET 0x55 173 #define RF_GAIN_OFFSET_MASK 0xfffff 174 #else 175 #define REG_RF_BB_GAIN_OFFSET 0x55 176 #define RF_GAIN_OFFSET_MASK 0xfffff 177 #endif /* CONFIG_RTL8723B */ 178 #endif /*CONFIG_RF_POWER_TRIM*/ 179 180 /* For store initial value of BB register */ 181 typedef struct _BB_INIT_REGISTER { 182 u16 offset; 183 u32 value; 184 185 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 186 187 #define PAGE_SIZE_128 128 188 #define PAGE_SIZE_256 256 189 #define PAGE_SIZE_512 512 190 191 #define HCI_SUS_ENTER 0 192 #define HCI_SUS_LEAVING 1 193 #define HCI_SUS_LEAVE 2 194 #define HCI_SUS_ENTERING 3 195 #define HCI_SUS_ERR 4 196 197 #define EFUSE_FILE_UNUSED 0 198 #define EFUSE_FILE_FAILED 1 199 #define EFUSE_FILE_LOADED 2 200 201 #define MACADDR_FILE_UNUSED 0 202 #define MACADDR_FILE_FAILED 1 203 #define MACADDR_FILE_LOADED 2 204 205 #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 206 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 207 208 struct kfree_data_t { 209 u8 flag; 210 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 211 212 #if CONFIG_IEEE80211_BAND_5GHZ 213 s8 pa_bias_5g[RF_PATH_MAX]; 214 s8 pad_bias_5g[RF_PATH_MAX]; 215 #endif 216 s8 thermal; 217 }; 218 219 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 220 221 struct hal_spec_t { 222 char *ic_name; 223 u8 macid_num; 224 225 u8 sec_cam_ent_num; 226 u8 sec_cap; 227 u8 wow_cap; 228 u8 macid_cap; 229 u16 macid_txrpt; 230 u8 macid_txrpt_pgsz; 231 232 u8 rfpath_num_2g:4; /* used for tx power index path */ 233 u8 rfpath_num_5g:4; /* used for tx power index path */ 234 u8 rf_reg_path_num; 235 u8 rf_reg_path_avail_num; 236 u8 rf_reg_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */ 237 u8 max_tx_cnt; 238 239 u8 tx_nss_num:4; 240 u8 rx_nss_num:4; 241 242 u8 band_cap; /* value of BAND_CAP_XXX */ 243 u8 bw_cap; /* value of BW_CAP_XXX */ 244 u8 port_num; 245 u8 proto_cap; /* value of PROTO_CAP_XXX */ 246 247 u8 txgi_max; /* maximum tx power gain index */ 248 u8 txgi_pdbm; /* tx power gain index per dBm */ 249 250 u8 wl_func; /* value of WL_FUNC_XXX */ 251 252 u8 tx_aclt_unit_factor; /* how many 32us */ 253 254 u8 rx_tsf_filter:1; 255 256 u8 pg_txpwr_saddr; /* starting address of PG tx power info */ 257 u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */ 258 259 u8 hci_type; /* value of HCI Type */ 260 }; 261 262 #define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path)) 263 #define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path)) 264 #define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \ 265 _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \ 266 _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0) 267 268 #ifdef CONFIG_PHY_CAPABILITY_QUERY 269 struct phy_spec_t { 270 u32 trx_cap; 271 u32 stbc_cap; 272 u32 ldpc_cap; 273 u32 txbf_param; 274 u32 txbf_cap; 275 }; 276 #endif 277 struct hal_iqk_reg_backup { 278 u8 central_chnl; 279 u8 bw_mode; 280 u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; 281 }; 282 283 284 typedef struct hal_p2p_ps_para { 285 /*DW0*/ 286 u8 offload_en:1; 287 u8 role:1; 288 u8 ctwindow_en:1; 289 u8 noa_en:1; 290 u8 noa_sel:1; 291 u8 all_sta_sleep:1; 292 u8 discovery:1; 293 u8 disable_close_rf:1; 294 u8 p2p_port_id; 295 u8 p2p_group; 296 u8 p2p_macid; 297 298 /*DW1*/ 299 u8 ctwindow_length; 300 u8 rsvd3; 301 u8 rsvd4; 302 u8 rsvd5; 303 304 /*DW2*/ 305 u32 noa_duration_para; 306 307 /*DW3*/ 308 u32 noa_interval_para; 309 310 /*DW4*/ 311 u32 noa_start_time_para; 312 313 /*DW5*/ 314 u32 noa_count_para; 315 } HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; 316 317 #define TXPWR_LMT_RS_CCK 0 318 #define TXPWR_LMT_RS_OFDM 1 319 #define TXPWR_LMT_RS_HT 2 320 #define TXPWR_LMT_RS_VHT 3 321 #define TXPWR_LMT_RS_NUM 4 322 323 #define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */ 324 #define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */ 325 326 #if CONFIG_TXPWR_LIMIT 327 extern const char *const _txpwr_lmt_rs_str[]; 328 #define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)]) 329 330 struct txpwr_lmt_ent { 331 _list list; 332 333 s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM] 334 [TXPWR_LMT_RS_NUM_2G] 335 [CENTER_CH_2G_NUM] 336 [MAX_TX_COUNT]; 337 338 #if CONFIG_IEEE80211_BAND_5GHZ 339 s8 lmt_5g[MAX_5G_BANDWIDTH_NUM] 340 [TXPWR_LMT_RS_NUM_5G] 341 [CENTER_CH_5G_ALL_NUM] 342 [MAX_TX_COUNT]; 343 #endif 344 345 char regd_name[0]; 346 }; 347 #endif /* CONFIG_TXPWR_LIMIT */ 348 349 typedef struct hal_com_data { 350 HAL_VERSION version_id; 351 RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ 352 RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ 353 RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ 354 u8 hw_init_completed; 355 /****** FW related ******/ 356 u32 firmware_size; 357 u16 firmware_version; 358 u16 FirmwareVersionRev; 359 u16 firmware_sub_version; 360 u16 FirmwareSignature; 361 u8 RegFWOffload; 362 u8 bFWReady; 363 u8 bBTFWReady; 364 u8 fw_ractrl; 365 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 366 #ifdef CONFIG_LPS_1T1R 367 u8 lps_1t1r; 368 #endif 369 370 /****** current WIFI_PHY values ******/ 371 WIRELESS_MODE CurrentWirelessMode; 372 enum channel_width current_channel_bw; 373 BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ 374 u8 current_channel; 375 u8 cch_20; 376 u8 cch_40; 377 u8 cch_80; 378 u8 CurrentCenterFrequencyIndex1; 379 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 380 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 381 BOOLEAN bSwChnlAndSetBWInProgress; 382 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 383 u16 BasicRateSet; 384 u32 ReceiveConfig; 385 #ifdef CONFIG_WIFI_MONITOR 386 struct mon_reg_backup mon_backup; /* used for switching back from monitor mode */ 387 #endif /* CONFIG_WIFI_MONITOR */ 388 u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ 389 BOOLEAN bSwChnl; 390 BOOLEAN bSetChnlBW; 391 BOOLEAN bSWToBW40M; 392 BOOLEAN bSWToBW80M; 393 BOOLEAN bChnlBWInitialized; 394 395 #ifdef CONFIG_RTW_ACS 396 struct auto_chan_sel acs; 397 #endif 398 #ifdef CONFIG_BCN_RECOVERY 399 u8 issue_bcn_fail; 400 #endif /*CONFIG_BCN_RECOVERY*/ 401 402 /****** rf_ctrl *****/ 403 u8 rf_chip; 404 405 u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */ 406 u8 rf_type; /*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/ 407 u8 NumTotalRFPath; /*GET_HAL_RFPATH_NUM*/ 408 u8 max_tx_cnt; 409 u8 tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS*/ 410 u8 rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS*/ 411 412 u8 PackageType; 413 u8 antenna_test; 414 415 /* runtime TRX path setting */ 416 enum bb_path txpath; /* TX path bmp */ 417 enum bb_path rxpath; /* RX path bmp */ 418 enum bb_path txpath_nss[4]; /* path bmp for NSS TX, [0] for 1SS, [3] for 4SS */ 419 u8 txpath_num_nss[4]; /* path num for NSS TX, [0] for 1SS, [3] for 4SS */ 420 421 /****** Debug ******/ 422 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 423 u8 bDumpRxPkt; 424 u8 bDumpTxPkt; 425 u8 dis_turboedca; /* 1: disable turboedca, 426 2: disable turboedca and setting EDCA parameter based on the input parameter*/ 427 u32 edca_param_mode; 428 429 /****** EEPROM setting.******/ 430 u8 bautoload_fail_flag; 431 u8 efuse_file_status; 432 u8 macaddr_file_status; 433 u8 EepromOrEfuse; 434 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 435 u8 InterfaceSel; /* board type kept in eFuse */ 436 u16 CustomerID; 437 438 u16 EEPROMVID; 439 u16 EEPROMSVID; 440 #ifdef CONFIG_USB_HCI 441 u8 EEPROMUsbSwitch; 442 u16 EEPROMPID; 443 u16 EEPROMSDID; 444 #endif 445 #ifdef CONFIG_PCI_HCI 446 u16 EEPROMDID; 447 u16 EEPROMSMID; 448 #endif 449 450 u8 EEPROMCustomerID; 451 u8 EEPROMSubCustomerID; 452 u8 EEPROMVersion; 453 u8 EEPROMRegulatory; 454 u8 eeprom_thermal_meter; 455 u8 EEPROMBluetoothCoexist; 456 u8 EEPROMBluetoothType; 457 u8 EEPROMBluetoothAntNum; 458 u8 EEPROMBluetoothAntIsolation; 459 u8 EEPROMBluetoothRadioShared; 460 u8 EEPROMMACAddr[ETH_ALEN]; 461 462 u8 eeprom_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp. 0x00:not specified */ 463 u8 eeprom_max_tx_cnt; /* 0: not specified */ 464 465 u8 tx_bbswing_24G; 466 u8 tx_bbswing_5G; 467 u8 efuse0x3d7; /* efuse[0x3D7] */ 468 u8 efuse0x3d8; /* efuse[0x3D8] */ 469 470 #ifdef CONFIG_RF_POWER_TRIM 471 u8 EEPROMRFGainOffset; 472 u8 EEPROMRFGainVal; 473 struct kfree_data_t kfree_data; 474 #endif /*CONFIG_RF_POWER_TRIM*/ 475 476 #ifdef CONFIG_RTL8814A 477 u32 BackUp_BB_REG_4_2nd_CCA[3]; 478 #endif 479 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ 480 defined(CONFIG_RTL8723D) || \ 481 defined(CONFIG_RTL8192F) 482 483 u8 adjuseVoltageVal; 484 u8 need_restore; 485 #endif 486 u8 EfuseUsedPercentage; 487 u16 EfuseUsedBytes; 488 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 489 EFUSE_HAL EfuseHal; 490 491 u8 txpwr_pg_mode; /* enum txpwr_pg_mode */ 492 493 /*---------------------------------------------------------------------------------*/ 494 #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX 495 /* 2.4G TX power info for target TX power*/ 496 u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 497 u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 498 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 499 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 500 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 501 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 502 503 /* 5G TX power info for target TX power*/ 504 #if CONFIG_IEEE80211_BAND_5GHZ 505 u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; 506 u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; 507 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 508 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 509 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 510 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 511 #endif 512 #endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */ 513 514 u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] 515 [TX_PWR_BY_RATE_NUM_RF]; 516 517 s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND] 518 [TX_PWR_BY_RATE_NUM_RF] 519 [TX_PWR_BY_RATE_NUM_RATE]; 520 521 /* Store the target power for each rate section and rf path */ 522 u8 target_txpwr_2g[TX_PWR_BY_RATE_NUM_RF] 523 [NUM_OF_TARGET_TXPWR_2G]; 524 u8 target_txpwr_5g[TX_PWR_BY_RATE_NUM_RF] 525 [NUM_OF_TARGET_TXPWR_5G]; 526 527 bool set_entire_txpwr; 528 529 #if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) 530 u32 txagc_set_buf; 531 #endif 532 533 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX 534 u8 txpwr_idx_offload_buf[3]; /* for CCK, OFDM, HT1SS */ 535 struct submit_ctx txpwr_idx_offload_sctx; 536 #endif 537 538 u8 txpwr_by_rate_loaded:1; 539 u8 txpwr_by_rate_from_file:1; 540 u8 txpwr_limit_loaded:1; 541 u8 txpwr_limit_from_file:1; 542 543 /* Read/write are allow for following hardware information variables */ 544 u8 crystal_cap; 545 546 u8 PAType_2G; 547 u8 PAType_5G; 548 u8 LNAType_2G; 549 u8 LNAType_5G; 550 u8 ExternalPA_2G; 551 u8 ExternalLNA_2G; 552 u8 external_pa_5g; 553 u8 external_lna_5g; 554 u16 TypeGLNA; 555 u16 TypeGPA; 556 u16 TypeALNA; 557 u16 TypeAPA; 558 u16 rfe_type; 559 560 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 561 u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */ 562 u8 is_turbo_edca; 563 u8 prv_traffic_idx; 564 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ 565 566 u32 RfRegChnlVal[MAX_RF_PATH]; 567 568 /* RDG enable */ 569 BOOLEAN bRDGEnable; 570 571 #if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) 572 u32 RegRRSR; 573 #endif 574 575 /****** antenna diversity ******/ 576 u8 AntDivCfg; 577 u8 with_extenal_ant_switch; 578 u8 b_fix_tx_ant; 579 u8 AntDetection; 580 u8 TRxAntDivType; 581 u8 ant_path; /* for 8723B s0/s1 selection */ 582 u32 antenna_tx_path; /* Antenna path Tx */ 583 u32 AntennaRxPath; /* Antenna path Rx */ 584 u8 sw_antdiv_bl_state; 585 586 /******** PHY DM & DM Section **********/ 587 _lock IQKSpinLock; 588 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 589 590 struct dm_struct odmpriv; 591 u64 bk_rf_ability; 592 u8 bIQKInitialized; 593 u8 bNeedIQK; 594 u8 neediqk_24g; 595 u8 IQK_MP_Switch; 596 u8 bScanInProcess; 597 u8 phydm_init_result; /*BB and RF para match or not*/ 598 /******** PHY DM & DM Section **********/ 599 600 601 602 /* 2010/08/09 MH Add CU power down mode. */ 603 BOOLEAN pwrdown; 604 605 #ifdef CONFIG_P2P 606 #ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 607 u16 p2p_ps_offload; 608 #else 609 u8 p2p_ps_offload; 610 #endif 611 #endif 612 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 613 u8 bMacPwrCtrlOn; 614 u8 hci_sus_state; 615 616 u8 RegIQKFWOffload; 617 struct submit_ctx iqk_sctx; 618 u8 ch_switch_offload; 619 struct submit_ctx chsw_sctx; 620 621 RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 622 623 u8 OutEpQueueSel; 624 u8 OutEpNumber; 625 626 #ifdef RTW_RX_AGGREGATION 627 RX_AGG_MODE rxagg_mode; 628 629 /* For RX Aggregation DMA Mode */ 630 u8 rxagg_dma_size; 631 u8 rxagg_dma_timeout; 632 #endif /* RTW_RX_AGGREGATION */ 633 634 bool intf_start; 635 636 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 637 /* */ 638 /* For SDIO Interface HAL related */ 639 /* */ 640 641 /* */ 642 /* SDIO ISR Related */ 643 /* 644 * u32 IntrMask[1]; 645 * u32 IntrMaskToSet[1]; 646 * LOG_INTERRUPT InterruptLog; */ 647 u32 sdio_himr; 648 u32 sdio_hisr; 649 #ifndef RTW_HALMAC 650 /* */ 651 /* SDIO Tx FIFO related. */ 652 /* */ 653 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 654 #ifdef CONFIG_RTL8192F 655 u16 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 656 #else 657 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 658 #endif/*CONFIG_RTL8192F*/ 659 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT 660 u8 sdio_avail_int_en_q; 661 #endif 662 _lock SdioTxFIFOFreePageLock; 663 u8 SdioTxOQTMaxFreeSpace; 664 u8 SdioTxOQTFreeSpace; 665 #else /* RTW_HALMAC */ 666 u16 SdioTxOQTFreeSpace; 667 #endif /* RTW_HALMAC */ 668 669 /* */ 670 /* SDIO Rx FIFO related. */ 671 /* */ 672 u8 SdioRxFIFOCnt; 673 #if defined (CONFIG_RTL8822C) || defined (CONFIG_RTL8192F) 674 u32 SdioRxFIFOSize; 675 #else 676 u16 SdioRxFIFOSize; 677 #endif 678 679 #ifndef RTW_HALMAC 680 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 681 #else 682 #ifdef CONFIG_RTL8821C 683 u16 tx_high_page; 684 u16 tx_low_page; 685 u16 tx_normal_page; 686 u16 tx_extra_page; 687 u16 tx_pub_page; 688 u8 max_oqt_size; 689 #ifdef XMIT_BUF_SIZE 690 u32 max_xmit_size_vovi; 691 u32 max_xmit_size_bebk; 692 #endif /*XMIT_BUF_SIZE*/ 693 u16 max_xmit_page; 694 u16 max_xmit_page_vo; 695 u16 max_xmit_page_vi; 696 u16 max_xmit_page_be; 697 u16 max_xmit_page_bk; 698 699 #endif /*#ifdef CONFIG_RTL8821C*/ 700 #endif /* !RTW_HALMAC */ 701 #endif /* CONFIG_SDIO_HCI */ 702 703 #ifdef CONFIG_USB_HCI 704 705 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ 706 BOOLEAN UsbRxHighSpeedMode; 707 BOOLEAN UsbTxVeryHighSpeedMode; 708 u32 UsbBulkOutSize; 709 BOOLEAN bSupportUSB3; 710 u8 usb_intf_start; 711 712 /* Interrupt relatd register information. */ 713 u32 IntArray[3];/* HISR0,HISR1,HSISR */ 714 u32 IntrMask[3]; 715 #ifdef CONFIG_USB_TX_AGGREGATION 716 u8 UsbTxAggMode; 717 u8 UsbTxAggDescNum; 718 #endif /* CONFIG_USB_TX_AGGREGATION */ 719 720 #ifdef CONFIG_USB_RX_AGGREGATION 721 u16 HwRxPageSize; /* Hardware setting */ 722 723 /* For RX Aggregation USB Mode */ 724 u8 rxagg_usb_size; 725 u8 rxagg_usb_timeout; 726 #endif/* CONFIG_USB_RX_AGGREGATION */ 727 #endif /* CONFIG_USB_HCI */ 728 729 730 #ifdef CONFIG_PCI_HCI 731 /* */ 732 /* EEPROM setting. */ 733 /* */ 734 u32 TransmitConfig; 735 u32 IntrMaskToSet[2]; 736 u32 IntArray[4]; 737 u32 IntrMask[4]; 738 u32 SysIntArray[1]; 739 u32 SysIntrMask[1]; 740 u32 IntrMaskReg[2]; 741 u32 IntrMaskDefault[4]; 742 743 u32 pci_backdoor_ctrl; 744 745 u8 bDefaultAntenna; 746 747 u8 bInterruptMigration; 748 u8 bDisableTxInt; 749 750 u16 RxTag; 751 #endif /* CONFIG_PCI_HCI */ 752 753 754 #ifdef DBG_CONFIG_ERROR_DETECT 755 struct sreset_priv srestpriv; 756 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */ 757 758 #ifdef CONFIG_BT_COEXIST 759 /* For bluetooth co-existance */ 760 BT_COEXIST bt_coexist; 761 #endif /* CONFIG_BT_COEXIST */ 762 763 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \ 764 || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F) 765 #ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */ 766 /* Interrupt relatd register information. */ 767 u32 SysIntrStatus; 768 u32 SysIntrMask; 769 #endif 770 #endif /*endif CONFIG_RTL8723B */ 771 772 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 773 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 774 char *mac_reg; 775 u32 mac_reg_len; 776 char *bb_phy_reg; 777 u32 bb_phy_reg_len; 778 char *bb_agc_tab; 779 u32 bb_agc_tab_len; 780 char *bb_phy_reg_pg; 781 u32 bb_phy_reg_pg_len; 782 char *bb_phy_reg_mp; 783 u32 bb_phy_reg_mp_len; 784 char *rf_radio_a; 785 u32 rf_radio_a_len; 786 char *rf_radio_b; 787 u32 rf_radio_b_len; 788 char *rf_tx_pwr_track; 789 u32 rf_tx_pwr_track_len; 790 char *rf_tx_pwr_lmt; 791 u32 rf_tx_pwr_lmt_len; 792 #endif 793 794 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 795 struct noise_monitor nm; 796 #endif 797 798 struct hal_spec_t hal_spec; 799 #ifdef CONFIG_PHY_CAPABILITY_QUERY 800 struct phy_spec_t phy_spec; 801 #endif 802 u8 RfKFreeEnable; 803 u8 RfKFree_ch_group; 804 BOOLEAN bCCKinCH14; 805 BB_INIT_REGISTER RegForRecover[5]; 806 807 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) 808 BOOLEAN bCorrectBCN; 809 #endif 810 #ifdef CONFIG_RTL8814A 811 u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ 812 u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ 813 #endif 814 struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; 815 816 #ifdef RTW_HALMAC 817 u16 drv_rsvd_page_number; 818 #endif 819 820 #ifdef CONFIG_BEAMFORMING 821 u8 backup_snd_ptcl_ctrl; 822 #ifdef RTW_BEAMFORMING_VERSION_2 823 struct beamforming_info beamforming_info; 824 #endif /* RTW_BEAMFORMING_VERSION_2 */ 825 #endif /* CONFIG_BEAMFORMING */ 826 827 u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ 828 u8 phydm_op_mode; 829 830 u8 in_cta_test; 831 832 #ifdef CONFIG_RTW_LED 833 struct led_priv led; 834 #endif 835 /* for multi channel case (ex: MCC/TDLS) */ 836 u8 multi_ch_switch_mode; 837 838 #ifdef CONFIG_RTL8814B 839 u8 dma_ch_map[32]; /* TXDESC qsel maximum size */ 840 #endif 841 842 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 843 844 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 845 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData)) 846 #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) 847 #define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led)) 848 849 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 850 851 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 852 853 #define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \ 854 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \ 855 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 856 857 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 858 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 859 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 860 #define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp) 861 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 862 863 /* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/ 864 #define GET_HAL_RFPATH(adapter) (GET_HAL_DATA(adapter)->rf_type) 865 #define GET_HAL_RFPATH_NUM(adapter) (GET_HAL_DATA(adapter)->NumTotalRFPath) 866 #define GET_HAL_TX_PATH_BMP(adapter) ((GET_HAL_DATA(adapter)->trx_path_bmp & 0xF0) >> 4) 867 #define GET_HAL_RX_PATH_BMP(adapter) (GET_HAL_DATA(adapter)->trx_path_bmp & 0x0F) 868 869 /* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/ 870 #define GET_HAL_TX_NSS(adapter) (GET_HAL_DATA(adapter)->tx_nss) 871 #define GET_HAL_RX_NSS(adapter) (GET_HAL_DATA(adapter)->rx_nss) 872 873 #endif 874 875 #ifdef RTW_HALMAC 876 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 877 #endif /* RTW_HALMAC */ 878 879 #endif /* __HAL_DATA_H__ */ 880