1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __HAL_COM_PHYCFG_H__ 16*4882a593Smuzhiyun #define __HAL_COM_PHYCFG_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef DBG_TX_POWER_IDX 19*4882a593Smuzhiyun #define DBG_TX_POWER_IDX 0 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define PathA 0x0 /* Useless */ 23*4882a593Smuzhiyun #define PathB 0x1 24*4882a593Smuzhiyun #define PathC 0x2 25*4882a593Smuzhiyun #define PathD 0x3 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun typedef enum _RF_TX_NUM { 28*4882a593Smuzhiyun RF_1TX = 0, 29*4882a593Smuzhiyun RF_2TX, 30*4882a593Smuzhiyun RF_3TX, 31*4882a593Smuzhiyun RF_4TX, 32*4882a593Smuzhiyun RF_MAX_TX_NUM, 33*4882a593Smuzhiyun RF_TX_NUM_NONIMPLEMENT, 34*4882a593Smuzhiyun } RF_TX_NUM; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun enum txpwr_pg_mode { 37*4882a593Smuzhiyun TXPWR_PG_WITH_PWR_IDX, 38*4882a593Smuzhiyun TXPWR_PG_WITH_TSSI_OFFSET, 39*4882a593Smuzhiyun TXPWR_PG_UNKNOWN, /* keep last */ 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /*------------------------------Define structure----------------------------*/ 43*4882a593Smuzhiyun typedef struct _BB_REGISTER_DEFINITION { 44*4882a593Smuzhiyun u32 rfintfs; /* set software control: */ 45*4882a593Smuzhiyun /* 0x870~0x877[8 bytes] */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun u32 rfintfo; /* output data: */ 48*4882a593Smuzhiyun /* 0x860~0x86f [16 bytes] */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun u32 rfintfe; /* output enable: */ 51*4882a593Smuzhiyun /* 0x860~0x86f [16 bytes] */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun u32 rf3wireOffset; /* LSSI data: */ 54*4882a593Smuzhiyun /* 0x840~0x84f [16 bytes] */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun u32 rfHSSIPara2; /* wire parameter control2 : */ 57*4882a593Smuzhiyun /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ 60*4882a593Smuzhiyun /* 0x8a0~0x8af [16 bytes] */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun extern const char *const _txpwr_pg_mode_str[]; 70*4882a593Smuzhiyun #define txpwr_pg_mode_str(_mode) (((_mode) >= TXPWR_PG_UNKNOWN) ? _txpwr_pg_mode_str[TXPWR_PG_UNKNOWN] : _txpwr_pg_mode_str[(_mode)]) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun u8 phy_get_target_txpwr( 73*4882a593Smuzhiyun PADAPTER Adapter, 74*4882a593Smuzhiyun u8 Band, 75*4882a593Smuzhiyun u8 RfPath, 76*4882a593Smuzhiyun RATE_SECTION RateSection 77*4882a593Smuzhiyun ); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun void 80*4882a593Smuzhiyun PHY_GetRateValuesOfTxPowerByRate( 81*4882a593Smuzhiyun PADAPTER pAdapter, 82*4882a593Smuzhiyun u32 RegAddr, 83*4882a593Smuzhiyun u32 BitMask, 84*4882a593Smuzhiyun u32 Value, 85*4882a593Smuzhiyun u8 *Rate, 86*4882a593Smuzhiyun s8 *PwrByRateVal, 87*4882a593Smuzhiyun u8 *RateNum 88*4882a593Smuzhiyun ); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun u8 91*4882a593Smuzhiyun PHY_GetRateIndexOfTxPowerByRate( 92*4882a593Smuzhiyun u8 Rate 93*4882a593Smuzhiyun ); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun void 96*4882a593Smuzhiyun phy_set_tx_power_index_by_rate_section( 97*4882a593Smuzhiyun PADAPTER pAdapter, 98*4882a593Smuzhiyun enum rf_path RFPath, 99*4882a593Smuzhiyun u8 Channel, 100*4882a593Smuzhiyun u8 RateSection 101*4882a593Smuzhiyun ); 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun s8 104*4882a593Smuzhiyun _PHY_GetTxPowerByRate( 105*4882a593Smuzhiyun PADAPTER pAdapter, 106*4882a593Smuzhiyun u8 Band, 107*4882a593Smuzhiyun enum rf_path RFPath, 108*4882a593Smuzhiyun u8 RateIndex 109*4882a593Smuzhiyun ); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun s8 112*4882a593Smuzhiyun PHY_GetTxPowerByRate( 113*4882a593Smuzhiyun PADAPTER pAdapter, 114*4882a593Smuzhiyun u8 Band, 115*4882a593Smuzhiyun enum rf_path RFPath, 116*4882a593Smuzhiyun RATE_SECTION rs, 117*4882a593Smuzhiyun enum MGN_RATE rate 118*4882a593Smuzhiyun ); 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun void 121*4882a593Smuzhiyun PHY_SetTxPowerByRate( 122*4882a593Smuzhiyun PADAPTER pAdapter, 123*4882a593Smuzhiyun u8 Band, 124*4882a593Smuzhiyun enum rf_path RFPath, 125*4882a593Smuzhiyun u8 Rate, 126*4882a593Smuzhiyun s8 Value 127*4882a593Smuzhiyun ); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun void 130*4882a593Smuzhiyun phy_set_tx_power_level_by_path( 131*4882a593Smuzhiyun PADAPTER Adapter, 132*4882a593Smuzhiyun u8 channel, 133*4882a593Smuzhiyun u8 path 134*4882a593Smuzhiyun ); 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun void 137*4882a593Smuzhiyun PHY_InitTxPowerByRate( 138*4882a593Smuzhiyun PADAPTER pAdapter 139*4882a593Smuzhiyun ); 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun void 142*4882a593Smuzhiyun phy_store_tx_power_by_rate( 143*4882a593Smuzhiyun PADAPTER pAdapter, 144*4882a593Smuzhiyun u32 Band, 145*4882a593Smuzhiyun u32 RfPath, 146*4882a593Smuzhiyun u32 TxNum, 147*4882a593Smuzhiyun u32 RegAddr, 148*4882a593Smuzhiyun u32 BitMask, 149*4882a593Smuzhiyun u32 Data 150*4882a593Smuzhiyun ); 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun void 153*4882a593Smuzhiyun PHY_TxPowerByRateConfiguration( 154*4882a593Smuzhiyun PADAPTER pAdapter 155*4882a593Smuzhiyun ); 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun bool phy_chk_ch_setting_consistency(_adapter *adapter, u8 ch); 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX 160*4882a593Smuzhiyun u8 phy_get_pg_txpwr_idx(_adapter *pAdapter 161*4882a593Smuzhiyun , enum rf_path RFPath, RATE_SECTION rs, u8 ntx_idx 162*4882a593Smuzhiyun , enum channel_width BandWidth, u8 band, u8 Channel); 163*4882a593Smuzhiyun #endif 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #if CONFIG_TXPWR_LIMIT 166*4882a593Smuzhiyun s8 phy_get_txpwr_lmt(_adapter *adapter 167*4882a593Smuzhiyun , const char *regd_name 168*4882a593Smuzhiyun , BAND_TYPE band, enum channel_width bw 169*4882a593Smuzhiyun , u8 tlrs, u8 ntx_idx, u8 cch, u8 lock 170*4882a593Smuzhiyun ); 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun s8 phy_get_txpwr_lmt_diff(_adapter *adapter 173*4882a593Smuzhiyun , const char *regd_name 174*4882a593Smuzhiyun , BAND_TYPE band, enum channel_width bw 175*4882a593Smuzhiyun , u8 rfpath, u8 rs, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock 176*4882a593Smuzhiyun ); 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun s8 phy_get_txpwr_lmt_sub_chs(_adapter *adapter 179*4882a593Smuzhiyun , const char *regd_name 180*4882a593Smuzhiyun , BAND_TYPE band, enum channel_width bw 181*4882a593Smuzhiyun , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, u8 opch 182*4882a593Smuzhiyun ); 183*4882a593Smuzhiyun #else 184*4882a593Smuzhiyun #define phy_get_txpwr_lmt(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max) 185*4882a593Smuzhiyun #define phy_get_txpwr_lmt_diff(adapter, regd_name, band, bw, rfpath, rs, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max) 186*4882a593Smuzhiyun #define phy_get_txpwr_lmt_sub_chs(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch, opch) (GET_HAL_SPEC(adapter)->txgi_max) 187*4882a593Smuzhiyun #endif /* CONFIG_TXPWR_LIMIT */ 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun void dump_txpwr_tpc_settings(void *sel, _adapter *adapter); 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun s8 phy_get_txpwr_target(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx 192*4882a593Smuzhiyun , enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic); 193*4882a593Smuzhiyun s8 phy_get_txpwr_amends(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx 194*4882a593Smuzhiyun , enum channel_width bw, BAND_TYPE band, u8 cch, struct txpwr_idx_comp *tic); 195*4882a593Smuzhiyun #ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 196*4882a593Smuzhiyun s8 phy_get_tssi_txpwr_by_rate_ref(_adapter *adapter, enum rf_path path 197*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch); 198*4882a593Smuzhiyun #endif 199*4882a593Smuzhiyun u8 hal_com_get_txpwr_idx(_adapter *adapter, enum rf_path rfpath 200*4882a593Smuzhiyun , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch 201*4882a593Smuzhiyun , struct txpwr_idx_comp *tic); 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun s16 phy_get_txpwr_single_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate 204*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic); 205*4882a593Smuzhiyun s16 phy_get_txpwr_total_mbm(_adapter *adapter, RATE_SECTION rs, u8 rate 206*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic); 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun s16 phy_get_txpwr_single_max_mbm(_adapter *adapter, u8 rfpath 209*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht); 210*4882a593Smuzhiyun s16 phy_get_txpwr_total_max_mbm(_adapter *adapter 211*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht); 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun s8 214*4882a593Smuzhiyun phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate, 215*4882a593Smuzhiyun enum channel_width bw, u8 channel); 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun s8 218*4882a593Smuzhiyun PHY_GetTxPowerTrackingOffset( 219*4882a593Smuzhiyun PADAPTER pAdapter, 220*4882a593Smuzhiyun enum rf_path RFPath, 221*4882a593Smuzhiyun u8 Rate 222*4882a593Smuzhiyun ); 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun struct txpwr_idx_comp { 225*4882a593Smuzhiyun u8 ntx_idx; 226*4882a593Smuzhiyun s8 target; 227*4882a593Smuzhiyun s8 base; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun /* for target */ 230*4882a593Smuzhiyun s8 by_rate; 231*4882a593Smuzhiyun s8 btc; 232*4882a593Smuzhiyun s8 extra; 233*4882a593Smuzhiyun s8 utarget; 234*4882a593Smuzhiyun s8 limit; 235*4882a593Smuzhiyun s8 ulimit; 236*4882a593Smuzhiyun s8 tpc; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /* for amends */ 239*4882a593Smuzhiyun s8 tpt; 240*4882a593Smuzhiyun s8 dpd; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun u8 phy_get_tx_power_index_ex(_adapter *adapter 244*4882a593Smuzhiyun , enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate 245*4882a593Smuzhiyun , enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch); 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun u8 248*4882a593Smuzhiyun phy_get_tx_power_index( 249*4882a593Smuzhiyun PADAPTER pAdapter, 250*4882a593Smuzhiyun enum rf_path RFPath, 251*4882a593Smuzhiyun u8 Rate, 252*4882a593Smuzhiyun enum channel_width BandWidth, 253*4882a593Smuzhiyun u8 Channel 254*4882a593Smuzhiyun ); 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun void 257*4882a593Smuzhiyun PHY_SetTxPowerIndex( 258*4882a593Smuzhiyun PADAPTER pAdapter, 259*4882a593Smuzhiyun u32 PowerIndex, 260*4882a593Smuzhiyun enum rf_path RFPath, 261*4882a593Smuzhiyun u8 Rate 262*4882a593Smuzhiyun ); 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun bool phy_is_txpwr_user_mbm_valid(_adapter *adapter, s16 mbm); 265*4882a593Smuzhiyun bool phy_is_txpwr_user_target_specified(_adapter *adapter); 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun void dump_tx_power_index_inline(void *sel, _adapter *adapter, u8 rfpath 268*4882a593Smuzhiyun , enum channel_width bw, u8 cch, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic); 269*4882a593Smuzhiyun #ifdef CONFIG_PROC_DEBUG 270*4882a593Smuzhiyun void dump_tx_power_idx_title(void *sel, _adapter *adapter 271*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch); 272*4882a593Smuzhiyun void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath 273*4882a593Smuzhiyun , RATE_SECTION rs, enum channel_width bw, u8 cch, u8 opch); 274*4882a593Smuzhiyun void dump_tx_power_idx(void *sel, _adapter *adapter 275*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch); 276*4882a593Smuzhiyun void dump_txpwr_total_dbm_title(void *sel, _adapter *adapter 277*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch); 278*4882a593Smuzhiyun void dump_txpwr_total_dbm_by_rs(void *sel, _adapter *adapter, u8 rs 279*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch); 280*4882a593Smuzhiyun void dump_txpwr_total_dbm(void *sel, _adapter *adapter 281*4882a593Smuzhiyun , enum channel_width bw, u8 cch, u8 opch); 282*4882a593Smuzhiyun #endif 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun bool phy_is_tx_power_limit_needed(_adapter *adapter); 285*4882a593Smuzhiyun bool phy_is_tx_power_by_rate_needed(_adapter *adapter); 286*4882a593Smuzhiyun int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file); 287*4882a593Smuzhiyun #if CONFIG_TXPWR_LIMIT 288*4882a593Smuzhiyun int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file); 289*4882a593Smuzhiyun #endif 290*4882a593Smuzhiyun void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file); 291*4882a593Smuzhiyun void phy_reload_tx_power_ext_info(_adapter *adapter); 292*4882a593Smuzhiyun void phy_reload_default_tx_power_ext_info(_adapter *adapter); 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter); 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun #ifdef CONFIG_EFUSE_CONFIG_FILE 297*4882a593Smuzhiyun int check_phy_efuse_tx_power_info_valid(_adapter *adapter); 298*4882a593Smuzhiyun #endif 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX 301*4882a593Smuzhiyun void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); 302*4882a593Smuzhiyun void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun void hal_load_txpwr_info(_adapter *adapter); 305*4882a593Smuzhiyun #endif 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun #ifdef CONFIG_PROC_DEBUG 308*4882a593Smuzhiyun void dump_tx_power_ext_info(void *sel, _adapter *adapter); 309*4882a593Smuzhiyun void dump_target_tx_power(void *sel, _adapter *adapter); 310*4882a593Smuzhiyun void dump_tx_power_by_rate(void *sel, _adapter *adapter); 311*4882a593Smuzhiyun #endif 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun int rtw_get_phy_file_path(_adapter *adapter, const char *file_name); 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 316*4882a593Smuzhiyun #define MAC_FILE_FW_NIC "FW_NIC.bin" 317*4882a593Smuzhiyun #define MAC_FILE_FW_WW_IMG "FW_WoWLAN.bin" 318*4882a593Smuzhiyun #define PHY_FILE_MAC_REG "MAC_REG.txt" 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun #define PHY_FILE_AGC_TAB "AGC_TAB.txt" 321*4882a593Smuzhiyun #define PHY_FILE_PHY_REG "PHY_REG.txt" 322*4882a593Smuzhiyun #define PHY_FILE_PHY_REG_MP "PHY_REG_MP.txt" 323*4882a593Smuzhiyun #define PHY_FILE_PHY_REG_PG "PHY_REG_PG.txt" 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #define PHY_FILE_RADIO_A "RadioA.txt" 326*4882a593Smuzhiyun #define PHY_FILE_RADIO_B "RadioB.txt" 327*4882a593Smuzhiyun #define PHY_FILE_RADIO_C "RadioC.txt" 328*4882a593Smuzhiyun #define PHY_FILE_RADIO_D "RadioD.txt" 329*4882a593Smuzhiyun #define PHY_FILE_TXPWR_TRACK "TxPowerTrack.txt" 330*4882a593Smuzhiyun #define PHY_FILE_TXPWR_LMT "TXPWR_LMT.txt" 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun #define PHY_FILE_WIFI_ANT_ISOLATION "wifi_ant_isolation.txt" 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun #define MAX_PARA_FILE_BUF_LEN 32768 /* 32k */ 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #define LOAD_MAC_PARA_FILE BIT0 337*4882a593Smuzhiyun #define LOAD_BB_PARA_FILE BIT1 338*4882a593Smuzhiyun #define LOAD_BB_PG_PARA_FILE BIT2 339*4882a593Smuzhiyun #define LOAD_BB_MP_PARA_FILE BIT3 340*4882a593Smuzhiyun #define LOAD_RF_PARA_FILE BIT4 341*4882a593Smuzhiyun #define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5 342*4882a593Smuzhiyun #define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun int phy_ConfigMACWithParaFile(PADAPTER Adapter, char *pFileName); 345*4882a593Smuzhiyun int phy_ConfigBBWithParaFile(PADAPTER Adapter, char *pFileName, u32 ConfigType); 346*4882a593Smuzhiyun int phy_ConfigBBWithPgParaFile(PADAPTER Adapter, const char *pFileName); 347*4882a593Smuzhiyun int phy_ConfigBBWithMpParaFile(PADAPTER Adapter, char *pFileName); 348*4882a593Smuzhiyun int PHY_ConfigRFWithParaFile(PADAPTER Adapter, char *pFileName, enum rf_path eRFPath); 349*4882a593Smuzhiyun int PHY_ConfigRFWithTxPwrTrackParaFile(PADAPTER Adapter, char *pFileName); 350*4882a593Smuzhiyun #if CONFIG_TXPWR_LIMIT 351*4882a593Smuzhiyun int PHY_ConfigRFWithPowerLimitTableParaFile(PADAPTER Adapter, const char *pFileName); 352*4882a593Smuzhiyun #endif 353*4882a593Smuzhiyun void phy_free_filebuf_mask(_adapter *padapter, u8 mask); 354*4882a593Smuzhiyun void phy_free_filebuf(_adapter *padapter); 355*4882a593Smuzhiyun #endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */ 356*4882a593Smuzhiyun u8 phy_check_under_survey_ch(_adapter *adapter); 357*4882a593Smuzhiyun #endif /* __HAL_COMMON_H__ */ 358