1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #define _USB_HALINIT_C_
17
18 #include <rtl8188f_hal.h>
19 #ifdef CONFIG_WOWLAN
20 #include "hal_com_h2c.h"
21 #endif
22
23
24 static void
_ConfigChipOutEP_8188F(PADAPTER pAdapter,u8 NumOutPipe)25 _ConfigChipOutEP_8188F(
26 PADAPTER pAdapter,
27 u8 NumOutPipe
28 )
29 {
30 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
31
32
33 pHalData->OutEpQueueSel = 0;
34 pHalData->OutEpNumber = 0;
35
36 switch (NumOutPipe) {
37 case 4:
38 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
39 pHalData->OutEpNumber = 4;
40 break;
41 case 3:
42 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
43 pHalData->OutEpNumber = 3;
44 break;
45 case 2:
46 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
47 pHalData->OutEpNumber = 2;
48 break;
49 case 1:
50 pHalData->OutEpQueueSel = TX_SELE_HQ;
51 pHalData->OutEpNumber = 1;
52 break;
53 default:
54 break;
55
56 }
57 RTW_INFO("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, pHalData->OutEpQueueSel, pHalData->OutEpNumber);
58
59 }
60
HalUsbSetQueuePipeMapping8188FUsb(PADAPTER pAdapter,u8 NumInPipe,u8 NumOutPipe)61 static BOOLEAN HalUsbSetQueuePipeMapping8188FUsb(
62 PADAPTER pAdapter,
63 u8 NumInPipe,
64 u8 NumOutPipe
65 )
66 {
67 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
68 BOOLEAN result = _FALSE;
69
70 _ConfigChipOutEP_8188F(pAdapter, NumOutPipe);
71
72 /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
73 if (1 == pHalData->OutEpNumber) {
74 if (1 != NumInPipe)
75 return result;
76 }
77
78 /* All config other than above support one Bulk IN and one Interrupt IN. */
79 /*if(2 != NumInPipe){ */
80 /* return result; */
81 /*} */
82
83 result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
84
85 return result;
86
87 }
88
rtl8188fu_interface_configure(_adapter * padapter)89 void rtl8188fu_interface_configure(_adapter *padapter)
90 {
91 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
92 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
93
94 if (IS_HIGH_SPEED_USB(padapter)) {
95 /* HIGH SPEED */
96 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/*512 bytes */
97 } else {
98 /* FULL SPEED */
99 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/*64 bytes */
100 }
101
102 #ifdef CONFIG_USB_TX_AGGREGATION
103 pHalData->UsbTxAggMode = 1;
104 pHalData->UsbTxAggDescNum = 0x6; /* only 4 bits */
105 #endif
106
107 #ifdef CONFIG_USB_RX_AGGREGATION
108 pHalData->rxagg_mode = RX_AGG_USB;
109 #ifdef CONFIG_PLATFORM_HISILICON
110 pHalData->rxagg_usb_size = 0x3; /* unit: 4KB */
111 pHalData->rxagg_usb_timeout = 0x8; /* unit: 32us */
112 pHalData->rxagg_dma_size = 0xC; /* uint: 1KB */
113 pHalData->rxagg_dma_timeout = 0x8; /* unit: 32us */
114 #else
115 pHalData->rxagg_usb_size = 0x5; /* unit: 4KB */
116 pHalData->rxagg_usb_timeout = 0x20; /* unit: 32us */
117 pHalData->rxagg_dma_size = 0xF; /* uint: 1KB */
118 pHalData->rxagg_dma_timeout = 0x20; /* unit: 32us */
119 #endif
120 #endif
121
122 HalUsbSetQueuePipeMapping8188FUsb(padapter,
123 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
124
125 }
126
_InitPowerOn_8188FU(PADAPTER padapter)127 static u32 _InitPowerOn_8188FU(PADAPTER padapter)
128 {
129 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
130 struct registry_priv *regsty = dvobj_to_regsty(dvobj);
131 u32 status = _SUCCESS;
132 u16 value16 = 0;
133 u8 value8 = 0;
134 u32 value32;
135
136 /* check to apply user defined pll_ref_clk_sel */
137 if ((regsty->pll_ref_clk_sel & 0x0F) != 0x0F)
138 rtl8188f_set_pll_ref_clk_sel(padapter, regsty->pll_ref_clk_sel);
139
140 /* HW Power on sequence */
141 if (!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8188F_card_enable_flow))
142 return _FAIL;
143
144 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
145 /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
146 rtw_write8(padapter, REG_CR_8188F, 0x00); /*suggseted by zhouzhou, by page, 20111230 */
147 value16 = rtw_read16(padapter, REG_CR_8188F);
148 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
149 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
150 rtw_write16(padapter, REG_CR_8188F, value16);
151
152 return status;
153 }
154
155 /*--------------------------------------------------------------- */
156 /* */
157 /* MAC init functions */
158 /* */
159 /*--------------------------------------------------------------- */
160 /*
161 * USB has no hardware interrupt,
162 * so no need to initialize HIMR.
163 */
_InitInterrupt(PADAPTER padapter)164 static void _InitInterrupt(PADAPTER padapter)
165 {
166 #ifdef CONFIG_SUPPORT_USB_INT
167 /* clear interrupt, write 1 clear */
168 rtw_write32(padapter, REG_HISR0_8188F, 0xFFFFFFFF);
169 rtw_write32(padapter, REG_HISR1_8188F, 0xFFFFFFFF);
170 #endif /* CONFIG_SUPPORT_USB_INT */
171 }
172
_InitQueueReservedPage(PADAPTER padapter)173 static void _InitQueueReservedPage(PADAPTER padapter)
174 {
175 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
176 struct registry_priv *pregistrypriv = &padapter->registrypriv;
177 u32 outEPNum = (u32)pHalData->OutEpNumber;
178 u32 numHQ = 0;
179 u32 numLQ = 0;
180 u32 numNQ = 0;
181 u32 numPubQ;
182 u32 value32;
183 u8 value8;
184 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
185
186 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
187 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8188F : NORMAL_PAGE_NUM_HPQ_8188F;
188
189 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
190 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8188F : NORMAL_PAGE_NUM_LPQ_8188F;
191
192 /* NOTE: This step shall be proceed before writing REG_RQPN. */
193 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
194 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8188F : NORMAL_PAGE_NUM_NPQ_8188F;
195 value8 = (u8)_NPQ(numNQ);
196 rtw_write8(padapter, REG_RQPN_NPQ, value8);
197
198 numPubQ = TX_TOTAL_PAGE_NUMBER_8188F - numHQ - numLQ - numNQ;
199
200 /* TX DMA */
201 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
202 rtw_write32(padapter, REG_RQPN, value32);
203
204 }
205
_InitTxBufferBoundary(PADAPTER padapter)206 static void _InitTxBufferBoundary(PADAPTER padapter)
207 {
208 struct registry_priv *pregistrypriv = &padapter->registrypriv;
209 #ifdef CONFIG_CONCURRENT_MODE
210 u8 val8;
211 #endif /* CONFIG_CONCURRENT_MODE */
212
213 /*u16 txdmactrl; */
214 u8 txpktbuf_bndy;
215
216 if (!pregistrypriv->wifi_spec)
217 txpktbuf_bndy = TX_PAGE_BOUNDARY_8188F;
218 else {
219 /*for WMM */
220 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8188F;
221 }
222
223 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8188F, txpktbuf_bndy);
224 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8188F, txpktbuf_bndy);
225 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F, txpktbuf_bndy);
226 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
227 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
228
229 #ifdef CONFIG_CONCURRENT_MODE
230 val8 = txpktbuf_bndy + 8;
231 rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
232 rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 1, val8); /* BCN1_HEAD */
233
234 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2);
235 val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
236 rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8);
237 #endif /* CONFIG_CONCURRENT_MODE */
238 }
239
240
241 void
_InitTransferPageSize_8188fu(PADAPTER Adapter)242 _InitTransferPageSize_8188fu(
243 PADAPTER Adapter
244 )
245 {
246
247 u8 value8;
248 value8 = _PSRX(PBP_256) | _PSTX(PBP_256);
249
250 rtw_write8(Adapter, REG_PBP_8188F, value8);
251 }
252
253
254 static void
_InitNormalChipRegPriority(PADAPTER Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)255 _InitNormalChipRegPriority(
256 PADAPTER Adapter,
257 u16 beQ,
258 u16 bkQ,
259 u16 viQ,
260 u16 voQ,
261 u16 mgtQ,
262 u16 hiQ
263 )
264 {
265 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL_8188F) & 0x7);
266
267 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
268 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
269 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
270
271 rtw_write16(Adapter, REG_TRXDMA_CTRL_8188F, value16);
272 }
273
274
275 static void
_InitNormalChipTwoOutEpPriority(PADAPTER Adapter)276 _InitNormalChipTwoOutEpPriority(
277 PADAPTER Adapter
278 )
279 {
280 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
281 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
282 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
283
284
285 u16 valueHi = 0;
286 u16 valueLow = 0;
287
288 switch (pHalData->OutEpQueueSel) {
289 case (TX_SELE_HQ | TX_SELE_LQ):
290 valueHi = QUEUE_HIGH;
291 valueLow = QUEUE_LOW;
292 break;
293 case (TX_SELE_NQ | TX_SELE_LQ):
294 valueHi = QUEUE_NORMAL;
295 valueLow = QUEUE_LOW;
296 break;
297 case (TX_SELE_HQ | TX_SELE_NQ):
298 valueHi = QUEUE_HIGH;
299 valueLow = QUEUE_NORMAL;
300 break;
301 default:
302 /*RT_ASSERT(FALSE,("Shall not reach here!\n")); */
303 break;
304 }
305
306 if (!pregistrypriv->wifi_spec) {
307 beQ = valueLow;
308 bkQ = valueLow;
309 viQ = valueHi;
310 voQ = valueHi;
311 mgtQ = valueHi;
312 hiQ = valueHi;
313 } else { /*for WMM ,CONFIG_OUT_EP_WIFI_MODE */
314 beQ = valueLow;
315 bkQ = valueHi;
316 viQ = valueHi;
317 voQ = valueLow;
318 mgtQ = valueHi;
319 hiQ = valueHi;
320 }
321
322 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
323
324 }
325
326 static void
_InitNormalChipThreeOutEpPriority(PADAPTER padapter)327 _InitNormalChipThreeOutEpPriority(
328 PADAPTER padapter
329 )
330 {
331 struct registry_priv *pregistrypriv = &padapter->registrypriv;
332 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
333
334 if (!pregistrypriv->wifi_spec) { /* typical setting */
335 beQ = QUEUE_LOW;
336 bkQ = QUEUE_LOW;
337 viQ = QUEUE_NORMAL;
338 voQ = QUEUE_HIGH;
339 mgtQ = QUEUE_HIGH;
340 hiQ = QUEUE_HIGH;
341 } else { /* for WMM */
342 beQ = QUEUE_LOW;
343 bkQ = QUEUE_NORMAL;
344 viQ = QUEUE_NORMAL;
345 voQ = QUEUE_HIGH;
346 mgtQ = QUEUE_HIGH;
347 hiQ = QUEUE_HIGH;
348 }
349 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
350 }
351
_InitQueuePriority(PADAPTER padapter)352 static void _InitQueuePriority(PADAPTER padapter)
353 {
354 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
355 switch (pHalData->OutEpNumber) {
356 case 2:
357 _InitNormalChipTwoOutEpPriority(padapter);
358 break;
359 case 3:
360 case 4:
361 _InitNormalChipThreeOutEpPriority(padapter);
362 break;
363 default:
364 /*RT_ASSERT(FALSE,("Shall not reach here!\n")); */
365 break;
366 }
367
368 }
369
370
_InitPageBoundary(PADAPTER padapter)371 static void _InitPageBoundary(PADAPTER padapter)
372 {
373 /* RX Page Boundary */
374 u16 rxff_bndy = RX_DMA_BOUNDARY_8188F;
375
376 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
377
378 /* TODO: ?? shall we set tx boundary? */
379 }
380
381 static void
_InitHardwareDropIncorrectBulkOut(PADAPTER Adapter)382 _InitHardwareDropIncorrectBulkOut(
383 PADAPTER Adapter
384 )
385 {
386 u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
387 value32 |= DROP_DATA_EN;
388 rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
389 }
390
391 static void
_InitNetworkType(PADAPTER Adapter)392 _InitNetworkType(
393 PADAPTER Adapter
394 )
395 {
396 u32 value32;
397
398 value32 = rtw_read32(Adapter, REG_CR);
399
400 /* TODO: use the other function to set network type */
401 #if 0/*RTL8191C_FPGA_NETWORKTYPE_ADHOC */
402 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
403 #else
404 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
405 #endif
406 rtw_write32(Adapter, REG_CR, value32);
407 /* RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2); */
408 }
409
410
411 static void
_InitDriverInfoSize(PADAPTER Adapter,u8 drvInfoSize)412 _InitDriverInfoSize(
413 PADAPTER Adapter,
414 u8 drvInfoSize
415 )
416 {
417 rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
418 }
419
420 static void
_InitWMACSetting(PADAPTER Adapter)421 _InitWMACSetting(
422 PADAPTER Adapter
423 )
424 {
425 /*u32 value32; */
426 u16 value16;
427 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
428 u32 rcr;
429
430 /* rcr = AAP | APM | AM |AB |ADD3|APWRMGT| APP_ICV | APP_MIC |APP_FCS|ADF |ACF|AMF|HTC_LOC_CTRL|APP_PHYSTS; */
431 /* rcr = AAP | APM | AM | AB | ADD3 | APWRMGT | APP_ICV | APP_MIC | ADF | ACF | AMF | HTC_LOC_CTRL | APP_PHYSTS; */
432 rcr = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYST_RXFF | RCR_APPFCS;
433 rtw_hal_set_hwreg(Adapter, HW_VAR_RCR, (u8 *)&rcr);
434
435 /* Accept all data frames */
436 value16 = 0xFFFF;
437 rtw_write16(Adapter, REG_RXFLTMAP2_8188F, value16);
438
439 /* 2010.09.08 hpfan */
440 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
441 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
442
443 value16 = 0x400;
444 rtw_write16(Adapter, REG_RXFLTMAP1_8188F, value16);
445
446 /* Accept all management frames */
447 value16 = 0xFFFF;
448 rtw_write16(Adapter, REG_RXFLTMAP0_8188F, value16);
449
450 }
451
452 static void
_InitAdaptiveCtrl(PADAPTER Adapter)453 _InitAdaptiveCtrl(
454 PADAPTER Adapter
455 )
456 {
457 u16 value16;
458 u32 value32;
459
460 /* Response Rate Set */
461 value32 = rtw_read32(Adapter, REG_RRSR);
462 value32 &= ~RATE_BITMAP_ALL;
463 value32 |= RATE_RRSR_CCK_ONLY_1M;
464
465 rtw_phydm_set_rrsr(Adapter, value32, TRUE);
466
467
468 /* CF-END Threshold */
469 /*m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
470
471 /* SIFS (used in NAV) */
472 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
473 rtw_write16(Adapter, REG_SPEC_SIFS, value16);
474
475 /* Retry Limit */
476 value16 = BIT_LRL(RL_VAL_STA) | BIT_SRL(RL_VAL_STA);
477 rtw_write16(Adapter, REG_RETRY_LIMIT, value16);
478
479 }
480
481 static void
_InitEDCA(PADAPTER Adapter)482 _InitEDCA(
483 PADAPTER Adapter
484 )
485 {
486 /* Set Spec SIFS (used in NAV) */
487 rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
488 rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
489
490 /* Set SIFS for CCK */
491 rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
492
493 /* Set SIFS for OFDM */
494 rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
495
496 /* TXOP */
497 rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
498 rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
499 rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
500 rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
501 }
502
503 #ifdef CONFIG_RTW_LED
_InitHWLed(PADAPTER Adapter)504 static void _InitHWLed(PADAPTER Adapter)
505 {
506 struct led_priv *pledpriv = adapter_to_led(Adapter);
507
508 if (pledpriv->LedStrategy != HW_LED)
509 return;
510
511 /* HW led control */
512 /* to do .... */
513 /*must consider cases of antenna diversity/ commbo card/solo card/mini card */
514
515 }
516 #endif /*CONFIG_RTW_LED */
517
518 static void
_InitRDGSetting_8188fu(PADAPTER Adapter)519 _InitRDGSetting_8188fu(
520 PADAPTER Adapter
521 )
522 {
523 rtw_write8(Adapter, REG_RD_CTRL_8188F, 0xFF);
524 rtw_write16(Adapter, REG_RD_NAV_NXT_8188F, 0x200);
525 rtw_write8(Adapter, REG_RD_RESP_PKT_TH_8188F, 0x05);
526 }
527
528 static void
_InitRetryFunction(PADAPTER Adapter)529 _InitRetryFunction(
530 PADAPTER Adapter
531 )
532 {
533 u8 value8;
534
535 value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
536 value8 |= EN_AMPDU_RTY_NEW;
537 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
538
539 /* Set ACK timeout */
540 rtw_write8(Adapter, REG_ACKTO, 0x40);
541 }
542
_InitBurstPktLen(PADAPTER padapter)543 static void _InitBurstPktLen(PADAPTER padapter)
544 {
545 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
546 u8 tmp8;
547
548
549 tmp8 = rtw_read8(padapter, REG_RXDMA_PRO_8188F);
550 tmp8 &= ~(BIT(4) | BIT(5));
551 switch (pHalData->UsbBulkOutSize) {
552 case USB_HIGH_SPEED_BULK_SIZE:
553 tmp8 |= BIT(4); /* set burst pkt len=512B */
554 break;
555 case USB_FULL_SPEED_BULK_SIZE:
556 default:
557 tmp8 |= BIT(5); /* set burst pkt len=64B */
558 break;
559 }
560 tmp8 |= BIT(1) | BIT(2) | BIT(3);
561 rtw_write8(padapter, REG_RXDMA_PRO_8188F, tmp8);
562
563 pHalData->bSupportUSB3 = _FALSE;
564
565 tmp8 = rtw_read8(padapter, REG_HT_SINGLE_AMPDU_8188F);
566 tmp8 |= BIT(7); /* enable single pkt ampdu */
567 rtw_write8(padapter, REG_HT_SINGLE_AMPDU_8188F, tmp8);
568 rtw_write16(padapter, REG_MAX_AGGR_NUM_8188F, 0x0C14);
569 rtw_write8(padapter, REG_AMPDU_MAX_TIME_8188F, 0x70);
570 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8188F, 0xffffffff);
571 if (pHalData->AMPDUBurstMode)
572 rtw_write8(padapter, REG_AMPDU_BURST_MODE_8188F, 0x5F);
573
574 /* for VHT packet length 11K */
575 rtw_write8(padapter, REG_RX_PKT_LIMIT_8188F, 0x18);
576
577 rtw_write8(padapter, REG_PIFS_8188F, 0x00);
578 rtw_write8(padapter, REG_FWHW_TXQ_CTRL_8188F, 0x80);
579 rtw_write32(padapter, REG_FAST_EDCA_CTRL_8188F, 0x03086666);
580 rtw_write8(padapter, REG_USTIME_TSF_8188F, 0x28);
581 rtw_write8(padapter, REG_USTIME_EDCA_8188F, 0x28);
582
583 /* to prevent mac is reseted by bus. 20111208, by Page */
584 tmp8 = rtw_read8(padapter, REG_RSV_CTRL_8188F);
585 tmp8 |= BIT(5) | BIT(6);
586 rtw_write8(padapter, REG_RSV_CTRL_8188F, tmp8);
587 }
588
589 /*-----------------------------------------------------------------------------
590 * Function: usb_AggSettingTxUpdate()
591 *
592 * Overview: Separate TX/RX parameters update independent for TP detection and
593 * dynamic TX/RX aggreagtion parameters update.
594 *
595 * Input: PADAPTER
596 *
597 * Output/Return: NONE
598 *
599 * Revised History:
600 * When Who Remark
601 * 12/10/2010 MHC Separate to smaller function.
602 *
603 *---------------------------------------------------------------------------*/
604 static void
usb_AggSettingTxUpdate(PADAPTER Adapter)605 usb_AggSettingTxUpdate(
606 PADAPTER Adapter
607 )
608 {
609 #ifdef CONFIG_USB_TX_AGGREGATION
610 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
611 /*PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
612 u32 value32;
613
614 if (Adapter->registrypriv.wifi_spec)
615 pHalData->UsbTxAggMode = _FALSE;
616
617 if (pHalData->UsbTxAggMode) {
618 value32 = rtw_read32(Adapter, REG_DWBCN0_CTRL_8188F);
619 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
620 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
621
622 rtw_write32(Adapter, REG_DWBCN0_CTRL_8188F, value32);
623 rtw_write8(Adapter, REG_DWBCN1_CTRL_8188F, pHalData->UsbTxAggDescNum << 1);
624 }
625
626 #endif
627 } /* usb_AggSettingTxUpdate */
628
629
630 /*-----------------------------------------------------------------------------
631 * Function: usb_AggSettingRxUpdate()
632 *
633 * Overview: Separate TX/RX parameters update independent for TP detection and
634 * dynamic TX/RX aggreagtion parameters update.
635 *
636 * Input: PADAPTER
637 *
638 * Output/Return: NONE
639 *
640 *---------------------------------------------------------------------------*/
usb_AggSettingRxUpdate(PADAPTER padapter)641 static void usb_AggSettingRxUpdate(PADAPTER padapter)
642 {
643 PHAL_DATA_TYPE pHalData;
644 u8 aggctrl;
645 u32 aggrx;
646 u32 agg_size;
647
648 pHalData = GET_HAL_DATA(padapter);
649
650 aggctrl = rtw_read8(padapter, REG_TRXDMA_CTRL);
651 aggctrl &= ~RXDMA_AGG_EN;
652
653 aggrx = rtw_read32(padapter, REG_RXDMA_AGG_PG_TH);
654 aggrx &= ~BIT_USB_RXDMA_AGG_EN;
655 aggrx &= ~0xFF0F; /* reset agg size and timeout */
656
657 #ifdef CONFIG_USB_RX_AGGREGATION
658 switch (pHalData->rxagg_mode) {
659 case RX_AGG_DMA:
660 agg_size = pHalData->rxagg_dma_size << 10;
661 if (agg_size > RX_DMA_BOUNDARY_8188F)
662 agg_size = RX_DMA_BOUNDARY_8188F >> 1;
663 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
664 agg_size = MAX_RECVBUF_SZ - 2048;
665 agg_size >>= 10; /* unit: 1K */
666 if (agg_size > 0xF)
667 agg_size = 0xF;
668
669 aggctrl |= RXDMA_AGG_EN;
670 aggrx |= BIT_USB_RXDMA_AGG_EN;
671 aggrx |= agg_size;
672 aggrx |= pHalData->rxagg_dma_timeout << 8;
673 RTW_INFO("%s: RX Aggregation DMA mode, size=%dKB, timeout=%dus\n",
674 __func__, pHalData->rxagg_dma_size & 0xF, pHalData->rxagg_dma_timeout * 32);
675 break;
676
677 case RX_AGG_USB:
678 case RX_AGG_MIX:
679 agg_size = pHalData->rxagg_usb_size << 12;
680 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
681 agg_size = MAX_RECVBUF_SZ - 2048;
682 agg_size >>= 12; /* unit: 4K */
683 if (agg_size > 0xF)
684 agg_size = 0xF;
685
686 aggctrl |= RXDMA_AGG_EN;
687 aggrx &= ~BIT_USB_RXDMA_AGG_EN;
688 aggrx |= agg_size;
689 aggrx |= pHalData->rxagg_usb_timeout << 8;
690 RTW_INFO("%s: RX Aggregation USB mode, size=%dKB, timeout=%dus\n",
691 __func__, (pHalData->rxagg_usb_size & 0xF) * 4, pHalData->rxagg_usb_timeout * 32);
692 break;
693
694 case RX_AGG_DISABLE:
695 default:
696 RTW_INFO("%s: RX Aggregation Disable!\n", __func__);
697 break;
698 }
699 #endif /* CONFIG_USB_RX_AGGREGATION */
700
701 rtw_write8(padapter, REG_TRXDMA_CTRL, aggctrl);
702 rtw_write32(padapter, REG_RXDMA_AGG_PG_TH, aggrx);
703 }
704
705 static void
_initUsbAggregationSetting(PADAPTER Adapter)706 _initUsbAggregationSetting(
707 PADAPTER Adapter
708 )
709 {
710 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
711
712 /* Tx aggregation setting */
713 usb_AggSettingTxUpdate(Adapter);
714
715 /* Rx aggregation setting */
716 usb_AggSettingRxUpdate(Adapter);
717
718 /* 201/12/10 MH Add for USB agg mode dynamic switch. */
719 pHalData->UsbRxHighSpeedMode = _FALSE;
720 }
721
722 static void
PHY_InitAntennaSelection8188F(PADAPTER Adapter)723 PHY_InitAntennaSelection8188F(
724 PADAPTER Adapter
725 )
726 {
727 /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
728 /* TODO: A better solution is configure it according EFUSE during the run-time. */
729 phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /*0x66[4]=0 */
730 phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /*0x66[8]=0 */
731 phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /*0x40[4]=0 */
732 phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /*0x40[3]=1 */
733 phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /*0x4C[24:23]=10 */
734 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[24:23]=10 */
735 phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /*0x944[1:0]=11 */
736 phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77); /*0x930[7:0]=77 */
737 phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1); /*0x38[11]=1 */
738 }
739
740 #if 0
741 /* */
742 /* 2010/08/09 MH Add for power down check. */
743 /* */
744 static BOOLEAN
745 HalDetectPwrDownMode(
746 PADAPTER Adapter
747 )
748 {
749 u8 tmpvalue;
750 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
751 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
752
753 EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8188F, (u32 *)&tmpvalue);
754
755 /* 2010/08/25 MH INF priority > PDN Efuse value. */
756 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
757 pHalData->pwrdown = _TRUE;
758 else
759 pHalData->pwrdown = _FALSE;
760
761 RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
762 return pHalData->pwrdown;
763
764 } /* HalDetectPwrDownMode */
765 #endif
766
767 /* */
768 /* 2010/08/26 MH Add for selective suspend mode check. */
769 /* If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and */
770 /* slim card. */
771 /* */
772 #if 0 /*amyma */
773 static void
774 HalDetectSelectiveSuspendMode(
775 PADAPTER Adapter
776 )
777 {
778 u8 tmpvalue;
779 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
780 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
781
782 /* If support HW radio detect, we need to enable WOL ability, otherwise, we */
783 /* can not use FW to notify host the power state switch. */
784
785 EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
786
787 RTW_INFO("HalDetectSelectiveSuspendMode(): SS ");
788 if (tmpvalue & BIT1)
789 RTW_INFO("Enable\n");
790 else {
791 RTW_INFO("Disable\n");
792 pdvobjpriv->RegUsbSS = _FALSE;
793 }
794
795 /* 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode. */
796 if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData)) {
797 /*PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
798
799 /*if (!pMgntInfo->bRegDongleSS) */
800 /*{ */
801 pdvobjpriv->RegUsbSS = _FALSE;
802 /*} */
803 }
804 } /* HalDetectSelectiveSuspendMode */
805 #endif
806
RfOnOffDetect(PADAPTER pAdapter)807 rt_rf_power_state RfOnOffDetect(PADAPTER pAdapter)
808 {
809 /*HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); */
810 u8 val8;
811 rt_rf_power_state rfpowerstate = rf_off;
812
813 if (adapter_to_pwrctl(pAdapter)->bHWPowerdown) {
814 val8 = rtw_read8(pAdapter, REG_HSISR);
815 RTW_INFO("pwrdown, 0x5c(BIT7)=%02x\n", val8);
816 rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
817 } else { /* rf on/off */
818 rtw_write8(pAdapter, REG_MAC_PINMUX_CFG, rtw_read8(pAdapter, REG_MAC_PINMUX_CFG) & ~(BIT3));
819 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
820 RTW_INFO("GPIO_IN=%02x\n", val8);
821 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
822 }
823 return rfpowerstate;
824 }
825 void _ps_open_RF(_adapter *padapter);
826
827 #ifdef CONFIG_8188FTV_SOLUTION_D
828 /*
829 Write corresponding register of efuse. Indirect Write.
830 Offset: reg offset.
831 Value: u8 value
832 */
WriteUSB2PHYReg(PADAPTER Adapter,u8 Offset,u8 Value)833 void WriteUSB2PHYReg(PADAPTER Adapter, u8 Offset, u8 Value)
834 {
835 rtw_write8(Adapter, 0xFE41, Value);
836 rtw_write8(Adapter, 0xFE40, Offset);
837 rtw_write8(Adapter, 0xFE42, 0x81);
838 }
839
840 /*
841 Read corresponding register of efuse. Indirect Read.
842 Offset: reg offset.
843 */
ReadUSB2PHYReg(PADAPTER Adapter,u8 Offset)844 u8 ReadUSB2PHYReg(PADAPTER Adapter, u8 Offset)
845 {
846 u8 value = 0;
847 rtw_write8(Adapter, 0xFE40, Offset);
848 rtw_write8(Adapter, 0xFE42, 0x81);
849 value = rtw_read8(Adapter, 0xFE43);
850
851 return value;
852 }
853
rtl8188fu_solution_d(PADAPTER Adapter)854 void rtl8188fu_solution_d(PADAPTER Adapter)
855 {
856 u8 reg_val[6] = {0};
857 u16 reg0mask = BIT(10) | BIT(11) | BIT(12) | BIT(13);
858 u16 reg1mask = BIT(0) | BIT(1) | BIT(2) | BIT(3);
859
860 reg_val[0] = phy_query_mac_reg(Adapter, 0x10, reg0mask); /* efuse 0x3 */
861 reg_val[1] = phy_query_mac_reg(Adapter, 0xC4, reg1mask); /* efuse 0xd */
862 reg_val[2] = ReadUSB2PHYReg(Adapter, 0xC1); /* efuse 0x131 */
863 reg_val[3] = phy_query_mac_reg(Adapter, 0x4, BIT(11)); /* efuse 0xa */
864 reg_val[4] = ReadUSB2PHYReg(Adapter, 0xD2); /* efuse 0x13a */
865 reg_val[5] = ReadUSB2PHYReg(Adapter, 0xD3); /* efuse 0x13b */
866
867 if(!(reg_val[3] == 0 && reg_val[4] == 0 && reg_val[5] == 0x31)) /* solution "EP" not applied */
868 {
869 if((reg_val[0] == 0xC && reg_val[1] == 0xC && reg_val[2] == 0xAE) /* solution O */
870 ||(reg_val[0] == 0xF && reg_val[1] == 0xC && reg_val[2] == 0xAE) /* solution A */
871 ||(reg_val[0] == 0xC && reg_val[1] == 0xB && reg_val[2] == 0xAE) /* solution B */
872 ||(reg_val[0] == 0xC && reg_val[1] == 0xC && reg_val[2] == 0xBE)) /* solution C */
873 {
874 /* apply solution D */
875 phy_set_mac_reg(Adapter, 0x10, reg0mask, 0xF);
876 phy_set_mac_reg(Adapter, 0xC4, reg1mask, 0x7);
877 WriteUSB2PHYReg(Adapter, 0xE1, 0xB6);
878 RTW_INFO("%s, Aplly Solution D\n", __func__);
879 }
880 else if(reg_val[0] == 0xF && reg_val[1] == 0x7 && reg_val[2] == 0xB6)
881 RTW_INFO("%s, Solution D already apllied\n", __func__);
882 else
883 RTW_INFO("%s, Unexpected efuse content\n", __func__);
884 }
885 else
886 RTW_INFO("%s, Solution EP already applied\n", __func__);
887 }
888 #endif
889
rtl8188fu_hal_init(PADAPTER padapter)890 u32 rtl8188fu_hal_init(PADAPTER padapter)
891 {
892 u8 value8 = 0, u1bRegCR;
893 u32 boundary, status = _SUCCESS;
894 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
895 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
896 struct registry_priv *pregistrypriv = &padapter->registrypriv;
897 rt_rf_power_state eRfPowerStateToSet;
898 u32 NavUpper = WiFiNavUpperUs;
899 u32 value32;
900 systime init_start_time = rtw_get_current_time();
901
902
903 #ifdef DBG_HAL_INIT_PROFILING
904
905 enum HAL_INIT_STAGES {
906 HAL_INIT_STAGES_BEGIN = 0,
907 HAL_INIT_STAGES_INIT_PW_ON,
908 HAL_INIT_STAGES_INIT_LLTT,
909 HAL_INIT_STAGES_MISC01,
910 HAL_INIT_STAGES_DOWNLOAD_FW,
911 HAL_INIT_STAGES_MAC,
912 HAL_INIT_STAGES_BB,
913 HAL_INIT_STAGES_RF,
914 HAL_INIT_STAGES_MISC02,
915 HAL_INIT_STAGES_TURN_ON_BLOCK,
916 HAL_INIT_STAGES_INIT_SECURITY,
917 HAL_INIT_STAGES_MISC11,
918 /*HAL_INIT_STAGES_RF_PS, */
919 HAL_INIT_STAGES_INIT_HAL_DM,
920 /* HAL_INIT_STAGES_IQK, */
921 /* HAL_INIT_STAGES_PW_TRACK, */
922 /* HAL_INIT_STAGES_LCK, */
923 HAL_INIT_STAGES_MISC21,
924 /*HAL_INIT_STAGES_INIT_PABIAS, */
925 HAL_INIT_STAGES_BT_COEXIST,
926 /*HAL_INIT_STAGES_ANTENNA_SEL, */
927 HAL_INIT_STAGES_MISC31,
928 HAL_INIT_STAGES_END,
929 HAL_INIT_STAGES_NUM
930 };
931
932 static char *const hal_init_stages_str[] = {
933 "HAL_INIT_STAGES_BEGIN",
934 "HAL_INIT_STAGES_INIT_PW_ON",
935 "HAL_INIT_STAGES_INIT_LLTT",
936 "HAL_INIT_STAGES_MISC01",
937 "HAL_INIT_STAGES_DOWNLOAD_FW",
938 "HAL_INIT_STAGES_MAC",
939 "HAL_INIT_STAGES_BB",
940 "HAL_INIT_STAGES_RF",
941 "HAL_INIT_STAGES_MISC02",
942 "HAL_INIT_STAGES_TURN_ON_BLOCK",
943 "HAL_INIT_STAGES_INIT_SECURITY",
944 "HAL_INIT_STAGES_MISC11",
945 /*"HAL_INIT_STAGES_RF_PS", */
946 "HAL_INIT_STAGES_INIT_HAL_DM",
947 /* "HAL_INIT_STAGES_IQK", */
948 /* "HAL_INIT_STAGES_PW_TRACK", */
949 /* "HAL_INIT_STAGES_LCK", */
950 "HAL_INIT_STAGES_MISC21",
951 /*"HAL_INIT_STAGES_INIT_PABIAS", */
952 "HAL_INIT_STAGES_BT_COEXIST",
953 /*"HAL_INIT_STAGES_ANTENNA_SEL", */
954 "HAL_INIT_STAGES_MISC31",
955 "HAL_INIT_STAGES_END",
956 };
957
958 int hal_init_profiling_i;
959 systime hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; /*used to record the time of each stage's starting point */
960
961 for (hal_init_profiling_i = 0; hal_init_profiling_i < HAL_INIT_STAGES_NUM; hal_init_profiling_i++)
962 hal_init_stages_timestamp[hal_init_profiling_i] = 0;
963
964 #define HAL_INIT_PROFILE_TAG(stage) { hal_init_stages_timestamp[(stage)] = rtw_get_current_time(); }
965 #else
966 #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
967 #endif /*DBG_HAL_INIT_PROFILING */
968
969
970
971
972 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
973
974 /* if (rtw_is_surprise_removed(Adapter)) */
975 /* return RT_STATUS_FAILURE; */
976
977 #if 0 /* To prevent Pomelo hanging. Added by tianzeyum. 2014.11.02 */
978 #define REG_USB_ACCESS_TIMEOUT 0xFE4C
979 rtw_write8(padapter, REG_USB_ACCESS_TIMEOUT, 0x80);
980 #undef REG_USB_ACCESS_TIMEOUT
981 #endif
982
983
984 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
985 status = rtw_hal_power_on(padapter);
986 if (status == _FAIL) {
987 goto exit;
988 }
989
990 /* Check if MAC has already power on. */
991 value8 = rtw_read8(padapter, REG_SYS_CLKR_8188F + 1);
992 u1bRegCR = rtw_read8(padapter, REG_CR_8188F);
993 RTW_INFO(" power-on :REG_SYS_CLKR 0x09=0x%02x. REG_CR 0x100=0x%02x.\n", value8, u1bRegCR);
994 if ((value8 & BIT3) && (u1bRegCR != 0 && u1bRegCR != 0xEA))
995 RTW_INFO(" MAC has already power on.\n");
996 else {
997 /* Set FwPSState to ALL_ON mode to prevent from the I/O be return because of 32k */
998 /* state which is set before sleep under wowlan mode. 2012.01.04. by tynli. */
999 /*pHalData->FwPSState = FW_PS_STATE_ALL_ON_88E; */
1000 RTW_INFO(" MAC has not been powered on yet.\n");
1001 }
1002
1003 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1004 if (!pregistrypriv->wifi_spec)
1005 boundary = TX_PAGE_BOUNDARY_8188F;
1006 else {
1007 /* for WMM */
1008 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY_8188F;
1009 }
1010 status = rtl8188f_InitLLTTable(padapter);
1011 if (status == _FAIL) {
1012 goto exit;
1013 }
1014
1015 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1016 if (pHalData->bRDGEnable)
1017 _InitRDGSetting_8188fu(padapter);
1018
1019
1020 /*Enable TX Report */
1021 /*Enable Tx Report Timer */
1022 value8 = rtw_read8(padapter, REG_TX_RPT_CTRL);
1023 rtw_write8(padapter, REG_TX_RPT_CTRL, value8 | BIT1);
1024 /*Set MAX RPT MACID */
1025 rtw_write8(padapter, REG_TX_RPT_CTRL + 1, 2);
1026 /*Tx RPT Timer. Unit: 32us */
1027 rtw_write16(padapter, REG_TX_RPT_TIME, 0xCdf0);
1028
1029 #ifdef CONFIG_TX_EARLY_MODE
1030 if (pHalData->AMPDUBurstMode) {
1031
1032 value8 = rtw_read8(padapter, REG_EARLY_MODE_CONTROL_8188F);
1033 #if RTL8188F_EARLY_MODE_PKT_NUM_10 == 1
1034 value8 = value8 | 0x1f;
1035 #else
1036 value8 = value8 | 0xf;
1037 #endif
1038 rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8188F, value8);
1039
1040 rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8188F + 3, 0x80);
1041
1042 value8 = rtw_read8(padapter, REG_TCR_8188F + 1);
1043 value8 = value8 | 0x40;
1044 rtw_write8(padapter, REG_TCR_8188F + 1, value8);
1045 } else
1046 rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8188F, 0);
1047 #endif
1048
1049 /* <Kordan> InitHalDm should be put ahead of FirmwareDownload. (HWConfig flow: FW->MAC->-BB->RF) */
1050 /*InitHalDm(Adapter); */
1051
1052 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1053 if (padapter->registrypriv.mp_mode == 0
1054 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
1055 || padapter->registrypriv.mp_customer_str
1056 #endif
1057 ) {
1058 status = rtl8188f_FirmwareDownload(padapter, _FALSE);
1059 if (status != _SUCCESS) {
1060 pHalData->bFWReady = _FALSE;
1061 pHalData->fw_ractrl = _FALSE;
1062 RTW_INFO("fw download fail!\n");
1063 goto exit;
1064 } else {
1065 pHalData->bFWReady = _TRUE;
1066 pHalData->fw_ractrl = _TRUE;
1067 RTW_INFO("fw download ok!\n");
1068 }
1069 }
1070
1071 if (pwrctrlpriv->reg_rfoff == _TRUE)
1072 pwrctrlpriv->rf_pwrstate = rf_off;
1073
1074 /* Set RF type for BB/RF configuration */
1075 /*_InitRFType(Adapter); */
1076
1077 /* We should call the function before MAC/BB configuration. */
1078 PHY_InitAntennaSelection8188F(padapter);
1079
1080
1081
1082 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1083 #if (HAL_MAC_ENABLE == 1)
1084 status = PHY_MACConfig8188F(padapter);
1085 if (status == _FAIL) {
1086 RTW_INFO("PHY_MACConfig8188F fault !!\n");
1087 goto exit;
1088 }
1089 #endif
1090 RTW_INFO("PHY_MACConfig8188F OK!\n");
1091
1092
1093 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1094 /* */
1095 /*d. Initialize BB related configurations. */
1096 /* */
1097 #if (HAL_BB_ENABLE == 1)
1098 status = PHY_BBConfig8188F(padapter);
1099 if (status == _FAIL) {
1100 RTW_INFO("PHY_BBConfig8188F fault !!\n");
1101 goto exit;
1102 }
1103 #endif
1104
1105 RTW_INFO("PHY_BBConfig8188F OK!\n");
1106
1107
1108
1109 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1110 #if (HAL_RF_ENABLE == 1)
1111 status = PHY_RFConfig8188F(padapter);
1112
1113 if (status == _FAIL) {
1114 RTW_INFO("PHY_RFConfig8188F fault !!\n");
1115 goto exit;
1116 }
1117
1118 RTW_INFO("PHY_RFConfig8188F OK!\n");
1119
1120
1121 #endif
1122
1123
1124
1125 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1126 _InitQueueReservedPage(padapter);
1127 _InitTxBufferBoundary(padapter);
1128 _InitQueuePriority(padapter);
1129 _InitPageBoundary(padapter);
1130 _InitTransferPageSize_8188fu(padapter);
1131
1132
1133 /* Get Rx PHY status in order to report RSSI and others. */
1134 _InitDriverInfoSize(padapter, DRVINFO_SZ);
1135
1136 _InitInterrupt(padapter);
1137 _InitNetworkType(padapter);/*set msr */
1138 _InitWMACSetting(padapter);
1139 _InitAdaptiveCtrl(padapter);
1140 _InitEDCA(padapter);
1141 _InitRetryFunction(padapter);
1142 /* _InitOperationMode(Adapter);//todo */
1143 rtl8188f_InitBeaconParameters(padapter);
1144 rtl8188f_InitBeaconMaxError(padapter, _TRUE);
1145
1146 _InitBurstPktLen(padapter);
1147 _initUsbAggregationSetting(padapter);
1148
1149 #ifdef ENABLE_USB_DROP_INCORRECT_OUT
1150 _InitHardwareDropIncorrectBulkOut(padapter);
1151 #endif
1152
1153 /* Enable MACTXEN/MACRXEN block */
1154 u1bRegCR = rtw_read8(padapter, REG_CR);
1155 u1bRegCR |= (MACTXEN | MACRXEN);
1156 rtw_write8(padapter, REG_CR, u1bRegCR);
1157
1158 #ifdef CONFIG_RTW_LED
1159 _InitHWLed(padapter);
1160 #endif /*CONFIG_RTW_LED */
1161
1162 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1163 BBTurnOnBlock_8188F(padapter);
1164 /*NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
1165
1166
1167 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
1168 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
1169
1170 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1171 invalidate_cam_all(padapter);
1172
1173 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1174 /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
1175 /*rtw_hal_set_tx_power_level(padapter, pHalData->current_channel); */
1176 rtl8188f_InitAntenna_Selection(padapter);
1177
1178 /* HW SEQ CTRL */
1179 /*set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1180 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
1181
1182 /* */
1183 /* Disable BAR, suggested by Scott */
1184 /* 2010.04.09 add by hpfan */
1185 /* */
1186 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1187
1188 if (pregistrypriv->wifi_spec)
1189 rtw_write16(padapter, REG_FAST_EDCA_CTRL , 0);
1190
1191 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1192 rtl8188f_InitHalDm(padapter);
1193
1194 #if (MP_DRIVER == 1)
1195 if (padapter->registrypriv.mp_mode == 1) {
1196 padapter->mppriv.channel = pHalData->current_channel;
1197 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1198 } else
1199 #endif
1200 {
1201 pwrctrlpriv->rf_pwrstate = rf_on;
1202
1203 /*phy_lc_calibrate_8188f(&pHalData->odmpriv);*/
1204 halrf_lck_trigger(&pHalData->odmpriv);
1205
1206 pHalData->neediqk_24g = _TRUE;
1207
1208 odm_txpowertracking_check(&pHalData->odmpriv);
1209 }
1210
1211
1212 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
1213
1214 /*HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
1215
1216 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
1217 #ifdef CONFIG_BT_COEXIST
1218 /* Init BT hw config. */
1219 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1220 #else
1221 /* rtw_btcoex_HAL_Initialize(padapter, _TRUE); // For Test. */
1222 #endif
1223
1224 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1225 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
1226
1227 #ifdef CONFIG_XMIT_ACK
1228 /*ack for xmit mgmt frames. */
1229 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
1230 #endif /*CONFIG_XMIT_ACK */
1231
1232 /* #if RTL8188F_USB_MAC_LOOPBACK */
1233 #if 0
1234 rtw_write8(padapter, REG_CR_8188F + 3, 0x0B);
1235 RTW_INFO("MAC loopback: REG_CR_8188F=%#X.\n", rtw_read32(padapter, REG_CR_8188F));
1236 #endif
1237
1238 #if FPGA_TWO_MAC_VERIFICATION
1239 /* #if 1 */
1240 /* Enable BB */
1241 value8 = rtw_read8(padapter, REG_SYS_FUNC_EN_8188F);
1242 RTW_INFO("RJZ: open 2-MAC mode: REG_SYS_FUNC_EN_8188F = %#x.\n", value8);
1243 rtw_write8(padapter, REG_SYS_FUNC_EN_8188F, value8 | BIT0 | BIT1 | BIT2);
1244 value8 = rtw_read8(padapter, REG_SYS_FUNC_EN_8188F);
1245 RTW_INFO("RJZ: open 2-MAC mode: REG_SYS_FUNC_EN_8188F = %#x.\n", value8);
1246
1247 /* Use 40MHz */
1248 value8 = rtw_read8(padapter, REG_SYS_CLKR_8188F);
1249 rtw_write8(padapter, REG_SYS_CLKR_8188F, value8 & ~BIT4);
1250 value8 = rtw_read8(padapter, REG_SYS_CLKR_8188F);
1251
1252 /* Clear 970~976. */
1253 rtw_write32(padapter, 0x0970, 0);
1254 rtw_write16(padapter, 0x0974, 0);
1255 rtw_write8(padapter, 0x0976, 0);
1256
1257 /* Set the microsecond time unit used by MAC TSF clock. */
1258 rtw_write8(padapter, REG_USTIME_TSF_8188F, 0x28);
1259 #endif
1260
1261
1262 exit:
1263 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1264
1265 RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
1266
1267 #ifdef DBG_HAL_INIT_PROFILING
1268 hal_init_stages_timestamp[HAL_INIT_STAGES_END] = rtw_get_current_time();
1269
1270 for (hal_init_profiling_i = 0; hal_init_profiling_i < HAL_INIT_STAGES_NUM - 1; hal_init_profiling_i++) {
1271 RTW_INFO("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1272 , hal_init_stages_str[hal_init_profiling_i]
1273 , hal_init_stages_timestamp[hal_init_profiling_i]
1274 , (hal_init_stages_timestamp[hal_init_profiling_i + 1] - hal_init_stages_timestamp[hal_init_profiling_i])
1275 , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i + 1])
1276 );
1277 }
1278 #endif
1279
1280
1281 return status;
1282 }
1283
1284 #if 0
1285 static void
1286 _ResetFWDownloadRegister(
1287 PADAPTER Adapter
1288 )
1289 {
1290 u32 value32;
1291
1292 value32 = rtw_read32(Adapter, REG_MCUFWDL);
1293 value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
1294 rtw_write32(Adapter, REG_MCUFWDL, value32);
1295 }
1296
1297 static void
1298 _ResetBB(
1299 PADAPTER Adapter
1300 )
1301 {
1302 u16 value16;
1303
1304 /*reset BB */
1305 value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1306 value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1307 rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1308 }
1309
1310 static void
1311 _ResetMCU(
1312 PADAPTER Adapter
1313 )
1314 {
1315 u16 value16;
1316
1317 /* reset MCU */
1318 value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1319 value16 &= ~FEN_CPUEN;
1320 rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1321 }
1322
1323 static void
1324 _DisableMAC_AFE_PLL(
1325 PADAPTER Adapter
1326 )
1327 {
1328 u32 value32;
1329
1330 /*disable MAC/ AFE PLL */
1331 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1332 value32 |= APDM_MAC;
1333 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1334
1335 value32 |= APFM_OFF;
1336 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1337 }
1338
1339 static void
1340 _AutoPowerDownToHostOff(
1341 PADAPTER Adapter
1342 )
1343 {
1344 u32 value32;
1345 rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
1346
1347 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1348
1349 value32 |= APDM_HOST;/*card disable */
1350 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1351
1352 /* set USB suspend */
1353 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1354 value32 &= ~AFSM_PCIE;
1355 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1356
1357 }
1358
1359 static void
1360 _SetUsbSuspend(
1361 PADAPTER Adapter
1362 )
1363 {
1364 u32 value32;
1365
1366 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1367
1368 /* set USB suspend */
1369 value32 |= AFSM_HSUS;
1370 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1371
1372 /*RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),("")); */
1373
1374 }
1375
1376 static void
1377 _DisableRFAFEAndResetBB(
1378 PADAPTER Adapter
1379 )
1380 {
1381 /*
1382 * a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1383 * b. RF path 0 offset 0x00 = 0x00 disable RF
1384 * c. APSD_CTRL 0x600[7:0] = 0x40
1385 * d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1386 * e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1387 */
1388 enum rf_path eRFPath = RF_PATH_A, value8 = 0;
1389 rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
1390 phy_set_rf_reg(Adapter, eRFPath, 0x0, bMaskByte0, 0x0);
1391
1392 value8 |= APSDOFF;
1393 rtw_write8(Adapter, REG_APSD_CTRL, value8);/*0x40 */
1394
1395 value8 = 0;
1396 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1397 rtw_write8(Adapter, REG_SYS_FUNC_EN, value8);/*0x16 */
1398
1399 value8 &= (~FEN_BB_GLB_RSTn);
1400 rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); /*0x14 */
1401
1402 }
1403
1404 static void
1405 _ResetDigitalProcedure1(
1406 PADAPTER Adapter,
1407 BOOLEAN bWithoutHWSM
1408 )
1409 {
1410
1411 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1412
1413 if (pHalData->firmware_version <= 0x20) {
1414 #if 0
1415 /*
1416 * f. SYS_FUNC_EN 0x03[7:0]=0x54 reset MAC register, DCORE
1417 * g. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1418 */
1419 u32 value32 = 0;
1420 PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN + 1, 0x54);
1421 PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0);
1422 #else
1423 /*
1424 * i. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1425 * g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset)
1426 * h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE
1427 * i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register, (8051 enable)
1428 */
1429 u16 valu16 = 0;
1430
1431 rtw_write8(Adapter, REG_MCUFWDL, 0);
1432
1433 valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1434 rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));/*reset MCU ,8051 */
1435
1436 valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN) & 0x0FFF;
1437 rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | (FEN_HWPDN | FEN_ELDR))); /*reset MAC */
1438
1439 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
1440 {
1441 u8 val;
1442
1443 val = rtw_read8(Adapter, REG_MCUFWDL)
1444
1445 if (val) {
1446 RTW_INFO("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n",
1447 __func__, __LINE__, val);
1448 }
1449 }
1450 #endif
1451
1452
1453 valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1454 rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));/*enable MCU ,8051 */
1455
1456
1457 #endif
1458 } else {
1459 u8 retry_cnts = 0;
1460
1461 if (rtw_read8(Adapter, REG_MCUFWDL) & BIT1) {
1462 /*IF fw in RAM code, do reset */
1463
1464 rtw_write8(Adapter, REG_MCUFWDL, 0);
1465 if (GET_HAL_DATA(Adapter)->bFWReady) {
1466 /* 2010/08/25 MH According to RD alfred's suggestion, we need to disable other */
1467 /* HRCV INT to influence 8051 reset. */
1468 rtw_write8(Adapter, REG_FWIMR, 0x20);
1469
1470 rtw_write8(Adapter, REG_HMETFR + 3, 0x20); /*8051 reset by self */
1471
1472 while ((retry_cnts++ < 100) && (FEN_CPUEN & rtw_read16(Adapter, REG_SYS_FUNC_EN))) {
1473 /*PlatformStallExecution(50); //us */
1474 rtw_udelay_os(50);
1475 }
1476
1477 if (retry_cnts >= 100) {
1478 RTW_INFO("%s #####=> 8051 reset failed!.........................\n", __func__);
1479 /* if 8051 reset fail we trigger GPIO 0 for LA */
1480 /*PlatformEFIOWrite4Byte( Adapter, */
1481 /* REG_GPIO_PIN_CTRL, */
1482 /* 0x00010100); */
1483 /* 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. */
1484 rtw_write8(Adapter, REG_SYS_FUNC_EN + 1, 0x50); /*Reset MAC and Enable 8051 */
1485 rtw_mdelay_os(10);
1486 } else {
1487 /*RTW_INFO("%s =====> 8051 reset success (%d) .\n", __func__, retry_cnts); */
1488 }
1489 } else
1490 RTW_INFO("%s =====> 8051 in RAM but !hal_data->bFWReady\n", __func__);
1491 } else {
1492 /*RTW_INFO("%s =====> 8051 in ROM.\n", __func__); */
1493 }
1494
1495 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
1496 {
1497 u8 val;
1498 val = rtw_read8(Adapter, REG_MCUFWDL)
1499
1500 if (val) {
1501 RTW_INFO("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n",
1502 __func__, __LINE__, val);
1503 }
1504 }
1505 #endif
1506
1507 rtw_write8(Adapter, REG_SYS_FUNC_EN + 1, 0x54); /*Reset MAC and Enable 8051 */
1508 }
1509
1510 /* Clear rpwm value for initial toggle bit trigger. */
1511 rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
1512
1513 if (bWithoutHWSM) {
1514 /*
1515 * Without HW auto state machine
1516 * g. SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1517 * h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1518 * i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1519 * j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1520 */
1521 /*rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3); */
1522 rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);/*modify to 0x70A3 by Scott. */
1523 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
1524 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
1525 rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
1526 } else {
1527 /* Disable all RF/BB power */
1528 rtw_write8(Adapter, REG_RF_CTRL, 0x00);
1529 }
1530
1531 }
1532
1533 static void
1534 _ResetDigitalProcedure2(
1535 PADAPTER Adapter
1536 )
1537 {
1538 /*
1539 * k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1540 * l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1541 * m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1542 */
1543 /*rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott. */
1544 /*rtw_write16(Adapter, REG_SYS_CLKR, 0x3083); */
1545 /*rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83); */
1546
1547 rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); /*modify to 0x70a3 by Scott. */
1548 rtw_write8(Adapter, REG_SYS_ISO_CTRL + 1, 0x82); /*modify to 0x82 by Scott. */
1549 }
1550
1551 static void
1552 _DisableAnalog(
1553 PADAPTER Adapter,
1554 BOOLEAN bWithoutHWSM
1555 )
1556 {
1557 u16 value16 = 0;
1558 u8 value8 = 0;
1559 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1560
1561 if (bWithoutHWSM) {
1562 /*
1563 * n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1564 * o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1565 * r. When driver call disable, the ASIC will turn off remaining clock automatically
1566 */
1567
1568 rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
1569 /*PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54); */
1570
1571 value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
1572 value8 &= (~LDV12_EN);
1573 rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
1574 }
1575
1576 /*
1577 * h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1578 * i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1579 */
1580
1581
1582 value8 = 0x23;
1583
1584 rtw_write8(Adapter, REG_SPS0_CTRL, value8);
1585
1586
1587 if (bWithoutHWSM) {
1588 /* 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. */
1589 /* Because suspend operation need the asistance of 8051 to wait for 3ms. */
1590 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1591 } else
1592 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1593
1594 rtw_write16(Adapter, REG_APS_FSMCO, value16);/*0x4802 */
1595
1596 rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
1597
1598 #if 0
1599 /*tynli_test for suspend mode. */
1600 if (!bWithoutHWSM)
1601 rtw_write8(Adapter, 0xfe10, 0x19);
1602 #endif
1603
1604 }
1605 #endif
1606
rtl8188fu_hw_power_down(_adapter * padapter)1607 static void rtl8188fu_hw_power_down(_adapter *padapter)
1608 {
1609 u8 u1bTmp;
1610
1611 RTW_INFO("PowerDownRTL8188FU\n");
1612
1613
1614 /* 1. Run Card Disable Flow */
1615 /* Done before this function call. */
1616
1617 /* 2. 0x04[16] = 0 // reset WLON */
1618 u1bTmp = rtw_read8(padapter, REG_APS_FSMCO + 2);
1619 rtw_write8(padapter, REG_APS_FSMCO + 2, (u1bTmp & (~BIT0)));
1620
1621 /* 3. 0x04[12:11] = 2b'11 // enable suspend */
1622 /* Done before this function call. */
1623
1624 /* 4. 0x04[15] = 1 // enable PDN */
1625 u1bTmp = rtw_read8(padapter, REG_APS_FSMCO + 1);
1626 rtw_write8(padapter, REG_APS_FSMCO + 1, (u1bTmp | BIT7));
1627 }
1628
1629 /* */
1630 /* Description: RTL8188F card disable power sequence v003 which suggested by Scott. */
1631 /* First created by tynli. 2011.01.28. */
1632 /* */
1633 void
CardDisableRTL8188FU(PADAPTER Adapter)1634 CardDisableRTL8188FU(
1635 PADAPTER Adapter
1636 )
1637 {
1638 u8 u1bTmp;
1639 /* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
1640
1641 RTW_INFO("CardDisableRTL8188FU\n");
1642
1643 /*Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
1644 u1bTmp = rtw_read8(Adapter, REG_TX_RPT_CTRL);
1645 rtw_write8(Adapter, REG_TX_RPT_CTRL, u1bTmp & (~BIT1));
1646
1647 /* stop rx */
1648 rtw_write8(Adapter, REG_CR_8188F, 0x0);
1649 if ((rtw_read8(Adapter, REG_MCUFWDL_8188F) & BIT7) &&
1650 GET_HAL_DATA(Adapter)->bFWReady) /*8051 RAM code */
1651 rtl8188f_FirmwareSelfReset(Adapter);
1652
1653 /* 1. Run LPS WL RFOFF flow */
1654 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8188F_enter_lps_flow);
1655
1656 /* Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */
1657 u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN_8188F + 1);
1658 rtw_write8(Adapter, REG_SYS_FUNC_EN_8188F + 1, (u1bTmp & (~BIT2)));
1659
1660 /* MCUFWDL 0x80[1:0]=0 // reset MCU ready status */
1661 rtw_write8(Adapter, REG_MCUFWDL_8188F, 0x00);
1662
1663 /* Card disable power action flow */
1664 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8188F_card_disable_flow);
1665
1666 GET_HAL_DATA(Adapter)->bFWReady = _FALSE;
1667 }
1668
rtl8188fu_hal_deinit(PADAPTER Adapter)1669 u32 rtl8188fu_hal_deinit(PADAPTER Adapter)
1670 {
1671 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
1672 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1673
1674 RTW_INFO("==> %s\n", __func__);
1675
1676 rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG) & (~BIT12));
1677
1678 rtw_write32(Adapter, REG_HISR0_8188F, 0xFFFFFFFF);
1679 rtw_write32(Adapter, REG_HISR1_8188F, 0xFFFFFFFF);
1680
1681 #if 0
1682 /* USB only need to clear HISR, no need to set HIMR, because there's no hardware interrupt for USB. */
1683 rtw_write32(Adapter, REG_HIMR0_8188F, IMR_DISABLED_8188F);
1684 rtw_write32(Adapter, REG_HIMR1_8188F, IMR_DISABLED_8188F);
1685 #endif
1686
1687 #ifdef CONFIG_MP_INCLUDED
1688 if (Adapter->registrypriv.mp_mode == 1)
1689 MPT_DeInitAdapter(Adapter);
1690 #endif
1691
1692 #ifdef SUPPORT_HW_RFOFF_DETECTED
1693 RTW_INFO("%s: bkeepfwalive(%x)\n", __func__, pwrctl->bkeepfwalive);
1694
1695 if (pwrctl->bkeepfwalive) {
1696 _ps_close_RF(Adapter);
1697 if ((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown))
1698 rtl8188fu_hw_power_down(Adapter);
1699 } else
1700 #endif
1701 {
1702 if (rtw_is_hw_init_completed(Adapter)) {
1703 rtw_hal_power_off(Adapter);
1704
1705 if ((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown))
1706 rtl8188fu_hw_power_down(Adapter);
1707 }
1708 pHalData->bMacPwrCtrlOn = _FALSE;
1709 }
1710 return _SUCCESS;
1711 }
1712
rtl8188fu_inirp_init(PADAPTER Adapter)1713 unsigned int rtl8188fu_inirp_init(PADAPTER Adapter)
1714 {
1715 struct registry_priv *regsty = adapter_to_regsty(Adapter);
1716 u8 i;
1717 struct recv_buf *precvbuf;
1718 uint status;
1719 struct dvobj_priv *pdev = adapter_to_dvobj(Adapter);
1720 struct intf_hdl *pintfhdl = &Adapter->iopriv.intf;
1721 struct recv_priv *precvpriv = &(Adapter->recvpriv);
1722
1723 u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
1724 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
1725 u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
1726 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1727 #endif /*CONFIG_USB_INTERRUPT_IN_PIPE */
1728
1729
1730 _read_port = pintfhdl->io_ops._read_port;
1731
1732 status = _SUCCESS;
1733
1734
1735 precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1736
1737 /*issue Rx irp to receive data */
1738 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1739 for (i = 0; i < regsty->recvbuf_nr; i++) {
1740 if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE) {
1741 status = _FAIL;
1742 goto exit;
1743 }
1744
1745 precvbuf++;
1746 precvpriv->free_recv_buf_queue_cnt--;
1747 }
1748
1749 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
1750 _read_interrupt = pintfhdl->io_ops._read_interrupt;
1751 if (_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE) {
1752 status = _FAIL;
1753 }
1754 pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR);
1755 RTW_INFO("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
1756 pHalData->IntrMask[0] |= UHIMR_C2HCMD | UHIMR_CPWM;
1757 rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
1758 #endif /*CONFIG_USB_INTERRUPT_IN_PIPE */
1759
1760 exit:
1761
1762
1763
1764 return status;
1765
1766 }
1767
rtl8188fu_inirp_deinit(PADAPTER Adapter)1768 unsigned int rtl8188fu_inirp_deinit(PADAPTER Adapter)
1769 {
1770 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
1771 u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
1772 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1773 #endif /*CONFIG_USB_INTERRUPT_IN_PIPE */
1774
1775 rtw_read_port_cancel(Adapter);
1776 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
1777 pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR);
1778 RTW_INFO("%s pHalData->IntrMask = 0x%04x\n", __func__, pHalData->IntrMask[0]);
1779 pHalData->IntrMask[0] = 0x0;
1780 rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
1781 #endif /*CONFIG_USB_INTERRUPT_IN_PIPE */
1782 return _SUCCESS;
1783 }
1784
1785 /*------------------------------------------------------------------- */
1786 /* */
1787 /* EEPROM/EFUSE Content Parsing */
1788 /* */
1789 /*------------------------------------------------------------------- */
1790 #if 0
1791 static void
1792 _ReadLEDSetting(
1793 PADAPTER Adapter,
1794 u8 *PROMContent,
1795 BOOLEAN AutoloadFail
1796 )
1797 {
1798 #ifdef CONFIG_RTW_LED
1799 struct led_priv *pledpriv = adapter_to_led(Adapter);
1800 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1801
1802 #ifdef CONFIG_RTW_SW_LED
1803 pledpriv->bRegUseLed = _TRUE;
1804
1805 /* */
1806 /* Led mode */
1807 /* */
1808 switch (pHalData->CustomerID) {
1809 case RT_CID_DEFAULT:
1810 pledpriv->LedStrategy = SW_LED_MODE1;
1811 pledpriv->bRegUseLed = _TRUE;
1812 break;
1813
1814 case RT_CID_819x_HP:
1815 pledpriv->LedStrategy = SW_LED_MODE6;
1816 break;
1817
1818 default:
1819 pledpriv->LedStrategy = SW_LED_MODE1;
1820 break;
1821 }
1822
1823 /* if( BOARD_MINICARD == pHalData->BoardType ) */
1824 /* { */
1825 /* pledpriv->LedStrategy = SW_LED_MODE6; */
1826 /* } */
1827 pHalData->bLedOpenDrain = _TRUE;/* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
1828 #else /* HW LED */
1829 pledpriv->LedStrategy = HW_LED;
1830 #endif /*CONFIG_RTW_SW_LED */
1831 #endif /*CONFIG_RTW_LED*/
1832 }
1833 #endif
1834
1835 void
Hal_EfuseParsePIDVID_8188FU(PADAPTER pAdapter,u8 * hwinfo,BOOLEAN AutoLoadFail)1836 Hal_EfuseParsePIDVID_8188FU(
1837 PADAPTER pAdapter,
1838 u8 *hwinfo,
1839 BOOLEAN AutoLoadFail
1840 )
1841 {
1842 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1843
1844 if (AutoLoadFail) {
1845 pHalData->EEPROMVID = 0;
1846 pHalData->EEPROMPID = 0;
1847 } else {
1848 /* VID, PID */
1849 pHalData->EEPROMVID = le16_to_cpu(*(u16 *)&hwinfo[EEPROM_VID_8188FU]);
1850 pHalData->EEPROMPID = le16_to_cpu(*(u16 *)&hwinfo[EEPROM_PID_8188FU]);
1851
1852 }
1853
1854 RTW_INFO("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
1855 RTW_INFO("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
1856 }
1857
1858 static u8
InitAdapterVariablesByPROM_8188FU(PADAPTER padapter)1859 InitAdapterVariablesByPROM_8188FU(
1860 PADAPTER padapter
1861 )
1862 {
1863 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1864 u8 *hwinfo = NULL;
1865 u8 ret = _FAIL;
1866
1867 if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8188F)
1868 RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8188F!\n");
1869
1870 hwinfo = pHalData->efuse_eeprom_data;
1871
1872 Hal_InitPGData(padapter, hwinfo);
1873
1874 Hal_EfuseParseIDCode(padapter, hwinfo);
1875 Hal_EfuseParsePIDVID_8188FU(padapter, hwinfo, pHalData->bautoload_fail_flag);
1876 Hal_EfuseParseEEPROMVer_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1877 hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
1878 Hal_EfuseParseTxPowerInfo_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1879 /* Hal_EfuseParseBTCoexistInfo_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); */
1880
1881 Hal_EfuseParseChnlPlan_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1882 Hal_EfuseParseThermalMeter_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1883 /* _ReadLEDSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag); */
1884 Hal_EfuseParsePowerSavingMode_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1885 Hal_EfuseParseAntennaDiversity_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1886
1887 Hal_EfuseParseEEPROMVer_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1888 Hal_EfuseParseCustomerID_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1889 /* Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pHalData->bautoload_fail_flag); */
1890 Hal_EfuseParseXtal_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1891 /* */
1892 /* The following part initialize some vars by PG info. */
1893 /* */
1894 /* Hal_InitChannelPlan(padapter); */
1895
1896
1897
1898 /*hal_CustomizedBehavior_8188FU(Adapter); */
1899
1900 Hal_EfuseParseKFreeData_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag);
1901
1902 if (hal_read_mac_hidden_rpt(padapter) != _SUCCESS)
1903 goto exit;
1904
1905 /* Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */
1906 RTW_INFO("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle);
1907
1908 ret = _SUCCESS;
1909
1910 exit:
1911 return ret;
1912 }
1913
_ReadPROMContent(PADAPTER Adapter)1914 static u8 _ReadPROMContent(
1915 PADAPTER Adapter
1916 )
1917 {
1918 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1919 u8 eeValue;
1920 u8 ret = _FAIL;
1921
1922 /* To check system boot selection. */
1923 eeValue = rtw_read8(Adapter, REG_SYS_EEPROM_CTRL);
1924 pHalData->EepromOrEfuse = (eeValue & EEPROMSEL) ? _TRUE : _FALSE;
1925 pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
1926
1927 RTW_INFO("Boot from %s, Autoload %s !\n", (pHalData->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1928 (pHalData->bautoload_fail_flag ? "Fail" : "OK"));
1929
1930 #ifdef CONFIG_8188FTV_SOLUTION_D
1931 rtl8188fu_solution_d(Adapter);
1932 #endif
1933
1934 if (InitAdapterVariablesByPROM_8188FU(Adapter) != _SUCCESS)
1935 goto exit;
1936
1937 ret = _SUCCESS;
1938
1939 exit:
1940 return ret;
1941 }
1942
1943 static void
_ReadRFType(PADAPTER Adapter)1944 _ReadRFType(
1945 PADAPTER Adapter
1946 )
1947 {
1948 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1949
1950 #if DISABLE_BB_RF
1951 pHalData->rf_chip = RF_PSEUDO_11N;
1952 #else
1953 pHalData->rf_chip = RF_6052;
1954 #endif
1955 }
1956
1957
1958
1959 /* */
1960 /* Description: */
1961 /* We should set Efuse cell selection to WiFi cell in default. */
1962 /* */
1963 /* Assumption: */
1964 /* PASSIVE_LEVEL */
1965 /* */
1966 /* Added by Roger, 2010.11.23. */
1967 /* */
1968 void
hal_EfuseCellSel(PADAPTER Adapter)1969 hal_EfuseCellSel(
1970 PADAPTER Adapter
1971 )
1972 {
1973 u32 value32;
1974
1975 value32 = rtw_read32(Adapter, EFUSE_TEST);
1976 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1977 rtw_write32(Adapter, EFUSE_TEST, value32);
1978 }
1979
ReadAdapterInfo8188FU(PADAPTER Adapter)1980 static u8 ReadAdapterInfo8188FU(PADAPTER Adapter)
1981 {
1982 u8 ret = _FAIL;
1983
1984 /* Read EEPROM size before call any EEPROM function */
1985 Adapter->EepromAddressSize = GetEEPROMSize8188F(Adapter);
1986
1987 hal_EfuseCellSel(Adapter);
1988
1989 _ReadRFType(Adapter);/*rf_chip->_InitRFType() */
1990 if (_ReadPROMContent(Adapter) != _SUCCESS)
1991 goto exit;
1992
1993 ret = _SUCCESS;
1994
1995 exit:
1996 return ret;
1997 }
1998
1999 #define GPIO_DEBUG_PORT_NUM 0
rtl8188fu_trigger_gpio_0(_adapter * padapter)2000 static void rtl8188fu_trigger_gpio_0(_adapter *padapter)
2001 {
2002
2003 u32 gpioctrl;
2004 RTW_INFO("==> trigger_gpio_0...\n");
2005 rtw_write16_async(padapter, REG_GPIO_PIN_CTRL, 0);
2006 rtw_write8_async(padapter, REG_GPIO_PIN_CTRL + 2, 0xFF);
2007 gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM) << 24) | (BIT(GPIO_DEBUG_PORT_NUM) << 16);
2008 rtw_write32_async(padapter, REG_GPIO_PIN_CTRL, gpioctrl);
2009 gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM) << 8);
2010 rtw_write32_async(padapter, REG_GPIO_PIN_CTRL, gpioctrl);
2011 RTW_INFO("<=== trigger_gpio_0...\n");
2012
2013 }
2014
2015 /*
2016 * If variable not handled here,
2017 * some variables will be processed in SetHwReg8188FU()
2018 */
SetHwReg8188FU(PADAPTER Adapter,u8 variable,u8 * val)2019 u8 SetHwReg8188FU(PADAPTER Adapter, u8 variable, u8 *val)
2020 {
2021 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
2022 u8 ret = _SUCCESS;
2023
2024
2025 switch (variable) {
2026 case HW_VAR_RXDMA_AGG_PG_TH:
2027 #ifdef CONFIG_USB_RX_AGGREGATION
2028 {
2029 /* threshold == 1 , Disable Rx-agg when AP is B/G mode or wifi_spec=1 to prevent bad TP. */
2030
2031 u8 threshold = *((u8 *)val);
2032 u32 agg_size;
2033
2034 if (threshold == 0) {
2035 switch (pHalData->rxagg_mode) {
2036 case RX_AGG_DMA:
2037 agg_size = pHalData->rxagg_dma_size << 10;
2038 if (agg_size > RX_DMA_BOUNDARY_8188F)
2039 agg_size = RX_DMA_BOUNDARY_8188F >> 1;
2040 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
2041 agg_size = MAX_RECVBUF_SZ - 2048;
2042 agg_size >>= 10; /* unit: 1K */
2043 if (agg_size > 0xF)
2044 agg_size = 0xF;
2045
2046 threshold = (agg_size & 0xF);
2047 break;
2048 case RX_AGG_USB:
2049 case RX_AGG_MIX:
2050 agg_size = pHalData->rxagg_usb_size << 12;
2051 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
2052 agg_size = MAX_RECVBUF_SZ - 2048;
2053 agg_size >>= 12; /* unit: 4K */
2054 if (agg_size > 0xF)
2055 agg_size = 0xF;
2056
2057 threshold = (agg_size & 0xF);
2058 break;
2059 case RX_AGG_DISABLE:
2060 default:
2061 break;
2062 }
2063 }
2064
2065 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
2066
2067 #ifdef CONFIG_80211N_HT
2068 {
2069 /* 2014-07-24 Fix WIFI Logo -5.2.4/5.2.9 - DT3 low TP issue */
2070 /* Adjust RxAggrTimeout to close to zero disable RxAggr for RxAgg-USB mode, suggested by designer */
2071 /* Timeout value is calculated by 34 / (2^n) */
2072 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
2073 struct ht_priv *phtpriv = &pmlmepriv->htpriv;
2074
2075 if (pHalData->rxagg_mode == RX_AGG_USB) {
2076 /* BG mode || (wifi_spec=1 && BG mode Testbed) */
2077 if ((threshold == 1) && (phtpriv->ht_option == _FALSE))
2078 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 1, 0);
2079 else
2080 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 1, pHalData->rxagg_usb_timeout);
2081 }
2082 }
2083 #endif/* CONFIG_80211N_HT */
2084 }
2085 #endif/* CONFIG_USB_RX_AGGREGATION */
2086 break;
2087
2088 case HW_VAR_SET_RPWM:
2089 #ifdef CONFIG_LPS_LCLK
2090 {
2091 u8 ps_state = *((u8 *)val);
2092
2093 /*rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e.
2094 BIT0 value - 1: 32k, 0:40MHz.
2095 BIT6 value - 1: report cpwm value after success set, 0:do not report.
2096 BIT7 value - Toggle bit change.
2097 modify by Thomas. 2012/4/2.*/
2098 ps_state = ps_state & 0xC1;
2099 /* RTW_INFO("##### Change RPWM value to = %x for switch clk #####\n", ps_state); */
2100 rtw_write8(Adapter, REG_USB_HRPWM, ps_state);
2101 }
2102 #endif
2103 break;
2104
2105 case HW_VAR_TRIGGER_GPIO_0:
2106 rtl8188fu_trigger_gpio_0(Adapter);
2107 break;
2108
2109 default:
2110 ret = SetHwReg8188F(Adapter, variable, val);
2111 break;
2112 }
2113
2114 return ret;
2115 }
2116
2117 /*
2118 * If variable not handled here,
2119 * some variables will be processed in GetHwReg8188FU()
2120 */
GetHwReg8188FU(PADAPTER Adapter,u8 variable,u8 * val)2121 void GetHwReg8188FU(PADAPTER Adapter, u8 variable, u8 *val)
2122 {
2123 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
2124
2125
2126 switch (variable) {
2127 case HW_VAR_CPWM:
2128 #ifdef CONFIG_LPS_LCLK
2129 *val = rtw_read8(Adapter, REG_USB_HCPWM);
2130 /* RTW_INFO("##### REG_USB_HCPWM(0x%02x) = 0x%02x #####\n", REG_USB_HCPWM, *val); */
2131 #endif /* CONFIG_LPS_LCLK */
2132 break;
2133 default:
2134 GetHwReg8188F(Adapter, variable, val);
2135 break;
2136 }
2137
2138 }
2139
2140 /* */
2141 /* Description: */
2142 /* Query setting of specified variable. */
2143 /* */
2144 u8
GetHalDefVar8188FUsb(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)2145 GetHalDefVar8188FUsb(
2146 PADAPTER Adapter,
2147 HAL_DEF_VARIABLE eVariable,
2148 void *pValue
2149 )
2150 {
2151 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2152 u8 bResult = _SUCCESS;
2153
2154 switch (eVariable) {
2155 case HAL_DEF_IS_SUPPORT_ANT_DIV:
2156 #ifdef CONFIG_ANTENNA_DIVERSITY
2157 *((u8 *)pValue) = (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;
2158 #endif
2159 break;
2160
2161 case HAL_DEF_DRVINFO_SZ:
2162 *((u32 *)pValue) = DRVINFO_SZ;
2163 break;
2164 case HAL_DEF_MAX_RECVBUF_SZ:
2165 *((u32 *)pValue) = MAX_RECVBUF_SZ;
2166 break;
2167 case HAL_DEF_RX_PACKET_OFFSET:
2168 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ * 8;
2169 break;
2170 case HW_VAR_MAX_RX_AMPDU_FACTOR:
2171 *((HT_CAP_AMPDU_FACTOR *)pValue) = MAX_AMPDU_FACTOR_64K;
2172 break;
2173 default:
2174 bResult = GetHalDefVar8188F(Adapter, eVariable, pValue);
2175 break;
2176 }
2177
2178 return bResult;
2179 }
2180
2181
2182
2183
2184 /* */
2185 /* Description: */
2186 /* Change default setting of specified variable. */
2187 /* */
2188 u8
SetHalDefVar8188FUsb(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)2189 SetHalDefVar8188FUsb(
2190 PADAPTER Adapter,
2191 HAL_DEF_VARIABLE eVariable,
2192 void *pValue
2193 )
2194 {
2195 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2196 u8 bResult = _SUCCESS;
2197
2198 switch (eVariable) {
2199 default:
2200 bResult = SetHalDefVar8188F(Adapter, eVariable, pValue);
2201 break;
2202 }
2203
2204 return bResult;
2205 }
2206
rtl8188fu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id,u8 * val)2207 static u8 rtl8188fu_ps_func(PADAPTER Adapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
2208 {
2209 u8 bResult = _TRUE;
2210 switch (efunc_id) {
2211
2212 default:
2213 break;
2214 }
2215 return bResult;
2216 }
2217
rtl8188fu_set_hal_ops(_adapter * padapter)2218 void rtl8188fu_set_hal_ops(_adapter *padapter)
2219 {
2220 struct hal_ops *pHalFunc = &padapter->hal_func;
2221
2222
2223 rtl8188f_set_hal_ops(pHalFunc);
2224
2225 pHalFunc->hal_power_on = &_InitPowerOn_8188FU;
2226 pHalFunc->hal_power_off = &CardDisableRTL8188FU;
2227
2228 pHalFunc->hal_init = &rtl8188fu_hal_init;
2229 pHalFunc->hal_deinit = &rtl8188fu_hal_deinit;
2230
2231 pHalFunc->inirp_init = &rtl8188fu_inirp_init;
2232 pHalFunc->inirp_deinit = &rtl8188fu_inirp_deinit;
2233
2234 pHalFunc->init_xmit_priv = &rtl8188fu_init_xmit_priv;
2235 pHalFunc->free_xmit_priv = &rtl8188fu_free_xmit_priv;
2236
2237 pHalFunc->init_recv_priv = &rtl8188fu_init_recv_priv;
2238 pHalFunc->free_recv_priv = &rtl8188fu_free_recv_priv;
2239 #ifdef CONFIG_RTW_SW_LED
2240 pHalFunc->InitSwLeds = &rtl8188fu_InitSwLeds;
2241 pHalFunc->DeInitSwLeds = &rtl8188fu_DeInitSwLeds;
2242 #endif/*CONFIG_RTW_SW_LED */
2243
2244 pHalFunc->init_default_value = &rtl8188f_init_default_value;
2245 pHalFunc->intf_chip_configure = &rtl8188fu_interface_configure;
2246 pHalFunc->read_adapter_info = &ReadAdapterInfo8188FU;
2247
2248 pHalFunc->set_hw_reg_handler = &SetHwReg8188FU;
2249 pHalFunc->GetHwRegHandler = &GetHwReg8188FU;
2250 pHalFunc->get_hal_def_var_handler = &GetHalDefVar8188FUsb;
2251 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188FUsb;
2252
2253 pHalFunc->hal_xmit = &rtl8188fu_hal_xmit;
2254 pHalFunc->mgnt_xmit = &rtl8188fu_mgnt_xmit;
2255 pHalFunc->hal_xmitframe_enqueue = &rtl8188fu_hal_xmitframe_enqueue;
2256
2257 #ifdef CONFIG_HOSTAPD_MLME
2258 pHalFunc->hostap_mgnt_xmit_entry = &rtl8188fu_hostap_mgnt_xmit_entry;
2259 #endif
2260 pHalFunc->interface_ps_func = &rtl8188fu_ps_func;
2261
2262 #ifdef CONFIG_XMIT_THREAD_MODE
2263 pHalFunc->xmit_thread_handler = &rtl8188fu_xmit_buf_handler;
2264 #endif
2265 #ifdef CONFIG_SUPPORT_USB_INT
2266 pHalFunc->interrupt_handler = interrupt_handler_8188fu;
2267 #endif
2268
2269 }
2270