1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #include "../phydm_precomp.h"
18
19 #if (RTL8188F_SUPPORT == 1)
20
odm_config_rf_reg_8188f(struct dm_struct * dm,u32 addr,u32 data,enum rf_path RF_PATH,u32 reg_addr)21 void odm_config_rf_reg_8188f(struct dm_struct *dm, u32 addr, u32 data,
22 enum rf_path RF_PATH, u32 reg_addr)
23 {
24 if (addr == 0xfe || addr == 0xffe) {
25 #ifdef CONFIG_LONG_DELAY_ISSUE
26 ODM_sleep_ms(50);
27 #else
28 ODM_delay_ms(50);
29 #endif
30 } else {
31 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
32 /* Add 1us delay between BB/RF register setting. */
33 ODM_delay_us(1);
34
35 /* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
36 if (addr == 0xb6) {
37 u32 getvalue = 0;
38 u8 count = 0;
39 getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
40
41 ODM_delay_us(1);
42
43 while ((getvalue >> 8) != (data >> 8)) {
44 count++;
45 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
46 ODM_delay_us(1);
47 getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
48 PHYDM_DBG(dm, ODM_COMP_INIT,
49 "===> odm_config_rf_with_header_file: [B6] getvalue 0x%x, data 0x%x, count %d\n",
50 getvalue, data, count);
51 if (count > 5)
52 break;
53 }
54 }
55
56 if (addr == 0xb2) {
57 u32 getvalue = 0;
58 u8 count = 0;
59 getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
60
61 ODM_delay_us(1);
62
63 while (getvalue != data) {
64 count++;
65 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
66 ODM_delay_us(1);
67 /* Do LCK againg */
68 odm_set_rf_reg(dm, RF_PATH, RF_0x18, RFREGOFFSETMASK, 0x0fc07);
69 ODM_delay_us(1);
70 getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
71 PHYDM_DBG(dm, ODM_COMP_INIT,
72 "===> odm_config_rf_with_header_file: [B2] getvalue 0x%x, data 0x%x, count %d\n",
73 getvalue, data, count);
74 if (count > 5)
75 break;
76 }
77 }
78 }
79 }
80
odm_config_rf_radio_a_8188f(struct dm_struct * dm,u32 addr,u32 data)81 void odm_config_rf_radio_a_8188f(struct dm_struct *dm, u32 addr, u32 data)
82 {
83 u32 content = 0x1000; /* RF_Content: radioa_txt */
84 u32 maskfor_phy_set = (u32)(content & 0xE000);
85
86 odm_config_rf_reg_8188f(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
87
88 PHYDM_DBG(dm, ODM_COMP_INIT,
89 "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
90 addr, data);
91 }
92
odm_config_rf_radio_b_8188f(struct dm_struct * dm,u32 addr,u32 data)93 void odm_config_rf_radio_b_8188f(struct dm_struct *dm, u32 addr, u32 data)
94 {
95 u32 content = 0x1001; /* RF_Content: radiob_txt */
96 u32 maskfor_phy_set = (u32)(content & 0xE000);
97
98 odm_config_rf_reg_8188f(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
99
100 PHYDM_DBG(dm, ODM_COMP_INIT,
101 "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
102 addr, data);
103 }
104
odm_config_mac_8188f(struct dm_struct * dm,u32 addr,u8 data)105 void odm_config_mac_8188f(struct dm_struct *dm, u32 addr, u8 data)
106 {
107 odm_write_1byte(dm, addr, data);
108 PHYDM_DBG(dm, ODM_COMP_INIT,
109 "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
110 addr, data);
111 }
112
odm_config_bb_agc_8188f(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)113 void odm_config_bb_agc_8188f(struct dm_struct *dm, u32 addr, u32 bitmask,
114 u32 data)
115 {
116 odm_set_bb_reg(dm, addr, bitmask, data);
117 /* Add 1us delay between BB/RF register setting. */
118 ODM_delay_us(1);
119
120 PHYDM_DBG(dm, ODM_COMP_INIT,
121 "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
122 addr, data);
123 }
124
odm_config_bb_phy_reg_pg_8188f(struct dm_struct * dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)125 void odm_config_bb_phy_reg_pg_8188f(struct dm_struct *dm, u32 band, u32 rf_path,
126 u32 tx_num, u32 addr, u32 bitmask, u32 data)
127
128 {
129 if (addr == 0xfe || addr == 0xffe)
130 #ifdef CONFIG_LONG_DELAY_ISSUE
131 ODM_sleep_ms(50);
132 #else
133 ODM_delay_ms(50);
134 #endif
135 else {
136 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
137 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
138 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
139 PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
140 #endif
141 }
142 PHYDM_DBG(dm, ODM_COMP_INIT,
143 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
144 addr, bitmask, data);
145 }
146
odm_config_bb_phy_8188f(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)147 void odm_config_bb_phy_8188f(struct dm_struct *dm, u32 addr, u32 bitmask,
148 u32 data)
149 {
150 if (addr == 0xfe)
151 #ifdef CONFIG_LONG_DELAY_ISSUE
152 ODM_sleep_ms(50);
153 #else
154 ODM_delay_ms(50);
155 #endif
156 else if (addr == 0xfd)
157 ODM_delay_ms(5);
158 else if (addr == 0xfc)
159 ODM_delay_ms(1);
160 else if (addr == 0xfb)
161 ODM_delay_us(50);
162 else if (addr == 0xfa)
163 ODM_delay_us(5);
164 else if (addr == 0xf9)
165 ODM_delay_us(1);
166 else
167 odm_set_bb_reg(dm, addr, bitmask, data);
168
169 /* Add 1us delay between BB/RF register setting. */
170 ODM_delay_us(1);
171 PHYDM_DBG(dm, ODM_COMP_INIT,
172 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
173 addr, data);
174 }
175
odm_config_bb_txpwr_lmt_8188f(struct dm_struct * dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)176 void odm_config_bb_txpwr_lmt_8188f(struct dm_struct *dm, u8 *regulation,
177 u8 *band, u8 *bandwidth, u8 *rate_section,
178 u8 *rf_path, u8 *channel, u8 *power_limit)
179 {
180 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
181 phy_set_tx_power_limit(dm, regulation, band,
182 bandwidth, rate_section, rf_path, channel, power_limit);
183 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
184 PHY_SetTxPowerLimit(dm, regulation, band,
185 bandwidth, rate_section, rf_path, channel, power_limit);
186 #endif
187 }
188
189 #endif
190