1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMDIG_H__ 27 #define __PHYDMDIG_H__ 28 29 /* 2019.10.25 remove redundant code*/ 30 #define DIG_VERSION "3.7" 31 32 #define DIG_HW 0 33 #define DIG_LIMIT_PERIOD 60 /*60 sec*/ 34 35 /*@--------------------Define ---------------------------------------*/ 36 37 /*@=== [DIG Boundary] ========================================*/ 38 /*@DIG coverage mode*/ 39 #define DIG_MAX_COVERAGR 0x26 40 #define DIG_MIN_COVERAGE 0x1c 41 #define DIG_MAX_OF_MIN_COVERAGE 0x22 42 43 /*@[DIG Balance mode]*/ 44 #if (DIG_HW == 1) 45 #define DIG_MAX_BALANCE_MODE 0x32 46 #else 47 #define DIG_MAX_BALANCE_MODE 0x3e 48 #endif 49 #define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a 50 51 /*@[DIG Performance mode]*/ 52 #define DIG_MAX_PERFORMANCE_MODE 0x5a 53 #define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/ 54 #define DIG_MIN_PERFORMANCE 0x20 55 56 /*@DIG DFS function*/ 57 #define DIG_MAX_DFS 0x28 58 #define DIG_MIN_DFS 0x20 59 60 /*@DIG LPS function*/ 61 #define DIG_MAX_LPS 0x3e 62 #define DIG_MIN_LPS 0x20 63 64 #ifdef PHYDM_TDMA_DIG_SUPPORT 65 #define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/ 66 #define DIG_TIMER_MS 250 67 #define ONE_SEC_MS 1000 68 #endif 69 70 /*@=== [DIG FA Threshold] ======================================*/ 71 72 /*Normal*/ 73 #define DM_DIG_FA_TH0 500 74 #define DM_DIG_FA_TH1 750 75 76 /*@LPS*/ 77 #define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */ 78 #define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */ 79 #define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */ 80 81 #define RSSI_OFFSET_DIG_LPS 5 82 #define DIG_RECORD_NUM 4 83 84 /*@--------------------Enum-----------------------------------*/ 85 enum phydm_dig_mode { 86 PHYDM_DIG_PERFORAMNCE_MODE = 0, 87 PHYDM_DIG_COVERAGE_MODE = 1, 88 }; 89 90 enum phydm_dig_trend { 91 DIG_STABLE = 0, 92 DIG_INCREASING = 1, 93 DIG_DECREASING = 2 94 }; 95 96 enum phydm_fw_dig_mode_e { 97 DIG_PERFORMANCE_MODE = 0, 98 DIG_COVERAGE_MODE = 1, 99 DIG_LPS_MODE = 2 100 }; 101 102 #ifdef PHYDM_TDMA_DIG_SUPPORT 103 enum upd_type { 104 ENABLE_TDMA, 105 MODE_DECISION 106 }; 107 108 enum tdma_opmode { 109 MODE_PERFORMANCE = 1, 110 MODE_COVERAGE = 2 111 }; 112 113 #ifdef IS_USE_NEW_TDMA 114 enum tdma_dig_timer { 115 INIT_TDMA_DIG_TIMMER, 116 CANCEL_TDMA_DIG_TIMMER, 117 RELEASE_TDMA_DIG_TIMMER 118 }; 119 120 enum tdma_dig_state { 121 TDMA_DIG_LOW_STATE = 0, 122 TDMA_DIG_HIGH_STATE = 1, 123 NORMAL_DIG = 2 124 }; 125 #endif 126 #endif 127 128 /*@--------------------Define Struct-----------------------------------*/ 129 #ifdef CFG_DIG_DAMPING_CHK 130 struct phydm_dig_recorder_strcut { 131 u8 igi_bitmap; /*@Don't add any new parameter before this*/ 132 u8 igi_history[DIG_RECORD_NUM]; 133 u32 fa_history[DIG_RECORD_NUM]; 134 u8 damping_limit_en; 135 u8 damping_limit_val; /*@Limit IGI_dyn_min*/ 136 u32 limit_time; 137 u8 limit_rssi; 138 }; 139 #endif 140 141 struct phydm_mcc_dig { 142 u8 mcc_rssi_A; 143 u8 mcc_rssi_B; 144 }; 145 146 struct phydm_dig_struct { 147 #ifdef CFG_DIG_DAMPING_CHK 148 struct phydm_dig_recorder_strcut dig_recorder_t; 149 u8 dig_dl_en; /*@damping limit function enable*/ 150 #endif 151 boolean fw_dig_enable; 152 boolean is_dbg_fa_th; 153 u8 cur_ig_value; 154 boolean igi_dyn_up_hit; 155 u8 igi_trend; 156 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 157 u8 igi_backup; 158 u8 rx_gain_range_max; /*@dig_dynamic_max*/ 159 u8 rx_gain_range_min; /*@dig_dynamic_min*/ 160 u8 dm_dig_max; /*@Absolutly upper bound*/ 161 u8 dm_dig_min; /*@Absolutly lower bound*/ 162 u8 dig_max_of_min; /*@Absolutly max of min*/ 163 u32 ant_div_rssi_max; 164 u8 *is_p2p_in_process; 165 u16 fa_th[3]; 166 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ 167 RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\ 168 RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\ 169 RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 170 u8 rf_gain_idx; 171 u8 agc_table_idx; 172 u8 big_jump_lmt[16]; 173 u8 enable_adjust_big_jump:1; 174 u8 big_jump_step1:3; 175 u8 big_jump_step2:2; 176 u8 big_jump_step3:2; 177 #endif 178 u8 upcheck_init_val; 179 u8 lv0_ratio_reciprocal; 180 u8 lv1_ratio_reciprocal; 181 #ifdef PHYDM_TDMA_DIG_SUPPORT 182 u8 cur_ig_value_tdma; 183 u8 low_ig_value; 184 u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/ 185 u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/ 186 u8 pre_tdma_dig_cnt; 187 u8 sec_factor; 188 u32 cur_timestamp; 189 u32 pre_timestamp; 190 u32 fa_start_timestamp; 191 u32 fa_end_timestamp; 192 u32 fa_acc_1sec_timestamp; 193 #ifdef IS_USE_NEW_TDMA 194 u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/ 195 /*@dynamic upper bound for L/H state*/ 196 u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES]; 197 /*@dynamic lower bound for L/H state*/ 198 u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES]; 199 /*To distinguish current state(L-sate or H-state)*/ 200 #endif 201 u8 tdma_force_l_igi; 202 u8 tdma_force_h_igi; 203 #endif 204 }; 205 206 struct phydm_fa_struct { 207 u32 cnt_parity_fail; 208 u32 cnt_rate_illegal; 209 u32 cnt_crc8_fail; 210 u32 cnt_crc8_fail_vhta; 211 u32 cnt_crc8_fail_vhtb; 212 u32 cnt_mcs_fail; 213 u32 cnt_mcs_fail_vht; 214 u32 cnt_ofdm_fail; 215 u32 cnt_ofdm_fail_pre; /* @For RTL8881A */ 216 u32 cnt_cck_fail; 217 u32 cnt_all; 218 u32 cnt_all_accumulated; 219 u32 cnt_all_pre; 220 u32 cnt_fast_fsync; 221 u32 cnt_sb_search_fail; 222 u32 cnt_ofdm_cca; 223 u32 cnt_cck_cca; 224 u32 cnt_cca_all; 225 u32 cnt_bw_usc; 226 u32 cnt_bw_lsc; 227 u32 cnt_cck_crc32_error; 228 u32 cnt_cck_crc32_ok; 229 u32 cnt_ofdm_crc32_error; 230 u32 cnt_ofdm_crc32_ok; 231 u32 cnt_ht_crc32_error; 232 u32 cnt_ht_crc32_ok; 233 u32 cnt_ht_crc32_error_agg; 234 u32 cnt_ht_crc32_ok_agg; 235 u32 cnt_vht_crc32_error; 236 u32 cnt_vht_crc32_ok; 237 u32 cnt_crc32_error_all; 238 u32 cnt_crc32_ok_all; 239 u32 time_fa_all; 240 boolean cck_block_enable; 241 boolean ofdm_block_enable; 242 u32 dbg_port0; 243 boolean edcca_flag; 244 u8 ofdm2_rate_idx; 245 u32 cnt_ofdm2_crc32_error; 246 u32 cnt_ofdm2_crc32_ok; 247 u8 ofdm2_pcr; 248 u8 ht2_rate_idx; 249 u32 cnt_ht2_crc32_error; 250 u32 cnt_ht2_crc32_ok; 251 u8 ht2_pcr; 252 u8 vht2_rate_idx; 253 u32 cnt_vht2_crc32_error; 254 u32 cnt_vht2_crc32_ok; 255 u8 vht2_pcr; 256 257 }; 258 259 #ifdef PHYDM_TDMA_DIG_SUPPORT 260 struct phydm_fa_acc_struct { 261 u32 cnt_parity_fail; 262 u32 cnt_rate_illegal; 263 u32 cnt_crc8_fail; 264 u32 cnt_mcs_fail; 265 u32 cnt_ofdm_fail; 266 u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/ 267 u32 cnt_cck_fail; 268 u32 cnt_all; 269 u32 cnt_all_pre; 270 u32 cnt_fast_fsync; 271 u32 cnt_sb_search_fail; 272 u32 cnt_ofdm_cca; 273 u32 cnt_cck_cca; 274 u32 cnt_cca_all; 275 u32 cnt_cck_crc32_error; 276 u32 cnt_cck_crc32_ok; 277 u32 cnt_ofdm_crc32_error; 278 u32 cnt_ofdm_crc32_ok; 279 u32 cnt_ht_crc32_error; 280 u32 cnt_ht_crc32_ok; 281 u32 cnt_vht_crc32_error; 282 u32 cnt_vht_crc32_ok; 283 u32 cnt_crc32_error_all; 284 u32 cnt_crc32_ok_all; 285 u32 cnt_all_1sec; 286 u32 cnt_cca_all_1sec; 287 u32 cnt_cck_fail_1sec; 288 }; 289 290 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 291 292 /*@--------------------Function declaration-----------------------------*/ 293 void phydm_write_dig_reg(void *dm_void, u8 igi); 294 295 void odm_write_dig(void *dm_void, u8 current_igi); 296 297 u8 phydm_get_igi(void *dm_void, enum bb_path path); 298 299 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len); 300 301 void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type, 302 enum phydm_pause_level pause_level, u8 igi_value); 303 304 #ifdef PHYDM_HW_IGI 305 void phydm_hwigi(void *dm_void); 306 307 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used, 308 char *output, u32 *_out_len); 309 #endif 310 311 void phydm_dig_init(void *dm_void); 312 313 void phydm_dig(void *dm_void); 314 315 void phydm_dig_lps_32k(void *dm_void); 316 317 void phydm_dig_by_rssi_lps(void *dm_void); 318 319 void phydm_false_alarm_counter_statistics(void *dm_void); 320 321 u32 phydm_get_edcca_report(void * dm_void); 322 323 #ifdef PHYDM_TDMA_DIG_SUPPORT 324 void phydm_set_tdma_dig_timer(void *dm_void); 325 326 void phydm_tdma_dig_timer_check(void *dm_void); 327 328 void phydm_tdma_dig(void *dm_void); 329 330 void phydm_tdma_false_alarm_counter_check(void *dm_void); 331 332 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void); 333 334 void phydm_false_alarm_counter_reset(void *dm_void); 335 336 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en); 337 338 void phydm_false_alarm_counter_acc_reset(void *dm_void); 339 340 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input); 341 342 #ifdef IS_USE_NEW_TDMA 343 void phydm_tdma_dig_timers(void *dm_void, u8 state); 344 345 void phydm_tdma_dig_cbk(void *dm_void); 346 347 void phydm_tdma_dig_workitem_callback(void *dm_void); 348 349 void phydm_tdma_fa_cnt_chk(void *dm_void); 350 351 void phydm_tdma_low_dig(void *dm_void); 352 353 void phydm_tdma_high_dig(void *dm_void); 354 355 void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en, 356 u8 cur_tdma_dig_state); 357 #endif /*@#ifdef IS_USE_NEW_TDMA*/ 358 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 359 360 void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel); 361 362 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, 363 u32 *_out_len); 364 365 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable, 366 u8 *para4, u8 *para8); 367 368 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used, 369 char *output, u32 *_out_len); 370 371 #ifdef CONFIG_MCC_DM 372 void phydm_mcc_igi_cal(void *dm_void); 373 #endif 374 375 #endif 376