1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef CFG_DIG_DAMPING_CHK
phydm_dig_recorder_reset(void * dm_void)34 void phydm_dig_recorder_reset(void *dm_void)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
38 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
39
40 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
41
42 odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
43 sizeof(struct phydm_dig_recorder_strcut));
44 }
45
phydm_dig_recorder(void * dm_void,u8 igi_curr,u32 fa_cnt)46 void phydm_dig_recorder(void *dm_void, u8 igi_curr,
47 u32 fa_cnt)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
51 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
52 u8 igi_pre = dig_rc->igi_history[0];
53 u8 igi_up = 0;
54
55 if (!dm->is_linked)
56 return;
57
58 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
59
60 if (dm->first_connect) {
61 phydm_dig_recorder_reset(dm);
62 dig_rc->igi_history[0] = igi_curr;
63 dig_rc->fa_history[0] = fa_cnt;
64 return;
65 }
66
67 if (igi_curr % 2)
68 igi_curr--;
69
70 igi_pre = dig_rc->igi_history[0];
71 igi_up = (igi_curr > igi_pre) ? 1 : 0;
72 dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
73
74 dig_rc->igi_history[3] = dig_rc->igi_history[2];
75 dig_rc->igi_history[2] = dig_rc->igi_history[1];
76 dig_rc->igi_history[1] = dig_rc->igi_history[0];
77 dig_rc->igi_history[0] = igi_curr;
78
79 dig_rc->fa_history[3] = dig_rc->fa_history[2];
80 dig_rc->fa_history[2] = dig_rc->fa_history[1];
81 dig_rc->fa_history[1] = dig_rc->fa_history[0];
82 dig_rc->fa_history[0] = fa_cnt;
83
84 PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
85 dig_rc->igi_history[3], dig_rc->igi_history[2],
86 dig_rc->igi_history[1], dig_rc->igi_history[0]);
87 PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
88 dig_rc->fa_history[3], dig_rc->fa_history[2],
89 dig_rc->fa_history[1], dig_rc->fa_history[0]);
90 PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
91 (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
92 (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
93 (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
94 (u8)(dig_rc->igi_bitmap & BIT(0)),
95 dig_rc->igi_bitmap);
96 }
97
phydm_dig_damping_chk(void * dm_void)98 void phydm_dig_damping_chk(void *dm_void)
99 {
100 struct dm_struct *dm = (struct dm_struct *)dm_void;
101 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
102 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
103 u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
104 u8 diff1 = 0, diff2 = 0;
105 u32 fa_low_th = dig_t->fa_th[0];
106 u32 fa_high_th = dig_t->fa_th[1];
107 u32 fa_high_th2 = dig_t->fa_th[2];
108 u8 fa_pattern_match = 0;
109 u32 time_tmp = 0;
110
111 if (!dm->is_linked)
112 return;
113
114 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
115
116 /*@== Release Damping ================================================*/
117 if (dig_rc->damping_limit_en) {
118 PHYDM_DBG(dm, DBG_DIG,
119 "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
120 dig_rc->limit_time, dm->phydm_sys_up_time);
121
122 time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
123
124 if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
125 time_tmp < dm->phydm_sys_up_time) {
126 dig_rc->damping_limit_en = 0;
127 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
128 dm->rssi_min, dig_rc->limit_rssi);
129 }
130 return;
131 }
132
133 /*@== Damping Pattern Check===========================================*/
134 PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
135
136 switch (igi_bitmap_4bit) {
137 case 0x5:
138 /*@ 4b'0101
139 * IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)
140 * FA: [3] >high1 ->[2] <low ->[1] >high1 ->[0] <low ->[new] <low
141 *
142 * IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
143 * FA: [3] >high2 ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
144 */
145 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
146 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
147
148 if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
149 diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
150
151 if (dig_rc->fa_history[0] < fa_low_th &&
152 dig_rc->fa_history[1] > fa_high_th &&
153 dig_rc->fa_history[2] < fa_low_th &&
154 dig_rc->fa_history[3] > fa_high_th) {
155 /*@Check each fa element*/
156 fa_pattern_match = 1;
157 }
158 break;
159 case 0x9:
160 /*@ 4b'1001
161 * IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
162 * FA: [3] <low ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
163 */
164 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
165 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
166
167 if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
168 diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
169
170 if (dig_rc->fa_history[0] < fa_low_th &&
171 dig_rc->fa_history[1] > fa_high_th2 &&
172 dig_rc->fa_history[2] < fa_low_th &&
173 dig_rc->fa_history[3] < fa_low_th) {
174 /*@Check each fa element*/
175 fa_pattern_match = 1;
176 }
177 break;
178 default:
179 break;
180 }
181
182 if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
183 dig_rc->damping_limit_en = 1;
184 dig_rc->damping_limit_val = dig_rc->igi_history[0];
185 dig_rc->limit_time = dm->phydm_sys_up_time;
186 dig_rc->limit_rssi = dm->rssi_min;
187
188 PHYDM_DBG(dm, DBG_DIG,
189 "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
190 dig_rc->damping_limit_val,
191 dig_rc->limit_time, dig_rc->limit_rssi);
192 }
193
194 PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
195 }
196 #endif
197
phydm_fa_threshold_check(void * dm_void,boolean is_dfs_band)198 void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
199 {
200 struct dm_struct *dm = (struct dm_struct *)dm_void;
201 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
202
203 if (dig_t->is_dbg_fa_th) {
204 PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
205 } else if (dm->is_linked) {
206 if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
207 dig_t->fa_th[0] = 500;
208 dig_t->fa_th[1] = 750;
209 dig_t->fa_th[2] = 1000;
210 } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
211 (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
212 dig_t->fa_th[0] = 125;
213 dig_t->fa_th[1] = 250;
214 dig_t->fa_th[2] = 500;
215 } else {
216 dig_t->fa_th[0] = 250;
217 dig_t->fa_th[1] = 500;
218 dig_t->fa_th[2] = 750;
219 }
220 } else {
221 if (is_dfs_band) { /* @For DFS band and no link */
222
223 dig_t->fa_th[0] = 250;
224 dig_t->fa_th[1] = 1000;
225 dig_t->fa_th[2] = 2000;
226 } else {
227 dig_t->fa_th[0] = 2000;
228 dig_t->fa_th[1] = 4000;
229 dig_t->fa_th[2] = 5000;
230 }
231 }
232
233 PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
234 dig_t->fa_th[1], dig_t->fa_th[2]);
235 }
236
phydm_set_big_jump_step(void * dm_void,u8 curr_igi)237 void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
238 {
239 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
240 struct dm_struct *dm = (struct dm_struct *)dm_void;
241 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
242 u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
243 u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
244 u8 i;
245
246 if (dig_t->enable_adjust_big_jump == 0)
247 return;
248
249 for (i = 0; i <= dig_t->big_jump_step1; i++) {
250 if ((curr_igi + step1[i]) > big_jump_lmt) {
251 if (i != 0)
252 i = i - 1;
253 break;
254 } else if (i == dig_t->big_jump_step1) {
255 break;
256 }
257 }
258 if (dm->support_ic_type & ODM_RTL8822B)
259 odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
260 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
261 odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
262
263 PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
264 dig_t->big_jump_step1, big_jump_lmt);
265 #endif
266 }
267
268 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_write_dig_reg_jgr3(void * dm_void,u8 igi)269 void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
270 {
271 struct dm_struct *dm = (struct dm_struct *)dm_void;
272 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
273
274 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
275
276 /* Set IGI value */
277 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
278 return;
279
280 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
281
282 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
283 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
284 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
285 #endif
286
287 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
288 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
289 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
290 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
291 }
292 #endif
293 }
294
phydm_get_igi_reg_val_jgr3(void * dm_void,enum bb_path path)295 u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
296 {
297 struct dm_struct *dm = (struct dm_struct *)dm_void;
298 u32 val = 0;
299
300 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
301
302 /* Set IGI value */
303 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
304 return (u8)val;
305
306 if (path == BB_PATH_A)
307 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
308 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
309 else if (path == BB_PATH_B)
310 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
311 #endif
312
313 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
314 else if (path == BB_PATH_C)
315 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
316 #endif
317
318 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
319 else if (path == BB_PATH_D)
320 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
321 #endif
322 return (u8)val;
323 }
324
phydm_fa_cnt_statistics_jgr3(void * dm_void)325 void phydm_fa_cnt_statistics_jgr3(void *dm_void)
326 {
327 struct dm_struct *dm = (struct dm_struct *)dm_void;
328 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
329 u32 ret_value = 0;
330 u32 cck_enable = 0;
331
332 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
333 return;
334
335 ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
336 fa_t->cnt_fast_fsync = ret_value & 0xffff;
337 fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16;
338
339 ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
340 fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16;
341
342 ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
343 fa_t->cnt_rate_illegal = ret_value & 0xffff;
344 fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16;
345
346 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
347 fa_t->cnt_mcs_fail = ret_value & 0xffff;
348
349 /* read CCK CRC32 counter */
350 ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
351 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
352 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
353
354 /* read OFDM CRC32 counter */
355 ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
356 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
357 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
358
359 /* read OFDM2 CRC32 counter */
360 ret_value = odm_get_bb_reg(dm, R_0x2c1c, MASKDWORD);
361 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
362 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
363
364 /* read HT CRC32 counter */
365 ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
366 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
367 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
368
369 /* read HT2 CRC32 counter */
370 ret_value = odm_get_bb_reg(dm, R_0x2c18, MASKDWORD);
371 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
372 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
373
374 /*for VHT part */
375 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
376 ODM_RTL8814B)) {
377 /*read VHT CRC32 counter */
378 ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
379 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
380 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
381
382 /*read VHT2 CRC32 counter */
383 ret_value = odm_get_bb_reg(dm, R_0x2c54, MASKDWORD);
384 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
385 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
386
387 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
388 fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16;
389
390 ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
391 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
392 fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16;
393 } else {
394 fa_t->cnt_vht_crc32_error = 0;
395 fa_t->cnt_vht_crc32_ok = 0;
396 fa_t->cnt_vht2_crc32_error = 0;
397 fa_t->cnt_vht2_crc32_ok = 0;
398 fa_t->cnt_mcs_fail_vht = 0;
399 fa_t->cnt_crc8_fail_vhta = 0;
400 fa_t->cnt_crc8_fail_vhtb = 0;
401 }
402
403 /* @calculate OFDM FA counter instead of reading brk_cnt*/
404 fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
405 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
406 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +
407 fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta;
408
409 /* Read CCK FA counter */
410 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
411
412 /* read CCK/OFDM CCA counter */
413 ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
414 fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
415 fa_t->cnt_cck_cca = ret_value & 0xffff;
416
417 /* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */
418 cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);
419 if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
420 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
421 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
422 } else {
423 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
424 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
425 }
426 }
427
428 #endif
429
phydm_write_dig_reg_c50(void * dm_void,u8 igi)430 void phydm_write_dig_reg_c50(void *dm_void, u8 igi)
431 {
432 struct dm_struct *dm = (struct dm_struct *)dm_void;
433
434 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
435
436 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
437
438 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
439 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
440 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
441 #endif
442
443 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
444 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
445 odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
446 odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
447 }
448 #endif
449 }
450
phydm_write_dig_reg(void * dm_void,u8 igi)451 void phydm_write_dig_reg(void *dm_void, u8 igi)
452 {
453 struct dm_struct *dm = (struct dm_struct *)dm_void;
454 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
455 u8 rf_gain = 0;
456
457 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
458
459 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
460 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
461 phydm_write_dig_reg_jgr3(dm, igi);
462 else
463 #endif
464 phydm_write_dig_reg_c50(dm, igi);
465
466 #if (RTL8721D_SUPPORT)
467 if (dm->invalid_mode) {
468 if (igi <= 0x10)
469 rf_gain = 0xfa;
470 else if (igi <= 0x40)
471 rf_gain = 0xe3 + 0x20 - (igi >> 1);
472 else if (igi <= 0x50)
473 rf_gain = 0xcb - (igi >> 1);
474 else if (igi <= 0x5e)
475 rf_gain = 0x92 - (igi >> 1);
476 else if (igi <= 0x64)
477 rf_gain = 0x74 - (igi >> 1);
478 else
479 rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0;
480 odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain);
481 }
482 #endif
483
484 if (igi == dig_t->cur_ig_value)
485 dig_t->igi_trend = DIG_STABLE;
486 else if (igi > dig_t->cur_ig_value)
487 dig_t->igi_trend = DIG_INCREASING;
488 else
489 dig_t->igi_trend = DIG_DECREASING;
490
491 PHYDM_DBG(dm, DBG_DIG, "Update IGI:0x%x -> 0x%x\n",
492 dig_t->cur_ig_value, igi);
493
494 dig_t->cur_ig_value = igi;
495 }
496
odm_write_dig(void * dm_void,u8 new_igi)497 void odm_write_dig(void *dm_void, u8 new_igi)
498 {
499 struct dm_struct *dm = (struct dm_struct *)dm_void;
500 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
501 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
502
503 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
504
505 /* @1 Check IGI by upper bound */
506 if (adaptivity->igi_lmt_en &&
507 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
508 new_igi = adaptivity->adapt_igi_up;
509
510 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
511 new_igi);
512 }
513
514 #if (RTL8192F_SUPPORT)
515 if ((dm->support_ic_type & ODM_RTL8192F) &&
516 dm->cut_version == ODM_CUT_A &&
517 new_igi > 0x38) {
518 new_igi = 0x38;
519 PHYDM_DBG(dm, DBG_DIG,
520 "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
521 }
522 #endif
523
524 if (dig_t->cur_ig_value != new_igi) {
525 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
526 /* @Modify big jump step for 8822B and 8197F */
527 if (dm->support_ic_type &
528 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
529 phydm_set_big_jump_step(dm, new_igi);
530 #endif
531
532 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
533 /* Set IGI value of CCK for new CCK AGC */
534 if (dm->cck_new_agc &&
535 (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
536 odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
537 #endif
538
539 /*@Add by YuChen for USB IO too slow issue*/
540 if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
541 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
542 new_igi < dig_t->cur_ig_value) {
543 dig_t->cur_ig_value = new_igi;
544 phydm_adaptivity(dm);
545 }
546 } else {
547 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
548 new_igi > dig_t->cur_ig_value) {
549 dig_t->cur_ig_value = new_igi;
550 phydm_adaptivity(dm);
551 }
552 }
553 phydm_write_dig_reg(dm, new_igi);
554 } else {
555 dig_t->igi_trend = DIG_STABLE;
556 }
557
558 PHYDM_DBG(dm, DBG_DIG, "[%s]New_igi=((0x%x))\n\n",
559 ((dig_t->igi_trend == DIG_STABLE) ? "=" :
560 ((dig_t->igi_trend == DIG_INCREASING) ? "+" : "-")),
561 new_igi);
562 }
563
phydm_get_igi_reg_val(void * dm_void,enum bb_path path)564 u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
565 {
566 struct dm_struct *dm = (struct dm_struct *)dm_void;
567 u32 val = 0;
568 u32 bit_map = ODM_BIT(IGI, dm);
569
570 switch (path) {
571 case BB_PATH_A:
572 val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
573 break;
574 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
575 case BB_PATH_B:
576 val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
577 break;
578 #endif
579
580 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
581 case BB_PATH_C:
582 val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
583 break;
584 #endif
585
586 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
587 case BB_PATH_D:
588 val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
589 break;
590 #endif
591
592 default:
593 break;
594 }
595
596 return (u8)val;
597 }
598
phydm_get_igi(void * dm_void,enum bb_path path)599 u8 phydm_get_igi(void *dm_void, enum bb_path path)
600 {
601 struct dm_struct *dm = (struct dm_struct *)dm_void;
602 u8 val = 0;
603
604 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
605 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
606 val = phydm_get_igi_reg_val_jgr3(dm, path);
607 else
608 #endif
609 val = phydm_get_igi_reg_val(dm, path);
610
611 return val;
612 }
613
phydm_set_dig_val(void * dm_void,u32 * val_buf,u8 val_len)614 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
615 {
616 struct dm_struct *dm = (struct dm_struct *)dm_void;
617
618 if (val_len != 1) {
619 PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
620 return;
621 }
622
623 odm_write_dig(dm, (u8)(*val_buf));
624 }
625
odm_pause_dig(void * dm_void,enum phydm_pause_type type,enum phydm_pause_level lv,u8 igi_input)626 void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
627 enum phydm_pause_level lv, u8 igi_input)
628 {
629 struct dm_struct *dm = (struct dm_struct *)dm_void;
630 u8 rpt = false;
631 u32 igi = (u32)igi_input;
632
633 PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
634 lv, igi);
635
636 switch (type) {
637 case PHYDM_PAUSE:
638 case PHYDM_PAUSE_NO_SET: {
639 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
640 break;
641 }
642
643 case PHYDM_RESUME: {
644 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
645 break;
646 }
647 default:
648 PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
649 break;
650 }
651
652 PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt);
653 }
654
655 boolean
phydm_dig_abort(void * dm_void)656 phydm_dig_abort(void *dm_void)
657 {
658 struct dm_struct *dm = (struct dm_struct *)dm_void;
659 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
660 void *adapter = dm->adapter;
661 #endif
662
663 /* support_ability */
664 if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
665 (!(dm->support_ability & ODM_BB_DIG))) {
666 PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n");
667 return true;
668 }
669
670 if (dm->pause_ability & ODM_BB_DIG) {
671 PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
672 dm->pause_lv_table.lv_dig);
673 return true;
674 }
675
676 if (*dm->is_scan_in_process) {
677 PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n");
678 return true;
679 }
680
681 if (dm->dm_dig_table.fw_dig_enable) {
682 PHYDM_DBG(dm, DBG_DIG, "Return: FW DIG enable\n");
683 return true;
684 }
685
686 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
687 #if OS_WIN_FROM_WIN7(OS_VERSION)
688 if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
689 PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
690 return true;
691 }
692 #endif
693 #endif
694
695 return false;
696 }
697
698 #ifdef PHYDM_HW_IGI
699 #ifdef BB_RAM_SUPPORT
phydm_rd_hwigi_pre_setting(void * dm_void,u32 * _used,char * output,u32 * _out_len)700 void phydm_rd_hwigi_pre_setting(void *dm_void, u32 *_used, char *output,
701 u32 *_out_len)
702 {
703 struct dm_struct *dm = (struct dm_struct *)dm_void;
704 u32 used = *_used;
705 u32 out_len = *_out_len;
706 u8 igi_ofst = 0x0;
707 u32 t1, t2, t3 = 0x0;
708
709 igi_ofst = (u8)odm_get_bb_reg(dm, R_0x1e80, MASKBYTE0);
710 t1 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE1) * 400;
711 t2 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE2) * 400;
712 t3 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE3) * 400;
713
714 PDM_SNPF(out_len, used, output + used, out_len - used,
715 "igi_offset:0x%x, t1:%d(ns), t2:%d(ns), t3:%d(ns)\n",
716 igi_ofst, t1, t2, t3);
717 }
718
phydm_set_hwigi_pre_setting(void * dm_void,u8 igi_ofst,u8 t1,u8 t2,u8 t3)719 void phydm_set_hwigi_pre_setting(void *dm_void, u8 igi_ofst, u8 t1, u8 t2,
720 u8 t3)
721 {
722 struct dm_struct *dm = (struct dm_struct *)dm_void;
723 u32 reg_0x1e80 = 0;
724
725 reg_0x1e80 = igi_ofst + (t1 << 8) + (t2 << 16) + (t3 << 24);
726 odm_set_bb_reg(dm, R_0x1e80, MASKDWORD, reg_0x1e80);
727 }
728
phydm_rd_hwigi_table(void * dm_void,u8 macid,u32 * _used,char * output,u32 * _out_len)729 void phydm_rd_hwigi_table(void *dm_void, u8 macid, u32 *_used, char *output,
730 u32 *_out_len)
731 {
732 struct dm_struct *dm = (struct dm_struct *)dm_void;
733 u32 used = *_used;
734 u32 out_len = *_out_len;
735 boolean hwigi_en = false;
736 u8 hwigi = 0x0;
737 u8 hwigi_rx_offset = 0x0;
738 u32 reg_0x1e84 = 0x0;
739
740 reg_0x1e84 |= (macid & 0x3f) << 24; /*macid*/
741 reg_0x1e84 |= BIT(31); /*read_en*/
742 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
743
744 hwigi_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(15));
745 hwigi = (u8)odm_get_bb_reg(dm, R_0x2de8, 0x7f00);
746 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
747
748 PDM_SNPF(out_len, used, output + used, out_len - used,
749 "(macid:%d) hwigi_en:%d, hwigi:0x%x\n", macid, hwigi_en,
750 hwigi);
751
752 *_used = used;
753 *_out_len = out_len;
754 }
755
phydm_wt_hwigi_table(void * dm_void,u8 macid,boolean hwigi_en,u8 hwigi)756 void phydm_wt_hwigi_table(void *dm_void, u8 macid, boolean hwigi_en, u8 hwigi)
757 {
758 struct dm_struct *dm = (struct dm_struct *)dm_void;
759 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
760 u32 reg_0x1e84 = 0;
761
762 if (macid > 63)
763 macid = 63;
764
765 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
766 dm_ram_per_sta->hw_igi_en = hwigi_en;
767 dm_ram_per_sta->hw_igi = hwigi;
768
769 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
770 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
771 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
772 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
773
774 reg_0x1e84 |= (hwigi_en << 7) + (hwigi & 0x7f);
775 reg_0x1e84 |= (macid & 0x3f) << 24;/*macid*/
776 reg_0x1e84 |= BIT(30); /*write_en*/
777 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
778 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /*read_en*/
779 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /*disable rd/wt*/
780 }
781
phydm_rst_hwigi(void * dm_void)782 void phydm_rst_hwigi(void *dm_void)
783 {
784 struct dm_struct *dm = (struct dm_struct *)dm_void;
785 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
786 u32 reg_0x1e84 = 0;
787 u8 i = 0;
788
789 PHYDM_DBG(dm, DBG_DIG, "reset hwigi!\n");
790
791 for (i = 0; i < 64; i++) {
792 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
793 dm_ram_per_sta->hw_igi_en = false;
794 dm_ram_per_sta->hw_igi = 0x0;
795
796 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
797 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
798 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
799 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
800
801 reg_0x1e84 |= (i & 0x3f) << 24;
802 reg_0x1e84 |= BIT(30);
803 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
804 }
805
806 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
807 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
808 }
809
phydm_hwigi_init(void * dm_void)810 void phydm_hwigi_init(void *dm_void)
811 {
812 struct dm_struct *dm = (struct dm_struct *)dm_void;
813 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
814 u8 igi_ofst = 0x0;
815 u8 t1 = 0x0;
816 u8 t2 = 0x0;
817 u8 t3 = 0x0;
818
819 t1 = 0x55; /*34 us*/
820 t3 = 0x55; /*34 us*/
821
822 bb_ctrl->hwigi_watchdog_en = false;
823 phydm_set_hwigi_pre_setting(dm, igi_ofst, t1, t2, t3);
824 }
825
phydm_hwigi(void * dm_void)826 void phydm_hwigi(void *dm_void)
827 {
828 struct dm_struct *dm = (struct dm_struct *)dm_void;
829 struct cmn_sta_info *sta = NULL;
830 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
831 struct rssi_info *rssi = NULL;
832 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
833 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
834 u8 sta_cnt = 0;
835 u8 i = 0;
836 u8 hwigi = 0x0;
837 u8 macid = 0;
838
839 if (!(bb_ctrl->hwigi_watchdog_en)) {
840 return;
841 } else if (dm->first_disconnect) {
842 phydm_rst_hwigi(dm);
843 return;
844 }
845
846 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
847 sta = dm->phydm_sta_info[i];
848 if (is_sta_active(sta)) {
849 sta_cnt++;
850
851 if (sta->mac_id > 63)
852 macid = 63;
853 else
854 macid = sta->mac_id;
855
856 dm_ram_per_sta = &bb_ctrl->pram_sta_ctrl[macid];
857 rssi = &sta->rssi_stat;
858 PHYDM_DBG(dm, DBG_DIG,
859 "STA_id=%d, MACID=%d, RSSI=%d, hwigi_en=%d, hwigi=0x%x\n",
860 i, sta->mac_id, rssi->rssi,
861 dm_ram_per_sta->hw_igi_en,
862 dm_ram_per_sta->hw_igi);
863
864 hwigi = MAX_2((u8)(rssi->rssi + 10),
865 dig_t->cur_ig_value);
866
867 if (rssi->rssi + 10 > DIG_MAX_PERFORMANCE_MODE)
868 hwigi = DIG_MAX_PERFORMANCE_MODE;
869 else if (rssi->rssi + 10 < DIG_MIN_PERFORMANCE)
870 hwigi = DIG_MIN_PERFORMANCE;
871
872 if (dm_ram_per_sta->hw_igi == hwigi) {
873 PHYDM_DBG(dm, DBG_DIG,
874 "hwigi not change!\n");
875 return;
876 }
877
878 PHYDM_DBG(dm, DBG_DIG,
879 "hwigi update: ((0x%x)) -> ((0x%x))\n",
880 dm_ram_per_sta->hw_igi, hwigi);
881
882 phydm_wt_hwigi_table(dm, sta->mac_id, true, hwigi);
883
884 if (sta_cnt == dm->number_linked_client)
885 break;
886 }
887 }
888 }
889
phydm_hwigi_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)890 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
891 char *output, u32 *_out_len)
892 {
893 struct dm_struct *dm = (struct dm_struct *)dm_void;
894 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
895 char help[] = "-h";
896 u32 used = *_used;
897 u32 out_len = *_out_len;
898 u32 var1[7] = {0};
899 u8 i = 0;
900
901 if ((strcmp(input[1], help) == 0)) {
902 PDM_SNPF(out_len, used, output + used, out_len - used,
903 "Disable/Enable watchdog : {0/1}\n");
904 PDM_SNPF(out_len, used, output + used, out_len - used,
905 "Set hwigi pre-setting: {2} {IGI offset} {T1(after data tx)} {T2(after Rx)} {T3(after rsp tx)}\n");
906 PDM_SNPF(out_len, used, output + used, out_len - used,
907 "Set hwigi table: {3} {en} {value} {macid}\n");
908 PDM_SNPF(out_len, used, output + used, out_len - used,
909 "Read hwigi : {4} {macid(0~63), 255:all}\n");
910 PDM_SNPF(out_len, used, output + used, out_len - used,
911 "Reset all hwigi : {5}\n");
912 } else {
913 for (i = 0; i < 7; i++) {
914 if (input[i + 1])
915 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
916 &var1[i]);
917 }
918 switch (var1[0]) {
919 case 0:
920 case 1:
921 bb_ctrl->hwigi_watchdog_en = (var1[0]) ? true : false;
922 break;
923 case 2:
924 phydm_set_hwigi_pre_setting(dm, (u8)var1[1],
925 (u8)var1[2], (u8)var1[3],
926 (u8)var1[4]);
927 break;
928 case 3:
929 phydm_wt_hwigi_table(dm, (u8)var1[3], (boolean)var1[1],
930 (boolean)var1[2]);
931 break;
932 case 4:
933 phydm_rd_hwigi_pre_setting(dm, &used, output, &out_len);
934 if ((u8)var1[1] == 0xff)
935 for (i = 0; i < 64; i++)
936 phydm_rd_hwigi_table(dm, i, &used,
937 output, &out_len);
938 else
939 phydm_rd_hwigi_table(dm, (u8)var1[1], &used,
940 output, &out_len);
941 break;
942 case 5:
943 phydm_rst_hwigi(dm);
944 break;
945 }
946 }
947 *_used = used;
948 *_out_len = out_len;
949 }
950 #endif
951 #endif
952
phydm_dig_init(void * dm_void)953 void phydm_dig_init(void *dm_void)
954 {
955 struct dm_struct *dm = (struct dm_struct *)dm_void;
956 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
957 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
958 struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
959 #endif
960 u32 ret_value = 0;
961 u8 i;
962
963 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
964 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
965 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
966
967 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
968
969 dig_t->fa_th[0] = 250;
970 dig_t->fa_th[1] = 500;
971 dig_t->fa_th[2] = 750;
972 dig_t->is_dbg_fa_th = false;
973 dig_t->igi_dyn_up_hit = false;
974 dig_t->fw_dig_enable = false;
975
976 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
977 /* @For RTL8881A */
978 false_alm_cnt->cnt_ofdm_fail_pre = 0;
979 #endif
980
981 dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
982 dig_t->rx_gain_range_min = dig_t->cur_ig_value;
983
984 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
985 if (dm->support_ic_type &
986 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
987 dig_t->enable_adjust_big_jump = 1;
988
989 if (dm->support_ic_type & ODM_RTL8822B)
990 ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
991 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
992 ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
993
994 dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
995 dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
996 dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
997
998 for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
999 if (dig_t->big_jump_lmt[i] == 0)
1000 dig_t->big_jump_lmt[i] = 0x64;
1001 /* Set -10dBm as default value */
1002 }
1003 }
1004 #endif
1005
1006 #ifdef PHYDM_TDMA_DIG_SUPPORT
1007 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1008 dm->original_dig_restore = true;
1009 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
1010 dm->tdma_dig_timer_ms = DIG_TIMER_MS;
1011 #endif
1012 dig_t->tdma_force_l_igi = 0xff;
1013 dig_t->tdma_force_h_igi = 0xff;
1014 #endif
1015 #ifdef CFG_DIG_DAMPING_CHK
1016 phydm_dig_recorder_reset(dm);
1017 dig_t->dig_dl_en = 1;
1018 #endif
1019
1020 #ifdef PHYDM_HW_IGI
1021 phydm_hwigi_init(dm);
1022 #endif
1023 }
phydm_dig_abs_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1024 void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1025 {
1026 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1027 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
1028
1029 if (is_dfs_band) {
1030 if (*dm->band_width == CHANNEL_WIDTH_20){
1031 if (dm->support_ic_type &
1032 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
1033 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
1034 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
1035 else
1036 dig_t->dm_dig_min = DIG_MIN_DFS;
1037 }
1038 else
1039 dig_t->dm_dig_min = DIG_MIN_DFS;
1040 }
1041 else
1042 dig_t->dm_dig_min = DIG_MIN_DFS;
1043
1044 dig_t->dig_max_of_min = DIG_MIN_DFS;
1045 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1046 } else if (!dm->is_linked) {
1047 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
1048 dig_t->dm_dig_min = DIG_MIN_COVERAGE;
1049 } else {
1050 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
1051 /*service > 2 devices*/
1052 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1053 #if (DIG_HW == 1)
1054 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
1055 #else
1056 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
1057 #endif
1058 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
1059 /*service 1 devices*/
1060 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
1061 dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1062 /*dig_max shouldn't be too high because of adaptivity*/
1063 dig_t->dm_dig_max =
1064 MIN_2((adapt->th_l2h + 40),
1065 DIG_MAX_PERFORMANCE_MODE);
1066 else
1067 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
1068
1069 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
1070 }
1071
1072 if (dm->support_ic_type &
1073 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
1074 dig_t->dm_dig_min = 0x1c;
1075 else if (dm->support_ic_type & ODM_RTL8197F)
1076 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
1077 else
1078 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
1079 }
1080
1081 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
1082 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
1083 }
1084
phydm_dig_dym_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1085 void phydm_dig_dym_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1086 {
1087 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1088 #ifdef CFG_DIG_DAMPING_CHK
1089 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
1090 #endif
1091 u8 offset = 15, tmp_max = 0;
1092 u8 max_of_rssi_min = 0;
1093
1094 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
1095
1096 if (!dm->is_linked) {
1097 /*@if no link, always stay at lower bound*/
1098 dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
1099 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1100
1101 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
1102 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1103 return;
1104 }
1105
1106 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
1107
1108 /* @DIG lower bound */
1109 if (is_dfs_band)
1110 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1111 else if (dm->rssi_min > dig_t->dig_max_of_min)
1112 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1113 else if (dm->rssi_min < dig_t->dm_dig_min)
1114 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1115 else
1116 dig_t->rx_gain_range_min = dm->rssi_min;
1117
1118 #ifdef CFG_DIG_DAMPING_CHK
1119 /*@Limit Dyn min by damping*/
1120 if (dig_t->dig_dl_en &&
1121 dig_rc->damping_limit_en &&
1122 dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
1123 PHYDM_DBG(dm, DBG_DIG,
1124 "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
1125 dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
1126
1127 dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
1128 }
1129 #endif
1130
1131 /* @DIG upper bound */
1132 tmp_max = dig_t->rx_gain_range_min + offset;
1133 if (dig_t->rx_gain_range_min != dm->rssi_min) {
1134 max_of_rssi_min = dm->rssi_min + offset;
1135 if (tmp_max > max_of_rssi_min)
1136 tmp_max = max_of_rssi_min;
1137 }
1138
1139 if (tmp_max > dig_t->dm_dig_max)
1140 dig_t->rx_gain_range_max = dig_t->dm_dig_max;
1141 else if (tmp_max < dig_t->dm_dig_min)
1142 dig_t->rx_gain_range_max = dig_t->dm_dig_min;
1143 else
1144 dig_t->rx_gain_range_max = tmp_max;
1145
1146 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1147 /* @1 Force Lower Bound for AntDiv */
1148 if (!dm->is_one_entry_only &&
1149 (dm->support_ability & ODM_BB_ANT_DIV) &&
1150 (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
1151 dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
1152 if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
1153 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1154 else
1155 dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
1156
1157 PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
1158 dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
1159 }
1160 #endif
1161
1162 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
1163 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1164 }
1165
phydm_dig_abnormal_case(struct dm_struct * dm)1166 void phydm_dig_abnormal_case(struct dm_struct *dm)
1167 {
1168 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1169
1170 /* @Abnormal lower bound case */
1171 if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
1172 dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
1173
1174 PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
1175 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1176 }
1177
phydm_new_igi_by_fa(struct dm_struct * dm,u8 igi,u32 fa_cnt,u8 * step_size)1178 u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size)
1179 {
1180 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1181
1182 if (fa_cnt > dig_t->fa_th[2])
1183 igi = igi + step_size[0];
1184 else if (fa_cnt > dig_t->fa_th[1])
1185 igi = igi + step_size[1];
1186 else if (fa_cnt < dig_t->fa_th[0])
1187 igi = igi - step_size[2];
1188
1189 return igi;
1190 }
1191
phydm_get_new_igi(struct dm_struct * dm,u8 igi,u32 fa_cnt,boolean is_dfs_band)1192 u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
1193 boolean is_dfs_band)
1194 {
1195 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1196 u8 step[3] = {0};
1197
1198 if (dm->is_linked) {
1199 if (dm->pre_rssi_min <= dm->rssi_min) {
1200 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
1201 step[0] = 2;
1202 step[1] = 1;
1203 step[2] = 2;
1204 } else {
1205 step[0] = 4;
1206 step[1] = 2;
1207 step[2] = 2;
1208 }
1209 } else {
1210 step[0] = 2;
1211 step[1] = 1;
1212 step[2] = 2;
1213 }
1214
1215 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
1216 step[0]);
1217
1218 if (dm->first_connect) {
1219 if (is_dfs_band) {
1220 if (dm->rssi_min > DIG_MAX_DFS)
1221 igi = DIG_MAX_DFS;
1222 else
1223 igi = dm->rssi_min;
1224 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
1225 dig_t->rx_gain_range_max);
1226 } else {
1227 igi = dig_t->rx_gain_range_min;
1228 }
1229
1230 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1231 #if (RTL8812A_SUPPORT)
1232 if (dm->support_ic_type == ODM_RTL8812)
1233 odm_config_bb_with_header_file(dm,
1234 CONFIG_BB_AGC_TAB_DIFF);
1235 #endif
1236 #endif
1237 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
1238 } else if (dm->is_linked) {
1239 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
1240 /* @4 Abnormal # beacon case */
1241 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1242 if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
1243 fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
1244 dm->support_ic_type != ODM_RTL8723D &&
1245 dm->support_ic_type != ODM_RTL8822C) {
1246 dig_t->rx_gain_range_min = 0x1c;
1247 igi = dig_t->rx_gain_range_min;
1248 PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
1249 dm->phy_dbg_info.num_qry_beacon_pkt, igi);
1250 } else {
1251 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
1252 }
1253 #else
1254 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
1255 #endif
1256 } else {
1257 /* @2 Before link */
1258 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
1259
1260 if (dm->first_disconnect) {
1261 igi = dig_t->dm_dig_min;
1262 PHYDM_DBG(dm, DBG_DIG,
1263 "First disconnect:foce IGI to lower bound\n");
1264 } else {
1265 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
1266 igi, fa_cnt);
1267
1268 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
1269 }
1270 }
1271
1272 /*@Check IGI by dyn-upper/lower bound */
1273 if (igi < dig_t->rx_gain_range_min)
1274 igi = dig_t->rx_gain_range_min;
1275
1276 if (igi >= dig_t->rx_gain_range_max) {
1277 igi = dig_t->rx_gain_range_max;
1278 dig_t->igi_dyn_up_hit = true;
1279 } else {
1280 dig_t->igi_dyn_up_hit = false;
1281 }
1282 PHYDM_DBG(dm, DBG_DIG, "igi_dyn_up_hit=%d\n",
1283 dig_t->igi_dyn_up_hit);
1284
1285 PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
1286 fa_cnt, dig_t->cur_ig_value, igi);
1287
1288 return igi;
1289 }
1290
phydm_dig_dfs_mode_en(void * dm_void)1291 boolean phydm_dig_dfs_mode_en(void *dm_void)
1292 {
1293 struct dm_struct *dm = (struct dm_struct *)dm_void;
1294 boolean dfs_mode_en = false;
1295
1296 /* @Modify lower bound for DFS band */
1297 if (dm->is_dfs_band) {
1298 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1299 dfs_mode_en = true;
1300 #else
1301 if (phydm_dfs_master_enabled(dm))
1302 dfs_mode_en = true;
1303 #endif
1304 PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
1305 }
1306 return dfs_mode_en;
1307 }
1308
phydm_dig(void * dm_void)1309 void phydm_dig(void *dm_void)
1310 {
1311 struct dm_struct *dm = (struct dm_struct *)dm_void;
1312 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1313 struct phydm_fa_struct *fa = &dm->false_alm_cnt;
1314 #ifdef PHYDM_TDMA_DIG_SUPPORT
1315 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1316 #endif
1317 u8 igi = dig_t->cur_ig_value;
1318 u8 new_igi = 0x20;
1319 u32 fa_cnt = fa->cnt_all;
1320 boolean dfs_mode_en = false;
1321
1322 #ifdef PHYDM_DCC_ENHANCE
1323 if (dm->dm_dcc_info.dcc_en)
1324 fa_cnt = fa->cnt_ofdm_fail; /*OFDM FA only*/
1325 #endif
1326
1327 #ifdef PHYDM_TDMA_DIG_SUPPORT
1328 if (!(dm->original_dig_restore)) {
1329 if (dig_t->cur_ig_value_tdma == 0)
1330 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1331
1332 igi = dig_t->cur_ig_value_tdma;
1333 fa_cnt = falm_cnt_acc->cnt_all_1sec;
1334 }
1335 #endif
1336
1337 if (phydm_dig_abort(dm)) {
1338 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
1339 return;
1340 }
1341
1342 PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
1343 PHYDM_DBG(dm, DBG_DIG,
1344 "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
1345 dm->is_linked, dm->rssi_min,
1346 dm->first_connect, dm->first_disconnect);
1347
1348 PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
1349 (*dm->bb_op_mode ? "Balance" : "Performance"));
1350
1351 /*@DFS mode enable check*/
1352 dfs_mode_en = phydm_dig_dfs_mode_en(dm);
1353
1354 #ifdef CFG_DIG_DAMPING_CHK
1355 /*Record IGI History*/
1356 phydm_dig_recorder(dm, igi, fa_cnt);
1357
1358 /*@DIG Damping Check*/
1359 phydm_dig_damping_chk(dm);
1360 #endif
1361
1362 /*@Absolute Boundary Decision */
1363 phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
1364
1365 /*@Dynamic Boundary Decision*/
1366 phydm_dig_dym_boundary_decision(dm, dfs_mode_en);
1367
1368 /*@Abnormal case check*/
1369 phydm_dig_abnormal_case(dm);
1370
1371 /*@FA threshold decision */
1372 phydm_fa_threshold_check(dm, dfs_mode_en);
1373
1374 /*Select new IGI by FA */
1375 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
1376
1377 /* @1 Update status */
1378 #ifdef PHYDM_TDMA_DIG_SUPPORT
1379 if (!(dm->original_dig_restore)) {
1380 dig_t->cur_ig_value_tdma = new_igi;
1381 /*@It is possible fa_acc_1sec_tsf >= */
1382 /*@1sec while tdma_dig_state == 0*/
1383 if (dig_t->tdma_dig_state != 0)
1384 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
1385 } else
1386 #endif
1387 odm_write_dig(dm, new_igi);
1388 }
1389
phydm_dig_lps_32k(void * dm_void)1390 void phydm_dig_lps_32k(void *dm_void)
1391 {
1392 struct dm_struct *dm = (struct dm_struct *)dm_void;
1393 u8 current_igi = dm->rssi_min;
1394
1395 odm_write_dig(dm, current_igi);
1396 }
1397
phydm_dig_by_rssi_lps(void * dm_void)1398 void phydm_dig_by_rssi_lps(void *dm_void)
1399 {
1400 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1401 struct dm_struct *dm = (struct dm_struct *)dm_void;
1402 struct phydm_fa_struct *falm_cnt;
1403
1404 u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
1405 u8 current_igi = dm->rssi_min;
1406
1407 falm_cnt = &dm->false_alm_cnt;
1408 if (phydm_dig_abort(dm))
1409 return;
1410
1411 current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
1412 PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
1413
1414 /* Using FW PS mode to make IGI */
1415 /* @Adjust by FA in LPS MODE */
1416 if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
1417 current_igi = current_igi + 4;
1418 else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
1419 current_igi = current_igi + 2;
1420 else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
1421 current_igi = current_igi - 2;
1422
1423 /* @Lower bound checking */
1424
1425 /* RSSI Lower bound check */
1426 if ((dm->rssi_min - 10) > DIG_MIN_LPS)
1427 rssi_lower = (dm->rssi_min - 10);
1428 else
1429 rssi_lower = DIG_MIN_LPS;
1430
1431 /* Upper and Lower Bound checking */
1432 if (current_igi > DIG_MAX_LPS)
1433 current_igi = DIG_MAX_LPS;
1434 else if (current_igi < rssi_lower)
1435 current_igi = rssi_lower;
1436
1437 PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
1438 falm_cnt->cnt_all, dm->rssi_min, current_igi);
1439 odm_write_dig(dm, current_igi);
1440 #endif
1441 }
1442
1443 /* @3============================================================
1444 * 3 FASLE ALARM CHECK
1445 * 3============================================================
1446 */
phydm_false_alarm_counter_reg_reset(void * dm_void)1447 void phydm_false_alarm_counter_reg_reset(void *dm_void)
1448 {
1449 struct dm_struct *dm = (struct dm_struct *)dm_void;
1450 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
1451 #ifdef PHYDM_TDMA_DIG_SUPPORT
1452 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1453 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1454 #endif
1455 u32 false_alm_cnt = 0;
1456
1457 #ifdef PHYDM_TDMA_DIG_SUPPORT
1458 if (!(dm->original_dig_restore)) {
1459 if (dig_t->cur_ig_value_tdma == 0)
1460 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1461
1462 false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
1463 } else
1464 #endif
1465 {
1466 false_alm_cnt = falm_cnt->cnt_all;
1467 }
1468
1469 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1470 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1471 /* @reset CCK FA counter */
1472 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
1473 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
1474
1475 /* @reset CCK CCA counter */
1476 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
1477 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
1478
1479 /* @Disable common rx clk gating => WLANBB-1106*/
1480 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0);
1481 /* @reset OFDM CCA counter, OFDM FA counter*/
1482 phydm_reset_bb_hw_cnt(dm);
1483 /* @Enable common rx clk gating => WLANBB-1106*/
1484 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1);
1485 }
1486 #endif
1487 #if (ODM_IC_11N_SERIES_SUPPORT)
1488 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1489 /* @reset false alarm counter registers*/
1490 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
1491 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
1492 odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
1493 odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
1494
1495 /* @update ofdm counter*/
1496 /* @update page C counter*/
1497 odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
1498 /* @update page D counter*/
1499 odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
1500
1501 /* @reset CCK CCA counter*/
1502 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
1503 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
1504
1505 /* @reset CCK FA counter*/
1506 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
1507 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
1508
1509 /* @reset CRC32 counter*/
1510 odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
1511 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
1512 }
1513 #endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
1514
1515 #if (ODM_IC_11AC_SERIES_SUPPORT)
1516 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1517 #if (RTL8881A_SUPPORT)
1518 /* @Reset FA counter by enable/disable OFDM */
1519 if ((dm->support_ic_type == ODM_RTL8881A) &&
1520 false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
1521 /* reset OFDM */
1522 odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
1523 odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
1524 false_alm_cnt->cnt_ofdm_fail_pre = 0;
1525 PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
1526 }
1527 #endif /* @#if (RTL8881A_SUPPORT) */
1528
1529 /* @reset OFDM FA countner */
1530 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
1531 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
1532
1533 /* @reset CCK FA counter */
1534 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
1535 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
1536
1537 /* @reset CCA counter */
1538 phydm_reset_bb_hw_cnt(dm);
1539 }
1540 #endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
1541 }
1542
phydm_false_alarm_counter_reg_hold(void * dm_void)1543 void phydm_false_alarm_counter_reg_hold(void *dm_void)
1544 {
1545 struct dm_struct *dm = (struct dm_struct *)dm_void;
1546
1547 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1548 /* @hold cck counter */
1549 odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
1550 odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
1551 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1552 /*@hold ofdm counter*/
1553 /*@hold page C counter*/
1554 odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
1555 /*@hold page D counter*/
1556 odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
1557
1558 /*@hold cck counter*/
1559 odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
1560 odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
1561 }
1562 }
1563
1564 #if (ODM_IC_11N_SERIES_SUPPORT)
phydm_fa_cnt_statistics_n(void * dm_void)1565 void phydm_fa_cnt_statistics_n(void *dm_void)
1566 {
1567 struct dm_struct *dm = (struct dm_struct *)dm_void;
1568 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1569 u32 reg = 0;
1570
1571 if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
1572 return;
1573
1574 /* @hold ofdm & cck counter */
1575 phydm_false_alarm_counter_reg_hold(dm);
1576
1577 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
1578 fa_t->cnt_fast_fsync = (reg & 0xffff);
1579 fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
1580
1581 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
1582 fa_t->cnt_ofdm_cca = (reg & 0xffff);
1583 fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
1584
1585 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
1586 fa_t->cnt_rate_illegal = (reg & 0xffff);
1587 fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
1588
1589 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
1590 fa_t->cnt_mcs_fail = (reg & 0xffff);
1591
1592 fa_t->cnt_ofdm_fail =
1593 fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
1594 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
1595 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
1596
1597 /* read CCK CRC32 counter */
1598 fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
1599 fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
1600
1601 /* read OFDM CRC32 counter */
1602 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
1603 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1604 fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
1605
1606 /* read OFDM2 CRC32 counter */
1607 reg = odm_get_bb_reg(dm, R_0xf9c, MASKDWORD);
1608 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1609 fa_t->cnt_ofdm2_crc32_ok = reg & 0xffff;
1610
1611 /* read HT CRC32 counter */
1612 reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
1613 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1614 fa_t->cnt_ht_crc32_ok = reg & 0xffff;
1615
1616 /* read HT2 CRC32 counter */
1617 reg = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
1618 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1619 fa_t->cnt_ht2_crc32_ok = reg & 0xffff;
1620
1621 /* read VHT CRC32 counter */
1622 fa_t->cnt_vht_crc32_error = 0;
1623 fa_t->cnt_vht_crc32_ok = 0;
1624
1625 #if (RTL8723D_SUPPORT)
1626 if (dm->support_ic_type == ODM_RTL8723D) {
1627 /* read HT CRC32 agg counter */
1628 reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
1629 fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
1630 fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
1631 }
1632 #endif
1633
1634 #if (RTL8188E_SUPPORT)
1635 if (dm->support_ic_type == ODM_RTL8188E) {
1636 reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
1637 fa_t->cnt_bw_lsc = (reg & 0xffff);
1638 fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
1639 }
1640 #endif
1641
1642 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
1643 fa_t->cnt_cck_fail = reg;
1644
1645 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
1646 fa_t->cnt_cck_fail += (reg & 0xff) << 8;
1647
1648 reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
1649 fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
1650
1651 fa_t->cnt_all_pre = fa_t->cnt_all;
1652
1653 fa_t->cnt_all = fa_t->cnt_fast_fsync +
1654 fa_t->cnt_sb_search_fail +
1655 fa_t->cnt_parity_fail +
1656 fa_t->cnt_rate_illegal +
1657 fa_t->cnt_crc8_fail +
1658 fa_t->cnt_mcs_fail +
1659 fa_t->cnt_cck_fail;
1660
1661 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
1662 }
1663 #endif
1664
1665 #if (ODM_IC_11AC_SERIES_SUPPORT)
phydm_fa_cnt_statistics_ac(void * dm_void)1666 void phydm_fa_cnt_statistics_ac(void *dm_void)
1667 {
1668 struct dm_struct *dm = (struct dm_struct *)dm_void;
1669 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1670 u32 ret_value = 0;
1671 u32 cck_enable = 0;
1672
1673 if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
1674 return;
1675
1676 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
1677 fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16;
1678
1679 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
1680 fa_t->cnt_sb_search_fail = ret_value & 0xffff;
1681
1682 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
1683 fa_t->cnt_parity_fail = ret_value & 0xffff;
1684 fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16;
1685
1686 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
1687 fa_t->cnt_crc8_fail = ret_value & 0xffff;
1688 fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16;
1689
1690 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
1691 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
1692 fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16;
1693
1694 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
1695 fa_t->cnt_mcs_fail_vht = ret_value & 0xffff;
1696
1697 /* read OFDM FA counter */
1698 fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
1699
1700 /* Read CCK FA counter */
1701 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
1702
1703 /* read CCK/OFDM CCA counter */
1704 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
1705 fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
1706 fa_t->cnt_cck_cca = ret_value & 0xffff;
1707
1708 /* read CCK CRC32 counter */
1709 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
1710 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
1711 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
1712
1713 /* read OFDM CRC32 counter */
1714 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
1715 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
1716 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1717
1718 /* read OFDM2 CRC32 counter */
1719 ret_value = odm_get_bb_reg(dm, R_0xf1c, MASKDWORD);
1720 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
1721 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
1722
1723 /* read HT CRC32 counter */
1724 ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
1725 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
1726 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
1727
1728 /* read HT2 CRC32 counter */
1729 ret_value = odm_get_bb_reg(dm, R_0xf18, MASKDWORD);
1730 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
1731 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1732
1733 /* read VHT CRC32 counter */
1734 ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
1735 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
1736 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
1737
1738 /*read VHT2 CRC32 counter */
1739 ret_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
1740 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
1741 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1742
1743 #if (RTL8881A_SUPPORT)
1744 if (dm->support_ic_type == ODM_RTL8881A) {
1745 u32 tmp = 0;
1746
1747 if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
1748 tmp = fa_t->cnt_ofdm_fail_pre;
1749 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1750 fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
1751 } else {
1752 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1753 }
1754
1755 PHYDM_DBG(dm, DBG_FA_CNT,
1756 "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
1757 fa_t->cnt_ofdm_fail_pre, tmp);
1758 }
1759 #endif
1760
1761 cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1762
1763 if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
1764 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
1765 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
1766 } else {
1767 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
1768 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
1769 }
1770 }
1771 #endif
1772
phydm_get_edcca_report(void * dm_void)1773 u32 phydm_get_edcca_report(void *dm_void)
1774 {
1775 struct dm_struct *dm = (struct dm_struct *)dm_void;
1776 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1777 u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
1778 u32 val = 0;
1779
1780 if (dm->support_ic_type & ODM_RTL8723D) {
1781 val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
1782 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1783 val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
1784 } else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
1785 if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
1786 val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
1787 else
1788 val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
1789 phydm_release_bb_dbg_port(dm);
1790 }
1791
1792 return val;
1793 }
1794
phydm_get_dbg_port_info(void * dm_void)1795 void phydm_get_dbg_port_info(void *dm_void)
1796 {
1797 struct dm_struct *dm = (struct dm_struct *)dm_void;
1798 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1799
1800 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1801 fa_t->dbg_port0 = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD);
1802 } else {
1803 /*set debug port to 0x0*/
1804 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
1805 fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
1806 phydm_release_bb_dbg_port(dm);
1807 }
1808 }
1809
1810 fa_t->edcca_flag = (boolean)phydm_get_edcca_report(dm);
1811
1812 PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n",
1813 fa_t->dbg_port0, fa_t->edcca_flag);
1814 }
1815
phydm_set_crc32_cnt2_rate(void * dm_void,u8 rate_idx)1816 void phydm_set_crc32_cnt2_rate(void *dm_void, u8 rate_idx)
1817 {
1818 struct dm_struct *dm = (struct dm_struct *)dm_void;
1819 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1820 boolean is_ofdm_rate = phydm_is_ofdm_rate(dm, rate_idx);
1821 boolean is_ht_rate = phydm_is_ht_rate(dm, rate_idx);
1822 boolean is_vht_rate = phydm_is_vht_rate(dm, rate_idx);
1823 u32 reg_addr = 0x0;
1824 u32 ofdm_rate_bitmask = 0x0;
1825 u32 ht_mcs_bitmask = 0x0;
1826 u32 vht_mcs_bitmask = 0x0;
1827 u32 vht_ss_bitmask = 0x0;
1828 u8 rate = 0x0;
1829 u8 ss = 0x0;
1830
1831 if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate)
1832 PHYDM_DBG(dm, DBG_FA_CNT,
1833 "[FA CNT] rate_idx = (0x%x) is not supported !\n",
1834 rate_idx);
1835
1836 switch (dm->ic_ip_series) {
1837 case PHYDM_IC_N:
1838 reg_addr = R_0xf04;
1839 ofdm_rate_bitmask = 0x0000f000;
1840 ht_mcs_bitmask = 0x007f0000;
1841 break;
1842 case PHYDM_IC_AC:
1843 reg_addr = R_0xb04;
1844 ofdm_rate_bitmask = 0x0000f000;
1845 ht_mcs_bitmask = 0x007f0000;
1846 vht_mcs_bitmask = 0x0f000000;
1847 vht_ss_bitmask = 0x30000000;
1848 break;
1849 case PHYDM_IC_JGR3:
1850 reg_addr = R_0x1eb8;
1851 ofdm_rate_bitmask = 0x00000f00;
1852 ht_mcs_bitmask = 0x007f0000;
1853 vht_mcs_bitmask = 0x0000f000;
1854 vht_ss_bitmask = 0x000000c0;
1855 break;
1856 default:
1857 break;
1858 }
1859
1860 if (is_ofdm_rate) {
1861 rate = phydm_legacy_rate_2_spec_rate(dm, rate_idx);
1862
1863 odm_set_bb_reg(dm, reg_addr, ofdm_rate_bitmask, rate);
1864 fa_t->ofdm2_rate_idx = rate_idx;
1865 } else if (is_ht_rate) {
1866 rate = phydm_rate_2_rate_digit(dm, rate_idx);
1867
1868 odm_set_bb_reg(dm, reg_addr, ht_mcs_bitmask, rate);
1869 fa_t->ht2_rate_idx = rate_idx;
1870 } else if (is_vht_rate) {
1871 rate = phydm_rate_2_rate_digit(dm, rate_idx);
1872 ss = phydm_rate_to_num_ss(dm, rate_idx);
1873
1874 odm_set_bb_reg(dm, reg_addr, vht_mcs_bitmask, rate);
1875 odm_set_bb_reg(dm, reg_addr, vht_ss_bitmask, ss - 1);
1876 fa_t->vht2_rate_idx = rate_idx;
1877 }
1878 }
1879
phydm_false_alarm_counter_statistics(void * dm_void)1880 void phydm_false_alarm_counter_statistics(void *dm_void)
1881 {
1882 struct dm_struct *dm = (struct dm_struct *)dm_void;
1883 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1884 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
1885 u32 tmp = 0;
1886
1887 if (!(dm->support_ability & ODM_BB_FA_CNT))
1888 return;
1889
1890 PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
1891
1892 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1893 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1894 phydm_fa_cnt_statistics_jgr3(dm);
1895 #endif
1896 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1897 #if (ODM_IC_11N_SERIES_SUPPORT)
1898 phydm_fa_cnt_statistics_n(dm);
1899 #endif
1900 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1901 #if (ODM_IC_11AC_SERIES_SUPPORT)
1902 phydm_fa_cnt_statistics_ac(dm);
1903 #endif
1904 }
1905
1906 phydm_get_dbg_port_info(dm);
1907 phydm_false_alarm_counter_reg_reset(dm_void);
1908
1909 fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
1910 fa_t->cnt_sb_search_fail * 12 +
1911 fa_t->cnt_parity_fail * 28 +
1912 fa_t->cnt_rate_illegal * 28 +
1913 fa_t->cnt_crc8_fail * 20 +
1914 fa_t->cnt_crc8_fail_vhta * 28 +
1915 fa_t->cnt_mcs_fail_vht * 36 +
1916 fa_t->cnt_mcs_fail * 32 +
1917 fa_t->cnt_cck_fail * 80;
1918
1919 fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
1920 fa_t->cnt_ht_crc32_error +
1921 fa_t->cnt_ofdm_crc32_error +
1922 fa_t->cnt_cck_crc32_error;
1923
1924 fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
1925 fa_t->cnt_ht_crc32_ok +
1926 fa_t->cnt_ofdm_crc32_ok +
1927 fa_t->cnt_cck_crc32_ok;
1928
1929 PHYDM_DBG(dm, DBG_FA_CNT,
1930 "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1931 fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
1932 PHYDM_DBG(dm, DBG_FA_CNT,
1933 "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1934 fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
1935 PHYDM_DBG(dm, DBG_FA_CNT,
1936 "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
1937 fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
1938 fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
1939 PHYDM_DBG(dm, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n",
1940 fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
1941 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
1942 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
1943 PHYDM_DBG(dm, DBG_FA_CNT,
1944 "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
1945 fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
1946 fa_t->cnt_mcs_fail_vht);
1947 }
1948 #endif
1949
1950 PHYDM_DBG(dm, DBG_FA_CNT,
1951 "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
1952 fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
1953 fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
1954 fa_t->cnt_crc32_ok_all);
1955 PHYDM_DBG(dm, DBG_FA_CNT,
1956 "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
1957 fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
1958 fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
1959 fa_t->cnt_crc32_error_all);
1960
1961 if (fa_t->ofdm2_rate_idx) {
1962 tmp = fa_t->cnt_ofdm2_crc32_error + fa_t->cnt_ofdm2_crc32_ok;
1963 fa_t->ofdm2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ofdm2_crc32_ok * 100,
1964 tmp);
1965 phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, dbg_buf,
1966 PHYDM_SNPRINT_SIZE);
1967 PHYDM_DBG(dm, DBG_FA_CNT,
1968 "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
1969 dbg_buf, fa_t->cnt_ofdm2_crc32_error,
1970 fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
1971 } else {
1972 phydm_set_crc32_cnt2_rate(dm, ODM_RATE6M);
1973 }
1974
1975 if (fa_t->ht2_rate_idx) {
1976 tmp = fa_t->cnt_ht2_crc32_error + fa_t->cnt_ht2_crc32_ok;
1977 fa_t->ht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ht2_crc32_ok * 100,
1978 tmp);
1979 phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
1980 PHYDM_SNPRINT_SIZE);
1981 PHYDM_DBG(dm, DBG_FA_CNT,
1982 "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
1983 dbg_buf, fa_t->cnt_ht2_crc32_error,
1984 fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
1985 } else {
1986 phydm_set_crc32_cnt2_rate(dm, ODM_RATEMCS0);
1987 }
1988
1989 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
1990 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
1991 if (fa_t->vht2_rate_idx) {
1992 tmp = fa_t->cnt_vht2_crc32_error +
1993 fa_t->cnt_vht2_crc32_ok;
1994 fa_t->vht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_vht2_crc32_ok *
1995 100, tmp);
1996 phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
1997 dbg_buf, PHYDM_SNPRINT_SIZE);
1998 PHYDM_DBG(dm, DBG_FA_CNT,
1999 "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2000 dbg_buf, fa_t->cnt_vht2_crc32_error,
2001 fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
2002 } else {
2003 phydm_set_crc32_cnt2_rate(dm, ODM_RATEVHTSS1MCS0);
2004 }
2005 }
2006 #endif
2007 }
2008
phydm_fill_fw_dig_info(void * dm_void,boolean * enable,u8 * para4,u8 * para8)2009 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
2010 u8 *para4, u8 *para8) {
2011 struct dm_struct *dm = (struct dm_struct *)dm_void;
2012 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2013
2014 dig_t->fw_dig_enable = *enable;
2015 para8[0] = dig_t->rx_gain_range_max;
2016 para8[1] = dig_t->rx_gain_range_min;
2017 para8[2] = dm->number_linked_client;
2018 para4[0] = (u8)DIG_LPS_MODE;
2019 }
2020
phydm_crc32_cnt_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2021 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
2022 char *output, u32 *_out_len)
2023 {
2024 struct dm_struct *dm = (struct dm_struct *)dm_void;
2025 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2026 char help[] = "-h";
2027 u32 var1[10] = {0};
2028 u32 used = *_used;
2029 u32 out_len = *_out_len;
2030 u8 i = 0;
2031 u8 rate = 0x0;
2032
2033 if ((strcmp(input[1], help) == 0)) {
2034 PDM_SNPF(out_len, used, output + used, out_len - used,
2035 "[CRC32 Cnt] {rate_idx}\n");
2036 } else {
2037 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2038 rate = (u8)var1[0];
2039
2040 PDM_SNPF(out_len, used, output + used, out_len - used,
2041 "{rate}={0x%x}", rate);
2042
2043 phydm_set_crc32_cnt2_rate(dm, rate);
2044 }
2045 *_used = used;
2046 *_out_len = out_len;
2047 }
2048
2049 #ifdef PHYDM_TDMA_DIG_SUPPORT
phydm_set_tdma_dig_timer(void * dm_void)2050 void phydm_set_tdma_dig_timer(void *dm_void)
2051 {
2052 struct dm_struct *dm = (struct dm_struct *)dm_void;
2053 u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
2054 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2055 u32 timeout = 0;
2056 u32 current_time_stamp, diff_time_stamp, regb0 = 0;
2057
2058 /*some IC has no FREERUN_CUNT register, like 92E*/
2059 if (dm->support_ic_type & ODM_RTL8197F)
2060 current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
2061 else
2062 return;
2063
2064 timeout = current_time_stamp + delta_time_us;
2065
2066 diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
2067 dig_t->pre_timestamp = dig_t->cur_timestamp;
2068 dig_t->cur_timestamp = current_time_stamp;
2069
2070 /*@HIMR0, it shows HW interrupt mask*/
2071 regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
2072
2073 PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
2074 PHYDM_DBG(dm, DBG_DIG,
2075 "curr_time_stamp=%d, delta_time_us=%d\n",
2076 current_time_stamp, delta_time_us);
2077 PHYDM_DBG(dm, DBG_DIG,
2078 "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
2079 timeout, diff_time_stamp, regb0);
2080
2081 if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
2082 odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
2083 else {
2084 PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
2085 return;
2086 }
2087 }
2088
phydm_tdma_dig_timer_check(void * dm_void)2089 void phydm_tdma_dig_timer_check(void *dm_void)
2090 {
2091 struct dm_struct *dm = (struct dm_struct *)dm_void;
2092 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2093
2094 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
2095 dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
2096
2097 if (dig_t->tdma_dig_cnt == 0 ||
2098 dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
2099 if (dm->support_ability & ODM_BB_DIG) {
2100 #ifdef IS_USE_NEW_TDMA
2101 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |
2102 ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |
2103 ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |
2104 ODM_RTL8723D)) {
2105 PHYDM_DBG(dm, DBG_DIG,
2106 "Check fail, Restart timer\n\n");
2107 phydm_false_alarm_counter_reset(dm);
2108 odm_set_timer(dm, &dm->tdma_dig_timer,
2109 dm->tdma_dig_timer_ms);
2110 } else {
2111 PHYDM_DBG(dm, DBG_DIG,
2112 "Not support TDMADIG, no SW timer\n");
2113 }
2114 #else
2115 /*@if interrupt mask info is got.*/
2116 /*Reg0xb0 is no longer needed*/
2117 #if 0
2118 /*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
2119 #endif
2120 PHYDM_DBG(dm, DBG_DIG,
2121 "Check fail, Mask[0]=0x%x, restart timer\n",
2122 *dm->interrupt_mask);
2123
2124 phydm_tdma_dig_add_interrupt_mask_handler(dm);
2125 phydm_enable_rx_related_interrupt_handler(dm);
2126 phydm_set_tdma_dig_timer(dm);
2127 #endif
2128 }
2129 } else {
2130 PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
2131 }
2132
2133 dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
2134 }
2135
2136 /*@different IC/team may use different timer for tdma-dig*/
phydm_tdma_dig_add_interrupt_mask_handler(void * dm_void)2137 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
2138 {
2139 struct dm_struct *dm = (struct dm_struct *)dm_void;
2140
2141 #if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
2142 if (dm->support_ic_type & ODM_RTL8197F) {
2143 /*@HAL_INT_TYPE_PSTIMEOUT2*/
2144 phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
2145 }
2146 #elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
2147 #elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
2148 #endif
2149 }
2150
2151 /* will be triggered by HW timer*/
phydm_tdma_dig(void * dm_void)2152 void phydm_tdma_dig(void *dm_void)
2153 {
2154 struct dm_struct *dm = (struct dm_struct *)dm_void;
2155 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2156 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2157 u32 reg_c50 = 0;
2158
2159 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
2160 RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)
2161 #ifdef IS_USE_NEW_TDMA
2162 if (dm->support_ic_type &
2163 (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B |
2164 ODM_RTL8192F | ODM_RTL8821C)) {
2165 PHYDM_DBG(dm, DBG_DIG, "98F/14B/12F/22B/92F/21C, new tdma\n");
2166 return;
2167 }
2168 #endif
2169 #endif
2170 reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
2171
2172 dig_t->tdma_dig_state =
2173 dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2174
2175 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
2176 dig_t->tdma_dig_state, reg_c50);
2177
2178 dig_t->tdma_dig_cnt++;
2179
2180 if (dig_t->tdma_dig_state == 1) {
2181 /* update IGI from tdma_dig_state == 0*/
2182 if (dig_t->cur_ig_value_tdma == 0)
2183 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
2184
2185 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2186 phydm_tdma_false_alarm_counter_check(dm);
2187 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
2188 dig_t->tdma_dig_state);
2189
2190 } else if (dig_t->tdma_dig_state == 0) {
2191 /* update dig_t->CurIGValue,*/
2192 /* @it may different from dig_t->cur_ig_value_tdma */
2193 /* TDMA IGI upperbond @ L-state = */
2194 /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
2195
2196 if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
2197 dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
2198 else
2199 dig_t->low_ig_value = dig_t->cur_ig_value;
2200
2201 odm_write_dig(dm, dig_t->low_ig_value);
2202 phydm_tdma_false_alarm_counter_check(dm);
2203 } else {
2204 phydm_tdma_false_alarm_counter_check(dm);
2205 }
2206 }
2207
2208 /*@============================================================*/
2209 /*@FASLE ALARM CHECK*/
2210 /*@============================================================*/
phydm_tdma_false_alarm_counter_check(void * dm_void)2211 void phydm_tdma_false_alarm_counter_check(void *dm_void)
2212 {
2213 struct dm_struct *dm = (struct dm_struct *)dm_void;
2214 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2215 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2216 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2217 boolean rssi_dump_en = 0;
2218 u32 timestamp = 0;
2219 u8 tdma_dig_state_number = 0;
2220 u32 start_th = 0;
2221
2222 if (dig_t->tdma_dig_state == 1)
2223 phydm_false_alarm_counter_reset(dm);
2224 /* Reset FalseAlarmCounterStatistics */
2225 /* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
2226 /* @fa_end_tsf = fa_start_tsf = TSF */
2227 else {
2228 phydm_false_alarm_counter_statistics(dm);
2229 if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
2230 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2231 else {
2232 PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
2233 return;
2234 }
2235 dig_t->fa_end_timestamp = timestamp;
2236 dig_t->fa_acc_1sec_timestamp +=
2237 (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
2238
2239 /*prevent dumb*/
2240 if (dm->tdma_dig_state_number == 1)
2241 dm->tdma_dig_state_number = 2;
2242
2243 tdma_dig_state_number = dm->tdma_dig_state_number;
2244 dig_t->sec_factor =
2245 tdma_dig_state_number / (tdma_dig_state_number - 1);
2246
2247 /*@1sec = 1000000us*/
2248 if (dig_t->sec_factor)
2249 start_th = (u32)(1000000 / dig_t->sec_factor);
2250
2251 if (dig_t->fa_acc_1sec_timestamp >= start_th) {
2252 rssi_dump_en = 1;
2253 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2254 PHYDM_DBG(dm, DBG_DIG,
2255 "sec_factor=%d, total FA=%d, is_linked=%d\n",
2256 dig_t->sec_factor, falm_cnt_acc->cnt_all,
2257 dm->is_linked);
2258
2259 phydm_noisy_detection(dm);
2260 #ifdef PHYDM_SUPPORT_CCKPD
2261 phydm_cck_pd_th(dm);
2262 #endif
2263 phydm_dig(dm);
2264 phydm_false_alarm_counter_acc_reset(dm);
2265
2266 /* Reset FalseAlarmCounterStatistics */
2267 /* @fa_end_tsf = fa_start_tsf = TSF, keep */
2268 /* @fa_acc_1sec_tsf = 0 */
2269 phydm_false_alarm_counter_reset(dm);
2270 } else {
2271 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2272 }
2273 }
2274 }
2275
phydm_false_alarm_counter_acc(void * dm_void,boolean rssi_dump_en)2276 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
2277 {
2278 struct dm_struct *dm = (struct dm_struct *)dm_void;
2279 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2280 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2281 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2282
2283 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
2284 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
2285 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
2286 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
2287 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
2288 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
2289 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
2290 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
2291 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
2292 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
2293 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
2294 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
2295 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
2296 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
2297 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
2298 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
2299 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
2300 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
2301 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
2302 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
2303 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
2304 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
2305
2306 if (rssi_dump_en == 1) {
2307 falm_cnt_acc->cnt_all_1sec =
2308 falm_cnt_acc->cnt_all * dig_t->sec_factor;
2309 falm_cnt_acc->cnt_cca_all_1sec =
2310 falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
2311 falm_cnt_acc->cnt_cck_fail_1sec =
2312 falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
2313 }
2314 }
2315
phydm_false_alarm_counter_acc_reset(void * dm_void)2316 void phydm_false_alarm_counter_acc_reset(void *dm_void)
2317 {
2318 struct dm_struct *dm = (struct dm_struct *)dm_void;
2319 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
2320
2321 #ifdef IS_USE_NEW_TDMA
2322 struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
2323 u32 tmp_cca_1sec = 0;
2324 u32 tmp_fa_1sec = 0;
2325
2326 /*@clear L-fa_acc struct*/
2327 falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
2328 tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
2329 tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
2330 odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
2331 falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
2332 falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
2333
2334 /*@clear H-fa_acc struct*/
2335 falm_cnt_acc = &dm->false_alm_cnt_acc;
2336 tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
2337 tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
2338 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
2339 falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
2340 falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
2341 #else
2342 falm_cnt_acc = &dm->false_alm_cnt_acc;
2343 /* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
2344 /* @do NOT need to be reset */
2345 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
2346 #endif
2347 }
2348
phydm_false_alarm_counter_reset(void * dm_void)2349 void phydm_false_alarm_counter_reset(void *dm_void)
2350 {
2351 struct dm_struct *dm = (struct dm_struct *)dm_void;
2352 struct phydm_fa_struct *falm_cnt;
2353 struct phydm_dig_struct *dig_t;
2354 u32 timestamp;
2355
2356 falm_cnt = &dm->false_alm_cnt;
2357 dig_t = &dm->dm_dig_table;
2358
2359 memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
2360 phydm_false_alarm_counter_reg_reset(dm);
2361
2362 #ifdef IS_USE_NEW_TDMA
2363 return;
2364 #endif
2365 if (dig_t->tdma_dig_state != 1)
2366 dig_t->fa_acc_1sec_timestamp = 0;
2367 else
2368 dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
2369
2370 /*REG_FREERUN_CNT*/
2371 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2372 dig_t->fa_start_timestamp = timestamp;
2373 dig_t->fa_end_timestamp = timestamp;
2374 }
2375
phydm_tdma_dig_para_upd(void * dm_void,enum upd_type type,u8 input)2376 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
2377 {
2378 struct dm_struct *dm = (struct dm_struct *)dm_void;
2379
2380 switch (type) {
2381 case ENABLE_TDMA:
2382 dm->original_dig_restore = !((boolean)input);
2383 break;
2384 case MODE_DECISION:
2385 if (input == (u8)MODE_PERFORMANCE)
2386 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;
2387 else if (input == (u8)MODE_COVERAGE)
2388 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2389 else
2390 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2391 break;
2392 }
2393 }
2394
2395 #ifdef IS_USE_NEW_TDMA
2396 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
pre_phydm_tdma_dig_cbk(unsigned long task_dm)2397 static void pre_phydm_tdma_dig_cbk(unsigned long task_dm)
2398 {
2399 struct dm_struct *dm = (struct dm_struct *)task_dm;
2400 struct rtl8192cd_priv *priv = dm->priv;
2401 struct priv_shared_info *pshare = priv->pshare;
2402
2403 if (!(priv->drv_state & DRV_STATE_OPEN))
2404 return;
2405
2406 if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
2407 printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
2408 __FUNCTION__, pshare->bDriverStopped,
2409 pshare->bSurpriseRemoved);
2410 return;
2411 }
2412
2413 rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event,
2414 ENQUEUE_TO_TAIL);
2415 }
2416
phydm_tdma_dig_timers_usb(void * dm_void,u8 state)2417 void phydm_tdma_dig_timers_usb(void *dm_void, u8 state)
2418 {
2419 struct dm_struct *dm = (struct dm_struct *)dm_void;
2420 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2421
2422 if (state == INIT_TDMA_DIG_TIMMER) {
2423 struct rtl8192cd_priv *priv = dm->priv;
2424
2425 init_timer(&dm->tdma_dig_timer);
2426 dm->tdma_dig_timer.data = (unsigned long)dm;
2427 dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk;
2428 INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event,
2429 phydm_tdma_dig_cbk,
2430 (unsigned long)dm);
2431 } else if (state == CANCEL_TDMA_DIG_TIMMER) {
2432 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2433 } else if (state == RELEASE_TDMA_DIG_TIMMER) {
2434 odm_release_timer(dm, &dm->tdma_dig_timer);
2435 }
2436 }
2437 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2438
phydm_tdma_dig_timers(void * dm_void,u8 state)2439 void phydm_tdma_dig_timers(void *dm_void, u8 state)
2440 {
2441 struct dm_struct *dm = (struct dm_struct *)dm_void;
2442 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2443 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
2444 struct rtl8192cd_priv *priv = dm->priv;
2445
2446 if (priv->hci_type == RTL_HCI_USB) {
2447 phydm_tdma_dig_timers_usb(dm_void, state);
2448 return;
2449 }
2450 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2451
2452 if (state == INIT_TDMA_DIG_TIMMER)
2453 odm_initialize_timer(dm, &dm->tdma_dig_timer,
2454 (void *)phydm_tdma_dig_cbk,
2455 NULL, "phydm_tdma_dig_timer");
2456 else if (state == CANCEL_TDMA_DIG_TIMMER)
2457 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2458 else if (state == RELEASE_TDMA_DIG_TIMMER)
2459 odm_release_timer(dm, &dm->tdma_dig_timer);
2460 }
2461
get_new_igi_bound(struct dm_struct * dm,u8 igi,u32 fa_cnt,u8 * rx_gain_max,u8 * rx_gain_min,boolean is_dfs_band)2462 u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
2463 u8 *rx_gain_min, boolean is_dfs_band)
2464 {
2465 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2466 u8 step[3] = {0};
2467 u8 cur_igi = igi;
2468
2469 if (dm->is_linked) {
2470 if (dm->pre_rssi_min <= dm->rssi_min) {
2471 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
2472 step[0] = 2;
2473 step[1] = 1;
2474 step[2] = 2;
2475 } else {
2476 step[0] = 4;
2477 step[1] = 2;
2478 step[2] = 2;
2479 }
2480 } else {
2481 step[0] = 2;
2482 step[1] = 1;
2483 step[2] = 2;
2484 }
2485
2486 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
2487 step[0]);
2488
2489 if (dm->first_connect) {
2490 if (is_dfs_band) {
2491 if (dm->rssi_min > DIG_MAX_DFS)
2492 igi = DIG_MAX_DFS;
2493 else
2494 igi = dm->rssi_min;
2495 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
2496 *rx_gain_max);
2497 } else {
2498 igi = *rx_gain_min;
2499 }
2500
2501 #if 0
2502 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2503 #if (RTL8812A_SUPPORT)
2504 if (dm->support_ic_type == ODM_RTL8812)
2505 odm_config_bb_with_header_file(dm,
2506 CONFIG_BB_AGC_TAB_DIFF);
2507 #endif
2508 #endif
2509 #endif
2510 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
2511 } else {
2512 /* @2 Before link */
2513 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
2514
2515 if (dm->first_disconnect) {
2516 igi = dig_t->dm_dig_min;
2517 PHYDM_DBG(dm, DBG_DIG,
2518 "First disconnect:foce IGI to lower bound\n");
2519 } else {
2520 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
2521 igi, fa_cnt);
2522
2523 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
2524 }
2525 }
2526 /*@Check IGI by dyn-upper/lower bound */
2527 if (igi < *rx_gain_min)
2528 igi = *rx_gain_min;
2529
2530 if (igi > *rx_gain_max)
2531 igi = *rx_gain_max;
2532
2533 PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
2534 fa_cnt, cur_igi, igi);
2535
2536 return igi;
2537 }
2538
phydm_write_tdma_dig(void * dm_void,u8 new_igi)2539 void phydm_write_tdma_dig(void *dm_void, u8 new_igi)
2540 {
2541 struct dm_struct *dm = (struct dm_struct *)dm_void;
2542 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2543 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
2544
2545 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
2546 #if 0
2547 /* @1 Check IGI by upper bound */
2548 if (adaptivity->igi_lmt_en &&
2549 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
2550 new_igi = adaptivity->adapt_igi_up;
2551
2552 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
2553 new_igi);
2554 }
2555 #endif
2556 phydm_write_dig_reg(dm, new_igi);
2557
2558 PHYDM_DBG(dm, DBG_DIG, "New %s-IGI=((0x%x))\n",
2559 (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) ? "L" : "H",
2560 new_igi);
2561 }
2562
phydm_tdma_dig_new(void * dm_void)2563 void phydm_tdma_dig_new(void *dm_void)
2564 {
2565 struct dm_struct *dm = (struct dm_struct *)dm_void;
2566 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2567
2568 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2569 return;
2570 /*@
2571 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2572 * dig_t->tdma_dig_state);
2573 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2574 * dig_t->cur_ig_value_tdma,
2575 * dig_t->low_ig_value);
2576 */
2577 phydm_tdma_fa_cnt_chk(dm);
2578
2579 /*@prevent dumb*/
2580 if (dm->tdma_dig_state_number < 2)
2581 dm->tdma_dig_state_number = 2;
2582
2583 /*@update state*/
2584 dig_t->tdma_dig_cnt++;
2585 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2586
2587 /*@
2588 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2589 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2590 */
2591
2592 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2593 odm_write_dig(dm, dig_t->low_ig_value);
2594 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2595 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2596
2597 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2598 }
2599
2600 /*@callback function triggered by SW timer*/
2601 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_tdma_dig_cbk(struct phydm_timer_list * timer)2602 void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
2603 {
2604 void *adapter = (void *)timer->Adapter;
2605 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2606 struct dm_struct *dm = &hal_data->DM_OutSrcs;
2607
2608 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
2609 #if USE_WORKITEM
2610 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2611 #else
2612 phydm_tdma_dig_new(dm);
2613 #endif
2614 #else
2615 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2616 #endif
2617 }
2618
phydm_tdma_dig_workitem_callback(void * context)2619 void phydm_tdma_dig_workitem_callback(void *context)
2620 {
2621 void *adapter = (void *)context;
2622 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2623 struct dm_struct *dm = &hal_data->DM_OutSrc;
2624
2625 phydm_tdma_dig_new(dm);
2626 }
2627
2628 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_tdma_dig_cbk(void * dm_void)2629 void phydm_tdma_dig_cbk(void *dm_void)
2630 {
2631 struct dm_struct *dm = (struct dm_struct *)dm_void;
2632 void *padapter = dm->adapter;
2633
2634 if (dm->support_interface == ODM_ITRF_PCIE)
2635 phydm_tdma_dig_workitem_callback(dm);
2636 /* @Can't do I/O in timer callback*/
2637 else
2638 phydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback,
2639 dm);
2640 }
2641
phydm_tdma_dig_workitem_callback(void * dm_void)2642 void phydm_tdma_dig_workitem_callback(void *dm_void)
2643 {
2644 struct dm_struct *dm = (struct dm_struct *)dm_void;
2645 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2646
2647 if (phydm_dig_abort(dm) || (dm->original_dig_restore))
2648 return;
2649 /*@
2650 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2651 * dig_t->tdma_dig_state);
2652 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2653 * dig_t->cur_ig_value_tdma,
2654 * dig_t->low_ig_value);
2655 */
2656 phydm_tdma_fa_cnt_chk(dm);
2657
2658 /*@prevent dumb*/
2659 if (dm->tdma_dig_state_number < 2)
2660 dm->tdma_dig_state_number = 2;
2661
2662 /*@update state*/
2663 dig_t->tdma_dig_cnt++;
2664 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2665
2666 /*@
2667 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2668 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2669 */
2670
2671 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2672 odm_write_dig(dm, dig_t->low_ig_value);
2673 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2674 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2675
2676 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2677 }
2678 #else
phydm_tdma_dig_cbk(void * dm_void)2679 void phydm_tdma_dig_cbk(void *dm_void)
2680 {
2681 struct dm_struct *dm = (struct dm_struct *)dm_void;
2682 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2683
2684 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2685 return;
2686 /*@
2687 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2688 * dig_t->tdma_dig_state);
2689 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2690 * dig_t->cur_ig_value_tdma,
2691 * dig_t->low_ig_value);
2692 */
2693 phydm_tdma_fa_cnt_chk(dm);
2694
2695 /*@prevent dumb*/
2696 if (dm->tdma_dig_state_number < 2)
2697 dm->tdma_dig_state_number = 2;
2698
2699 /*@update state*/
2700 dig_t->tdma_dig_cnt++;
2701 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2702
2703 /*@
2704 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2705 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2706 */
2707
2708 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2709 phydm_write_tdma_dig(dm, dig_t->low_ig_value);
2710 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2711 phydm_write_tdma_dig(dm, dig_t->cur_ig_value_tdma);
2712
2713 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2714 }
2715 #endif
2716 /*@============================================================*/
2717 /*@FASLE ALARM CHECK*/
2718 /*@============================================================*/
phydm_tdma_fa_cnt_chk(void * dm_void)2719 void phydm_tdma_fa_cnt_chk(void *dm_void)
2720 {
2721 struct dm_struct *dm = (struct dm_struct *)dm_void;
2722 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2723 struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;
2724 struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;
2725 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2726 boolean tdma_dig_block_1sec_flag = false;
2727 u32 timestamp = 0;
2728 u8 states_per_block = dm->tdma_dig_state_number;
2729 u8 cur_tdma_dig_state = 0;
2730 u32 start_th = 0;
2731 u8 state_diff = 0;
2732 u32 tdma_dig_block_period_ms = 0;
2733 u32 tdma_dig_block_cnt_thd = 0;
2734 u32 timestamp_diff = 0;
2735
2736 /*@calculate duration of a tdma block*/
2737 tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
2738
2739 /*@
2740 *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
2741 *or FA will be fewer.
2742 */
2743 tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
2744
2745 /*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
2746 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2747 cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
2748 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2749 cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
2750 /*@
2751 *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
2752 * cur_tdma_dig_state, dig_t->tdma_dig_cnt);
2753 */
2754 if (cur_tdma_dig_state == 0) {
2755 /*@L-state indicates next block*/
2756 dig_t->tdma_dig_block_cnt++;
2757
2758 /*@1sec dump check*/
2759 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2760 tdma_dig_block_1sec_flag = true;
2761
2762 /*@
2763 *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
2764 * dig_t->tdma_dig_block_cnt);
2765 */
2766
2767 /*@collect FA till this block end*/
2768 phydm_false_alarm_counter_statistics(dm);
2769 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
2770 cur_tdma_dig_state);
2771 /*@1s L-FA collect end*/
2772
2773 /*@1sec dump reached*/
2774 if (tdma_dig_block_1sec_flag) {
2775 /*@L-DIG*/
2776 phydm_noisy_detection(dm);
2777 #ifdef PHYDM_SUPPORT_CCKPD
2778 phydm_cck_pd_th(dm);
2779 #endif
2780 PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
2781 phydm_tdma_low_dig(dm);
2782 PHYDM_DBG(dm, DBG_DIG, "\n\n");
2783 }
2784 } else if (cur_tdma_dig_state == 1) {
2785 /*@1sec dump check*/
2786 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2787 tdma_dig_block_1sec_flag = true;
2788
2789 /*@
2790 *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
2791 * dig_t->tdma_dig_block_cnt);
2792 */
2793
2794 /*@collect FA till this block end*/
2795 phydm_false_alarm_counter_statistics(dm);
2796 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
2797 cur_tdma_dig_state);
2798 /*@1s H-FA collect end*/
2799
2800 /*@1sec dump reached*/
2801 state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
2802 if (tdma_dig_block_1sec_flag && state_diff == 1) {
2803 /*@H-DIG*/
2804 phydm_noisy_detection(dm);
2805 #ifdef PHYDM_SUPPORT_CCKPD
2806 phydm_cck_pd_th(dm);
2807 #endif
2808 PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
2809 phydm_tdma_high_dig(dm);
2810 PHYDM_DBG(dm, DBG_DIG, "\n\n");
2811 PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
2812 dm->is_linked);
2813 PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
2814 fa_t_acc_low->cnt_cca_all_1sec,
2815 fa_t_acc_low->cnt_all_1sec);
2816 PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
2817 fa_t_acc->cnt_cca_all_1sec,
2818 fa_t_acc->cnt_all_1sec);
2819 PHYDM_DBG(dm, DBG_DIG,
2820 "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
2821 fa_t_acc->cnt_cca_all +
2822 fa_t_acc_low->cnt_cca_all,
2823 fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
2824
2825 /*@Reset AccFalseAlarmCounterStatistics */
2826 phydm_false_alarm_counter_acc_reset(dm);
2827 dig_t->tdma_dig_block_cnt = 0;
2828 }
2829 }
2830 /*@Reset FalseAlarmCounterStatistics */
2831 phydm_false_alarm_counter_reset(dm);
2832 }
2833
phydm_tdma_low_dig(void * dm_void)2834 void phydm_tdma_low_dig(void *dm_void)
2835 {
2836 struct dm_struct *dm = (struct dm_struct *)dm_void;
2837 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2838 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2839 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
2840 #ifdef CFG_DIG_DAMPING_CHK
2841 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
2842 #endif
2843 u8 igi = dig_t->cur_ig_value;
2844 u8 new_igi = 0x20;
2845 u8 tdma_l_igi = dig_t->low_ig_value;
2846 u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
2847 u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
2848 u32 fa_cnt = falm_cnt->cnt_all;
2849 boolean dfs_mode_en = false, is_performance = true;
2850 u8 rssi_min = dm->rssi_min;
2851 u8 igi_upper_rssi_min = 0;
2852 u8 offset = 15;
2853
2854 if (!(dm->original_dig_restore)) {
2855 if (tdma_l_igi == 0)
2856 tdma_l_igi = igi;
2857
2858 fa_cnt = falm_cnt_acc->cnt_all_1sec;
2859 }
2860
2861 if (phydm_dig_abort(dm)) {
2862 dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
2863 return;
2864 }
2865
2866 /*@Mode Decision*/
2867 dfs_mode_en = false;
2868 is_performance = true;
2869
2870 /* @Abs Boundary Decision*/
2871 dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
2872 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
2873 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
2874
2875 if (dm->is_dfs_band) {
2876 if (*dm->band_width == CHANNEL_WIDTH_20){
2877 if (dm->support_ic_type &
2878 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
2879 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
2880 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
2881 else
2882 dig_t->dm_dig_min = DIG_MIN_DFS;
2883 }
2884 else
2885 dig_t->dm_dig_min = DIG_MIN_DFS;
2886 }
2887 else
2888 dig_t->dm_dig_min = DIG_MIN_DFS;
2889
2890 } else {
2891 #if 0
2892 if (dm->support_ic_type &
2893 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
2894 dig_t->dm_dig_min = 0x1c;
2895 else if (dm->support_ic_type & ODM_RTL8197F)
2896 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
2897 #endif
2898 }
2899
2900 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
2901 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
2902
2903 /* @Dyn Boundary by RSSI*/
2904 if (!dm->is_linked) {
2905 /*@if no link, always stay at lower bound*/
2906 tdma_l_dym_max = 0x26;
2907 tdma_l_dym_min = dig_t->dm_dig_min;
2908
2909 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
2910 tdma_l_dym_max, tdma_l_dym_min);
2911 } else {
2912 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
2913 dm->rssi_min, offset);
2914
2915 /* @DIG lower bound in L-state*/
2916 tdma_l_dym_min = dig_t->dm_dig_min;
2917 if (dm->is_dfs_band)
2918 tdma_l_dym_min = DIG_MIN_DFS;
2919 /*@
2920 *#ifdef CFG_DIG_DAMPING_CHK
2921 *@Limit Dyn min by damping
2922 *if (dig_t->dig_dl_en &&
2923 * dig_rc->damping_limit_en &&
2924 * tdma_l_dym_min < dig_rc->damping_limit_val) {
2925 * PHYDM_DBG(dm, DBG_DIG,
2926 * "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
2927 * tdma_l_dym_min, dig_rc->damping_limit_val);
2928 *
2929 * tdma_l_dym_min = dig_rc->damping_limit_val;
2930 *}
2931 *#endif
2932 */
2933
2934 /*@DIG upper bound in L-state*/
2935 igi_upper_rssi_min = rssi_min + offset;
2936 if (igi_upper_rssi_min > dig_t->dm_dig_max)
2937 tdma_l_dym_max = dig_t->dm_dig_max;
2938 else if (igi_upper_rssi_min < dig_t->dm_dig_min)
2939 tdma_l_dym_max = dig_t->dm_dig_min;
2940 else
2941 tdma_l_dym_max = igi_upper_rssi_min;
2942
2943 /* @1 Force Lower Bound for AntDiv */
2944 /*@
2945 *if (!dm->is_one_entry_only &&
2946 *(dm->support_ability & ODM_BB_ANT_DIV) &&
2947 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
2948 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
2949 *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
2950 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
2951 *else
2952 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
2953 *
2954 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
2955 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
2956 *}
2957 */
2958
2959 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
2960 tdma_l_dym_max, tdma_l_dym_min);
2961 }
2962
2963 /*@Abnormal Case Check*/
2964 /*@Abnormal lower bound case*/
2965 if (tdma_l_dym_min > tdma_l_dym_max)
2966 tdma_l_dym_min = tdma_l_dym_max;
2967
2968 PHYDM_DBG(dm, DBG_DIG,
2969 "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
2970 tdma_l_dym_max, tdma_l_dym_min);
2971
2972 /*@False Alarm Threshold Decision*/
2973 phydm_fa_threshold_check(dm, dfs_mode_en);
2974
2975 /*@Adjust Initial Gain by False Alarm*/
2976 /*Select new IGI by FA */
2977 if (!(dm->original_dig_restore)) {
2978 tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
2979 &tdma_l_dym_max,
2980 &tdma_l_dym_min,
2981 dfs_mode_en);
2982 } else {
2983 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
2984 }
2985
2986 /*Update status*/
2987 if (!(dm->original_dig_restore)) {
2988 if (dig_t->tdma_force_l_igi == 0xff)
2989 dig_t->low_ig_value = tdma_l_igi;
2990 else
2991 dig_t->low_ig_value = dig_t->tdma_force_l_igi;
2992 dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
2993 dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
2994 #if 0
2995 /*odm_write_dig(dm, tdma_l_igi);*/
2996 #endif
2997 } else {
2998 odm_write_dig(dm, new_igi);
2999 }
3000 }
3001
phydm_tdma_high_dig(void * dm_void)3002 void phydm_tdma_high_dig(void *dm_void)
3003 {
3004 struct dm_struct *dm = (struct dm_struct *)dm_void;
3005 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3006 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3007 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
3008 #ifdef CFG_DIG_DAMPING_CHK
3009 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
3010 #endif
3011 u8 igi = dig_t->cur_ig_value;
3012 u8 new_igi = 0x20;
3013 u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
3014 u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
3015 u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
3016 u32 fa_cnt = falm_cnt->cnt_all;
3017 boolean dfs_mode_en = false, is_performance = true;
3018 u8 rssi_min = dm->rssi_min;
3019 u8 igi_upper_rssi_min = 0;
3020 u8 offset = 15;
3021
3022 if (!(dm->original_dig_restore)) {
3023 if (tdma_h_igi == 0)
3024 tdma_h_igi = igi;
3025
3026 fa_cnt = falm_cnt_acc->cnt_all_1sec;
3027 }
3028
3029 if (phydm_dig_abort(dm)) {
3030 dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
3031 return;
3032 }
3033
3034 /*@Mode Decision*/
3035 dfs_mode_en = false;
3036 is_performance = true;
3037
3038 /*@Abs Boundary Decision*/
3039 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
3040
3041 if (!dm->is_linked) {
3042 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
3043 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
3044 } else if (dm->is_dfs_band) {
3045 if (*dm->band_width == CHANNEL_WIDTH_20){
3046 if (dm->support_ic_type &
3047 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
3048 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
3049 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
3050 else
3051 dig_t->dm_dig_min = DIG_MIN_DFS;
3052 }
3053 else
3054 dig_t->dm_dig_min = DIG_MIN_DFS;
3055 }
3056 else
3057 dig_t->dm_dig_min = DIG_MIN_DFS;
3058
3059 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3060 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3061 } else {
3062 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
3063 /*service > 2 devices*/
3064 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3065 #if (DIG_HW == 1)
3066 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
3067 #else
3068 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3069 #endif
3070 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
3071 /*service 1 devices*/
3072 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
3073 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
3074 }
3075
3076 #if 0
3077 if (dm->support_ic_type &
3078 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
3079 dig_t->dm_dig_min = 0x1c;
3080 else if (dm->support_ic_type & ODM_RTL8197F)
3081 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
3082 else
3083 #endif
3084 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
3085 }
3086 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
3087 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
3088
3089 /*@Dyn Boundary by RSSI*/
3090 if (!dm->is_linked) {
3091 /*@if no link, always stay at lower bound*/
3092 tdma_h_dym_max = dig_t->dig_max_of_min;
3093 tdma_h_dym_min = dig_t->dm_dig_min;
3094
3095 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
3096 tdma_h_dym_max, tdma_h_dym_min);
3097 } else {
3098 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
3099 dm->rssi_min, offset);
3100
3101 /* @DIG lower bound in H-state*/
3102 if (dm->is_dfs_band)
3103 tdma_h_dym_min = DIG_MIN_DFS;
3104 else if (rssi_min < dig_t->dm_dig_min)
3105 tdma_h_dym_min = dig_t->dm_dig_min;
3106 else
3107 tdma_h_dym_min = rssi_min; // turbo not considered yet
3108
3109 #ifdef CFG_DIG_DAMPING_CHK
3110 /*@Limit Dyn min by damping*/
3111 if (dig_t->dig_dl_en &&
3112 dig_rc->damping_limit_en &&
3113 tdma_h_dym_min < dig_rc->damping_limit_val) {
3114 PHYDM_DBG(dm, DBG_DIG,
3115 "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
3116 tdma_h_dym_min, dig_rc->damping_limit_val);
3117
3118 tdma_h_dym_min = dig_rc->damping_limit_val;
3119 }
3120 #endif
3121
3122 /*@DIG upper bound in H-state*/
3123 igi_upper_rssi_min = rssi_min + offset;
3124 if (igi_upper_rssi_min > dig_t->dm_dig_max)
3125 tdma_h_dym_max = dig_t->dm_dig_max;
3126 else
3127 tdma_h_dym_max = igi_upper_rssi_min;
3128
3129 /* @1 Force Lower Bound for AntDiv */
3130 /*@
3131 *if (!dm->is_one_entry_only &&
3132 *(dm->support_ability & ODM_BB_ANT_DIV) &&
3133 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
3134 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
3135 * if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
3136 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
3137 * else
3138 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
3139 */
3140 /*@
3141 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
3142 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
3143 *}
3144 */
3145 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
3146 tdma_h_dym_max, tdma_h_dym_min);
3147 }
3148
3149 /*@Abnormal Case Check*/
3150 /*@Abnormal low higher bound case*/
3151 if (tdma_h_dym_max < dig_t->dm_dig_min)
3152 tdma_h_dym_max = dig_t->dm_dig_min;
3153 /*@Abnormal lower bound case*/
3154 if (tdma_h_dym_min > tdma_h_dym_max)
3155 tdma_h_dym_min = tdma_h_dym_max;
3156
3157 PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
3158 tdma_h_dym_max, tdma_h_dym_min);
3159
3160 /*@False Alarm Threshold Decision*/
3161 phydm_fa_threshold_check(dm, dfs_mode_en);
3162
3163 /*@Adjust Initial Gain by False Alarm*/
3164 /*Select new IGI by FA */
3165 if (!(dm->original_dig_restore)) {
3166 tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
3167 &tdma_h_dym_max,
3168 &tdma_h_dym_min,
3169 dfs_mode_en);
3170 } else {
3171 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
3172 }
3173
3174 /*Update status*/
3175 if (!(dm->original_dig_restore)) {
3176 if (dig_t->tdma_force_h_igi == 0xff)
3177 dig_t->cur_ig_value_tdma = tdma_h_igi;
3178 else
3179 dig_t->cur_ig_value_tdma = dig_t->tdma_force_h_igi;
3180 dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
3181 dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
3182 #if 0
3183 /*odm_write_dig(dm, tdma_h_igi);*/
3184 #endif
3185 } else {
3186 odm_write_dig(dm, new_igi);
3187 }
3188 }
3189
phydm_fa_cnt_acc(void * dm_void,boolean tdma_dig_block_1sec_flag,u8 cur_tdma_dig_state)3190 void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag,
3191 u8 cur_tdma_dig_state)
3192 {
3193 struct dm_struct *dm = (struct dm_struct *)dm_void;
3194 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3195 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
3196 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3197 u8 factor_num = 0;
3198 u8 factor_denum = 1;
3199 u8 total_state_number = 0;
3200
3201 if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
3202 falm_cnt_acc = &dm->false_alm_cnt_acc_low;
3203 else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
3204
3205 falm_cnt_acc = &dm->false_alm_cnt_acc;
3206 /*@
3207 *PHYDM_DBG(dm, DBG_DIG,
3208 * "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
3209 * cur_tdma_dig_state, tdma_dig_block_1sec_flag);
3210 */
3211 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
3212 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
3213 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
3214 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
3215 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
3216 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
3217 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
3218 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
3219 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
3220 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
3221 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
3222 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
3223 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
3224 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
3225 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
3226 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
3227 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
3228 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
3229 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
3230 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
3231 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
3232 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
3233
3234 /*@
3235 *PHYDM_DBG(dm, DBG_DIG,
3236 * "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3237 * falm_cnt->cnt_cck_cca,
3238 * falm_cnt->cnt_ofdm_cca,
3239 * falm_cnt->cnt_cca_all);
3240 *PHYDM_DBG(dm, DBG_DIG,
3241 * "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3242 * falm_cnt->cnt_cck_fail,
3243 * falm_cnt->cnt_ofdm_fail,
3244 * falm_cnt->cnt_all);
3245 */
3246 if (tdma_dig_block_1sec_flag) {
3247 total_state_number = dm->tdma_dig_state_number;
3248
3249 if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
3250 factor_num = total_state_number;
3251 factor_denum = total_state_number - 1;
3252 } else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
3253 factor_num = total_state_number;
3254 factor_denum = 1;
3255 }
3256
3257 falm_cnt_acc->cnt_all_1sec =
3258 falm_cnt_acc->cnt_all * factor_num / factor_denum;
3259 falm_cnt_acc->cnt_cca_all_1sec =
3260 falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
3261 falm_cnt_acc->cnt_cck_fail_1sec =
3262 falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
3263
3264 PHYDM_DBG(dm, DBG_DIG,
3265 "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3266 falm_cnt_acc->cnt_cck_cca,
3267 falm_cnt_acc->cnt_ofdm_cca,
3268 falm_cnt_acc->cnt_cca_all);
3269 PHYDM_DBG(dm, DBG_DIG,
3270 "[ACC FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
3271 falm_cnt_acc->cnt_cck_fail,
3272 falm_cnt_acc->cnt_ofdm_fail,
3273 falm_cnt_acc->cnt_all);
3274
3275 }
3276 }
3277 #endif /*@#ifdef IS_USE_NEW_TDMA*/
3278 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
3279
phydm_dig_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3280 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
3281 u32 *_out_len)
3282 {
3283 struct dm_struct *dm = (struct dm_struct *)dm_void;
3284 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3285 char help[] = "-h";
3286 u32 var1[10] = {0};
3287 u32 used = *_used;
3288 u32 out_len = *_out_len;
3289 u8 i = 0;
3290
3291 if ((strcmp(input[1], help) == 0)) {
3292 PDM_SNPF(out_len, used, output + used, out_len - used,
3293 "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
3294 PDM_SNPF(out_len, used, output + used, out_len - used,
3295 "{1} {Damping Limit en}\n");
3296 #ifdef PHYDM_TDMA_DIG_SUPPORT
3297 PDM_SNPF(out_len, used, output + used, out_len - used,
3298 "{2} {original_dig_restore = %d}\n",
3299 dm->original_dig_restore);
3300 PDM_SNPF(out_len, used, output + used, out_len - used,
3301 "{3} {tdma_dig_timer_ms = %d}\n",
3302 dm->tdma_dig_timer_ms);
3303 PDM_SNPF(out_len, used, output + used, out_len - used,
3304 "{4} {tdma_dig_state_number = %d}\n",
3305 dm->tdma_dig_state_number);
3306 PDM_SNPF(out_len, used, output + used, out_len - used,
3307 "{5} {0:L-state,1:H-state} {force IGI} (L,H)=(%2x,%2x)\n",
3308 dig_t->tdma_force_l_igi, dig_t->tdma_force_h_igi);
3309 #endif
3310 PDM_SNPF(out_len, used, output + used, out_len - used,
3311 "{6} {fw_dig_en}\n");
3312 } else {
3313 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
3314
3315 for (i = 1; i < 10; i++)
3316 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
3317
3318 if (var1[0] == 0) {
3319 if (var1[1] == 1) {
3320 dig_t->is_dbg_fa_th = true;
3321 dig_t->fa_th[0] = (u16)var1[2];
3322 dig_t->fa_th[1] = (u16)var1[3];
3323 dig_t->fa_th[2] = (u16)var1[4];
3324
3325 PDM_SNPF(out_len, used, output + used,
3326 out_len - used,
3327 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
3328 dig_t->fa_th[0], dig_t->fa_th[1],
3329 dig_t->fa_th[2]);
3330 } else {
3331 dig_t->is_dbg_fa_th = false;
3332 }
3333 #ifdef PHYDM_TDMA_DIG_SUPPORT
3334 } else if (var1[0] == 2) {
3335 dm->original_dig_restore = (u8)var1[1];
3336 if (dm->original_dig_restore == 1) {
3337 PDM_SNPF(out_len, used, output + used,
3338 out_len - used, "Disable TDMA-DIG\n");
3339 } else {
3340 PDM_SNPF(out_len, used, output + used,
3341 out_len - used, "Enable TDMA-DIG\n");
3342 }
3343 } else if (var1[0] == 3) {
3344 dm->tdma_dig_timer_ms = (u8)var1[1];
3345 PDM_SNPF(out_len, used, output + used,
3346 out_len - used, "tdma_dig_timer_ms = %d\n",
3347 dm->tdma_dig_timer_ms);
3348 } else if (var1[0] == 4) {
3349 dm->tdma_dig_state_number = (u8)var1[1];
3350 PDM_SNPF(out_len, used, output + used,
3351 out_len - used, "tdma_dig_state_number = %d\n",
3352 dm->tdma_dig_state_number);
3353 } else if (var1[0] == 5) {
3354 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
3355 if (var1[1] == 0) {
3356 dig_t->tdma_force_l_igi = (u8)var1[2];
3357 PDM_SNPF(out_len, used, output + used,
3358 out_len - used,
3359 "force L-state IGI = %2x\n",
3360 dig_t->tdma_force_l_igi);
3361 } else if (var1[1] == 1) {
3362 dig_t->tdma_force_h_igi = (u8)var1[2];
3363 PDM_SNPF(out_len, used, output + used,
3364 out_len - used,
3365 "force H-state IGI = %2x\n",
3366 dig_t->tdma_force_h_igi);
3367 }
3368 #endif
3369 }
3370
3371 #ifdef CFG_DIG_DAMPING_CHK
3372 else if (var1[0] == 1) {
3373 dig_t->dig_dl_en = (u8)var1[1];
3374 /*@*/
3375 }
3376 #endif
3377 else if (var1[0] == 6) {
3378 phydm_fw_dm_ctrl_en(dm, F00_DIG, (boolean)var1[1]);
3379 PDM_SNPF(out_len, used, output + used, out_len - used,
3380 "fw_dig_enable = %2x\n", dig_t->fw_dig_enable);
3381 }
3382 }
3383 *_used = used;
3384 *_out_len = out_len;
3385 }
3386
3387 #ifdef CONFIG_MCC_DM
3388 #if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
phydm_mcc_igi_clr(void * dm_void,u8 clr_port)3389 void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
3390 {
3391 struct dm_struct *dm = (struct dm_struct *)dm_void;
3392 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3393
3394 mcc_dm->mcc_rssi[clr_port] = 0xff;
3395 mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
3396 mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
3397 }
3398
phydm_mcc_igi_chk(void * dm_void)3399 void phydm_mcc_igi_chk(void *dm_void)
3400 {
3401 struct dm_struct *dm = (struct dm_struct *)dm_void;
3402 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3403
3404 if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
3405 mcc_dm->mcc_dm_val[0][1] == 0xff) {
3406 mcc_dm->mcc_dm_reg[0] = 0xffff;
3407 mcc_dm->mcc_reg_id[0] = 0xff;
3408 }
3409 if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
3410 mcc_dm->mcc_dm_val[1][1] == 0xff) {
3411 mcc_dm->mcc_dm_reg[1] = 0xffff;
3412 mcc_dm->mcc_reg_id[1] = 0xff;
3413 }
3414 }
3415
phydm_mcc_igi_cal(void * dm_void)3416 void phydm_mcc_igi_cal(void *dm_void)
3417 {
3418 struct dm_struct *dm = (struct dm_struct *)dm_void;
3419 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3420 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3421 u8 shift = 0;
3422 u8 igi_val0, igi_val1;
3423
3424 if (mcc_dm->mcc_rssi[0] == 0xff)
3425 phydm_mcc_igi_clr(dm, 0);
3426 if (mcc_dm->mcc_rssi[1] == 0xff)
3427 phydm_mcc_igi_clr(dm, 1);
3428 phydm_mcc_igi_chk(dm);
3429 igi_val0 = mcc_dm->mcc_rssi[0] - shift;
3430 igi_val1 = mcc_dm->mcc_rssi[1] - shift;
3431
3432 if (igi_val0 < DIG_MIN_PERFORMANCE)
3433 igi_val0 = DIG_MIN_PERFORMANCE;
3434
3435 if (igi_val1 < DIG_MIN_PERFORMANCE)
3436 igi_val1 = DIG_MIN_PERFORMANCE;
3437
3438 switch (dm->ic_ip_series) {
3439 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
3440 case PHYDM_IC_JGR3:
3441 phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);
3442 phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);
3443 break;
3444 #endif
3445 default:
3446 phydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1);
3447 phydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1);
3448 break;
3449 }
3450
3451 PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
3452 mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
3453 mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
3454 }
3455 #endif /*#if (RTL8822B_SUPPORT)*/
3456 #endif /*#ifdef CONFIG_MCC_DM*/
3457