1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 const u16 phy_rate_table[] = {
34 /*@20M*/
35 1, 2, 5, 11,
36 6, 9, 12, 18, 24, 36, 48, 54,
37 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
38 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
39 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
40 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
41 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
42 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
43 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
44 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
45 };
46
phydm_traffic_load_decision(void * dm_void)47 void phydm_traffic_load_decision(void *dm_void)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 u8 shift = 0;
51
52 /*@---TP & Trafic-load calculation---*/
53
54 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
55 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
56
57 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
58 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
59
60 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
61 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
62 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
63 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
64
65 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
66 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
67 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
68
69 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
70 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
71
72 dm->total_tp = dm->tx_tp + dm->rx_tp;
73
74 /*@[Calculate TX/RX state]*/
75 if (dm->tx_tp > (dm->rx_tp << 1))
76 dm->txrx_state_all = TX_STATE;
77 else if (dm->rx_tp > (dm->tx_tp << 1))
78 dm->txrx_state_all = RX_STATE;
79 else
80 dm->txrx_state_all = BI_DIRECTION_STATE;
81
82 /*@[Traffic load decision]*/
83 dm->pre_traffic_load = dm->traffic_load;
84
85 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
86 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
87 dm->traffic_load = TRAFFIC_HIGH;
88 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
89 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
90 dm->traffic_load = TRAFFIC_MID;
91 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
92 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
93 dm->traffic_load = TRAFFIC_LOW;
94 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
95 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
96 dm->traffic_load = TRAFFIC_ULTRA_LOW;
97 } else {
98 dm->traffic_load = TRAFFIC_NO_TP;
99 }
100
101 /*@[Calculate consecutive idlel time]*/
102 if (dm->traffic_load == 0)
103 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
104 else
105 dm->consecutive_idlel_time = 0;
106
107 #if 0
108 PHYDM_DBG(dm, DBG_COMMON_FLOW,
109 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
110 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
111 dm->last_rx_ok_cnt);
112
113 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
114 dm->rx_tp);
115 #endif
116 }
117
phydm_cck_new_agc_chk(struct dm_struct * dm)118 void phydm_cck_new_agc_chk(struct dm_struct *dm)
119 {
120 u32 new_agc_addr = 0x0;
121
122 dm->cck_new_agc = false;
123 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
124 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
125 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
126 RTL8721D_SUPPORT || RTL8710C_SUPPORT)
127 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
128 ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
129 ODM_RTL8721D | ODM_RTL8710C)) {
130 new_agc_addr = R_0xa9c;
131 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
132 ODM_RTL8814B | ODM_RTL8197G)) {
133 new_agc_addr = R_0x1a9c;
134 }
135
136 /*@1: new agc 0: old agc*/
137 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
138 #endif
139 }
140
141 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)142 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
143 {
144 boolean report_type = 0;
145 #if (RTL8192E_SUPPORT)
146 u32 value_824, value_82c;
147 #endif
148
149 #if (RTL8192E_SUPPORT)
150 if (dm->support_ic_type & (ODM_RTL8192E)) {
151 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
152 * should be equal or CCK RSSI report may be incorrect
153 */
154 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
155 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
156
157 if (value_824 != value_82c)
158 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
159 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
160 report_type = (boolean)value_824;
161 }
162 #endif
163
164 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
165 if (dm->support_ic_type &
166 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
167 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
168
169 if (report_type != 1)
170 pr_debug("[Warning] CCK should be 4bit LNA\n");
171 }
172 #endif
173
174 #if (RTL8821C_SUPPORT)
175 if (dm->support_ic_type & ODM_RTL8821C) {
176 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
177 report_type = 1;
178 }
179 #endif
180
181 dm->cck_agc_report_type = report_type;
182
183 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
184 dm->cck_agc_report_type);
185 }
186
phydm_init_cck_setting(struct dm_struct * dm)187 void phydm_init_cck_setting(struct dm_struct *dm)
188 {
189 u32 reg_tmp = 0;
190 u32 mask_tmp = 0;
191
192 phydm_cck_new_agc_chk(dm);
193
194 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
195 return;
196
197 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
198 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
199 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
200
201 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
202
203 phydm_config_cck_rx_antenna_init(dm);
204
205 if (dm->support_ic_type & ODM_RTL8192F)
206 phydm_config_cck_rx_path(dm, BB_PATH_AB);
207 else if (dm->valid_path_set == BB_PATH_A)
208 phydm_config_cck_rx_path(dm, BB_PATH_A);
209 else if (dm->valid_path_set == BB_PATH_B)
210 phydm_config_cck_rx_path(dm, BB_PATH_B);
211
212 phydm_cck_lna_bit_num_chk(dm);
213 phydm_get_cck_rssi_table_from_reg(dm);
214 }
215
216 #ifdef CONFIG_RFE_BY_HW_INFO
phydm_init_hw_info_by_rfe(struct dm_struct * dm)217 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
218 {
219 #if (RTL8821C_SUPPORT)
220 if (dm->support_ic_type & ODM_RTL8821C)
221 phydm_init_hw_info_by_rfe_type_8821c(dm);
222 #endif
223 #if (RTL8197F_SUPPORT)
224 if (dm->support_ic_type & ODM_RTL8197F)
225 phydm_init_hw_info_by_rfe_type_8197f(dm);
226 #endif
227 #if (RTL8197G_SUPPORT)
228 if (dm->support_ic_type & ODM_RTL8197G)
229 phydm_init_hw_info_by_rfe_type_8197g(dm);
230 #endif
231 }
232 #endif
233
phydm_common_info_self_init(struct dm_struct * dm)234 void phydm_common_info_self_init(struct dm_struct *dm)
235 {
236 u32 reg_tmp = 0;
237 u32 mask_tmp = 0;
238
239 dm->run_in_drv_fw = RUN_IN_DRIVER;
240
241 /*@BB IP Generation*/
242 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
243 dm->ic_ip_series = PHYDM_IC_JGR3;
244 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
245 dm->ic_ip_series = PHYDM_IC_AC;
246 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
247 dm->ic_ip_series = PHYDM_IC_N;
248
249 /*@BB phy-status Generation*/
250 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
251 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
252 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
253 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
254 else
255 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
256
257 phydm_init_cck_setting(dm);
258
259 reg_tmp = ODM_REG(BB_RX_PATH, dm);
260 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
261 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
262 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
263 dm->is_net_closed = &dm->BOOLEAN_temp;
264
265 phydm_init_debug_setting(dm);
266 #endif
267 phydm_init_soft_ml_setting(dm);
268
269 dm->phydm_sys_up_time = 0;
270
271 if (dm->support_ic_type & ODM_IC_1SS)
272 dm->num_rf_path = 1;
273 else if (dm->support_ic_type & ODM_IC_2SS)
274 dm->num_rf_path = 2;
275 #if 0
276 /* @RTK do not has IC which is equipped with 3 RF paths,
277 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
278 */
279 else if (dm->support_ic_type & ODM_IC_3SS)
280 dm->num_rf_path = 3;
281 #endif
282 else if (dm->support_ic_type & ODM_IC_4SS)
283 dm->num_rf_path = 4;
284 else
285 dm->num_rf_path = 1;
286
287 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
288
289 dm->tx_rate = 0xFF;
290 dm->rssi_min_by_path = 0xFF;
291
292 dm->number_linked_client = 0;
293 dm->pre_number_linked_client = 0;
294 dm->number_active_client = 0;
295 dm->pre_number_active_client = 0;
296
297 dm->last_tx_ok_cnt = 0;
298 dm->last_rx_ok_cnt = 0;
299 dm->tx_tp = 0;
300 dm->rx_tp = 0;
301 dm->total_tp = 0;
302 dm->traffic_load = TRAFFIC_LOW;
303
304 dm->nbi_set_result = 0;
305 dm->is_init_hw_info_by_rfe = false;
306 dm->pre_dbg_priority = DBGPORT_RELEASE;
307 dm->tp_active_th = 5;
308 dm->disable_phydm_watchdog = 0;
309
310 dm->u8_dummy = 0xf;
311 dm->u16_dummy = 0xffff;
312 dm->u32_dummy = 0xffffffff;
313 #if (RTL8814B_SUPPORT)
314 /*@------------For spur detection Default Mode------------@*/
315 dm->dsde_sel = DET_CSI;
316 dm->csi_wgt = 4;
317 /*@-------------------------------------------------------@*/
318 #endif
319 dm->pre_is_linked = false;
320 dm->is_linked = false;
321 /*dym bw thre and it can config by registry*/
322 if (dm->en_auto_bw_th == 0)
323 dm->en_auto_bw_th = 20;
324
325 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
326 if (!(dm->is_fcs_mode_enable)) {
327 dm->is_fcs_mode_enable = &dm->boolean_dummy;
328 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
329 }
330 #endif
331 /*init IOT table*/
332 odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
333 }
334
phydm_iot_patch_id_update(void * dm_void,u32 iot_idx,boolean en)335 void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
336 {
337 struct dm_struct *dm = (struct dm_struct *)dm_void;
338 struct phydm_iot_center *iot_table = &dm->iot_table;
339
340 PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
341 switch (iot_idx) {
342 case 0x100f0401:
343 iot_table->patch_id_100f0401 = en;
344 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
345 iot_table->patch_id_100f0401);
346 break;
347 case 0x10120200:
348 iot_table->patch_id_10120200 = en;
349 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
350 iot_table->patch_id_10120200);
351 break;
352 case 0x40010700:
353 iot_table->patch_id_40010700 = en;
354 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
355 iot_table->patch_id_40010700);
356 break;
357 case 0x021f0800:
358 iot_table->patch_id_021f0800 = en;
359 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
360 iot_table->patch_id_021f0800);
361 break;
362 default:
363 pr_debug("[%s] warning!\n", __func__);
364 break;
365 }
366 }
367
phydm_cmn_sta_info_update(void * dm_void,u8 macid)368 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
369 {
370 struct dm_struct *dm = (struct dm_struct *)dm_void;
371 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
372 struct ra_sta_info *ra = NULL;
373
374 if (is_sta_active(sta)) {
375 ra = &sta->ra_info;
376 } else {
377 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
378 __func__);
379 return;
380 }
381
382 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
383 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
384
385 /*@[Calculate TX/RX state]*/
386 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
387 ra->txrx_state = TX_STATE;
388 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
389 ra->txrx_state = RX_STATE;
390 else
391 ra->txrx_state = BI_DIRECTION_STATE;
392
393 ra->is_noisy = dm->noisy_decision;
394 }
395
phydm_common_info_self_update(struct dm_struct * dm)396 void phydm_common_info_self_update(struct dm_struct *dm)
397 {
398 u8 sta_cnt = 0, num_active_client = 0;
399 u32 i, one_entry_macid = 0;
400 u32 ma_rx_tp = 0;
401 u32 tp_diff = 0;
402 struct cmn_sta_info *sta;
403 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
404 PADAPTER adapter = (PADAPTER)dm->adapter;
405 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
406
407 sta = dm->phydm_sta_info[0];
408
409 /* STA mode is linked to AP */
410 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
411 dm->bsta_state = true;
412 else
413 dm->bsta_state = false;
414 #endif
415
416 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
417 sta = dm->phydm_sta_info[i];
418 if (is_sta_active(sta)) {
419 sta_cnt++;
420
421 if (sta_cnt == 1)
422 one_entry_macid = i;
423
424 phydm_cmn_sta_info_update(dm, (u8)i);
425 #ifdef PHYDM_BEAMFORMING_SUPPORT
426 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
427 #endif
428
429 ma_rx_tp = sta->rx_moving_average_tp +
430 sta->tx_moving_average_tp;
431
432 PHYDM_DBG(dm, DBG_COMMON_FLOW,
433 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
434
435 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
436 num_active_client++;
437 }
438 }
439
440 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
441 dm->is_linked = (sta_cnt != 0) ? true : false;
442 #endif
443
444 if (sta_cnt == 1) {
445 dm->is_one_entry_only = true;
446 dm->one_entry_macid = one_entry_macid;
447 dm->one_entry_tp = ma_rx_tp;
448
449 dm->tp_active_occur = 0;
450
451 PHYDM_DBG(dm, DBG_COMMON_FLOW,
452 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
453 dm->one_entry_tp, dm->pre_one_entry_tp);
454
455 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
456 dm->pre_one_entry_tp <= 2) {
457 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
458
459 if (tp_diff > dm->tp_active_th)
460 dm->tp_active_occur = 1;
461 }
462 dm->pre_one_entry_tp = dm->one_entry_tp;
463 } else {
464 dm->is_one_entry_only = false;
465 }
466
467 dm->pre_number_linked_client = dm->number_linked_client;
468 dm->pre_number_active_client = dm->number_active_client;
469
470 dm->number_linked_client = sta_cnt;
471 dm->number_active_client = num_active_client;
472
473 /*Traffic load information update*/
474 phydm_traffic_load_decision(dm);
475
476 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
477
478 dm->is_dfs_band = phydm_is_dfs_band(dm);
479 dm->phy_dbg_info.show_phy_sts_cnt = 0;
480
481 /*[Link Status Check]*/
482 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
483 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
484 dm->pre_is_linked = dm->is_linked;
485 }
486
phydm_common_info_self_reset(struct dm_struct * dm)487 void phydm_common_info_self_reset(struct dm_struct *dm)
488 {
489 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
490
491 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
492 dbg_t->num_qry_beacon_pkt = 0;
493
494 dm->rxsc_l = 0xff;
495 dm->rxsc_20 = 0xff;
496 dm->rxsc_40 = 0xff;
497 dm->rxsc_80 = 0xff;
498 }
499
500 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)501 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
502
503 {
504 void *structure = NULL;
505
506 switch (structure_type) {
507 case PHYDM_FALSEALMCNT:
508 structure = &dm->false_alm_cnt;
509 break;
510
511 case PHYDM_CFOTRACK:
512 structure = &dm->dm_cfo_track;
513 break;
514
515 case PHYDM_ADAPTIVITY:
516 structure = &dm->adaptivity;
517 break;
518 #ifdef CONFIG_PHYDM_DFS_MASTER
519 case PHYDM_DFS:
520 structure = &dm->dfs;
521 break;
522 #endif
523 default:
524 break;
525 }
526
527 return structure;
528 }
529
phydm_phy_info_update(struct dm_struct * dm)530 void phydm_phy_info_update(struct dm_struct *dm)
531 {
532 #if (RTL8822B_SUPPORT)
533 if (dm->support_ic_type == ODM_RTL8822B)
534 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
535 #endif
536 }
537
phydm_hw_setting(struct dm_struct * dm)538 void phydm_hw_setting(struct dm_struct *dm)
539 {
540 #if (RTL8821A_SUPPORT)
541 if (dm->support_ic_type & ODM_RTL8821)
542 odm_hw_setting_8821a(dm);
543 #endif
544
545 #if (RTL8814A_SUPPORT)
546 if (dm->support_ic_type & ODM_RTL8814A)
547 phydm_hwsetting_8814a(dm);
548 #endif
549
550 #if (RTL8822B_SUPPORT)
551 if (dm->support_ic_type & ODM_RTL8822B)
552 phydm_hwsetting_8822b(dm);
553 #endif
554
555 #if (RTL8812A_SUPPORT)
556 if (dm->support_ic_type & ODM_RTL8812)
557 phydm_hwsetting_8812a(dm);
558 #endif
559
560 #if (RTL8197F_SUPPORT)
561 if (dm->support_ic_type & ODM_RTL8197F)
562 phydm_hwsetting_8197f(dm);
563 #endif
564
565 #if (RTL8192F_SUPPORT)
566 if (dm->support_ic_type & ODM_RTL8192F)
567 phydm_hwsetting_8192f(dm);
568 #endif
569
570 #if (RTL8822C_SUPPORT)
571 if (dm->support_ic_type & ODM_RTL8822C)
572 phydm_hwsetting_8822c(dm);
573 #endif
574
575 #if (RTL8197G_SUPPORT)
576 if (dm->support_ic_type & ODM_RTL8197G)
577 phydm_hwsetting_8197g(dm);
578 #endif
579
580 #if (RTL8821C_SUPPORT)
581 if (dm->support_ic_type & ODM_RTL8821C)
582 phydm_hwsetting_8821c(dm);
583 #endif
584
585 #if (RTL8812F_SUPPORT)
586 if (dm->support_ic_type & ODM_RTL8812F)
587 phydm_hwsetting_8812f(dm);
588 #endif
589
590 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
591 phydm_cck_rx_pathdiv_watchdog(dm);
592 #endif
593 }
594
595 __odm_func__
phydm_chk_bb_rf_pkg_set_valid(struct dm_struct * dm)596 boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
597 {
598 boolean valid = true;
599
600 if (dm->support_ic_type == ODM_RTL8822C) {
601 #if (RTL8822C_SUPPORT)
602 valid = phydm_chk_pkg_set_valid_8822c(dm,
603 RELEASE_VERSION_8822C,
604 RF_RELEASE_VERSION_8822C);
605 #else
606 valid = true; /*@Just for preventing compile warnings*/
607 #endif
608 #if (RTL8812F_SUPPORT)
609 } else if (dm->support_ic_type == ODM_RTL8812F) {
610 valid = phydm_chk_pkg_set_valid_8812f(dm,
611 RELEASE_VERSION_8812F,
612 RF_RELEASE_VERSION_8812F);
613 #endif
614 #if (RTL8197G_SUPPORT)
615 } else if (dm->support_ic_type == ODM_RTL8197G) {
616 valid = phydm_chk_pkg_set_valid_8197g(dm,
617 RELEASE_VERSION_8197G,
618 RF_RELEASE_VERSION_8197G);
619 #endif
620 #if (RTL8812F_SUPPORT)
621 } else if (dm->support_ic_type == ODM_RTL8812F) {
622 valid = phydm_chk_pkg_set_valid_8812f(dm,
623 RELEASE_VERSION_8812F,
624 RF_RELEASE_VERSION_8812F);
625 #endif
626 #if (RTL8198F_SUPPORT)
627 } else if (dm->support_ic_type == ODM_RTL8198F) {
628 valid = phydm_chk_pkg_set_valid_8198f(dm,
629 RELEASE_VERSION_8198F,
630 RF_RELEASE_VERSION_8198F);
631 #endif
632 #if (RTL8814B_SUPPORT)
633 } else if (dm->support_ic_type == ODM_RTL8814B) {
634 valid = phydm_chk_pkg_set_valid_8814b(dm,
635 RELEASE_VERSION_8814B,
636 RF_RELEASE_VERSION_8814B);
637 #endif
638 }
639
640 return valid;
641 }
642
643 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)644 u64 phydm_supportability_init_win(
645 void *dm_void)
646 {
647 struct dm_struct *dm = (struct dm_struct *)dm_void;
648 u64 support_ability = 0;
649
650 switch (dm->support_ic_type) {
651 /*@---------------N Series--------------------*/
652 #if (RTL8188E_SUPPORT)
653 case ODM_RTL8188E:
654 support_ability |=
655 ODM_BB_DIG |
656 ODM_BB_RA_MASK |
657 /*ODM_BB_DYNAMIC_TXPWR |*/
658 ODM_BB_FA_CNT |
659 ODM_BB_RSSI_MONITOR |
660 ODM_BB_CCK_PD |
661 /*ODM_BB_PWR_TRAIN |*/
662 ODM_BB_RATE_ADAPTIVE |
663 ODM_BB_ADAPTIVITY |
664 ODM_BB_CFO_TRACKING |
665 ODM_BB_ENV_MONITOR |
666 ODM_BB_PRIMARY_CCA;
667 break;
668 #endif
669
670 #if (RTL8192E_SUPPORT)
671 case ODM_RTL8192E:
672 support_ability |=
673 ODM_BB_DIG |
674 ODM_BB_RA_MASK |
675 /*ODM_BB_DYNAMIC_TXPWR |*/
676 ODM_BB_FA_CNT |
677 ODM_BB_RSSI_MONITOR |
678 ODM_BB_CCK_PD |
679 /*ODM_BB_PWR_TRAIN |*/
680 ODM_BB_RATE_ADAPTIVE |
681 ODM_BB_ADAPTIVITY |
682 ODM_BB_CFO_TRACKING |
683 ODM_BB_ENV_MONITOR |
684 ODM_BB_PRIMARY_CCA;
685 break;
686 #endif
687
688 #if (RTL8723B_SUPPORT)
689 case ODM_RTL8723B:
690 support_ability |=
691 ODM_BB_DIG |
692 ODM_BB_RA_MASK |
693 /*ODM_BB_DYNAMIC_TXPWR |*/
694 ODM_BB_FA_CNT |
695 ODM_BB_RSSI_MONITOR |
696 ODM_BB_CCK_PD |
697 /*ODM_BB_PWR_TRAIN |*/
698 ODM_BB_RATE_ADAPTIVE |
699 ODM_BB_ADAPTIVITY |
700 ODM_BB_CFO_TRACKING |
701 ODM_BB_ENV_MONITOR |
702 ODM_BB_PRIMARY_CCA;
703 break;
704 #endif
705
706 #if (RTL8703B_SUPPORT)
707 case ODM_RTL8703B:
708 support_ability |=
709 ODM_BB_DIG |
710 ODM_BB_RA_MASK |
711 /*ODM_BB_DYNAMIC_TXPWR |*/
712 ODM_BB_FA_CNT |
713 ODM_BB_RSSI_MONITOR |
714 ODM_BB_CCK_PD |
715 /*ODM_BB_PWR_TRAIN |*/
716 ODM_BB_RATE_ADAPTIVE |
717 ODM_BB_ADAPTIVITY |
718 ODM_BB_CFO_TRACKING |
719 ODM_BB_ENV_MONITOR;
720 break;
721 #endif
722
723 #if (RTL8723D_SUPPORT)
724 case ODM_RTL8723D:
725 support_ability |=
726 ODM_BB_DIG |
727 ODM_BB_RA_MASK |
728 /*ODM_BB_DYNAMIC_TXPWR |*/
729 ODM_BB_FA_CNT |
730 ODM_BB_RSSI_MONITOR |
731 ODM_BB_CCK_PD |
732 ODM_BB_PWR_TRAIN |
733 ODM_BB_RATE_ADAPTIVE |
734 ODM_BB_ADAPTIVITY |
735 ODM_BB_CFO_TRACKING |
736 ODM_BB_ENV_MONITOR;
737 break;
738 #endif
739
740 #if (RTL8710B_SUPPORT)
741 case ODM_RTL8710B:
742 support_ability |=
743 ODM_BB_DIG |
744 ODM_BB_RA_MASK |
745 /*ODM_BB_DYNAMIC_TXPWR |*/
746 ODM_BB_FA_CNT |
747 ODM_BB_RSSI_MONITOR |
748 ODM_BB_CCK_PD |
749 ODM_BB_PWR_TRAIN |
750 ODM_BB_RATE_ADAPTIVE |
751 ODM_BB_ADAPTIVITY |
752 ODM_BB_CFO_TRACKING |
753 ODM_BB_ENV_MONITOR;
754 break;
755 #endif
756
757 #if (RTL8188F_SUPPORT)
758 case ODM_RTL8188F:
759 support_ability |=
760 ODM_BB_DIG |
761 ODM_BB_RA_MASK |
762 /*ODM_BB_DYNAMIC_TXPWR |*/
763 ODM_BB_FA_CNT |
764 ODM_BB_RSSI_MONITOR |
765 ODM_BB_CCK_PD |
766 /*ODM_BB_PWR_TRAIN |*/
767 ODM_BB_RATE_ADAPTIVE |
768 ODM_BB_ADAPTIVITY |
769 ODM_BB_CFO_TRACKING |
770 ODM_BB_ENV_MONITOR;
771 break;
772 #endif
773
774 #if (RTL8192F_SUPPORT)
775 case ODM_RTL8192F:
776 support_ability |=
777 ODM_BB_DIG |
778 ODM_BB_RA_MASK |
779 ODM_BB_FA_CNT |
780 ODM_BB_RSSI_MONITOR |
781 ODM_BB_CCK_PD |
782 ODM_BB_PWR_TRAIN |
783 ODM_BB_RATE_ADAPTIVE |
784 /*ODM_BB_PATH_DIV |*/
785 ODM_BB_ADAPTIVITY |
786 ODM_BB_CFO_TRACKING |
787 ODM_BB_ADAPTIVE_SOML |
788 ODM_BB_ENV_MONITOR;
789 /*ODM_BB_LNA_SAT_CHK |*/
790 /*ODM_BB_PRIMARY_CCA*/
791
792 break;
793 #endif
794
795 /*@---------------AC Series-------------------*/
796
797 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
798 case ODM_RTL8812:
799 case ODM_RTL8821:
800 support_ability |=
801 ODM_BB_DIG |
802 ODM_BB_RA_MASK |
803 ODM_BB_DYNAMIC_TXPWR |
804 ODM_BB_FA_CNT |
805 ODM_BB_RSSI_MONITOR |
806 ODM_BB_CCK_PD |
807 /*ODM_BB_PWR_TRAIN |*/
808 ODM_BB_RATE_ADAPTIVE |
809 ODM_BB_ADAPTIVITY |
810 ODM_BB_CFO_TRACKING |
811 ODM_BB_ENV_MONITOR;
812 break;
813 #endif
814
815 #if (RTL8814A_SUPPORT)
816 case ODM_RTL8814A:
817 support_ability |=
818 ODM_BB_DIG |
819 ODM_BB_RA_MASK |
820 ODM_BB_DYNAMIC_TXPWR |
821 ODM_BB_FA_CNT |
822 ODM_BB_RSSI_MONITOR |
823 ODM_BB_CCK_PD |
824 /*ODM_BB_PWR_TRAIN |*/
825 ODM_BB_RATE_ADAPTIVE |
826 ODM_BB_ADAPTIVITY |
827 ODM_BB_CFO_TRACKING |
828 ODM_BB_ENV_MONITOR;
829 break;
830 #endif
831
832 #if (RTL8822B_SUPPORT)
833 case ODM_RTL8822B:
834 support_ability |=
835 ODM_BB_DIG |
836 ODM_BB_RA_MASK |
837 /*ODM_BB_DYNAMIC_TXPWR |*/
838 ODM_BB_FA_CNT |
839 ODM_BB_RSSI_MONITOR |
840 ODM_BB_CCK_PD |
841 /*ODM_BB_PWR_TRAIN |*/
842 /*ODM_BB_ADAPTIVE_SOML |*/
843 ODM_BB_RATE_ADAPTIVE |
844 /*ODM_BB_PATH_DIV |*/
845 ODM_BB_ADAPTIVITY |
846 ODM_BB_CFO_TRACKING |
847 ODM_BB_ENV_MONITOR;
848 break;
849 #endif
850
851 #if (RTL8821C_SUPPORT)
852 case ODM_RTL8821C:
853 support_ability |=
854 ODM_BB_DIG |
855 ODM_BB_RA_MASK |
856 /*ODM_BB_DYNAMIC_TXPWR |*/
857 ODM_BB_FA_CNT |
858 ODM_BB_RSSI_MONITOR |
859 ODM_BB_CCK_PD |
860 /*ODM_BB_PWR_TRAIN |*/
861 ODM_BB_RATE_ADAPTIVE |
862 ODM_BB_ADAPTIVITY |
863 ODM_BB_CFO_TRACKING |
864 ODM_BB_ENV_MONITOR;
865 break;
866 #endif
867
868 /*@---------------JGR3 Series-------------------*/
869
870 #if (RTL8822C_SUPPORT)
871 case ODM_RTL8822C:
872 support_ability |=
873 ODM_BB_DIG |
874 ODM_BB_RA_MASK |
875 ODM_BB_DYNAMIC_TXPWR |
876 ODM_BB_FA_CNT |
877 ODM_BB_RSSI_MONITOR |
878 ODM_BB_CCK_PD |
879 ODM_BB_RATE_ADAPTIVE |
880 ODM_BB_PATH_DIV |
881 ODM_BB_ADAPTIVITY |
882 ODM_BB_CFO_TRACKING |
883 ODM_BB_ENV_MONITOR;
884 break;
885 #endif
886
887 #if (RTL8814B_SUPPORT)
888 case ODM_RTL8814B:
889 support_ability |=
890 ODM_BB_DIG |
891 ODM_BB_RA_MASK |
892 /*ODM_BB_DYNAMIC_TXPWR |*/
893 ODM_BB_FA_CNT |
894 ODM_BB_RSSI_MONITOR |
895 ODM_BB_CCK_PD |
896 /*ODM_BB_PWR_TRAIN |*/
897 ODM_BB_RATE_ADAPTIVE |
898 ODM_BB_ADAPTIVITY |
899 ODM_BB_CFO_TRACKING;
900 /*ODM_BB_ENV_MONITOR;*/
901 break;
902 #endif
903
904 default:
905 support_ability |=
906 ODM_BB_DIG |
907 ODM_BB_RA_MASK |
908 /*ODM_BB_DYNAMIC_TXPWR |*/
909 ODM_BB_FA_CNT |
910 ODM_BB_RSSI_MONITOR |
911 ODM_BB_CCK_PD |
912 /*ODM_BB_PWR_TRAIN |*/
913 ODM_BB_RATE_ADAPTIVE |
914 ODM_BB_ADAPTIVITY |
915 ODM_BB_CFO_TRACKING |
916 ODM_BB_ENV_MONITOR;
917
918 pr_debug("[Warning] Supportability Init Warning !!!\n");
919 break;
920 }
921
922 return support_ability;
923 }
924 #endif
925
926 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)927 u64 phydm_supportability_init_ce(void *dm_void)
928 {
929 struct dm_struct *dm = (struct dm_struct *)dm_void;
930 u64 support_ability = 0;
931
932 switch (dm->support_ic_type) {
933 /*@---------------N Series--------------------*/
934 #if (RTL8188E_SUPPORT)
935 case ODM_RTL8188E:
936 support_ability |=
937 ODM_BB_DIG |
938 ODM_BB_RA_MASK |
939 /*@ODM_BB_DYNAMIC_TXPWR |*/
940 ODM_BB_FA_CNT |
941 ODM_BB_RSSI_MONITOR |
942 ODM_BB_CCK_PD |
943 /*@ODM_BB_PWR_TRAIN |*/
944 ODM_BB_RATE_ADAPTIVE |
945 ODM_BB_ADAPTIVITY |
946 ODM_BB_CFO_TRACKING |
947 ODM_BB_ENV_MONITOR |
948 ODM_BB_PRIMARY_CCA;
949 break;
950 #endif
951
952 #if (RTL8192E_SUPPORT)
953 case ODM_RTL8192E:
954 support_ability |=
955 ODM_BB_DIG |
956 ODM_BB_RA_MASK |
957 /*@ODM_BB_DYNAMIC_TXPWR |*/
958 ODM_BB_FA_CNT |
959 ODM_BB_RSSI_MONITOR |
960 ODM_BB_CCK_PD |
961 /*@ODM_BB_PWR_TRAIN |*/
962 ODM_BB_RATE_ADAPTIVE |
963 ODM_BB_ADAPTIVITY |
964 ODM_BB_CFO_TRACKING |
965 ODM_BB_ENV_MONITOR |
966 ODM_BB_PRIMARY_CCA;
967 break;
968 #endif
969
970 #if (RTL8723B_SUPPORT)
971 case ODM_RTL8723B:
972 support_ability |=
973 ODM_BB_DIG |
974 ODM_BB_RA_MASK |
975 /*@ODM_BB_DYNAMIC_TXPWR |*/
976 ODM_BB_FA_CNT |
977 ODM_BB_RSSI_MONITOR |
978 ODM_BB_CCK_PD |
979 /*@ODM_BB_PWR_TRAIN |*/
980 ODM_BB_RATE_ADAPTIVE |
981 ODM_BB_ADAPTIVITY |
982 ODM_BB_CFO_TRACKING |
983 ODM_BB_ENV_MONITOR |
984 ODM_BB_PRIMARY_CCA;
985 break;
986 #endif
987
988 #if (RTL8703B_SUPPORT)
989 case ODM_RTL8703B:
990 support_ability |=
991 ODM_BB_DIG |
992 ODM_BB_RA_MASK |
993 /*@ODM_BB_DYNAMIC_TXPWR |*/
994 ODM_BB_FA_CNT |
995 ODM_BB_RSSI_MONITOR |
996 ODM_BB_CCK_PD |
997 /*@ODM_BB_PWR_TRAIN |*/
998 ODM_BB_RATE_ADAPTIVE |
999 ODM_BB_ADAPTIVITY |
1000 ODM_BB_CFO_TRACKING |
1001 ODM_BB_ENV_MONITOR;
1002 break;
1003 #endif
1004
1005 #if (RTL8723D_SUPPORT)
1006 case ODM_RTL8723D:
1007 support_ability |=
1008 ODM_BB_DIG |
1009 ODM_BB_RA_MASK |
1010 /*@ODM_BB_DYNAMIC_TXPWR |*/
1011 ODM_BB_FA_CNT |
1012 ODM_BB_RSSI_MONITOR |
1013 ODM_BB_CCK_PD |
1014 ODM_BB_PWR_TRAIN |
1015 ODM_BB_RATE_ADAPTIVE |
1016 ODM_BB_ADAPTIVITY |
1017 ODM_BB_CFO_TRACKING |
1018 ODM_BB_ENV_MONITOR;
1019 break;
1020 #endif
1021
1022 #if (RTL8710B_SUPPORT)
1023 case ODM_RTL8710B:
1024 support_ability |=
1025 ODM_BB_DIG |
1026 ODM_BB_RA_MASK |
1027 /*@ODM_BB_DYNAMIC_TXPWR |*/
1028 ODM_BB_FA_CNT |
1029 ODM_BB_RSSI_MONITOR |
1030 ODM_BB_CCK_PD |
1031 /*@ODM_BB_PWR_TRAIN |*/
1032 ODM_BB_RATE_ADAPTIVE |
1033 ODM_BB_ADAPTIVITY |
1034 ODM_BB_CFO_TRACKING |
1035 ODM_BB_ENV_MONITOR;
1036 break;
1037 #endif
1038
1039 #if (RTL8188F_SUPPORT)
1040 case ODM_RTL8188F:
1041 support_ability |=
1042 ODM_BB_DIG |
1043 ODM_BB_RA_MASK |
1044 /*@ODM_BB_DYNAMIC_TXPWR |*/
1045 ODM_BB_FA_CNT |
1046 ODM_BB_RSSI_MONITOR |
1047 ODM_BB_CCK_PD |
1048 /*@ODM_BB_PWR_TRAIN |*/
1049 ODM_BB_RATE_ADAPTIVE |
1050 ODM_BB_ADAPTIVITY |
1051 ODM_BB_CFO_TRACKING |
1052 ODM_BB_ENV_MONITOR;
1053 break;
1054 #endif
1055
1056 #if (RTL8192F_SUPPORT)
1057 case ODM_RTL8192F:
1058 support_ability |=
1059 ODM_BB_DIG |
1060 ODM_BB_RA_MASK |
1061 ODM_BB_FA_CNT |
1062 ODM_BB_RSSI_MONITOR |
1063 ODM_BB_CCK_PD |
1064 ODM_BB_PWR_TRAIN |
1065 ODM_BB_RATE_ADAPTIVE |
1066 /*ODM_BB_PATH_DIV |*/
1067 ODM_BB_ADAPTIVITY |
1068 ODM_BB_CFO_TRACKING |
1069 /*@ODM_BB_ADAPTIVE_SOML |*/
1070 ODM_BB_ENV_MONITOR;
1071 /*@ODM_BB_LNA_SAT_CHK |*/
1072 /*@ODM_BB_PRIMARY_CCA*/
1073 break;
1074 #endif
1075 /*@---------------AC Series-------------------*/
1076
1077 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
1078 case ODM_RTL8812:
1079 case ODM_RTL8821:
1080 support_ability |=
1081 ODM_BB_DIG |
1082 ODM_BB_RA_MASK |
1083 /*@ODM_BB_DYNAMIC_TXPWR |*/
1084 ODM_BB_FA_CNT |
1085 ODM_BB_RSSI_MONITOR |
1086 ODM_BB_CCK_PD |
1087 /*@ODM_BB_PWR_TRAIN |*/
1088 ODM_BB_RATE_ADAPTIVE |
1089 ODM_BB_ADAPTIVITY |
1090 ODM_BB_CFO_TRACKING |
1091 ODM_BB_ENV_MONITOR;
1092 break;
1093 #endif
1094
1095 #if (RTL8814A_SUPPORT)
1096 case ODM_RTL8814A:
1097 support_ability |=
1098 ODM_BB_DIG |
1099 ODM_BB_RA_MASK |
1100 /*@ODM_BB_DYNAMIC_TXPWR |*/
1101 ODM_BB_FA_CNT |
1102 ODM_BB_RSSI_MONITOR |
1103 ODM_BB_CCK_PD |
1104 /*@ODM_BB_PWR_TRAIN |*/
1105 ODM_BB_RATE_ADAPTIVE |
1106 ODM_BB_ADAPTIVITY |
1107 ODM_BB_CFO_TRACKING |
1108 ODM_BB_ENV_MONITOR;
1109 break;
1110 #endif
1111
1112 #if (RTL8822B_SUPPORT)
1113 case ODM_RTL8822B:
1114 support_ability |=
1115 ODM_BB_DIG |
1116 ODM_BB_RA_MASK |
1117 ODM_BB_DYNAMIC_TXPWR |
1118 ODM_BB_FA_CNT |
1119 ODM_BB_RSSI_MONITOR |
1120 ODM_BB_CCK_PD |
1121 /*@ODM_BB_PWR_TRAIN |*/
1122 ODM_BB_RATE_ADAPTIVE |
1123 /*ODM_BB_PATH_DIV |*/
1124 ODM_BB_ADAPTIVITY |
1125 ODM_BB_CFO_TRACKING |
1126 ODM_BB_ENV_MONITOR;
1127 break;
1128 #endif
1129
1130 #if (RTL8821C_SUPPORT)
1131 case ODM_RTL8821C:
1132 support_ability |=
1133 ODM_BB_DIG |
1134 ODM_BB_RA_MASK |
1135 /*@ODM_BB_DYNAMIC_TXPWR |*/
1136 ODM_BB_FA_CNT |
1137 ODM_BB_RSSI_MONITOR |
1138 ODM_BB_CCK_PD |
1139 /*@ODM_BB_PWR_TRAIN |*/
1140 ODM_BB_RATE_ADAPTIVE |
1141 ODM_BB_ADAPTIVITY |
1142 ODM_BB_CFO_TRACKING |
1143 ODM_BB_ENV_MONITOR;
1144 break;
1145 #endif
1146
1147 /*@---------------JGR3 Series-------------------*/
1148
1149 #if (RTL8822C_SUPPORT)
1150 case ODM_RTL8822C:
1151 support_ability |=
1152 ODM_BB_DIG |
1153 ODM_BB_RA_MASK |
1154 ODM_BB_DYNAMIC_TXPWR |
1155 ODM_BB_FA_CNT |
1156 ODM_BB_RSSI_MONITOR |
1157 ODM_BB_CCK_PD |
1158 ODM_BB_RATE_ADAPTIVE |
1159 /* ODM_BB_PATH_DIV | */
1160 ODM_BB_ADAPTIVITY |
1161 ODM_BB_CFO_TRACKING |
1162 ODM_BB_ENV_MONITOR;
1163 break;
1164 #endif
1165
1166 #if (RTL8814B_SUPPORT)
1167 case ODM_RTL8814B:
1168 support_ability |=
1169 ODM_BB_DIG |
1170 ODM_BB_RA_MASK |
1171 /*@ODM_BB_DYNAMIC_TXPWR |*/
1172 ODM_BB_FA_CNT |
1173 ODM_BB_RSSI_MONITOR |
1174 ODM_BB_CCK_PD |
1175 /*@ODM_BB_PWR_TRAIN |*/
1176 /*ODM_BB_RATE_ADAPTIVE |*/
1177 ODM_BB_ADAPTIVITY |
1178 ODM_BB_CFO_TRACKING;
1179 /*ODM_BB_ENV_MONITOR;*/
1180 break;
1181 #endif
1182
1183 default:
1184 support_ability |=
1185 ODM_BB_DIG |
1186 ODM_BB_RA_MASK |
1187 /*@ODM_BB_DYNAMIC_TXPWR |*/
1188 ODM_BB_FA_CNT |
1189 ODM_BB_RSSI_MONITOR |
1190 ODM_BB_CCK_PD |
1191 /*@ODM_BB_PWR_TRAIN |*/
1192 ODM_BB_RATE_ADAPTIVE |
1193 ODM_BB_ADAPTIVITY |
1194 ODM_BB_CFO_TRACKING |
1195 ODM_BB_ENV_MONITOR;
1196
1197 pr_debug("[Warning] Supportability Init Warning !!!\n");
1198 break;
1199 }
1200
1201 return support_ability;
1202 }
1203 #endif
1204
1205 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1206 u64 phydm_supportability_init_ap(
1207 void *dm_void)
1208 {
1209 struct dm_struct *dm = (struct dm_struct *)dm_void;
1210 u64 support_ability = 0;
1211
1212 switch (dm->support_ic_type) {
1213 /*@---------------N Series--------------------*/
1214 #if (RTL8188E_SUPPORT)
1215 case ODM_RTL8188E:
1216 support_ability |=
1217 ODM_BB_DIG |
1218 ODM_BB_RA_MASK |
1219 ODM_BB_FA_CNT |
1220 ODM_BB_RSSI_MONITOR |
1221 ODM_BB_CCK_PD |
1222 /*ODM_BB_PWR_TRAIN |*/
1223 ODM_BB_RATE_ADAPTIVE |
1224 ODM_BB_ADAPTIVITY |
1225 ODM_BB_CFO_TRACKING |
1226 ODM_BB_ENV_MONITOR |
1227 ODM_BB_PRIMARY_CCA;
1228 break;
1229 #endif
1230
1231 #if (RTL8192E_SUPPORT)
1232 case ODM_RTL8192E:
1233 support_ability |=
1234 ODM_BB_DIG |
1235 ODM_BB_RA_MASK |
1236 ODM_BB_FA_CNT |
1237 ODM_BB_RSSI_MONITOR |
1238 ODM_BB_CCK_PD |
1239 /*ODM_BB_PWR_TRAIN |*/
1240 ODM_BB_RATE_ADAPTIVE |
1241 ODM_BB_ADAPTIVITY |
1242 ODM_BB_CFO_TRACKING |
1243 ODM_BB_ENV_MONITOR |
1244 ODM_BB_PRIMARY_CCA;
1245 break;
1246 #endif
1247
1248 #if (RTL8723B_SUPPORT)
1249 case ODM_RTL8723B:
1250 support_ability |=
1251 ODM_BB_DIG |
1252 ODM_BB_RA_MASK |
1253 ODM_BB_FA_CNT |
1254 ODM_BB_RSSI_MONITOR |
1255 ODM_BB_CCK_PD |
1256 /*ODM_BB_PWR_TRAIN |*/
1257 ODM_BB_RATE_ADAPTIVE |
1258 ODM_BB_ADAPTIVITY |
1259 ODM_BB_CFO_TRACKING |
1260 ODM_BB_ENV_MONITOR;
1261 break;
1262 #endif
1263
1264 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1265 case ODM_RTL8198F:
1266 support_ability |=
1267 ODM_BB_DIG |
1268 ODM_BB_RA_MASK |
1269 ODM_BB_FA_CNT |
1270 ODM_BB_RSSI_MONITOR |
1271 ODM_BB_CCK_PD |
1272 /*ODM_BB_PWR_TRAIN |*/
1273 /*ODM_BB_RATE_ADAPTIVE |*/
1274 ODM_BB_ADAPTIVITY |
1275 ODM_BB_CFO_TRACKING;
1276 /*ODM_BB_ADAPTIVE_SOML |*/
1277 /*ODM_BB_ENV_MONITOR |*/
1278 /*ODM_BB_LNA_SAT_CHK |*/
1279 /*ODM_BB_PRIMARY_CCA;*/
1280 break;
1281 case ODM_RTL8197F:
1282 support_ability |=
1283 ODM_BB_DIG |
1284 ODM_BB_RA_MASK |
1285 ODM_BB_FA_CNT |
1286 ODM_BB_RSSI_MONITOR |
1287 ODM_BB_CCK_PD |
1288 /*ODM_BB_PWR_TRAIN |*/
1289 ODM_BB_RATE_ADAPTIVE |
1290 ODM_BB_ADAPTIVITY |
1291 ODM_BB_CFO_TRACKING |
1292 ODM_BB_ADAPTIVE_SOML |
1293 ODM_BB_ENV_MONITOR |
1294 ODM_BB_LNA_SAT_CHK |
1295 ODM_BB_PRIMARY_CCA;
1296 break;
1297 #endif
1298
1299 #if (RTL8192F_SUPPORT)
1300 case ODM_RTL8192F:
1301 support_ability |=
1302 ODM_BB_DIG |
1303 ODM_BB_RA_MASK |
1304 ODM_BB_FA_CNT |
1305 ODM_BB_RSSI_MONITOR |
1306 ODM_BB_CCK_PD |
1307 /*ODM_BB_PWR_TRAIN |*/
1308 ODM_BB_RATE_ADAPTIVE |
1309 ODM_BB_ADAPTIVITY |
1310 /*ODM_BB_CFO_TRACKING |*/
1311 ODM_BB_ADAPTIVE_SOML |
1312 /*ODM_BB_PATH_DIV |*/
1313 ODM_BB_ENV_MONITOR |
1314 /*ODM_BB_LNA_SAT_CHK |*/
1315 /*ODM_BB_PRIMARY_CCA |*/
1316 0;
1317 break;
1318 #endif
1319
1320 /*@---------------AC Series-------------------*/
1321
1322 #if (RTL8881A_SUPPORT)
1323 case ODM_RTL8881A:
1324 support_ability |=
1325 ODM_BB_DIG |
1326 ODM_BB_RA_MASK |
1327 ODM_BB_FA_CNT |
1328 ODM_BB_RSSI_MONITOR |
1329 ODM_BB_CCK_PD |
1330 /*ODM_BB_PWR_TRAIN |*/
1331 ODM_BB_RATE_ADAPTIVE |
1332 ODM_BB_ADAPTIVITY |
1333 ODM_BB_CFO_TRACKING |
1334 ODM_BB_ENV_MONITOR;
1335 break;
1336 #endif
1337
1338 #if (RTL8814A_SUPPORT)
1339 case ODM_RTL8814A:
1340 support_ability |=
1341 ODM_BB_DIG |
1342 ODM_BB_RA_MASK |
1343 ODM_BB_FA_CNT |
1344 ODM_BB_RSSI_MONITOR |
1345 ODM_BB_CCK_PD |
1346 /*ODM_BB_PWR_TRAIN |*/
1347 ODM_BB_RATE_ADAPTIVE |
1348 ODM_BB_ADAPTIVITY |
1349 ODM_BB_CFO_TRACKING |
1350 ODM_BB_ENV_MONITOR;
1351 break;
1352 #endif
1353
1354 #if (RTL8822B_SUPPORT)
1355 case ODM_RTL8822B:
1356 support_ability |=
1357 ODM_BB_DIG |
1358 ODM_BB_RA_MASK |
1359 ODM_BB_FA_CNT |
1360 ODM_BB_RSSI_MONITOR |
1361 ODM_BB_CCK_PD |
1362 /*ODM_BB_PWR_TRAIN |*/
1363 /*ODM_BB_ADAPTIVE_SOML |*/
1364 ODM_BB_RATE_ADAPTIVE |
1365 ODM_BB_ADAPTIVITY |
1366 ODM_BB_CFO_TRACKING |
1367 ODM_BB_ENV_MONITOR;
1368 break;
1369 #endif
1370
1371 #if (RTL8821C_SUPPORT)
1372 case ODM_RTL8821C:
1373 support_ability |=
1374 ODM_BB_DIG |
1375 ODM_BB_RA_MASK |
1376 ODM_BB_FA_CNT |
1377 ODM_BB_RSSI_MONITOR |
1378 ODM_BB_CCK_PD |
1379 /*ODM_BB_PWR_TRAIN |*/
1380 ODM_BB_RATE_ADAPTIVE |
1381 ODM_BB_ADAPTIVITY |
1382 ODM_BB_CFO_TRACKING |
1383 ODM_BB_ENV_MONITOR;
1384
1385 break;
1386 #endif
1387
1388 /*@---------------JGR3 Series-------------------*/
1389
1390 #if (RTL8814B_SUPPORT)
1391 case ODM_RTL8814B:
1392 support_ability |=
1393 ODM_BB_DIG |
1394 ODM_BB_RA_MASK |
1395 ODM_BB_FA_CNT |
1396 ODM_BB_RSSI_MONITOR |
1397 ODM_BB_CCK_PD |
1398 /*ODM_BB_PWR_TRAIN |*/
1399 /*ODM_BB_RATE_ADAPTIVE |*/
1400 ODM_BB_ADAPTIVITY |
1401 ODM_BB_CFO_TRACKING |
1402 ODM_BB_ENV_MONITOR;
1403 break;
1404 #endif
1405
1406 #if (RTL8197G_SUPPORT)
1407 case ODM_RTL8197G:
1408 support_ability |=
1409 ODM_BB_DIG |
1410 ODM_BB_RA_MASK |
1411 ODM_BB_FA_CNT |
1412 ODM_BB_RSSI_MONITOR |
1413 ODM_BB_CCK_PD |
1414 /*ODM_BB_PWR_TRAIN |*/
1415 ODM_BB_RATE_ADAPTIVE |
1416 ODM_BB_ADAPTIVITY |
1417 ODM_BB_CFO_TRACKING |
1418 ODM_BB_ENV_MONITOR;
1419 break;
1420 #endif
1421
1422 #if (RTL8812F_SUPPORT)
1423 case ODM_RTL8812F:
1424 support_ability |=
1425 ODM_BB_DIG |
1426 ODM_BB_RA_MASK |
1427 ODM_BB_DYNAMIC_TXPWR |
1428 ODM_BB_FA_CNT |
1429 ODM_BB_RSSI_MONITOR |
1430 /*ODM_BB_CCK_PD |*/
1431 /*ODM_BB_PWR_TRAIN |*/
1432 ODM_BB_RATE_ADAPTIVE |
1433 ODM_BB_ADAPTIVITY |
1434 ODM_BB_CFO_TRACKING |
1435 ODM_BB_ENV_MONITOR;
1436 break;
1437 #endif
1438
1439 default:
1440 support_ability |=
1441 ODM_BB_DIG |
1442 ODM_BB_RA_MASK |
1443 ODM_BB_FA_CNT |
1444 ODM_BB_RSSI_MONITOR |
1445 ODM_BB_CCK_PD |
1446 /*ODM_BB_PWR_TRAIN |*/
1447 ODM_BB_RATE_ADAPTIVE |
1448 ODM_BB_ADAPTIVITY |
1449 ODM_BB_CFO_TRACKING |
1450 ODM_BB_ENV_MONITOR;
1451
1452 pr_debug("[Warning] Supportability Init Warning !!!\n");
1453 break;
1454 }
1455
1456 return support_ability;
1457 }
1458 #endif
1459
1460 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1461 u64 phydm_supportability_init_iot(
1462 void *dm_void)
1463 {
1464 struct dm_struct *dm = (struct dm_struct *)dm_void;
1465 u64 support_ability = 0;
1466
1467 switch (dm->support_ic_type) {
1468 #if (RTL8710B_SUPPORT)
1469 case ODM_RTL8710B:
1470 support_ability |=
1471 ODM_BB_DIG |
1472 ODM_BB_RA_MASK |
1473 /*ODM_BB_DYNAMIC_TXPWR |*/
1474 ODM_BB_FA_CNT |
1475 ODM_BB_RSSI_MONITOR |
1476 ODM_BB_CCK_PD |
1477 /*ODM_BB_PWR_TRAIN |*/
1478 ODM_BB_RATE_ADAPTIVE |
1479 ODM_BB_CFO_TRACKING |
1480 ODM_BB_ENV_MONITOR;
1481 break;
1482 #endif
1483
1484 #if (RTL8195A_SUPPORT)
1485 case ODM_RTL8195A:
1486 support_ability |=
1487 ODM_BB_DIG |
1488 ODM_BB_RA_MASK |
1489 /*ODM_BB_DYNAMIC_TXPWR |*/
1490 ODM_BB_FA_CNT |
1491 ODM_BB_RSSI_MONITOR |
1492 ODM_BB_CCK_PD |
1493 /*ODM_BB_PWR_TRAIN |*/
1494 ODM_BB_RATE_ADAPTIVE |
1495 ODM_BB_CFO_TRACKING |
1496 ODM_BB_ENV_MONITOR;
1497 break;
1498 #endif
1499
1500 #if (RTL8195B_SUPPORT)
1501 case ODM_RTL8195B:
1502 support_ability |=
1503 ODM_BB_DIG |
1504 ODM_BB_RA_MASK |
1505 /*ODM_BB_DYNAMIC_TXPWR |*/
1506 ODM_BB_FA_CNT |
1507 ODM_BB_RSSI_MONITOR |
1508 ODM_BB_CCK_PD |
1509 /*ODM_BB_PWR_TRAIN |*/
1510 ODM_BB_RATE_ADAPTIVE |
1511 ODM_BB_ADAPTIVITY |
1512 ODM_BB_CFO_TRACKING |
1513 ODM_BB_ENV_MONITOR;
1514 break;
1515 #endif
1516
1517 #if (RTL8721D_SUPPORT)
1518 case ODM_RTL8721D:
1519 support_ability |=
1520 ODM_BB_DIG |
1521 ODM_BB_RA_MASK |
1522 /*ODM_BB_DYNAMIC_TXPWR |*/
1523 ODM_BB_FA_CNT |
1524 ODM_BB_RSSI_MONITOR |
1525 ODM_BB_CCK_PD |
1526 /*ODM_BB_PWR_TRAIN |*/
1527 ODM_BB_RATE_ADAPTIVE |
1528 ODM_BB_ADAPTIVITY |
1529 ODM_BB_CFO_TRACKING |
1530 ODM_BB_ENV_MONITOR;
1531 break;
1532 #endif
1533
1534 #if (RTL8710C_SUPPORT)
1535 case ODM_RTL8710C:
1536 support_ability |=
1537 ODM_BB_DIG |
1538 ODM_BB_RA_MASK |
1539 /*ODM_BB_DYNAMIC_TXPWR |*/
1540 ODM_BB_FA_CNT |
1541 ODM_BB_RSSI_MONITOR |
1542 ODM_BB_CCK_PD |
1543 /*ODM_BB_PWR_TRAIN |*/
1544 ODM_BB_RATE_ADAPTIVE |
1545 ODM_BB_ADAPTIVITY |
1546 ODM_BB_CFO_TRACKING |
1547 ODM_BB_ENV_MONITOR;
1548 break;
1549 #endif
1550 default:
1551 support_ability |=
1552 ODM_BB_DIG |
1553 ODM_BB_RA_MASK |
1554 /*ODM_BB_DYNAMIC_TXPWR |*/
1555 ODM_BB_FA_CNT |
1556 ODM_BB_RSSI_MONITOR |
1557 ODM_BB_CCK_PD |
1558 /*ODM_BB_PWR_TRAIN |*/
1559 ODM_BB_RATE_ADAPTIVE |
1560 ODM_BB_CFO_TRACKING |
1561 ODM_BB_ENV_MONITOR;
1562
1563 pr_debug("[Warning] Supportability Init Warning !!!\n");
1564 break;
1565 }
1566
1567 return support_ability;
1568 }
1569 #endif
1570
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1571 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1572 enum phydm_offload_ability offload_ability)
1573 {
1574 switch (offload_ability) {
1575 case PHYDM_PHY_PARAM_OFFLOAD:
1576 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1577 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1578 break;
1579
1580 case PHYDM_RF_IQK_OFFLOAD:
1581 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1582 break;
1583
1584 case PHYDM_RF_DPK_OFFLOAD:
1585 dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
1586 break;
1587
1588 default:
1589 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1590 break;
1591 }
1592
1593 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1594 dm->fw_offload_ability);
1595 }
1596
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1597 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1598 enum phydm_offload_ability offload_ability)
1599 {
1600 switch (offload_ability) {
1601 case PHYDM_PHY_PARAM_OFFLOAD:
1602 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1603 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1604 break;
1605
1606 case PHYDM_RF_IQK_OFFLOAD:
1607 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1608 break;
1609
1610 case PHYDM_RF_DPK_OFFLOAD:
1611 dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
1612 break;
1613
1614 default:
1615 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1616 break;
1617 }
1618
1619 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1620 dm->fw_offload_ability);
1621 }
1622
phydm_supportability_init(void * dm_void)1623 void phydm_supportability_init(void *dm_void)
1624 {
1625 struct dm_struct *dm = (struct dm_struct *)dm_void;
1626 u64 support_ability;
1627
1628 if (dm->manual_supportability &&
1629 *dm->manual_supportability != 0xffffffff) {
1630 support_ability = *dm->manual_supportability;
1631 } else if (*dm->mp_mode) {
1632 support_ability = 0;
1633 } else {
1634 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1635 support_ability = phydm_supportability_init_win(dm);
1636 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1637 support_ability = phydm_supportability_init_ap(dm);
1638 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1639 support_ability = phydm_supportability_init_ce(dm);
1640 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1641 support_ability = phydm_supportability_init_iot(dm);
1642 #endif
1643
1644 /*@[Config Antenna Diversity]*/
1645 if (IS_FUNC_EN(dm->enable_antdiv))
1646 support_ability |= ODM_BB_ANT_DIV;
1647
1648 /*@[Config TXpath Diversity]*/
1649 if (IS_FUNC_EN(dm->enable_pathdiv))
1650 support_ability |= ODM_BB_PATH_DIV;
1651
1652 /*@[Config Adaptive SOML]*/
1653 if (IS_FUNC_EN(dm->en_adap_soml))
1654 support_ability |= ODM_BB_ADAPTIVE_SOML;
1655
1656 }
1657 dm->support_ability = support_ability;
1658 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1659 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1660 }
1661
phydm_rfe_init(void * dm_void)1662 void phydm_rfe_init(void *dm_void)
1663 {
1664 struct dm_struct *dm = (struct dm_struct *)dm_void;
1665
1666 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1667 #if (RTL8822B_SUPPORT == 1)
1668 if (dm->support_ic_type == ODM_RTL8822B)
1669 phydm_rfe_8822b_init(dm);
1670 #endif
1671 }
1672
1673 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
phydm_tx_collsion_th_init(void * dm_void)1674 void phydm_tx_collsion_th_init(void *dm_void)
1675 {
1676
1677 struct dm_struct *dm = (struct dm_struct *)dm_void;
1678
1679 #if (RTL8197G_SUPPORT)
1680 if (dm->support_ic_type & ODM_RTL8197G)
1681 phydm_tx_collsion_th_init_8197g(dm);
1682 #endif
1683
1684 #if (RTL8812F_SUPPORT)
1685 if (dm->support_ic_type & ODM_RTL8812F)
1686 phydm_tx_collsion_th_init_8812f(dm);
1687 #endif
1688
1689 }
1690
phydm_tx_collsion_th_set(void * dm_void,u8 val_r2t,u8 val_t2r)1691 void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r)
1692 {
1693 struct dm_struct *dm = (struct dm_struct *)dm_void;
1694
1695 #if (RTL8197G_SUPPORT)
1696 if (dm->support_ic_type & ODM_RTL8197G)
1697 phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r);
1698 #endif
1699
1700 #if (RTL8812F_SUPPORT)
1701 if (dm->support_ic_type & ODM_RTL8812F)
1702 phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r);
1703 #endif
1704
1705 }
1706 #endif
1707
phydm_dm_early_init(struct dm_struct * dm)1708 void phydm_dm_early_init(struct dm_struct *dm)
1709 {
1710 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1711 phydm_init_debug_setting(dm);
1712 #endif
1713 }
1714
odm_dm_init(struct dm_struct * dm)1715 enum phydm_init_result odm_dm_init(struct dm_struct *dm)
1716 {
1717 enum phydm_init_result result = PHYDM_INIT_SUCCESS;
1718
1719 if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
1720 pr_debug("[Warning][%s] Init fail\n", __func__);
1721 return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
1722 }
1723
1724 halrf_init(dm);
1725 phydm_supportability_init(dm);
1726 phydm_pause_func_init(dm);
1727 phydm_rfe_init(dm);
1728 phydm_common_info_self_init(dm);
1729 phydm_rx_phy_status_init(dm);
1730 #ifdef PHYDM_AUTO_DEGBUG
1731 phydm_auto_dbg_engine_init(dm);
1732 #endif
1733 phydm_dig_init(dm);
1734 #ifdef PHYDM_SUPPORT_CCKPD
1735 #ifdef PHYDM_DCC_ENHANCE
1736 phydm_dig_cckpd_coex_init(dm);
1737 #endif
1738 phydm_cck_pd_init(dm);
1739 #endif
1740 phydm_env_monitor_init(dm);
1741 phydm_enhance_monitor_init(dm);
1742 phydm_adaptivity_init(dm);
1743 phydm_ra_info_init(dm);
1744 phydm_rssi_monitor_init(dm);
1745 phydm_cfo_tracking_init(dm);
1746 phydm_rf_init(dm);
1747 phydm_dc_cancellation(dm);
1748 #ifdef PHYDM_TXA_CALIBRATION
1749 phydm_txcurrentcalibration(dm);
1750 phydm_get_pa_bias_offset(dm);
1751 #endif
1752 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1753 odm_antenna_diversity_init(dm);
1754 #endif
1755 #ifdef CONFIG_ADAPTIVE_SOML
1756 phydm_adaptive_soml_init(dm);
1757 #endif
1758 #ifdef CONFIG_PATH_DIVERSITY
1759 phydm_tx_path_diversity_init(dm);
1760 #endif
1761 #ifdef CONFIG_DYNAMIC_TX_TWR
1762 phydm_dynamic_tx_power_init(dm);
1763 #endif
1764 #if (PHYDM_LA_MODE_SUPPORT)
1765 phydm_la_init(dm);
1766 #endif
1767
1768 #ifdef PHYDM_BEAMFORMING_VERSION1
1769 phydm_beamforming_init(dm);
1770 #endif
1771
1772 #if (RTL8188E_SUPPORT)
1773 odm_ra_info_init_all(dm);
1774 #endif
1775 #ifdef PHYDM_PRIMARY_CCA
1776 phydm_primary_cca_init(dm);
1777 #endif
1778 #ifdef CONFIG_PSD_TOOL
1779 phydm_psd_init(dm);
1780 #endif
1781
1782 #ifdef CONFIG_SMART_ANTENNA
1783 phydm_smt_ant_init(dm);
1784 #endif
1785 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1786 phydm_lna_sat_check_init(dm);
1787 #endif
1788 #ifdef CONFIG_MCC_DM
1789 phydm_mcc_init(dm);
1790 #endif
1791
1792 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
1793 phydm_cck_rx_pathdiv_init(dm);
1794 #endif
1795
1796 #ifdef CONFIG_MU_RSOML
1797 phydm_mu_rsoml_init(dm);
1798 #endif
1799
1800 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
1801 phydm_tx_collsion_th_init(dm);
1802 #endif
1803
1804 return result;
1805 }
1806
odm_dm_reset(struct dm_struct * dm)1807 void odm_dm_reset(struct dm_struct *dm)
1808 {
1809 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1810 odm_ant_div_reset(dm);
1811 #endif
1812 phydm_set_edcca_threshold_api(dm);
1813 }
1814
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1815 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1816 char *output, u32 *_out_len)
1817 {
1818 struct dm_struct *dm = (struct dm_struct *)dm_void;
1819 u32 dm_value[10] = {0};
1820 u64 pre_support_ability, one = 1;
1821 u64 comp = 0;
1822 u32 used = *_used;
1823 u32 out_len = *_out_len;
1824 u8 i;
1825
1826 for (i = 0; i < 5; i++) {
1827 if (input[i + 1])
1828 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1829 }
1830
1831 pre_support_ability = dm->support_ability;
1832 comp = dm->support_ability;
1833
1834 PDM_SNPF(out_len, used, output + used, out_len - used,
1835 "\n================================\n");
1836
1837 if (dm_value[0] == 100) {
1838 PDM_SNPF(out_len, used, output + used, out_len - used,
1839 "[Supportability] PhyDM Selection\n");
1840 PDM_SNPF(out_len, used, output + used, out_len - used,
1841 "================================\n");
1842 PDM_SNPF(out_len, used, output + used, out_len - used,
1843 "00. (( %s ))DIG\n",
1844 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1845 PDM_SNPF(out_len, used, output + used, out_len - used,
1846 "01. (( %s ))RA_MASK\n",
1847 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1848 PDM_SNPF(out_len, used, output + used, out_len - used,
1849 "02. (( %s ))DYN_TXPWR\n",
1850 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1851 PDM_SNPF(out_len, used, output + used, out_len - used,
1852 "03. (( %s ))FA_CNT\n",
1853 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1854 PDM_SNPF(out_len, used, output + used, out_len - used,
1855 "04. (( %s ))RSSI_MNTR\n",
1856 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1857 PDM_SNPF(out_len, used, output + used, out_len - used,
1858 "05. (( %s ))CCK_PD\n",
1859 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1860 PDM_SNPF(out_len, used, output + used, out_len - used,
1861 "06. (( %s ))ANT_DIV\n",
1862 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1863 PDM_SNPF(out_len, used, output + used, out_len - used,
1864 "07. (( %s ))SMT_ANT\n",
1865 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1866 PDM_SNPF(out_len, used, output + used, out_len - used,
1867 "08. (( %s ))PWR_TRAIN\n",
1868 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1869 PDM_SNPF(out_len, used, output + used, out_len - used,
1870 "09. (( %s ))RA\n",
1871 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1872 PDM_SNPF(out_len, used, output + used, out_len - used,
1873 "10. (( %s ))PATH_DIV\n",
1874 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1875 PDM_SNPF(out_len, used, output + used, out_len - used,
1876 "11. (( %s ))DFS\n",
1877 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1878 PDM_SNPF(out_len, used, output + used, out_len - used,
1879 "12. (( %s ))DYN_ARFR\n",
1880 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1881 PDM_SNPF(out_len, used, output + used, out_len - used,
1882 "13. (( %s ))ADAPTIVITY\n",
1883 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1884 PDM_SNPF(out_len, used, output + used, out_len - used,
1885 "14. (( %s ))CFO_TRACK\n",
1886 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1887 PDM_SNPF(out_len, used, output + used, out_len - used,
1888 "15. (( %s ))ENV_MONITOR\n",
1889 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1890 PDM_SNPF(out_len, used, output + used, out_len - used,
1891 "16. (( %s ))PRI_CCA\n",
1892 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1893 PDM_SNPF(out_len, used, output + used, out_len - used,
1894 "17. (( %s ))ADPTV_SOML\n",
1895 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1896 PDM_SNPF(out_len, used, output + used, out_len - used,
1897 "18. (( %s ))LNA_SAT_CHK\n",
1898 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1899 PDM_SNPF(out_len, used, output + used, out_len - used,
1900 "================================\n");
1901 PDM_SNPF(out_len, used, output + used, out_len - used,
1902 "[Supportability] PhyDM offload ability\n");
1903 PDM_SNPF(out_len, used, output + used, out_len - used,
1904 "================================\n");
1905
1906 PDM_SNPF(out_len, used, output + used, out_len - used,
1907 "00. (( %s ))PHY PARAM OFFLOAD\n",
1908 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
1909 ("V") : (".")));
1910 PDM_SNPF(out_len, used, output + used, out_len - used,
1911 "01. (( %s ))RF IQK OFFLOAD\n",
1912 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
1913 ("V") : (".")));
1914 PDM_SNPF(out_len, used, output + used, out_len - used,
1915 "================================\n");
1916
1917 } else if (dm_value[0] == 101) {
1918 dm->support_ability = 0;
1919 PDM_SNPF(out_len, used, output + used, out_len - used,
1920 "Disable all support_ability components\n");
1921 } else {
1922 if (dm_value[1] == 1) { /* @enable */
1923 dm->support_ability |= (one << dm_value[0]);
1924 } else if (dm_value[1] == 2) {/* @disable */
1925 dm->support_ability &= ~(one << dm_value[0]);
1926 } else {
1927 PDM_SNPF(out_len, used, output + used, out_len - used,
1928 "[Warning!!!] 1:enable, 2:disable\n");
1929 }
1930 }
1931 PDM_SNPF(out_len, used, output + used, out_len - used,
1932 "pre-supportability = 0x%llx\n", pre_support_ability);
1933 PDM_SNPF(out_len, used, output + used, out_len - used,
1934 "Cur-supportability = 0x%llx\n", dm->support_ability);
1935 PDM_SNPF(out_len, used, output + used, out_len - used,
1936 "================================\n");
1937
1938 *_used = used;
1939 *_out_len = out_len;
1940 }
1941
phydm_watchdog_lps_32k(struct dm_struct * dm)1942 void phydm_watchdog_lps_32k(struct dm_struct *dm)
1943 {
1944 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1945
1946 phydm_common_info_self_update(dm);
1947 phydm_rssi_monitor_check(dm);
1948 phydm_dig_lps_32k(dm);
1949 phydm_common_info_self_reset(dm);
1950 }
1951
phydm_watchdog_lps(struct dm_struct * dm)1952 void phydm_watchdog_lps(struct dm_struct *dm)
1953 {
1954 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1955 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1956
1957 phydm_common_info_self_update(dm);
1958 phydm_rssi_monitor_check(dm);
1959 phydm_basic_dbg_message(dm);
1960 phydm_receiver_blocking(dm);
1961 phydm_false_alarm_counter_statistics(dm);
1962 phydm_dig_by_rssi_lps(dm);
1963 #ifdef PHYDM_SUPPORT_CCKPD
1964 phydm_cck_pd_th(dm);
1965 #endif
1966 phydm_adaptivity(dm);
1967 #ifdef CONFIG_BW_INDICATION
1968 phydm_dyn_bw_indication(dm);
1969 #endif
1970 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1971 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1972 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
1973 odm_antenna_diversity(dm);
1974 #endif
1975 #endif
1976 phydm_common_info_self_reset(dm);
1977 #endif
1978 }
1979
phydm_watchdog_mp(struct dm_struct * dm)1980 void phydm_watchdog_mp(struct dm_struct *dm)
1981 {
1982 }
1983
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)1984 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
1985 {
1986 struct dm_struct *dm = (struct dm_struct *)dm_void;
1987
1988 if (pause_type == PHYDM_PAUSE) {
1989 dm->disable_phydm_watchdog = 1;
1990 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
1991 } else {
1992 dm->disable_phydm_watchdog = 0;
1993 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
1994 }
1995 }
1996
phydm_pause_func_init(void * dm_void)1997 void phydm_pause_func_init(void *dm_void)
1998 {
1999 struct dm_struct *dm = (struct dm_struct *)dm_void;
2000
2001 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
2002 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2003 dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
2004 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2005 dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
2006 dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
2007 }
2008
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)2009 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
2010 enum phydm_pause_type pause_type,
2011 enum phydm_pause_level pause_lv, u8 val_lehgth,
2012 u32 *val_buf)
2013 {
2014 struct dm_struct *dm = (struct dm_struct *)dm_void;
2015 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
2016 s8 *pause_lv_pre = &dm->s8_dummy;
2017 u32 *bkp_val = &dm->u32_dummy;
2018 u32 ori_val[5] = {0};
2019 u64 pause_func_bitmap = (u64)BIT(pause_func);
2020 u8 i = 0;
2021 u8 en_2rcca = 0;
2022 u8 en_bw40m = 0;
2023 u8 pause_result = PAUSE_FAIL;
2024
2025 PHYDM_DBG(dm, ODM_COMP_API, "\n");
2026 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
2027 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2028 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2029 pause_lv, val_lehgth);
2030
2031 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
2032 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
2033 return PAUSE_FAIL;
2034 }
2035
2036 if (pause_func == F00_DIG) {
2037 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
2038
2039 if (val_lehgth != 1) {
2040 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2041 return PAUSE_FAIL;
2042 }
2043
2044 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
2045 pause_lv_pre = &dm->pause_lv_table.lv_dig;
2046 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
2047 /*@function pointer hook*/
2048 func_t->pause_phydm_handler = phydm_set_dig_val;
2049
2050 #ifdef PHYDM_SUPPORT_CCKPD
2051 } else if (pause_func == F05_CCK_PD) {
2052 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
2053
2054 if (val_lehgth != 1) {
2055 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2056 return PAUSE_FAIL;
2057 }
2058
2059 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
2060 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
2061 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
2062 /*@function pointer hook*/
2063 func_t->pause_phydm_handler = phydm_set_cckpd_val;
2064 #endif
2065
2066 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2067 } else if (pause_func == F06_ANT_DIV) {
2068 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
2069
2070 if (val_lehgth != 1) {
2071 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2072 return PAUSE_FAIL;
2073 }
2074 /*@default antenna*/
2075 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
2076 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
2077 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
2078 /*@function pointer hook*/
2079 func_t->pause_phydm_handler = phydm_set_antdiv_val;
2080
2081 #endif
2082 #ifdef PHYDM_SUPPORT_ADAPTIVITY
2083 } else if (pause_func == F13_ADPTVTY) {
2084 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
2085
2086 if (val_lehgth != 2) {
2087 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
2088 return PAUSE_FAIL;
2089 }
2090
2091 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
2092 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
2093 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
2094 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
2095 /*@function pointer hook*/
2096 func_t->pause_phydm_handler = phydm_set_edcca_val;
2097
2098 #endif
2099 #ifdef CONFIG_ADAPTIVE_SOML
2100 } else if (pause_func == F17_ADPTV_SOML) {
2101 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
2102
2103 if (val_lehgth != 1) {
2104 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2105 return PAUSE_FAIL;
2106 }
2107 /*SOML_ON/OFF*/
2108 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
2109
2110 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
2111 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
2112 /*@function pointer hook*/
2113 func_t->pause_phydm_handler = phydm_set_adsl_val;
2114
2115 #endif
2116 } else {
2117 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
2118 return PAUSE_FAIL;
2119 }
2120
2121 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
2122 pause_lv, *pause_lv_pre);
2123
2124 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
2125 if (pause_lv <= *pause_lv_pre) {
2126 PHYDM_DBG(dm, ODM_COMP_API,
2127 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
2128 return PAUSE_FAIL;
2129 }
2130
2131 if (!(dm->pause_ability & pause_func_bitmap)) {
2132 for (i = 0; i < val_lehgth; i++)
2133 bkp_val[i] = ori_val[i];
2134 }
2135
2136 dm->pause_ability |= pause_func_bitmap;
2137 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2138 dm->pause_ability);
2139
2140 if (pause_type == PHYDM_PAUSE) {
2141 for (i = 0; i < val_lehgth; i++)
2142 PHYDM_DBG(dm, ODM_COMP_API,
2143 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
2144 i, val_buf[i], bkp_val[i]);
2145 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
2146 } else {
2147 for (i = 0; i < val_lehgth; i++)
2148 PHYDM_DBG(dm, ODM_COMP_API,
2149 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
2150 i, bkp_val[i]);
2151 }
2152
2153 *pause_lv_pre = pause_lv;
2154 pause_result = PAUSE_SUCCESS;
2155
2156 } else if (pause_type == PHYDM_RESUME) {
2157 if (pause_lv < *pause_lv_pre) {
2158 PHYDM_DBG(dm, ODM_COMP_API,
2159 "[Resume FAIL] Pre_LV >= Curr_LV\n");
2160 return PAUSE_FAIL;
2161 }
2162
2163 if ((dm->pause_ability & pause_func_bitmap) == 0) {
2164 PHYDM_DBG(dm, ODM_COMP_API,
2165 "[RESUME] No Need to Revert\n");
2166 return PAUSE_SUCCESS;
2167 }
2168
2169 dm->pause_ability &= ~pause_func_bitmap;
2170 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2171 dm->pause_ability);
2172
2173 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
2174
2175 for (i = 0; i < val_lehgth; i++) {
2176 PHYDM_DBG(dm, ODM_COMP_API,
2177 "[RESUME] val_idx[%d]={0x%x}\n", i,
2178 bkp_val[i]);
2179 }
2180
2181 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
2182
2183 pause_result = PAUSE_SUCCESS;
2184 } else {
2185 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
2186 pause_result = PAUSE_FAIL;
2187 }
2188 return pause_result;
2189 }
2190
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2191 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
2192 char *output, u32 *_out_len)
2193 {
2194 struct dm_struct *dm = (struct dm_struct *)dm_void;
2195 char help[] = "-h";
2196 u32 var1[10] = {0};
2197 u32 used = *_used;
2198 u32 out_len = *_out_len;
2199 u32 i;
2200 u8 length = 0;
2201 u32 buf[5] = {0};
2202 u8 set_result = 0;
2203 enum phydm_func_idx func = 0;
2204 enum phydm_pause_type type = 0;
2205 enum phydm_pause_level lv = 0;
2206
2207 if ((strcmp(input[1], help) == 0)) {
2208 PDM_SNPF(out_len, used, output + used, out_len - used,
2209 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
2210
2211 goto out;
2212 }
2213
2214 for (i = 0; i < 10; i++) {
2215 if (input[i + 1])
2216 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2217 }
2218
2219 func = (enum phydm_func_idx)var1[0];
2220 type = (enum phydm_pause_type)var1[1];
2221 lv = (enum phydm_pause_level)var1[2];
2222
2223 for (i = 0; i < 5; i++)
2224 buf[i] = var1[3 + i];
2225
2226 if (func == F00_DIG) {
2227 PDM_SNPF(out_len, used, output + used, out_len - used,
2228 "[DIG]\n");
2229 length = 1;
2230
2231 } else if (func == F05_CCK_PD) {
2232 PDM_SNPF(out_len, used, output + used, out_len - used,
2233 "[CCK_PD]\n");
2234 length = 1;
2235 } else if (func == F06_ANT_DIV) {
2236 PDM_SNPF(out_len, used, output + used, out_len - used,
2237 "[Ant_Div]\n");
2238 length = 1;
2239 } else if (func == F13_ADPTVTY) {
2240 PDM_SNPF(out_len, used, output + used, out_len - used,
2241 "[Adaptivity]\n");
2242 length = 2;
2243 } else if (func == F17_ADPTV_SOML) {
2244 PDM_SNPF(out_len, used, output + used, out_len - used,
2245 "[ADSL]\n");
2246 length = 1;
2247 } else {
2248 PDM_SNPF(out_len, used, output + used, out_len - used,
2249 "[Set Function Error]\n");
2250 length = 0;
2251 }
2252
2253 if (length != 0) {
2254 PDM_SNPF(out_len, used, output + used, out_len - used,
2255 "{%s, lv=%d} val = %d, %d}\n",
2256 ((type == PHYDM_PAUSE) ? "Pause" :
2257 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2258 lv, var1[3], var1[4]);
2259
2260 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
2261 }
2262
2263 PDM_SNPF(out_len, used, output + used, out_len - used,
2264 "set_result = %d\n", set_result);
2265
2266 out:
2267 *_used = used;
2268 *_out_len = out_len;
2269 }
2270
phydm_pause_dm_by_asso_pkt(struct dm_struct * dm,enum phydm_pause_type pause_type,u8 rssi)2271 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
2272 enum phydm_pause_type pause_type, u8 rssi)
2273 {
2274 u32 igi_val = rssi + 10;
2275 u32 th_buf[2];
2276
2277 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
2278 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2279 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2280 rssi);
2281
2282 if (pause_type == PHYDM_RESUME) {
2283 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
2284 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2285
2286 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
2287 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2288 } else {
2289 odm_write_dig(dm, (u8)igi_val);
2290 phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
2291 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2292
2293 th_buf[0] = 0xff;
2294 th_buf[1] = 0xff;
2295
2296 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
2297 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2298 }
2299 }
2300
phydm_stop_dm_watchdog_check(void * dm_void)2301 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2302 {
2303 struct dm_struct *dm = (struct dm_struct *)dm_void;
2304
2305 if (dm->disable_phydm_watchdog == 1) {
2306 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2307 return true;
2308 } else {
2309 return false;
2310 }
2311 }
2312
phydm_watchdog(struct dm_struct * dm)2313 void phydm_watchdog(struct dm_struct *dm)
2314 {
2315 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2316
2317 phydm_common_info_self_update(dm);
2318 phydm_phy_info_update(dm);
2319 phydm_rssi_monitor_check(dm);
2320 phydm_basic_dbg_message(dm);
2321 phydm_dm_summary(dm, FIRST_MACID);
2322 #ifdef PHYDM_AUTO_DEGBUG
2323 phydm_auto_dbg_engine(dm);
2324 #endif
2325 phydm_receiver_blocking(dm);
2326
2327 if (phydm_stop_dm_watchdog_check(dm) == true)
2328 return;
2329
2330 phydm_hw_setting(dm);
2331
2332 #ifdef PHYDM_TDMA_DIG_SUPPORT
2333 if (dm->original_dig_restore == 0) {
2334 phydm_tdma_dig_timer_check(dm);
2335 } else
2336 #endif
2337 {
2338 phydm_false_alarm_counter_statistics(dm);
2339 phydm_noisy_detection(dm);
2340
2341 #if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
2342 phydm_dig_cckpd_coex(dm);
2343 #else
2344 phydm_dig(dm);
2345 #ifdef PHYDM_SUPPORT_CCKPD
2346 phydm_cck_pd_th(dm);
2347 #endif
2348 #endif
2349 }
2350
2351 #ifdef PHYDM_HW_IGI
2352 phydm_hwigi(dm);
2353 #endif
2354 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2355 phydm_update_power_training_state(dm);
2356 #endif
2357 phydm_adaptivity(dm);
2358 phydm_ra_info_watchdog(dm);
2359 #ifdef CONFIG_PATH_DIVERSITY
2360 phydm_tx_path_diversity(dm);
2361 #endif
2362 phydm_cfo_tracking(dm);
2363 #ifdef CONFIG_DYNAMIC_TX_TWR
2364 phydm_dynamic_tx_power(dm);
2365 #endif
2366 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2367 odm_antenna_diversity(dm);
2368 #endif
2369 #ifdef CONFIG_ADAPTIVE_SOML
2370 phydm_adaptive_soml(dm);
2371 #endif
2372
2373 #ifdef PHYDM_BEAMFORMING_VERSION1
2374 phydm_beamforming_watchdog(dm);
2375 #endif
2376
2377 halrf_watchdog(dm);
2378 #ifdef PHYDM_PRIMARY_CCA
2379 phydm_primary_cca(dm);
2380 #endif
2381 #ifdef CONFIG_BW_INDICATION
2382 phydm_dyn_bw_indication(dm);
2383 #endif
2384 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2385 odm_dtc(dm);
2386 #endif
2387
2388 phydm_env_mntr_watchdog(dm);
2389 phydm_enhance_mntr_watchdog(dm);
2390
2391 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2392 phydm_lna_sat_chk_watchdog(dm);
2393 #endif
2394
2395 #ifdef CONFIG_MCC_DM
2396 phydm_mcc_switch(dm);
2397 #endif
2398
2399 #ifdef CONFIG_MU_RSOML
2400 phydm_mu_rsoml_decision(dm);
2401 #endif
2402
2403 phydm_common_info_self_reset(dm);
2404 }
2405
phydm_fw_dm_ctrl_en(void * dm_void,enum phydm_func_idx fun_idx,boolean enable)2406 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
2407 boolean enable)
2408 {
2409 struct dm_struct *dm = (struct dm_struct *)dm_void;
2410 u8 h2c_val[H2C_MAX_LENGTH] = {0};
2411 u8 para4[4]; /*4 bit*/
2412 u8 para8[4]; /*8 bit*/
2413 u8 i = 0;
2414
2415 for (i = 0; i < 4; i++) {
2416 para4[i] = 0;
2417 para8[i] = 0;
2418 }
2419
2420 switch (fun_idx) {
2421 case F00_DIG:
2422 phydm_fill_fw_dig_info(dm, &enable, para4, para8);
2423 break;
2424 default:
2425 pr_debug("[Warning] %s\n", __func__);
2426 return;
2427 }
2428
2429 h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
2430 h2c_val[1] = para8[0];
2431 h2c_val[2] = para8[1];
2432 h2c_val[3] = para8[2];
2433 h2c_val[4] = para8[3];
2434 h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
2435 h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
2436
2437 PHYDM_DBG(dm, DBG_FW_DM,
2438 "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
2439 fun_idx, enable,
2440 para8[0], para8[1], para8[2], para8[3],
2441 para4[0], para4[1], para4[2], para4[3]);
2442
2443 odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
2444 }
2445
2446 /*@
2447 * Init /.. Fixed HW value. Only init time.
2448 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2449 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2450 u64 value)
2451 {
2452 /* This section is used for init value */
2453 switch (cmn_info) {
2454 /* @Fixed ODM value. */
2455 case ODM_CMNINFO_ABILITY:
2456 dm->support_ability = (u64)value;
2457 break;
2458
2459 case ODM_CMNINFO_RF_TYPE:
2460 dm->rf_type = (u8)value;
2461 break;
2462
2463 case ODM_CMNINFO_PLATFORM:
2464 dm->support_platform = (u8)value;
2465 break;
2466
2467 case ODM_CMNINFO_INTERFACE:
2468 dm->support_interface = (u8)value;
2469 break;
2470
2471 case ODM_CMNINFO_MP_TEST_CHIP:
2472 dm->is_mp_chip = (u8)value;
2473 break;
2474
2475 case ODM_CMNINFO_IC_TYPE:
2476 dm->support_ic_type = (u32)value;
2477 break;
2478
2479 case ODM_CMNINFO_CUT_VER:
2480 dm->cut_version = (u8)value;
2481 break;
2482
2483 case ODM_CMNINFO_FAB_VER:
2484 dm->fab_version = (u8)value;
2485 break;
2486 case ODM_CMNINFO_FW_VER:
2487 dm->fw_version = (u8)value;
2488 break;
2489 case ODM_CMNINFO_FW_SUB_VER:
2490 dm->fw_sub_version = (u8)value;
2491 break;
2492 case ODM_CMNINFO_RFE_TYPE:
2493 #if (RTL8821C_SUPPORT)
2494 if (dm->support_ic_type & ODM_RTL8821C)
2495 dm->rfe_type_expand = (u8)value;
2496 else
2497 #endif
2498 dm->rfe_type = (u8)value;
2499
2500 #ifdef CONFIG_RFE_BY_HW_INFO
2501 phydm_init_hw_info_by_rfe(dm);
2502 #endif
2503 break;
2504
2505 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2506 dm->ant_div_type = (u8)value;
2507 break;
2508
2509 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2510 dm->with_extenal_ant_switch = (u8)value;
2511 break;
2512
2513 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2514 case ODM_CMNINFO_BE_FIX_TX_ANT:
2515 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2516 break;
2517 #endif
2518
2519 case ODM_CMNINFO_BOARD_TYPE:
2520 if (!dm->is_init_hw_info_by_rfe)
2521 dm->board_type = (u8)value;
2522 break;
2523
2524 case ODM_CMNINFO_PACKAGE_TYPE:
2525 if (!dm->is_init_hw_info_by_rfe)
2526 dm->package_type = (u8)value;
2527 break;
2528
2529 case ODM_CMNINFO_EXT_LNA:
2530 if (!dm->is_init_hw_info_by_rfe)
2531 dm->ext_lna = (u8)value;
2532 break;
2533
2534 case ODM_CMNINFO_5G_EXT_LNA:
2535 if (!dm->is_init_hw_info_by_rfe)
2536 dm->ext_lna_5g = (u8)value;
2537 break;
2538
2539 case ODM_CMNINFO_EXT_PA:
2540 if (!dm->is_init_hw_info_by_rfe)
2541 dm->ext_pa = (u8)value;
2542 break;
2543
2544 case ODM_CMNINFO_5G_EXT_PA:
2545 if (!dm->is_init_hw_info_by_rfe)
2546 dm->ext_pa_5g = (u8)value;
2547 break;
2548
2549 case ODM_CMNINFO_GPA:
2550 if (!dm->is_init_hw_info_by_rfe)
2551 dm->type_gpa = (u16)value;
2552 break;
2553
2554 case ODM_CMNINFO_APA:
2555 if (!dm->is_init_hw_info_by_rfe)
2556 dm->type_apa = (u16)value;
2557 break;
2558
2559 case ODM_CMNINFO_GLNA:
2560 if (!dm->is_init_hw_info_by_rfe)
2561 dm->type_glna = (u16)value;
2562 break;
2563
2564 case ODM_CMNINFO_ALNA:
2565 if (!dm->is_init_hw_info_by_rfe)
2566 dm->type_alna = (u16)value;
2567 break;
2568
2569 case ODM_CMNINFO_EXT_TRSW:
2570 if (!dm->is_init_hw_info_by_rfe)
2571 dm->ext_trsw = (u8)value;
2572 break;
2573 case ODM_CMNINFO_EXT_LNA_GAIN:
2574 dm->ext_lna_gain = (u8)value;
2575 break;
2576 case ODM_CMNINFO_PATCH_ID:
2577 dm->iot_table.win_patch_id = (u8)value;
2578 break;
2579 case ODM_CMNINFO_BINHCT_TEST:
2580 dm->is_in_hct_test = (boolean)value;
2581 break;
2582 case ODM_CMNINFO_BWIFI_TEST:
2583 dm->wifi_test = (u8)value;
2584 break;
2585 case ODM_CMNINFO_SMART_CONCURRENT:
2586 dm->is_dual_mac_smart_concurrent = (boolean)value;
2587 break;
2588 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2589 case ODM_CMNINFO_CONFIG_BB_RF:
2590 dm->config_bbrf = (boolean)value;
2591 break;
2592 #endif
2593 case ODM_CMNINFO_IQKPAOFF:
2594 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2595 break;
2596 case ODM_CMNINFO_REGRFKFREEENABLE:
2597 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2598 break;
2599 case ODM_CMNINFO_RFKFREEENABLE:
2600 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2601 break;
2602 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2603 dm->normal_rx_path = (u8)value;
2604 break;
2605 case ODM_CMNINFO_VALID_PATH_SET:
2606 dm->valid_path_set = (u8)value;
2607 break;
2608 case ODM_CMNINFO_EFUSE0X3D8:
2609 dm->efuse0x3d8 = (u8)value;
2610 break;
2611 case ODM_CMNINFO_EFUSE0X3D7:
2612 dm->efuse0x3d7 = (u8)value;
2613 break;
2614 case ODM_CMNINFO_ADVANCE_OTA:
2615 dm->p_advance_ota = (u8)value;
2616 break;
2617
2618 #ifdef CONFIG_PHYDM_DFS_MASTER
2619 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2620 dm->dfs_region_domain = (u8)value;
2621 break;
2622 #endif
2623 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2624 dm->soft_ap_special_setting = (u32)value;
2625 break;
2626
2627 case ODM_CMNINFO_X_CAP_SETTING:
2628 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2629 break;
2630
2631 case ODM_CMNINFO_DPK_EN:
2632 /*@dm->dpk_en = (u1Byte)value;*/
2633 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2634 break;
2635
2636 case ODM_CMNINFO_HP_HWID:
2637 dm->hp_hw_id = (boolean)value;
2638 break;
2639 case ODM_CMNINFO_TSSI_ENABLE:
2640 dm->en_tssi_mode = (u8)value;
2641 break;
2642 case ODM_CMNINFO_DIS_DPD:
2643 dm->en_dis_dpd = (boolean)value;
2644 break;
2645 case ODM_CMNINFO_EN_AUTO_BW_TH:
2646 dm->en_auto_bw_th = (u8)value;
2647 break;
2648 #if (RTL8721D_SUPPORT)
2649 case ODM_CMNINFO_POWER_VOLTAGE:
2650 dm->power_voltage = (u8)value;
2651 break;
2652 case ODM_CMNINFO_ANTDIV_GPIO:
2653 dm->antdiv_gpio = (u8)value;
2654 break;
2655 case ODM_CMNINFO_PEAK_DETECT_MODE:
2656 dm->peak_detect_mode = (u8)value;
2657 break;
2658 #endif
2659 default:
2660 break;
2661 }
2662 }
2663
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2664 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2665 void *value)
2666 {
2667 /* @Hook call by reference pointer. */
2668 switch (cmn_info) {
2669 /* @Dynamic call by reference pointer. */
2670 case ODM_CMNINFO_TX_UNI:
2671 dm->num_tx_bytes_unicast = (u64 *)value;
2672 break;
2673
2674 case ODM_CMNINFO_RX_UNI:
2675 dm->num_rx_bytes_unicast = (u64 *)value;
2676 break;
2677
2678 case ODM_CMNINFO_BAND:
2679 dm->band_type = (u8 *)value;
2680 break;
2681
2682 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2683 dm->sec_ch_offset = (u8 *)value;
2684 break;
2685
2686 case ODM_CMNINFO_SEC_MODE:
2687 dm->security = (u8 *)value;
2688 break;
2689
2690 case ODM_CMNINFO_BW:
2691 dm->band_width = (u8 *)value;
2692 break;
2693
2694 case ODM_CMNINFO_CHNL:
2695 dm->channel = (u8 *)value;
2696 break;
2697
2698 case ODM_CMNINFO_SCAN:
2699 dm->is_scan_in_process = (boolean *)value;
2700 break;
2701
2702 case ODM_CMNINFO_POWER_SAVING:
2703 dm->is_power_saving = (boolean *)value;
2704 break;
2705
2706 case ODM_CMNINFO_TDMA:
2707 dm->is_tdma = (boolean *)value;
2708 break;
2709
2710 case ODM_CMNINFO_ONE_PATH_CCA:
2711 dm->one_path_cca = (u8 *)value;
2712 break;
2713
2714 case ODM_CMNINFO_DRV_STOP:
2715 dm->is_driver_stopped = (boolean *)value;
2716 break;
2717 case ODM_CMNINFO_INIT_ON:
2718 dm->pinit_adpt_in_progress = (boolean *)value;
2719 break;
2720
2721 case ODM_CMNINFO_ANT_TEST:
2722 dm->antenna_test = (u8 *)value;
2723 break;
2724
2725 case ODM_CMNINFO_NET_CLOSED:
2726 dm->is_net_closed = (boolean *)value;
2727 break;
2728
2729 case ODM_CMNINFO_FORCED_RATE:
2730 dm->forced_data_rate = (u16 *)value;
2731 break;
2732 case ODM_CMNINFO_ANT_DIV:
2733 dm->enable_antdiv = (u8 *)value;
2734 break;
2735 case ODM_CMNINFO_PATH_DIV:
2736 dm->enable_pathdiv = (u8 *)value;
2737 break;
2738 case ODM_CMNINFO_ADAPTIVE_SOML:
2739 dm->en_adap_soml = (u8 *)value;
2740 break;
2741 case ODM_CMNINFO_ADAPTIVITY:
2742 dm->edcca_mode = (u8 *)value;
2743 break;
2744
2745 case ODM_CMNINFO_P2P_LINK:
2746 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2747 break;
2748
2749 case ODM_CMNINFO_IS1ANTENNA:
2750 dm->is_1_antenna = (boolean *)value;
2751 break;
2752
2753 case ODM_CMNINFO_RFDEFAULTPATH:
2754 dm->rf_default_path = (u8 *)value;
2755 break;
2756
2757 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2758 dm->is_fcs_mode_enable = (boolean *)value;
2759 break;
2760
2761 case ODM_CMNINFO_HUBUSBMODE:
2762 dm->hub_usb_mode = (u8 *)value;
2763 break;
2764 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2765 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2766 break;
2767 case ODM_CMNINFO_TX_TP:
2768 dm->current_tx_tp = (u32 *)value;
2769 break;
2770 case ODM_CMNINFO_RX_TP:
2771 dm->current_rx_tp = (u32 *)value;
2772 break;
2773 case ODM_CMNINFO_SOUNDING_SEQ:
2774 dm->sounding_seq = (u8 *)value;
2775 break;
2776 #ifdef CONFIG_PHYDM_DFS_MASTER
2777 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2778 dm->dfs_master_enabled = (u8 *)value;
2779 break;
2780 #endif
2781
2782 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2783 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2784 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2785 break;
2786 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2787 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2788 break;
2789 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2790 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2791 break;
2792 #endif
2793
2794 case ODM_CMNINFO_SOFT_AP_MODE:
2795 dm->soft_ap_mode = (u32 *)value;
2796 break;
2797 case ODM_CMNINFO_MP_MODE:
2798 dm->mp_mode = (u8 *)value;
2799 break;
2800 case ODM_CMNINFO_INTERRUPT_MASK:
2801 dm->interrupt_mask = (u32 *)value;
2802 break;
2803 case ODM_CMNINFO_BB_OPERATION_MODE:
2804 dm->bb_op_mode = (u8 *)value;
2805 break;
2806 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2807 dm->manual_supportability = (u32 *)value;
2808 break;
2809 case ODM_CMNINFO_EN_DYM_BW_INDICATION:
2810 dm->dis_dym_bw_indication = (u8 *)value;
2811 default:
2812 /*do nothing*/
2813 break;
2814 }
2815 }
2816
2817 /*@
2818 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2819 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2820 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2821 {
2822 /* This init variable may be changed in run time. */
2823 switch (cmn_info) {
2824 case ODM_CMNINFO_LINK_IN_PROGRESS:
2825 dm->is_link_in_process = (boolean)value;
2826 break;
2827
2828 case ODM_CMNINFO_ABILITY:
2829 dm->support_ability = (u64)value;
2830 break;
2831
2832 case ODM_CMNINFO_RF_TYPE:
2833 dm->rf_type = (u8)value;
2834 break;
2835
2836 case ODM_CMNINFO_WIFI_DIRECT:
2837 dm->is_wifi_direct = (boolean)value;
2838 break;
2839
2840 case ODM_CMNINFO_WIFI_DISPLAY:
2841 dm->is_wifi_display = (boolean)value;
2842 break;
2843
2844 case ODM_CMNINFO_LINK:
2845 dm->is_linked = (boolean)value;
2846 break;
2847
2848 case ODM_CMNINFO_CMW500LINK:
2849 dm->iot_table.is_linked_cmw500 = (boolean)value;
2850 break;
2851
2852 case ODM_CMNINFO_STATION_STATE:
2853 dm->bsta_state = (boolean)value;
2854 break;
2855
2856 case ODM_CMNINFO_RSSI_MIN:
2857 #if 0
2858 dm->rssi_min = (u8)value;
2859 #endif
2860 break;
2861
2862 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2863 dm->rssi_min_by_path = (u8)value;
2864 break;
2865
2866 case ODM_CMNINFO_DBG_COMP:
2867 dm->debug_components = (u64)value;
2868 break;
2869
2870 #ifdef ODM_CONFIG_BT_COEXIST
2871 /* The following is for BT HS mode and BT coexist mechanism. */
2872 case ODM_CMNINFO_BT_ENABLED:
2873 dm->bt_info_table.is_bt_enabled = (boolean)value;
2874 break;
2875
2876 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2877 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2878 break;
2879
2880 case ODM_CMNINFO_BT_HS_RSSI:
2881 dm->bt_info_table.bt_hs_rssi = (u8)value;
2882 break;
2883
2884 case ODM_CMNINFO_BT_OPERATION:
2885 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2886 break;
2887
2888 case ODM_CMNINFO_BT_LIMITED_DIG:
2889 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2890 break;
2891 #endif
2892
2893 case ODM_CMNINFO_AP_TOTAL_NUM:
2894 dm->ap_total_num = (u8)value;
2895 break;
2896
2897 #ifdef CONFIG_PHYDM_DFS_MASTER
2898 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2899 dm->dfs_region_domain = (u8)value;
2900 break;
2901 #endif
2902
2903 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
2904 dm->is_bt_continuous_turn = (boolean)value;
2905 break;
2906 case ODM_CMNINFO_IS_DOWNLOAD_FW:
2907 dm->is_download_fw = (boolean)value;
2908 break;
2909 case ODM_CMNINFO_PHYDM_PATCH_ID:
2910 dm->iot_table.phydm_patch_id = (u32)value;
2911 break;
2912 case ODM_CMNINFO_RRSR_VAL:
2913 dm->dm_ra_table.rrsr_val_init = (u32)value;
2914 break;
2915 case ODM_CMNINFO_LINKED_BF_SUPPORT:
2916 dm->linked_bf_support = (u8)value;
2917 break;
2918 case ODM_CMNINFO_FLATNESS_TYPE:
2919 dm->flatness_type = (u8)value;
2920 break;
2921 case ODM_CMNINFO_TSSI_ENABLE:
2922 dm->en_tssi_mode = (u8)value;
2923 break;
2924 default:
2925 break;
2926 }
2927 }
2928
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)2929 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
2930 {
2931 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2932 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2933 struct ccx_info *ccx_info = &dm->dm_ccx_info;
2934
2935 switch (info_type) {
2936 /*@=== [FA Relative] ===========================================*/
2937 case PHYDM_INFO_FA_OFDM:
2938 return fa_t->cnt_ofdm_fail;
2939
2940 case PHYDM_INFO_FA_CCK:
2941 return fa_t->cnt_cck_fail;
2942
2943 case PHYDM_INFO_FA_TOTAL:
2944 return fa_t->cnt_all;
2945
2946 case PHYDM_INFO_CCA_OFDM:
2947 return fa_t->cnt_ofdm_cca;
2948
2949 case PHYDM_INFO_CCA_CCK:
2950 return fa_t->cnt_cck_cca;
2951
2952 case PHYDM_INFO_CCA_ALL:
2953 return fa_t->cnt_cca_all;
2954
2955 case PHYDM_INFO_CRC32_OK_VHT:
2956 return fa_t->cnt_vht_crc32_ok;
2957
2958 case PHYDM_INFO_CRC32_OK_HT:
2959 return fa_t->cnt_ht_crc32_ok;
2960
2961 case PHYDM_INFO_CRC32_OK_LEGACY:
2962 return fa_t->cnt_ofdm_crc32_ok;
2963
2964 case PHYDM_INFO_CRC32_OK_CCK:
2965 return fa_t->cnt_cck_crc32_ok;
2966
2967 case PHYDM_INFO_CRC32_ERROR_VHT:
2968 return fa_t->cnt_vht_crc32_error;
2969
2970 case PHYDM_INFO_CRC32_ERROR_HT:
2971 return fa_t->cnt_ht_crc32_error;
2972
2973 case PHYDM_INFO_CRC32_ERROR_LEGACY:
2974 return fa_t->cnt_ofdm_crc32_error;
2975
2976 case PHYDM_INFO_CRC32_ERROR_CCK:
2977 return fa_t->cnt_cck_crc32_error;
2978
2979 case PHYDM_INFO_EDCCA_FLAG:
2980 return fa_t->edcca_flag;
2981
2982 case PHYDM_INFO_OFDM_ENABLE:
2983 return fa_t->ofdm_block_enable;
2984
2985 case PHYDM_INFO_CCK_ENABLE:
2986 return fa_t->cck_block_enable;
2987
2988 case PHYDM_INFO_DBG_PORT_0:
2989 return fa_t->dbg_port0;
2990
2991 case PHYDM_INFO_CRC32_OK_HT_AGG:
2992 return fa_t->cnt_ht_crc32_ok_agg;
2993
2994 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
2995 return fa_t->cnt_ht_crc32_error_agg;
2996
2997 /*@=== [DIG] ================================================*/
2998
2999 case PHYDM_INFO_CURR_IGI:
3000 return dig_t->cur_ig_value;
3001
3002 /*@=== [RSSI] ===============================================*/
3003 case PHYDM_INFO_RSSI_MIN:
3004 return (u32)dm->rssi_min;
3005
3006 case PHYDM_INFO_RSSI_MAX:
3007 return (u32)dm->rssi_max;
3008
3009 case PHYDM_INFO_CLM_RATIO:
3010 return (u32)ccx_info->clm_ratio;
3011 case PHYDM_INFO_NHM_RATIO:
3012 return (u32)ccx_info->nhm_ratio;
3013 case PHYDM_INFO_NHM_NOISE_PWR:
3014 return (u32)ccx_info->nhm_level;
3015 case PHYDM_INFO_NHM_PWR:
3016 return (u32)ccx_info->nhm_pwr;
3017
3018 default:
3019 return 0xffffffff;
3020 }
3021 }
3022
3023 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)3024 void odm_init_all_work_items(struct dm_struct *dm)
3025 {
3026 void *adapter = dm->adapter;
3027 #if USE_WORKITEM
3028
3029 #ifdef CONFIG_ADAPTIVE_SOML
3030 odm_initialize_work_item(dm,
3031 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
3032 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
3033 (void *)adapter,
3034 "AdaptiveSOMLWorkitem");
3035 #endif
3036
3037 #ifdef ODM_EVM_ENHANCE_ANTDIV
3038 odm_initialize_work_item(dm,
3039 &dm->phydm_evm_antdiv_workitem,
3040 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
3041 (void *)adapter,
3042 "EvmAntdivWorkitem");
3043 #endif
3044
3045 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3046 odm_initialize_work_item(dm,
3047 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
3048 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
3049 (void *)adapter,
3050 "AntennaSwitchWorkitem");
3051 #endif
3052 #if (defined(CONFIG_HL_SMART_ANTENNA))
3053 odm_initialize_work_item(dm,
3054 &dm->dm_sat_table.hl_smart_antenna_workitem,
3055 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
3056 (void *)adapter,
3057 "hl_smart_ant_workitem");
3058
3059 odm_initialize_work_item(dm,
3060 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
3061 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
3062 (void *)adapter,
3063 "hl_smart_ant_decision_workitem");
3064 #endif
3065
3066 odm_initialize_work_item(
3067 dm,
3068 &dm->ra_rpt_workitem,
3069 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
3070 (void *)adapter,
3071 "ra_rpt_workitem");
3072
3073 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3074 odm_initialize_work_item(
3075 dm,
3076 &dm->fast_ant_training_workitem,
3077 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
3078 (void *)adapter,
3079 "fast_ant_training_workitem");
3080 #endif
3081
3082 #endif /*#if USE_WORKITEM*/
3083
3084 #ifdef PHYDM_BEAMFORMING_SUPPORT
3085 odm_initialize_work_item(
3086 dm,
3087 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
3088 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
3089 (void *)adapter,
3090 "txbf_enter_work_item");
3091
3092 odm_initialize_work_item(
3093 dm,
3094 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
3095 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
3096 (void *)adapter,
3097 "txbf_leave_work_item");
3098
3099 odm_initialize_work_item(
3100 dm,
3101 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
3102 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
3103 (void *)adapter,
3104 "txbf_fw_ndpa_work_item");
3105
3106 odm_initialize_work_item(
3107 dm,
3108 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
3109 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
3110 (void *)adapter,
3111 "txbf_clk_work_item");
3112
3113 odm_initialize_work_item(
3114 dm,
3115 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
3116 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
3117 (void *)adapter,
3118 "txbf_rate_work_item");
3119
3120 odm_initialize_work_item(
3121 dm,
3122 &dm->beamforming_info.txbf_info.txbf_status_work_item,
3123 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
3124 (void *)adapter,
3125 "txbf_status_work_item");
3126
3127 odm_initialize_work_item(
3128 dm,
3129 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
3130 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
3131 (void *)adapter,
3132 "txbf_reset_tx_path_work_item");
3133
3134 odm_initialize_work_item(
3135 dm,
3136 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
3137 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
3138 (void *)adapter,
3139 "txbf_get_tx_rate_work_item");
3140 #endif
3141
3142 #if (PHYDM_LA_MODE_SUPPORT == 1)
3143 odm_initialize_work_item(
3144 dm,
3145 &dm->adcsmp.adc_smp_work_item,
3146 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3147 (void *)adapter,
3148 "adc_smp_work_item");
3149
3150 odm_initialize_work_item(
3151 dm,
3152 &dm->adcsmp.adc_smp_work_item_1,
3153 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3154 (void *)adapter,
3155 "adc_smp_work_item_1");
3156 #endif
3157 }
3158
odm_free_all_work_items(struct dm_struct * dm)3159 void odm_free_all_work_items(struct dm_struct *dm)
3160 {
3161 #if USE_WORKITEM
3162
3163 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3164 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
3165 #endif
3166
3167 #ifdef CONFIG_ADAPTIVE_SOML
3168 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
3169 #endif
3170
3171 #ifdef ODM_EVM_ENHANCE_ANTDIV
3172 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
3173 #endif
3174
3175 #if (defined(CONFIG_HL_SMART_ANTENNA))
3176 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
3177 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
3178 #endif
3179
3180 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3181 odm_free_work_item(&dm->fast_ant_training_workitem);
3182 #endif
3183 odm_free_work_item(&dm->ra_rpt_workitem);
3184 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
3185 #endif
3186
3187 #ifdef PHYDM_BEAMFORMING_SUPPORT
3188 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
3189 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
3190 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
3191 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
3192 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
3193 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
3194 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
3195 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
3196 #endif
3197
3198 #if (PHYDM_LA_MODE_SUPPORT == 1)
3199 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
3200 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
3201 #endif
3202 }
3203 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
3204
odm_init_all_timers(struct dm_struct * dm)3205 void odm_init_all_timers(struct dm_struct *dm)
3206 {
3207 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3208 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
3209 #endif
3210 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
3211 #ifdef IS_USE_NEW_TDMA
3212 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
3213 #endif
3214 #endif
3215 #ifdef CONFIG_ADAPTIVE_SOML
3216 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
3217 #endif
3218 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3219 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3220 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
3221 #endif
3222 #endif
3223
3224 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3225 odm_initialize_timer(dm, &dm->sbdcnt_timer,
3226 (void *)phydm_sbd_callback, NULL, "SbdTimer");
3227 #ifdef PHYDM_BEAMFORMING_SUPPORT
3228 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
3229 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
3230 "txbf_fw_ndpa_timer");
3231 #endif
3232 #endif
3233
3234 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3235 #ifdef PHYDM_BEAMFORMING_SUPPORT
3236 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
3237 (void *)beamforming_sw_timer_callback, NULL,
3238 "beamforming_timer");
3239 #endif
3240 #endif
3241 }
3242
odm_cancel_all_timers(struct dm_struct * dm)3243 void odm_cancel_all_timers(struct dm_struct *dm)
3244 {
3245 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3246 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
3247 if (dm->adapter == NULL)
3248 return;
3249 #endif
3250
3251 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3252 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
3253 #endif
3254 #ifdef PHYDM_TDMA_DIG_SUPPORT
3255 #ifdef IS_USE_NEW_TDMA
3256 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
3257 #endif
3258 #endif
3259 #ifdef CONFIG_ADAPTIVE_SOML
3260 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
3261 #endif
3262 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3263 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3264 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
3265 #endif
3266 #endif
3267
3268 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3269 odm_cancel_timer(dm, &dm->sbdcnt_timer);
3270 #ifdef PHYDM_BEAMFORMING_SUPPORT
3271 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3272 #endif
3273 #endif
3274
3275 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3276 #ifdef PHYDM_BEAMFORMING_SUPPORT
3277 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
3278 #endif
3279 #endif
3280 }
3281
odm_release_all_timers(struct dm_struct * dm)3282 void odm_release_all_timers(struct dm_struct *dm)
3283 {
3284 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3285 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
3286 #endif
3287 #ifdef PHYDM_TDMA_DIG_SUPPORT
3288 #ifdef IS_USE_NEW_TDMA
3289 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
3290 #endif
3291 #endif
3292 #ifdef CONFIG_ADAPTIVE_SOML
3293 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
3294 #endif
3295 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3296 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3297 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
3298 #endif
3299 #endif
3300
3301 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3302 odm_release_timer(dm, &dm->sbdcnt_timer);
3303 #ifdef PHYDM_BEAMFORMING_SUPPORT
3304 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3305 #endif
3306 #endif
3307
3308 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3309 #ifdef PHYDM_BEAMFORMING_SUPPORT
3310 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
3311 #endif
3312 #endif
3313 }
3314
3315 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)3316 void odm_init_all_threads(
3317 struct dm_struct *dm)
3318 {
3319 #ifdef TPT_THREAD
3320 k_tpt_task_init(dm->priv);
3321 #endif
3322 }
3323
odm_stop_all_threads(struct dm_struct * dm)3324 void odm_stop_all_threads(
3325 struct dm_struct *dm)
3326 {
3327 #ifdef TPT_THREAD
3328 k_tpt_task_stop(dm->priv);
3329 #endif
3330 }
3331 #endif
3332
3333 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3334 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
3335 * 2012/11/05
3336 */
odm_dtc(struct dm_struct * dm)3337 void odm_dtc(struct dm_struct *dm)
3338 {
3339 #ifdef CONFIG_DM_RESP_TXAGC
3340 /* RSSI higher than this value, start to decade TX power */
3341 #define DTC_BASE 35
3342
3343 /* RSSI lower than this value, start to increase TX power */
3344 #define DTC_DWN_BASE (DTC_BASE - 5)
3345
3346 /* RSSI vs TX power step mapping: decade TX power */
3347 static const u8 dtc_table_down[] = {
3348 DTC_BASE,
3349 (DTC_BASE + 5),
3350 (DTC_BASE + 10),
3351 (DTC_BASE + 15),
3352 (DTC_BASE + 20),
3353 (DTC_BASE + 25)};
3354
3355 /* RSSI vs TX power step mapping: increase TX power */
3356 static const u8 dtc_table_up[] = {
3357 DTC_DWN_BASE,
3358 (DTC_DWN_BASE - 5),
3359 (DTC_DWN_BASE - 10),
3360 (DTC_DWN_BASE - 15),
3361 (DTC_DWN_BASE - 15),
3362 (DTC_DWN_BASE - 20),
3363 (DTC_DWN_BASE - 20),
3364 (DTC_DWN_BASE - 25),
3365 (DTC_DWN_BASE - 25),
3366 (DTC_DWN_BASE - 30),
3367 (DTC_DWN_BASE - 35)};
3368
3369 u8 i;
3370 u8 dtc_steps = 0;
3371 u8 sign;
3372 u8 resp_txagc = 0;
3373
3374 if (dm->rssi_min > DTC_BASE) {
3375 /* need to decade the CTS TX power */
3376 sign = 1;
3377 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
3378 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
3379 break;
3380 else
3381 dtc_steps++;
3382 }
3383 }
3384 #if 0
3385 else if (dm->rssi_min > DTC_DWN_BASE) {
3386 /* needs to increase the CTS TX power */
3387 sign = 0;
3388 dtc_steps = 1;
3389 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3390 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3391 break;
3392 else
3393 dtc_steps++;
3394 }
3395 }
3396 #endif
3397 else {
3398 sign = 0;
3399 dtc_steps = 0;
3400 }
3401
3402 resp_txagc = dtc_steps | (sign << 4);
3403 resp_txagc = resp_txagc | (resp_txagc << 5);
3404 odm_write_1byte(dm, 0x06d9, resp_txagc);
3405
3406 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3407 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3408 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3409 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3410 }
3411
3412 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3413
3414 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3415 void phydm_dc_cancellation(struct dm_struct *dm)
3416 {
3417 #ifdef PHYDM_DC_CANCELLATION
3418 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3419 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3420 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3421 u8 path = RF_PATH_A;
3422 u8 set_result;
3423
3424 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3425 return;
3426 if ((dm->support_ic_type & ODM_RTL8188F) &&
3427 dm->cut_version < ODM_CUT_D)
3428 return;
3429 if ((dm->support_ic_type & ODM_RTL8192F) &&
3430 dm->cut_version == ODM_CUT_A)
3431 return;
3432 if (*dm->band_width == CHANNEL_WIDTH_5)
3433 return;
3434 if (*dm->band_width == CHANNEL_WIDTH_10)
3435 return;
3436
3437 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3438
3439 /*@DC_Estimation (only for 2x2 ic now) */
3440
3441 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3442 if (path > RF_PATH_A &&
3443 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3444 ODM_RTL8710B | ODM_RTL8721D |
3445 ODM_RTL8710C | ODM_RTL8723D))
3446 break;
3447 else if (path > RF_PATH_B &&
3448 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3449 break;
3450 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3451 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3452 return;
3453 }
3454 odm_write_dig(dm, 0x7e);
3455 /*@Disable LNA*/
3456 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3457 ODM_RTL8710C))
3458 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3459 /*@Enable ADC short*/
3460 if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C))
3461 odm_set_bb_reg(dm, R_0x880, BIT(15), 0x1);
3462 /*Turn off 3-wire*/
3463 phydm_stop_3_wire(dm, PHYDM_SET);
3464 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3465 ODM_RTL8710B)) {
3466 /*set debug port to 0x235*/
3467 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3468 PHYDM_DBG(dm, ODM_COMP_API,
3469 "Set Debug port Fail\n");
3470 return;
3471 }
3472 } else if (dm->support_ic_type & (ODM_RTL8721D |
3473 ODM_RTL8710C)) {
3474 /*set debug port to 0x200*/
3475 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3476 PHYDM_DBG(dm, ODM_COMP_API,
3477 "Set Debug port Fail\n");
3478 return;
3479 }
3480 } else if (dm->support_ic_type & ODM_RTL8821C) {
3481 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3482 /*set debug port to 0x200*/
3483 PHYDM_DBG(dm, ODM_COMP_API,
3484 "Set Debug port Fail\n");
3485 return;
3486 }
3487 phydm_bb_dbg_port_header_sel(dm, 0x0);
3488 } else if (dm->support_ic_type & ODM_RTL8822B) {
3489 if (path == RF_PATH_A &&
3490 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3491 /*set debug port to 0x200*/
3492 PHYDM_DBG(dm, ODM_COMP_API,
3493 "Set Debug port Fail\n");
3494 return;
3495 }
3496 if (path == RF_PATH_B &&
3497 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3498 /*set debug port to 0x200*/
3499 PHYDM_DBG(dm, ODM_COMP_API,
3500 "Set Debug port Fail\n");
3501 return;
3502 }
3503 phydm_bb_dbg_port_header_sel(dm, 0x0);
3504 } else if (dm->support_ic_type & ODM_RTL8192F) {
3505 if (path == RF_PATH_A &&
3506 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3507 /*set debug port to 0x235*/
3508 PHYDM_DBG(dm, ODM_COMP_API,
3509 "Set Debug port Fail\n");
3510 return;
3511 }
3512 if (path == RF_PATH_B &&
3513 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3514 /*set debug port to 0x23d*/
3515 PHYDM_DBG(dm, ODM_COMP_API,
3516 "Set Debug port Fail\n");
3517 return;
3518 }
3519 }
3520
3521 /*@disable CCK DCNF*/
3522 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3523
3524 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3525
3526 phydm_stop_ck320(dm, true); /*stop ck320*/
3527
3528 /* the same debug port both for path-a and path-b*/
3529 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3530
3531 phydm_stop_ck320(dm, false); /*start ck320*/
3532
3533 phydm_release_bb_dbg_port(dm);
3534 /* @Turn on 3-wire*/
3535 phydm_stop_3_wire(dm, PHYDM_REVERT);
3536 /* @Disable ADC short*/
3537 if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C))
3538 odm_set_bb_reg(dm, R_0x880, BIT(15), 0x0);
3539 /* @Enable LNA*/
3540 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3541 ODM_RTL8710C))
3542 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3543
3544 odm_write_dig(dm, 0x20);
3545
3546 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3547
3548 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3549 }
3550
3551 /*@DC_Cancellation*/
3552 /*@DC compensation to CCK data path*/
3553 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3554 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3555 ODM_RTL8710B)) {
3556 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3557 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3558
3559 /*@Before filling into registers,
3560 *offset should be multiplexed (-1)
3561 */
3562 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3563 (0x400 - offset_i_hex[0]) :
3564 (0x1ff - offset_i_hex[0]);
3565 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3566 (0x400 - offset_q_hex[0]) :
3567 (0x1ff - offset_q_hex[0]);
3568
3569 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3570 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3571 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3572 /* Path-a */
3573 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3574 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3575
3576 /*@Before filling into registers,
3577 *offset should be multiplexed (-1)
3578 */
3579 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3580 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3581
3582 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3583 (0x3c0 & offset_i_hex[0]) >> 6);
3584 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3585 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3586 (0x3c0 & offset_q_hex[0]) >> 6);
3587 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3588
3589 /* Path-b */
3590 if (dm->rf_type > RF_1T1R) {
3591 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3592 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3593
3594 /*@Before filling into registers,
3595 *offset should be multiplexed (-1)
3596 */
3597 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3598 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3599
3600 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3601 (0x3c0 & offset_i_hex[1]) >> 6);
3602 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3603 0x3f & offset_i_hex[1]);
3604 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3605 (0x3c0 & offset_q_hex[1]) >> 6);
3606 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3607 0x3f & offset_q_hex[1]);
3608 }
3609 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3610 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3611 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3612 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3613
3614 /*@Before filling into registers,
3615 *offset should be multiplexed (-1)
3616 */
3617 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3618 (0x400 - offset_i_hex[0]) :
3619 (0xff - offset_i_hex[0]);
3620 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3621 (0x400 - offset_q_hex[0]) :
3622 (0xff - offset_q_hex[0]);
3623 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3624 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3625 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3626
3627 /* Path-b */
3628 if (dm->rf_type > RF_1T1R) {
3629 /* @I:df4[27:18],Q:df4[17:8]*/
3630 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3631 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3632
3633 /*@Before filling into registers,
3634 *offset should be multiplexed (-1)
3635 */
3636 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3637 (0x400 - offset_i_hex[1]) :
3638 (0xff - offset_i_hex[1]);
3639 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3640 (0x400 - offset_q_hex[1]) :
3641 (0xff - offset_q_hex[1]);
3642 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3643 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3644 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3645 }
3646 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
3647 /*judy modified 20180517*/
3648 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3649 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3650
3651 if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1)
3652 || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) {
3653 /*@Discard outliers*/
3654 offset_i_hex[0] = 0x0;
3655 offset_q_hex[0] = 0x0;
3656 } else {
3657 /*@Before filling into registers,
3658 *offset should be multiplexed (-1)
3659 */
3660 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3661 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3662 }
3663 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3664 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3665 }
3666 #endif
3667 }
3668
phydm_receiver_blocking(void * dm_void)3669 void phydm_receiver_blocking(void *dm_void)
3670 {
3671 #ifdef CONFIG_RECEIVER_BLOCKING
3672 struct dm_struct *dm = (struct dm_struct *)dm_void;
3673 u32 chnl = *dm->channel;
3674 u8 bw = *dm->band_width;
3675 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3676
3677 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3678 *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
3679 return;
3680
3681 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3682 dm->support_ic_type & ODM_RTL8192E) {
3683 /*@8188E_T version*/
3684 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3685 goto end;
3686
3687 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3688 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3689 PHYDM_DONT_CARE);
3690 dm->is_rx_blocking_en = true;
3691 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3692 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3693 PHYDM_DONT_CARE);
3694 dm->is_rx_blocking_en = true;
3695 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3696 phydm_nbi_enable(dm, FUNC_DISABLE);
3697 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3698 dm->is_rx_blocking_en = false;
3699 }
3700 return;
3701 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3702 /*@8188E_S version*/
3703 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3704 goto end;
3705
3706 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3707 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3708 PHYDM_DONT_CARE);
3709 dm->is_rx_blocking_en = true;
3710 } else if (dm->is_rx_blocking_en && chnl != 13) {
3711 phydm_nbi_enable(dm, FUNC_DISABLE);
3712 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3713 dm->is_rx_blocking_en = false;
3714 }
3715 return;
3716 }
3717
3718 end:
3719 if (dm->is_rx_blocking_en) {
3720 phydm_nbi_enable(dm, FUNC_DISABLE);
3721 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3722 dm->is_rx_blocking_en = false;
3723 }
3724 #endif
3725 }
3726
phydm_dyn_bw_indication(void * dm_void)3727 void phydm_dyn_bw_indication(void *dm_void)
3728 {
3729 #ifdef CONFIG_BW_INDICATION
3730 struct dm_struct *dm = (struct dm_struct *)dm_void;
3731 u8 en_auto_bw_th = dm->en_auto_bw_th;
3732
3733 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
3734 return;
3735
3736 /*driver decide bw cobime timing*/
3737 if (dm->dis_dym_bw_indication) {
3738 if (*dm->dis_dym_bw_indication)
3739 return;
3740 }
3741
3742 /*check for auto bw*/
3743 if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
3744 phydm_bw_fixed_enable(dm, FUNC_DISABLE);
3745 return;
3746 }
3747
3748 phydm_bw_fixed_setting(dm);
3749 #endif
3750 }
3751
3752