1 /* 2 * SPI device spec header file 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: spid.h 514727 2014-11-12 03:02:48Z $ 30 */ 31 32 #ifndef _SPI_H 33 #define _SPI_H 34 35 /* 36 * Brcm SPI Device Register Map. 37 * 38 */ 39 40 typedef volatile struct { 41 uint8 config; /* 0x00, len, endian, clock, speed, polarity, wakeup */ 42 uint8 response_delay; /* 0x01, read response delay in bytes (corerev < 3) */ 43 uint8 status_enable; /* 0x02, status-enable, intr with status, response_delay 44 * function selection, command/data error check 45 */ 46 uint8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */ 47 uint16 intr_reg; /* 0x04, Intr status register */ 48 uint16 intr_en_reg; /* 0x06, Intr mask register */ 49 uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */ 50 uint16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */ 51 uint16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */ 52 uint16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */ 53 uint32 test_read; /* 0x14, RO 0xfeedbead signature */ 54 uint32 test_rw; /* 0x18, RW */ 55 uint8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */ 56 uint8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */ 57 uint8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */ 58 uint8 resp_delay_f3; /* 0x1f, read resp delay bytes for F3 (corerev >= 3) */ 59 } spi_regs_t; 60 61 /* SPI device register offsets */ 62 #define SPID_CONFIG 0x00 63 #define SPID_RESPONSE_DELAY 0x01 64 #define SPID_STATUS_ENABLE 0x02 65 #define SPID_RESET_BP 0x03 /* (corerev >= 1) */ 66 #define SPID_INTR_REG 0x04 /* 16 bits - Interrupt status */ 67 #define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */ 68 #define SPID_STATUS_REG 0x08 /* 32 bits */ 69 #define SPID_F1_INFO_REG 0x0C /* 16 bits */ 70 #define SPID_F2_INFO_REG 0x0E /* 16 bits */ 71 #define SPID_F3_INFO_REG 0x10 /* 16 bits */ 72 #define SPID_TEST_READ 0x14 /* 32 bits */ 73 #define SPID_TEST_RW 0x18 /* 32 bits */ 74 #define SPID_RESP_DELAY_F0 0x1c /* 8 bits (corerev >= 3) */ 75 #define SPID_RESP_DELAY_F1 0x1d /* 8 bits (corerev >= 3) */ 76 #define SPID_RESP_DELAY_F2 0x1e /* 8 bits (corerev >= 3) */ 77 #define SPID_RESP_DELAY_F3 0x1f /* 8 bits (corerev >= 3) */ 78 79 /* Bit masks for SPID_CONFIG device register */ 80 #define WORD_LENGTH_32 0x1 /* 0/1 16/32 bit word length */ 81 #define ENDIAN_BIG 0x2 /* 0/1 Little/Big Endian */ 82 #define CLOCK_PHASE 0x4 /* 0/1 clock phase delay */ 83 #define CLOCK_POLARITY 0x8 /* 0/1 Idle state clock polarity is low/high */ 84 #define HIGH_SPEED_MODE 0x10 /* 1/0 High Speed mode / Normal mode */ 85 #define INTR_POLARITY 0x20 /* 1/0 Interrupt active polarity is high/low */ 86 #define WAKE_UP 0x80 /* 0/1 Wake-up command from Host to WLAN */ 87 88 /* Bit mask for SPID_RESPONSE_DELAY device register */ 89 #define RESPONSE_DELAY_MASK 0xFF /* Configurable rd response delay in multiples of 8 bits */ 90 91 /* Bit mask for SPID_STATUS_ENABLE device register */ 92 #define STATUS_ENABLE 0x1 /* 1/0 Status sent/not sent to host after read/write */ 93 #define INTR_WITH_STATUS 0x2 /* 0/1 Do-not / do-interrupt if status is sent */ 94 #define RESP_DELAY_ALL 0x4 /* Applicability of resp delay to F1 or all func's read */ 95 #define DWORD_PKT_LEN_EN 0x8 /* Packet len denoted in dwords instead of bytes */ 96 #define CMD_ERR_CHK_EN 0x20 /* Command error check enable */ 97 #define DATA_ERR_CHK_EN 0x40 /* Data error check enable */ 98 99 /* Bit mask for SPID_RESET_BP device register */ 100 #define RESET_ON_WLAN_BP_RESET 0x4 /* enable reset for WLAN backplane */ 101 #define RESET_ON_BT_BP_RESET 0x8 /* enable reset for BT backplane */ 102 #define RESET_SPI 0x80 /* reset the above enabled logic */ 103 104 /* Bit mask for card capability */ 105 #define SPID_CHIPID_PRESENT 0x20 /* duplicate of cardcapability chipid present */ 106 #define SPID_SECURE_MODE 0x40 /* duplicate of cardcapability secure mode */ 107 108 /* Bit mask for SPID_INTR_REG device register */ 109 #define DATA_UNAVAILABLE 0x0001 /* Requested data not available; Clear by writing a "1" */ 110 #define F2_F3_FIFO_RD_UNDERFLOW 0x0002 111 #define F2_F3_FIFO_WR_OVERFLOW 0x0004 112 #define COMMAND_ERROR 0x0008 /* Cleared by writing 1 */ 113 #define DATA_ERROR 0x0010 /* Cleared by writing 1 */ 114 #define F2_PACKET_AVAILABLE 0x0020 115 #define F3_PACKET_AVAILABLE 0x0040 116 #define F1_OVERFLOW 0x0080 /* Due to last write. Bkplane has pending write requests */ 117 #define MISC_INTR0 0x0100 118 #define MISC_INTR1 0x0200 119 #define MISC_INTR2 0x0400 120 #define MISC_INTR3 0x0800 121 #define MISC_INTR4 0x1000 122 #define F1_INTR 0x2000 123 #define F2_INTR 0x4000 124 #define F3_INTR 0x8000 125 126 /* Bit mask for 32bit SPID_STATUS_REG device register */ 127 #define STATUS_DATA_NOT_AVAILABLE 0x00000001 128 #define STATUS_UNDERFLOW 0x00000002 129 #define STATUS_OVERFLOW 0x00000004 130 #define STATUS_F2_INTR 0x00000008 131 #define STATUS_F3_INTR 0x00000010 132 #define STATUS_F2_RX_READY 0x00000020 133 #define STATUS_F3_RX_READY 0x00000040 134 #define STATUS_HOST_CMD_DATA_ERR 0x00000080 135 #define STATUS_F2_PKT_AVAILABLE 0x00000100 136 #define STATUS_F2_PKT_LEN_MASK 0x000FFE00 137 #define STATUS_F2_PKT_LEN_SHIFT 9 138 #define STATUS_F3_PKT_AVAILABLE 0x00100000 139 #define STATUS_F3_PKT_LEN_MASK 0xFFE00000 140 #define STATUS_F3_PKT_LEN_SHIFT 21 141 142 /* Bit mask for 16 bits SPID_F1_INFO_REG device register */ 143 #define F1_ENABLED 0x0001 144 #define F1_RDY_FOR_DATA_TRANSFER 0x0002 145 #define F1_MAX_PKT_SIZE 0x01FC 146 147 /* Bit mask for 16 bits SPID_F2_INFO_REG device register */ 148 #define F2_ENABLED 0x0001 149 #define F2_RDY_FOR_DATA_TRANSFER 0x0002 150 #define F2_MAX_PKT_SIZE 0x3FFC 151 152 /* Bit mask for 16 bits SPID_F3_INFO_REG device register */ 153 #define F3_ENABLED 0x0001 154 #define F3_RDY_FOR_DATA_TRANSFER 0x0002 155 #define F3_MAX_PKT_SIZE 0x3FFC 156 157 /* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */ 158 #define TEST_RO_DATA_32BIT_LE 0xFEEDBEAD 159 160 /* Maximum number of I/O funcs */ 161 #define SPI_MAX_IOFUNCS 4 162 163 #define SPI_MAX_PKT_LEN (2048*4) 164 165 /* Misc defines */ 166 #define SPI_FUNC_0 0 167 #define SPI_FUNC_1 1 168 #define SPI_FUNC_2 2 169 #define SPI_FUNC_3 3 170 171 #ifdef BCMQT 172 #define WAIT_F2RXFIFORDY 200 173 #define WAIT_F2RXFIFORDY_DELAY 100 174 #else 175 #define WAIT_F2RXFIFORDY 100 176 #define WAIT_F2RXFIFORDY_DELAY 20 177 #endif // endif 178 179 #endif /* _SPI_H */ 180