1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SD-SPI Protocol Standard 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1999-2017, Broadcom Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 9*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 10*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 11*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12*4882a593Smuzhiyun * following added to such license: 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 15*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 16*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 17*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 18*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 19*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 20*4882a593Smuzhiyun * modifications of the software. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Notwithstanding the above, under no circumstances may you combine this 23*4882a593Smuzhiyun * software in any way with any other Broadcom software provided under a license 24*4882a593Smuzhiyun * other than the GPL, without Broadcom's express prior written consent. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Open:>> 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * $Id$ 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #ifndef _SD_SPI_H 32*4882a593Smuzhiyun #define _SD_SPI_H 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define SPI_START_M BITFIELD_MASK(1) /* Bit [31] - Start Bit */ 35*4882a593Smuzhiyun #define SPI_START_S 31 36*4882a593Smuzhiyun #define SPI_DIR_M BITFIELD_MASK(1) /* Bit [30] - Direction */ 37*4882a593Smuzhiyun #define SPI_DIR_S 30 38*4882a593Smuzhiyun #define SPI_CMD_INDEX_M BITFIELD_MASK(6) /* Bits [29:24] - Command number */ 39*4882a593Smuzhiyun #define SPI_CMD_INDEX_S 24 40*4882a593Smuzhiyun #define SPI_RW_M BITFIELD_MASK(1) /* Bit [23] - Read=0, Write=1 */ 41*4882a593Smuzhiyun #define SPI_RW_S 23 42*4882a593Smuzhiyun #define SPI_FUNC_M BITFIELD_MASK(3) /* Bits [22:20] - Function Number */ 43*4882a593Smuzhiyun #define SPI_FUNC_S 20 44*4882a593Smuzhiyun #define SPI_RAW_M BITFIELD_MASK(1) /* Bit [19] - Read After Wr */ 45*4882a593Smuzhiyun #define SPI_RAW_S 19 46*4882a593Smuzhiyun #define SPI_STUFF_M BITFIELD_MASK(1) /* Bit [18] - Stuff bit */ 47*4882a593Smuzhiyun #define SPI_STUFF_S 18 48*4882a593Smuzhiyun #define SPI_BLKMODE_M BITFIELD_MASK(1) /* Bit [19] - Blockmode 1=blk */ 49*4882a593Smuzhiyun #define SPI_BLKMODE_S 19 50*4882a593Smuzhiyun #define SPI_OPCODE_M BITFIELD_MASK(1) /* Bit [18] - OP Code */ 51*4882a593Smuzhiyun #define SPI_OPCODE_S 18 52*4882a593Smuzhiyun #define SPI_ADDR_M BITFIELD_MASK(17) /* Bits [17:1] - Address */ 53*4882a593Smuzhiyun #define SPI_ADDR_S 1 54*4882a593Smuzhiyun #define SPI_STUFF0_M BITFIELD_MASK(1) /* Bit [0] - Stuff bit */ 55*4882a593Smuzhiyun #define SPI_STUFF0_S 0 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define SPI_RSP_START_M BITFIELD_MASK(1) /* Bit [7] - Start Bit (always 0) */ 58*4882a593Smuzhiyun #define SPI_RSP_START_S 7 59*4882a593Smuzhiyun #define SPI_RSP_PARAM_ERR_M BITFIELD_MASK(1) /* Bit [6] - Parameter Error */ 60*4882a593Smuzhiyun #define SPI_RSP_PARAM_ERR_S 6 61*4882a593Smuzhiyun #define SPI_RSP_RFU5_M BITFIELD_MASK(1) /* Bit [5] - RFU (Always 0) */ 62*4882a593Smuzhiyun #define SPI_RSP_RFU5_S 5 63*4882a593Smuzhiyun #define SPI_RSP_FUNC_ERR_M BITFIELD_MASK(1) /* Bit [4] - Function number error */ 64*4882a593Smuzhiyun #define SPI_RSP_FUNC_ERR_S 4 65*4882a593Smuzhiyun #define SPI_RSP_CRC_ERR_M BITFIELD_MASK(1) /* Bit [3] - COM CRC Error */ 66*4882a593Smuzhiyun #define SPI_RSP_CRC_ERR_S 3 67*4882a593Smuzhiyun #define SPI_RSP_ILL_CMD_M BITFIELD_MASK(1) /* Bit [2] - Illegal Command error */ 68*4882a593Smuzhiyun #define SPI_RSP_ILL_CMD_S 2 69*4882a593Smuzhiyun #define SPI_RSP_RFU1_M BITFIELD_MASK(1) /* Bit [1] - RFU (Always 0) */ 70*4882a593Smuzhiyun #define SPI_RSP_RFU1_S 1 71*4882a593Smuzhiyun #define SPI_RSP_IDLE_M BITFIELD_MASK(1) /* Bit [0] - In idle state */ 72*4882a593Smuzhiyun #define SPI_RSP_IDLE_S 0 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* SD-SPI Protocol Definitions */ 75*4882a593Smuzhiyun #define SDSPI_COMMAND_LEN 6 /* Number of bytes in an SD command */ 76*4882a593Smuzhiyun #define SDSPI_START_BLOCK 0xFE /* SD Start Block Token */ 77*4882a593Smuzhiyun #define SDSPI_IDLE_PAD 0xFF /* SD-SPI idle value for MOSI */ 78*4882a593Smuzhiyun #define SDSPI_START_BIT_MASK 0x80 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif /* _SD_SPI_H */ 81